Robust saturated control for low-power circuits

Robust Saturated Control for Low-Power Circuits C. Albea, F. Gordillo and C. Canudas de Wit Abstract —An important issue in the trends of miniaturization of Systems on Chips (SoCs) is to obtain a high energy efficiency. This can be reached by Dynamic Voltage Scaling (DVS) architectures as the novel discrete Vdd-Hopping circuit. Generally, this kind of systems present parameter uncertainties and delays. Likewise, current peaks and energy dissipation must be reduced. In this paper, an optimal and robust saturated control law is proposed for this Vdd-Hopping circuit via Lyapunov-Krasovskii theory that ensures asymptotic stability as well as system robustness with respect to delay presence and parameter uncertainties. The closed-loop system presents a regional stabilization due to the actuator saturation. An estimation of an attraction domain is provided. This controller also limites the current peaks and it provides an energyaware performance. The advantages achieved with this controller are shown in simulation. I. Introduction The continuous miniaturization of Systems on Chips (SoCs) is possible from emerging studies about energy saving in Very-Large-Scale Integration (VLSI), especially in portable electronics devices. Dynamic Voltage Scaling (DVS) [1] is a powerful method to reduce the power consumption in micro-circuits and in nano-circuits. The principle of DVS approach is to adapt levels of supply voltage for reducing power consumption. This kind of architectures adapt the core voltage, vc, of the cluster at the minimum performance level required by the process activity [2]. Generally, a DVS circuit is implemented by integrated dynamic DC-DC converters [3], [4], [5]. However, these DC-DC converters can present some limitations in fine grain. This is the reason why new discrete circuits with reduced size have been developed based on DVS [6], [7], as Vdd-Hopping circuit [8]. This structure allows changing the drain supply voltage level (Vdd) in nano-circuits in high speed. The main control problem for Vdd-Hopping circuit is the adaptation for various loading conditions, achieving high efficiency over a wide load-current range, what is critical for extended battery life. Likewise, other control objectives are to provide a correct and reliable operation during the switches transitions, i.e., small current peaks, This work has been conducted while C. Albea was with INPG, Gipsa-lab Grenoble, France and the Dpto. de Ing. de Sistemas y Autom´atica, Sevilla, Spain. Now, C.Albea is with both CNRS ; LAAS ; 7 avenue du colonel Roche, F-31077 Toulouse, France and Universit´e de Toulouse ; UPS, INSA, INP, ISAE ; UT1, UTM, LAAS ; F-31077 Toulouse, France [email protected] F. Gordillo is with the Dpto. de Ing. de Sistemas y Autom´atica, Sevilla, Spain [email protected] C. Canudas de Wit is with the CNRS, Gipsa-lab, Grenoble, France [email protected] faster transient periods, system stability and robustness with respect to delays and parameter uncertainties. Indeed, Vdd-Hopping circuits implemented in these SoC structures present delays at the input and output of its control block [9]. The control block input delay is required to ensure that the system is synchronized with the cluster clock. In the same way, there is a control block output delay associated with computational issues. Moreover, the presence of parameter uncertainties can generate a nondesirable performance and lack of reliability of the system. Other additional and relevant issue is to limit current peaks and energy consumption. In summary, delay presence, parameter uncertainties, current peaks and energy consumption must be considered in the design of the controller. In this paper, an optimal and robust saturated control law for the Vdd-hopping circuit is proposed in discrete time. This controller limites high current peaks. It provides an efficient tracking capability to handle two voltage levels required by the cluster. As a side effect, it also has high energy-efficiency, achieving fast transient periods. The system is rewritten into a suitable state-space representation to formulate an optimal and robust problem that can be solved by using Lyapunov-Krasovskii theory [10], [11]. In this process, the saturation in the controller is considered [12], [13]. The designed controller guarantees asymptotic stability as well as robustness of the system with respect to delays and uncertain parameters. The problem is expressed in terms of Linear Matrix Inequalities (LMIs). Likewise, an attraction domain is estimated in such a way that a regional stabilization for the saturated control is guaranteed. The robustness properties of the closed-loop system are tested by some simulations. An evaluation and comparison of this controller with respect to an ‘intuitive’ controller presented in [6] is performed. The rest of this work is organized as follows: in Section II, the error equation of the Vdd-hopping system is presented as well as the proposed control law. The robustness and optimization problem statement is presented in Section III and in Section IV, a control design is developed. The control gains are computed in Section V, being tested by simulations in Section VI. A comparison of this controller is performed in Section VII. The work closes with a section of conclusions. Notation. For a given x∈ R, satM m(x),   M if x > M x if m ≤x≤M m if x < m. and round(x) is the nearest integer to x. ∆x,x+−x− To cite this article: IEEE Transactions on Control Systems Technology. 2013. Vol. 21. Núm. 2. pp. 530-537 is the value of xin two consecutive sampling time. For a given set S,Co(S) denotes the convex hull of S. II. Error equation of the Vdd-Hopping circuit In [8] a discrete circuit that handles two-voltage levels with a Vdd-Hopping technique accomplishing a DVS architecture was presented. The Vdd-Hopping circuit is constituted by: a high voltages supply, Vh; a low voltage supply, Vl; a group of PMOS transistors connected in parallel between the Vhand the core voltage, vc, and a PMOS transistor that connects the Vlto vcwhen the low voltage level is the steadystate. This reduces the dissipated energy when the unit running is at low speed. The group of PMOS transistors connected in parallel allow evolving the output voltage from a low voltage level to a high voltage level (rising transient period) and from a high voltage level to a low voltage level (falling transient period). The steady state must correspond to a high voltage level or a low voltage level. For simplicity, the low voltage supply, Vl, as well as its PMOS transistor of connection with vcare disregarded for control design purposes. The main objective is to ensure that vcachieves the two voltage levels by switching the PMOS transistors. The sketch of this circuit is shown in Fig. 1. In this configuration, at least, one transistor must always be switched on. The load model taken in this work is an impedance which depends on the clock frequency, fclk, and sometimes, also on vc[14]. It is composed of a current supply, Ileak, a capacitance, C, and a dynamic resistance, RL(fclk, vc), representing the dynamic and short-circuit consumption. Ileak is assumed constant. M1R1 Mn−1Rn−1 MnRn Vh IMPEDANCE Il(vc) Ileak CRL M2R2 CONTROL uk vc Fig. 1: Vdd-hopping, voltage supply and load. Assumption 1: PMOS transistors are modeled as ideal resistors, R0, when they are switched on and, as resistors with infinite resistance when they are switched off. They are considered to have the same electrical characteristic. In the steady state, the maximum and minimum voltage are Vh−∆hand Vl−∆l, respectively. ∆h,∆l∈Rdepend on several factors and are difficult to estimate. These variables catch the PMOS model errors, current variations, supply voltage and the resistive losses through the PMOS transistors switched on. Assumption 2: ∆h, ∆lare small with respect to vc, and they do not change the system stability properties. The voltage loop equation yields the relationship Il(vc) = Vh−vc Ruk ,(1) where Ruk,R0 uk, being ukthe number of transistors switched on, thus, uk∈ U ={1,2, ..N}and it is the control variable. The discrete Vdd-hopping circuit is connected to a load that can be modeled as an impedance depending on the core voltage, vc. In this work, the load model presented in [14] is employed: Il(vc) = vc RL +Ileak +Cdvc dt (2) Consider ek,vr−vckwhere vris a constant voltage reference and vckis the sampling core voltage. Now, from Eqs. (1), (2), the approximate discrete-time voltage error equation is ek+1 = (1−Tsβ)ek+Tsb(vr−Vh)uk+Ts(βvr+δ−bukek), (3) where β,1 RLC>0, δ,Ileak C>0 and b,1 R0C>0. Ts must be less or equal to the smaller 1 fclk . The approximate time-discretization (3) is performed by using the forward Euler method, by assuming that the sampling time is small enough to the system evolution. A proposed controller for this system is based on a linear controller [15]: uk= satN 1{uk−1+ round (K1∆ek+K2ek−1)}.(4) Control (4) presents a simple enough structure such that it requires a small space in the silicon. The saturation function is due to the control signal constraint mentioned before. The control objective is to achieve a set-point reference signal. An approximate control structure for the Vdd-Hopping circuit that manages the current peaks is patent pending under the name of ENergy-AwaRe Control (ENARC) [16]. III. Problem statement Here, the problem statement is formulated rewriting the closed-loop system of (3) in a state-space form considering delays, uncertain parameters and current peak reduction. Figure 2 shows the Vdd-Hopping circuit including delays. The system has a h2-sample-period delay at the control block input and a h1-sample-period delay at the control block output, as mentioned before. CONTROL Vdd-HOPPING vrekukvck + -R0 LOAD RL, C K1K2 z−h2z−h1+ Fig. 2: Block diagram of the circuit control system. The open-loop system is ek+1 = (1 −Tsβ)ek+Tsb(vr−Vh)uk−h1+Ts(βvr+δ) −bTsuk−h1ek,(5) and the considered Control (4) is uk−h1= satN 1{uk−1−h1+ round(Kxk−h)},(6) where h,h1+h2,xk−h= [ek−hek−1−h]Tand K= [¯ K1¯ K2], where ¯ K1,K1and ¯ K2,K2−K1. For simplicity, the control variable ukis considered a real number. Thus, uk−h1= satN 1{uk−1−h1+Kxk−h} = satN 1{uk−1−h1+ ∆uk−h1},(7) A rigorous analysis should take uk∈Z. Note that if ∆uk−h1is bounded above, then, from Eq. (1), the maximum current peaks (∆uk−h1=R0 Vh−vc∆Ilmax , [17]) are limited. For this purpose, the quadratic cost functions Jk= ∞ X k=0 (xT kQxk+ ∆uT k−h1R∆uk−h1) (8) must be minimized. Note that the positiveness of the matrices Qand Rimplies that Jkis strictly positive. On the other hand, the parameters RL,R0and C that define β,band δcan be considered uncertain. Each uncertain parameter is within an uncertainty interval, whose corresponding extremes are •C∈[Cm, CM] , •RL∈[Rm L, RM L] , •R0∈[Rm 0, RM 0]. Remark 1: The asymptotic stability of system (5) is guaranteed in a point within an uncertainty interval for the low level voltage, Il, and within an uncertainty interval for the high level voltage, Ih, bounded by Il,Rm L(uklVh−RM 0Ileak) uklRm L+RM 0 ,Rm L(uklVh−Rm 0Ileak) uklRm L+Rm 0(9) Ih,RM L(ukhVh−RM 0Ileak) ukhRM L+RM 0 ,RM L(ukhVh−Rm 0Ileak) ukhRM L+Rm 0.(10) ukland ukhare the lower-bound and the upper-bound of uk, respectively. Consequently, the main objective is to design the optimal gain Kin such a way that Control (6) is robust with respect to delays as well as parameter uncertainties. Likewise, this optimal gain Kmust guarantee asymptotic stability and minimum current peaks for the known constant delays, h1and h2. A. Alternative representation for the saturated control (7) and the error equation (5) Firstly, some lemmas are given to rewrite the saturated control (7) and an alternative form. Define χk−h,uk−1−h1 xk−h. Note, from Eq.(5), uk−1−h1 directly depends on xk= [ek, ek−1]T. Lemma 1: [18], let K, G ∈R1×2be given. For all, χk−h∈R3×1, if χk−h∈ {χk−h∈R1×3: [1 G]χk−h∈ [1 N]}, then satN 1{[1 G]χk−h} ∈ Co{[1 K]χk−h,[1 G]χk−h}.  Lemma 2: Assume that there exists G∈R1×2,c > 0 and Ψ ,diag{ρ, P1}, where P1†>0∈R2,ρ > 0∈R1 such that for any χk−h∈X, where X=χk−h:χT k−hΨχk−h≤c−1,(11) then, 1 < uk−1−h1+Gxk−h< N, and Control (7) admits the following representation uk−h1= [αk(uk−1−h1+Kxk−h) +(1 −αk)(uk−1−h1+Gxk−h)] = [uk−1−h1+αkKxk−h+ (1 −αk)Gxk−h)] = [uk−1−h1+ ¯uk−h], where ¯uk−h,(αkK+ (1 −αk)G)xk−hwith αk∈[0,1], for all k > 0.  Then, Eq. (5) can be rewritten ek+1 = (1 −Tsβ)ek+Tsb(vr−Vh)(uk−1−h1+ ¯uk−h) +Ts(βvr+δ)−bTsuk−h1ek.(12) B. State-space representation The saturated control law and error equation, as redefined before, allow to system (5) rewrite it in a state-space form. From Eq. (5) , uk−h1=ek+1 −(1 −Tsβ)ek−Ts(βvr+δ) + bTsuk−h1ek Tsb(vr−Vh), and, therefore uk−1−h1=ek−(1 −Tsβ)ek−1−Ts(βvr+δ) Tsb(vr−Vh) +bTsuk−1−h1ek−1 Tsb(vr−Vh), which substituted in Eq. (12) gives ek+1 = (2 −Tsβ)ek−(1 −Tsβ)ek−1+Tsb(vr−Vh)¯uk−h −Tsb(uk−h1ek−uk−1−h1ek−1).(13) From Lemma 1 and 2, Eq. (13) can be rewritten in the following matrix form: xk+1 =A(uk−h1, uk−1−h1)xk+B¯uk−h,(14) where A,2−Tsβ−Tsbuk−h1Tsβ−1 + Tsbuk−1−h1 1 0 , B,Tsb(vr−Vh) 0. uk−h1and uk−1−h1of matrix Aare treated as uncertain parameters in Section IV-D. Their values will be inside the uncertainty interval [1, N]. †P1is a positive matrix defined to guarantee system stability. C. Stability and optimization problem Equation (14) can be rewritten in the following explicit closed-loop form. xk+1 =Axk+B(αkK+ (1 −αk)G)xk−h,(15) xl=φl,∀l∈[−h, 0] (16) zk=I2xk,(17) with C∈[Cm, CM] , RL∈[Rm L, RM L] , R0∈[Rm 0, RM 0], uk−h1, uk−1−h1∈[1, N] (18) αk∈[0,1],(19) and where xk, zk∈R2are the state vector and controlled output, respectively. φlis the initial condition and h≥0∈ Ris a fixed and known delay. Problem 1: The problem is to find a X(ρ, P1, c), some robust vectors Gand K, such that a) Lemma 2 holds and, hence, the closed-loop system (14) and b) there exists a Lyapunov-Krasovskii functional Vk> 0, a cost function Jk>0 such that Vk+1 −Vk+Jk along the solution of (15) fulfills Vk+1 −Vk+Jk<0.(20)  The solution to this problem minimizes a performance index that, among other considerations, limites high current peaks. Moreover, this solution guarantees the system stability for the time-delay system (15)–(17). IV. Optimal robust saturated control design A mathematical manipulation of Eq. (15) is performed via a descriptor model transformation [19]. The descriptor approach is just a variable change, which makes easier to work with Lyapunov-Krasovskii functional [20]. A. Descriptor model transformation Equation (15) is manipulated in order to achieve the previous objectives. A descriptor model transformation is applied. Define yk,xk+1 −xk, ψk,Pk−1 i=k−hyi.Next, rewrite Eq. (15) in the descriptor form [19]: xk+1 0=yk+xk −yk+Axk−xk+B(αkK+ (1 −αk)G)xk−h From xk−h=xk−ψk, this system can be compactly written as: E¯xk+1 =¯ A¯xk−0 B(αkK+ (1 −αk)G)ψk,(21) where ¯ A,I2I2 A+B(αkK+ (1 −αk)G)−I2−I2, E,diag{I2,02},¯xk,xk yk. B. Condition for state-space representation Condition a) of Problem 1 is satisfied, if 1< uk−1−h1+Gxk−h< N, ∀χk−h∈X(22) given in (11) is guaranteed. Subtracting N+1 2in inequality (22) and from [21], it is seen that, it is necessary satisfy 2N−2> N(1 + cxT k−hP1xk−h+cuT k−1−hρuk−1−h)−2 >4uk−1−h+ 4Gxk−h−2(N+ 1) (23) From Lemma 2, relationships (23) correspond to   1 ±uk−1−h1 ±xT k−h   T  3N−2−2G −2cNρ 0 −2GT0cNP1    1 ±uk−1−h1 ±xk−h  >0 (24) This inequality is satisfied if Λ,  c−2−2Y −2ρ3N20 −2YT0 3N2¯ P1  >0 (25) Note that this LMI is equivalent to (24) by means of employing the Schur’s complement, defining Y,GQ1 with Q1∈R2which is Hermitian, applying ¯ P1=Q1P1Q1 and preand post-multiplying by diag{1,1, Q1}. C. Stabilization and optimization For simplicity, assume here a nominal value of: αk,uk−h1 and uk−1−h1. In next subsection (18)–(19) will be considered as uncertain inside a convex polytope. Condition b) of Problem 1 can be formulated in terms of Linear Matrix Inequalties (LMIs) [10]. Fulfillment of condition (20) is looked for. Define P,P1P2 P20, being P2Hermitian. Consider as Lyapunov-Krasovskii candidate Vk=V1,k +V2,k +V3,k,(26) being V1,k = ¯xT kEPE¯xk, P1>0 (27) V2,k = h X n=1 k−1 X i=k−n yT iRyi, R > 0 (28) V3,k = k−1 X i=k−h xT iSxi, S > 0,(29) where V1,k guarantees asymptotic stability of system (21) without delays. Delay-dependent as well as delayindependent criteria are considered in V2,k and V3,k, respectively [10], [11]. Next, a sufficient condition for asymptotic stability and minimization of a performance index that, among other considerations, limites high current peaks, is derived. Theorem 1: Consider system (15)–(17) with nominal value of: αk,uk−h1and uk−1−h1.h > 0∈Nis a known constant delay and K, G ∈R1×2. If there exist Q,R, S, R, P1>0∈R2and c, µ > 0 such that minKµ P1>0 (30) Γ<0 (31)     −µI202I202 ∗ −µI202I2 ∗ ∗ −P1−S S ∗ ∗ ∗ −hR −S     <0,(32) Λ>0 (33) where Γ is defined in Eq. (34), found at the top of next page, then the equilibrium of the closed-loop system (15)– (17) is asymptotically stable and the current peaks are limited. Proof: The goal is to satisfy Vk+1 −Vk+Jk<0 for system (21). Lyapunov-Krasovskii method yields: V1,k+1 −V1,k = ¯xT k+1EP E ¯xk+1 −¯xT kEP E¯xk =n¯xT k¯ AT−ψT k[0 αkKTBT+ (1 −αk)GTBT]o P¯ A¯xk−0 αkBK + (1 −αk)BGψk−¯xT kEP E¯xk = ¯xT k[¯ ATP¯ A−P1]¯xk−¯xT k¯ AP 0 αkBK + (1 −αk)BGψk −ψT k[0 αkKTBT+ (1 −αk)GTBT]P¯ A¯xk. From (28) and Jensen Inequality [22]: V2,k+1 −V2,k =hyT kRyk− h X n=1 yT k−nRyk−n ≤¯xT k0 0 0hR¯xk−1 hψT kRψk Finally, V3,k+1 −V3,k =xT kSxk−xT k−hSxk−h =xT kSψk+ψT kSxk−ψT kSψk These developed expressions and Eq. (8) are applied to inequality (20), in such a way that the LMIs (31) are obtained. On the other side, summing (20) from n= 0 to ∞, it is obtained ∞ X k=0 (Vk+1 −Vk+Jk) = V∞−V0+ ∞ X k=0 Jk=−V0+ ∞ X k=0 Jk<0. Thus, P∞ k=0 Jk< V0<[¯x0ψ0]M[¯x0ψ0]T, where M, P1+S−S −S hR +S. To minimize the trace of Mmeans to minimize any µ > 0, such that, M< µI4, [23]. From this inequality and applying the Schur’s complement LMI (32) is obtained. D. Control design Now, consider uncertain parameters given in Section III and (18)–(19). For this purpose, Theorem 1 is extended in the case of polytopic uncertainties. Denote Ω,[A BK αkuk−h1uk−1−h1] and assume that Ω ∈ Co{Ωj, j = 1, ..., 64}, namely Ω = n X j=1 λjΩj,for all,0≤λj≤1, n X j=1 λj= 1 and being the vertices of the polytope described by Ωj= [A(j)B(j)K α(j) ku(j) k−h1u(j) k−1−h1] for j= 1,2, ..., 64. Preand post-multiplying LMI (31) by Q= diag{Q1, Q1, Q1}and apply the Schur’ complement. Preand post-multiplying LMI (32) by Q= diag{I2, I2, Q1, Q1}and taking Q1=P−1 2>0 and ¯ P1=Q1P1Q1,¯ R=Q1RQ1,¯ S=Q1SQ1, the following sufficient condition is achieved. Theorem 2: Consider system (15)–(17) with h≥0∈N is a known constant delay and K, G ∈R1×2. If there exist T, Y ∈R2×1and Q1∈R2with K=T Q−1 1,G=Y Q−1 1, Q,R,¯ R, ¯ P1,¯ S > 0∈R2for j= 1, ..., 64 and c, µ > 0 such that minKµ ¯ P1>0 (35) ¯ Γ(j)<0j= 1, ...., 64,(36)     −µI202I202 ∗ −µI202I2 ∗ ∗ −Q1−¯ S¯ S ∗ ∗ ∗ −h¯ R−¯ S     <0,(37) Λ>0 (38) being ¯ Γ(j)defined in (39), found at the top of next page, are satisfied. Then, in the vertices j, the equilibrium is asymptotically stable as well as the current peaks are limited in the entire polytope. Proof: This is an extension of Theorem 1 for polytopic uncertainties with some mathematical manipulations. Therefore, this theorem proof follows Theorem 1 proof. Remark 2: This robust control tuning method is conservative due to the definition of the matrix P, as well as, the attraction domain, X. Corollary 1: Gain K, obtained from Tand Q1in Theorem 2, fulfills Theorem 1 and consequently guarantees both robust stability and minimization of the current peaks for a fixed delay. As future work an optimization of the ellipsoid Xwill be interesting to perform. V. Robust control result In this section, the robust control gains for Control (7) are computed by employing the approach above. The VddHopping circuit parameters given in [8] and the load model parameter given in [14] are reported. Therefore, N= 24 is taken as the total number of PMOS transistors. The voltage supply is Vh= 1.2V. The reference signal, vr, is a step between the low voltage level Vcl= 0.8V−ǫhand the high voltage level Vch= 1.2−ǫh, being ǫh= 0.06Vand Γ,  ¯ ATP¯ A−EPE + diag{Q + Ξ, hR} − ¯ ATP0 B(αkK+ (1 −αk)G)+S−Ξ 0 ∗ − 1 hR−S+ Ξ  (34) Ξ = (αkK+ (1 −αk)G)R(αkKT+ (1 −αk)GT) ¯ Γ(j),         ¯ Γ(j) 1¯ Γ(j) 2−α(j) kB(j)T−(1 −α(j) k)B(j)Y+¯ S Q1Q¯ ΞR0 ∗¯ P1−2Q1+h¯ R0 0 0 0 ∗ ∗ − ¯ R h−¯ S0 0 ¯ ΞR ∗ ∗ ∗ −Q 0 0 ∗ ∗ ∗ ∗ −R R ∗ ∗ ∗ ∗ ∗ −R         , j = 1, ..., 64 (39) where ¯ Ξ(j),(α(j) kT+ (1 −α(j) k)Y) ¯ Γ(j) 1,Q1A(j)T+A(j)Q1−2Q1+α(j) kTTB(j)T+ (1 −α(j) k)YTB(j)T+α(j) kB(j)T+ (1 −α(j) k)B(j)Y ¯ Γ(j) 2,¯ P1+Q1A(j)T−2Q1+α(j) kTTB(j)T+ (1 −α(j) k)YTB(j)T, ǫl= 0.01 (Vcl≈Vl). These parameters comes from the equilibrium of Eq. (3). The system resistances are RL= 27.7Ω and R0= 31.41Ω, the capacitance is C= 9nF, while Ileak = 1.67 ·10−3. The clock frequency is taken fclk = 200MHz and Ts= 1.67ns. This introduces an onesample-period delay (h1= 1) in the control block output due to a power-performance trade-off. Likewise h2= 2, thus h= 3. The uncertain parameters take the following ranges: •transistor characteristic, R0, from 25Ω to 38Ω, •load dynamic resistance, RL, from 55.53Ω to 72.46Ω, •load capacitance, C, from 1pF to 1nF. And, Q= diag{10,10},R= diag{1000,1000}. Then, optimization problem is resolved, obtaining K1=−0.49, K2= 0.72. This was obtained for c= 1.1′,µ= 4.6·1010,G= −0.15 0.82and P1=0.0001 0.0002 0.0002 2.8574·106. Note that even if the control constant tuning is conservative, there is a feasible solution. VI. Simulation Results. Some simulations show the robustness of the optimal saturated control law proposed for the Vdd-Hopping circuit. Likewise, a comparison between the performance achieved with the control gains obtained in this paper with respect to another control gains obtained in [15] is performed. These simulations are done by using the parameter values given in Section above. A. Uncertain PMOS resistance In this kind of systems, the electrical characteristic of the PMOS can suffer changes due to temperature changes. In Fig. 3 the simulation is performed increasing the value of the PMOS resistance by 20%. The system in the low voltage level converges to 0.78V, which is inside the interval given by (9), Il= [0.74V, 0.86V]. Likewise, the high voltage level converges to 1.133V, which is inside the interval given by (10), Ih= [1.132V, 1.155V]. These tests show that the equilibrium is robust with respect to parameter uncertainties and delays. And, the current peaks are small. 0 0.2 0.4 0.6 0.8 1 x 10−6 0 10 20 a) NTrans t(s) 0 0.2 0.4 0.6 0.8 1 x 10−6 0.8 1 1.2 b) V(V) t(s) 0 0.2 0.4 0.6 0.8 1 x 10−6 0 0.05 d) I(A) t(s) Fig. 3: R0= 31.41Ω →R0= 37.7Ω, K1=−0.47, K2= 0.68. Evolution of the: a) number of transistors switched on, b) vr(dashed) and vc(solid), c) current Il. B. Uncertain load parameter Another example shows that system performance is sensitive to the values of K1and K2. The capacitance employed during the control design and the previous simulations has been C= 1nF. In the following, it is desired to validate the system robustness when C= 1pF, i.e., 1000 times smaller. The lack of knowledge of the load in the real applications of these systems may imply this change of three order of magnitude. Some simulations are shown using the robust control gains computed in this paper (Fig. 4) and the control gains computed in [15] (Fig. 5), which are K1=−19.3 and K2= 39.27. These gains were computed linearizing the closed-loop system around the set point. K= [ ¯ K1,¯ K2] are defined by ensuring that A+BK is Hurwitz and placing the poles by trial and error, in such a way, that the nonlinear system presents a suited behaviour. Note that, in Fig 5, the system does not respond to voltage variation. However, in Fig. 4 the system performance is satisfactory. This example shows the great robustness of the system when the robust control tuning is employed. 0 0.2 0.4 0.6 0.8 1 x 10−6 0 10 20 a) NTrans t(s) 0 0.2 0.4 0.6 0.8 1 x 10−6 0.8 1 1.2 b) V(V) t(s) 0 0.2 0.4 0.6 0.8 1 x 10−6 0 0.05 d) I(A) t(s) Fig. 4: C= 1nF →C= 1pF and K1=−0.47, K2= 0.68. Evolution of the: a) number of transistors switched on, b) vr(dashed) and vc(solid), c) current Il. 0 0.2 0.4 0.6 0.8 1 x 10−6 0 10 20 a) NTrans t(s) 0 0.2 0.4 0.6 0.8 1 x 10−6 0.8 1 1.2 b) V(V) t(s) 0 0.2 0.4 0.6 0.8 1 x 10−6 0 0.02 d) I(A) t(s) Fig. 5: C= 1nF →C= 1pF and K1=−19.3, K2= 39.27. Evolution of the: a) number of transistors switched on, b) vr(dashed) and vc(solid), c) current Il. VII. Comparison with the ‘intuitive’ controller of [8] A comparison is performed between the controller presented here and the ‘intuitive’ controller proposed in [8]: uk= satN 1{uk−1+sign(ek)}.(40) A. Voltage and current performance Control (40) switches on or off one transistor according to the sign of the error voltage signal. Therefore, this controller has the limitation that one only transistor can be switched on or off at every sampling time. On the other side, vrfollows a linear time evolution between Vl= 0.8V and Vch= 1.12Vwith a slope specified in [8] equal to 1.015106V/s. A simulation of this controller is performed by using the parameter values given in Section VI. This simulation is shown in Fig. 6,. Note that, the performance presents an oscillatory behavior, with important current peaks. In addition, transient periods are slower and occurs significant current peaks in comparison with Control (4). 0 0.2 0.4 0.6 0.8 1 x 10−6 0 10 20 a) NTrans t(s) 0 0.2 0.4 0.6 0.8 1 x 10−6 0.8 1 1.2 b) V(V) t(s) 0 0.2 0.4 0.6 0.8 1 x 10−6 0 0.05 c) I(A) t(s) Fig. 6: ‘Intuitive’ control. Evolution of: a) number of PMOS transistors switched on, b) vr(dashed) and vc (solid), c) current. Il. B. Energy evaluation In the set of PMOS, the dissipated energy in the transient period depends on the kind of control law employed, i.e., on the switching sequence. The purpose here is to evaluate the energy cost associated with the set of PMOS transistors during the rising transient period using Control (4) and the ‘intuitive’ controller proposed in [8] (assume that the falling transient period is similar). An estimation of the PMOS transistors during the transient period is Ed=Ztf t0 (Vh−vc)Ildt, where t0is the initial time and tfis the final time in such transient period. Figure 7 shows the dissipated energy during the rising transient period. Note that the energy consumption is much higher using the controller proposed in [8] than using Control (4). More precisely, this energy consumption has been reduced from 7.2µJ to 0.34µJ, i.e., 95% reduction. Notice that a nonsmooth behavior of the current transient and a larger transient period may result in a higher energy consumption. 0.5 1 1.5 2 2.5 3 3.5 x 10−7 0 1 2 3 4 5 6 7 x 10−6 Energy (J) t(s) Intuitive control Control (4) Fig. 7: Energy dissipated during the rising transient period. VIII. Conclusions In this paper an optimal and robust saturated controller was designed for the time-delay Vdd-hopping circuit. This optimal controller minimizes a performance index that, among other considerations, limites high current peaks. As side effect, this controller improves the dissipated energy and it achieves fast transient periods. The system is rewritten in a suited state-space representation, such that, an optimal and robust problem can be formulated to tune the control gains. This problem is dealt with Lyapunov Krasovskii theory, which provides some stability conditions through Linear Matrix Inequalities (LMIs). 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