VLSI design of universal approximator neuro-fuzzy systems

VLSI DESIGN OF UNIVERSAL APPROXIMATOR NEURO-FUZZY SYSTEMS I. Ba u one, S. Sánchez Solano, A. Ba iga, C. J. Jiménez, R. Senhadji-Na a o, D. R. López. Ins i u o de Mic oelec ónica de Se illa - Cen o Nacional de Mic oelec ónica A da. Reina Me cedes s/n, (Edi . CICA), E-41012, Se illa, Spain XVI Con e ence on Design o Ci cui s and In eg a ed Sys ems (DCIS2001), pp. 358-363, Opo o, No . 2001. This ma e ial is p esen ed o ensu e imely dissemina ion o schola ly and echnical wo k. Copy igh and all igh s he ein a e e ained by au ho s o by o he copy igh holde s. All pe sons copying his in o ma ion a e expec ed o adhe e o he e ms and cons ain s in oked by each au ho ’s copy igh . In mos cases, hese wo ks may no be epos ed wi hou he explici pe - mission o he copy igh holde . Abs ac Neu o- uzzy sys ems can heo e ically sol e any p oblem since hey a e uni e sal app oxima o s. Be- sides, hey combine he ad an ages o he neu o and uzzy pa adigms. This pape desc ibes and compa es he di e en s a egies ha can be adop ed o imple- men he lea ning and in e ence mechanisms in ol ed in a neu o- uzzy sys em. CAD ools, mos o hem in- eg a ed in o he uzzy sys em de elopmen en i on- men X uzzy 2.0 [1], ha e been de eloped o assis he designe in he implemen a ion o neu o- uzzy sys ems in FPGAs o ASICs. 1. In oduc ion Neu o- uzzy sys ems a e d awing ecen ly a g ea in e es in many applica ions because hey combine he ad an ages o he neu o and uzzy pa adigms: he au oma ic knowledge acquisi ion capabili y o neu al ne wo ks and he human-like knowledge ep esen a- ion and easoning capabili y o uzzy sys ems. Be- sides, neu o- uzzy sys ems a e uni e sal app oxima- o s and, since he p ocessing in ol ed is nume ical, hey can be implemen ed by mic oelec onic ci cui s. The design o an in eg a ed ci cui o implemen a neu o- uzzy sys em has o conside he equi emen s imposed no only by he uzzy in e ence p ocess bu also by he lea ning p ocess. This pape ocuses on discussing and compa ing di e en mic oelec onic s a egies o implemen ing uni e sal app oxima o neu o- uzzy sys ems, poin - ing ou he ad an ages o using CAD ools. Sec ion II desc ibes he app oxima ion capabili y o neu o- uzzy sys ems. Sec ion III discusses he wo basic VLSI s a egies o implemen ing he uzzy in e ence p ocess while Sec ion IV desc ibes he h ee s a e- gies o implemen ing he neu al lea ning p ocess. 2. Neu o-Fuzzy Sys ems as App oxima o s Among he uzzy logic-based in e ence me hods, he single on o ze o-o de Takagi-Sugeno me hod is he mos sui able o ha dwa e implemen a ion. In his me hod, he consequen s o he uzzy IF-THEN ules a e ep esen ed by single on alues, ci, and he ou pu p o ided is gi en by: (1) whe e hiis he ac i a ion deg ee o he i- h ule and R is he numbe o ules. This beha io is equi alen o ha o a neu al ne - wo k based on adial basis unc ions [2]. F om his equi alence, i is appa en ha he lea ning me hods employed o une adial basis unc ion ne wo ks can be applied o une single on uzzy sys ems. We will name hese so- uned single on uzzy sys ems as sin- gle on neu o- uzzy sys ems. Le us conside a single on neu o- uzzy sys em whose inpu uni e ses o discou se a e pa i ioned in o L linguis ic labels. I αis he maximum o e lap- ping deg ee, L+1-αin e als can be dis inguished pe inpu . They a e sepa a ed by he poin s {ai1,a i2, ..., aiN}, whe e N is L-α. Gi en an inpu ec o xo=(x1o, ..., xuo), he ou pu p o ided by he neu o- uzzy sys- em depends only on αu ac i e ules: (2) whe e hpk is he ac i a ion deg ee o one o he αu ac i e ules and cpk is i s co esponding consequen unc ion. yhici ⋅ i1= R ∑hi i1= R ∑ ⁄= yx o () hpk x()cpk x()⋅ k1= αu ∑ hpk x() k1= αu ∑ ------------------------------------------------ xx o = ypx() xx o = == VLSI design o uni e sal app oxima o neu o- uzzy sys ems I. Ba u one, S. Sánchez Solano, A. Ba iga, C. J. Jiménez, R. Senhadji-Na a o, D. R. López. Ins i u o de Mic oelec ónica de Se illa, I.M.S.E.-C.N.M. A da. Reina Me cedes s/n. Edi icio CICA. 41012-Se illa. Phone: 95 505 66 66 FAX: 95 505 66 86 E-mail: [email p o ec ed] This wo k has been pa ially suppo ed by he Spanish CICYT P ojec TIC98-0869 and he FEDER P ojec 1FD97-0956-C3-02. The pa ame e s ha de ine he piece yp(x) a e a ew o he global pa ame e s ha de ine he global ou pu , y(x). In his sense, a neu o- uzzy sys em is iewed as a local piecewise in e pola o . The in e po- la ion p o ided can be piecewise cons an , piecewise linea , piecewise quad a ic, o piecewise nonlinea , in gene al, depending on whe he ypis cons an , linea , quad a ic, o nonlinea in x. In pa icula , neu o- uzzy sys ems ha co e hei inpu uni e ses o discou se wi h no malized iangula membe ship unc ions (which a e B-splines o deg ee 1), as shown in Figu e 1, and ha employ he no malized p oduc o he mee -like ope a o as an eceden connec i e, a e piecewise mul ilinea in e pola o s [3]-[4]. Those neu o- uzzy sys ems which employ B-splines o de- g ee 2 and he p oduc o he mee -like ope a o as an- eceden connec i e a e piecewise mul iquad a ic in- e pola o s. In gene al, he use o nonlinea membe - ship unc ions o he minimum as connec i e lead o piecewise nonlinea in e pola o s. In any case, neu o- uzzy sys ems can app oxima e any inpu -ou pu su - ace and ha is why hey can be called uni e sal ap- p oxima o s [3]-[4]. 3. VLSI s a egies o he in e ence mechanism The e a e basically wo VLSI s a egies o imple- men ing he uzzy logic-based in e ence o a neu o- uzzy sys em. One o hem, which will be called memo y-based app oach, is o implemen di ec ly each piece ypo he in e pola ion. This app oach has been employed in digi al ealiza ions wi h DSPs [4] and analog ASICs [5]. P og ammable pa ame e s o his app oach can be he poin s aij ha allow iden i y- ing he ac i e g id cell, and he cons an s ha de ine he piece ypin ha g id cell. The o he s a egy is o implemen he di e en s ages o he uzzy in e ence mechanism. These s ages a e: calcula ion o he mem- be ship deg ees, µj(xi), (by membe ship unc ion ci - cui s, MFCs), calcula ion o he ac i a ion deg ees o he ules, hpk(x), (by connec i e ci cui s), and compu- a ion o a weigh ed a e age. This app oach will be called MFC-based app oach because i s main di e - ence wi h he p e ious one is ha membe ship de- g ees a e calcula ed explici ly. This app oach has been ollowed by many analog, digi al and mixed-sig- nal uzzy ASICs [6]. The p og ammable pa ame e s can be again he poin s aij (which sepa a e he Li+1-α in e als) and he pa ame e s o he consequen unc- ions cpk. Uni e sal app oxima o uzzy chips can be ob ained by bo h app oaches. They can be adjus ed o a pa icula applica ion by an adequa e lea ning mechanism. These wo app oaches o implemen ing piecewise in e pola o sys ems a e illus a ed in he ollowing. 3.1. Memo y-based app oach The mos di ec s a egy o app oxima e a gi en su ace is o implemen a look-up able ha con ains all he ou pu alues co esponding o e e y possible combina ion o he inpu signals. I he e a e uinpu s, x=(x1, ..., xu), coded by Nbi s, a look-up able di ides he inpu space in o 2N•ucells and associa es o each cell a cons an ou pu alue. Hence, look-up ables implemen piecewise cons an in e pola o s. The mic oelec onic ci cui s sui able o ca y ou his s a egy a e s anda d digi al memo ies and p o- g ammable logic de ices (PLDs). One ad an age o his ealiza ion is ha he esponse ime is e y sho because he only ope a ion (apa om he possible da a con e sions) is o e ie e da a om a memo y and his can be pe o med in a ew nanoseconds. As a d awback, look-up able implemen a ions a e p ac i- cal only when he numbe o inpu s and hei quan i- za ion deg ees a e low, o he wise he o al numbe o bi s o s o e is e y la ge. The uzzy sys em de elopmen en i onmen X uzzy [1] has a ool named x l which au oma ically di ec s he syn hesis ools o Synopsys and Xilinx o ob ain an implemen a ion o a piecewise cons an in- e pola o on an FPGA. The inpu o x l is he de- sc ip ion o he in e pola o sys em in he high-le el speci ica ion language o X uzzy: XFL ( his desc ip- ion can be pe o med ia g aphical use in e aces). The ou pu o x l consis s o wo iles. The i s ile con ains a o mal desc ip ion o he look-up able in PLA o ma . This able can be minimized by any ool able o accep he PLA o ma and implemen ed ei he by a combina ional ci cui o by a memo y. The sec- ond o he ou pu iles o x l is in ended o con ol he Synopsys logical syn hesis ools o minimizing he look-up able and ex ac ing he Boolean equa ions in o de o implemen he able using he combina ional esou ces o a Xilinx FPGA. The g aphical use in e - ace o x l is shown in Figu e 2. Ano he way o app oxima e a gi en su ace is o di ide he inpu space in o 2N•ucells and associa e o each cell a mul ilinea unc ion, y= yp(x). Compa ed wi h look-up ables, piecewise mul ilinea in e po- la o s need less inpu space esolu ion. In he case o wo inpu s, hey p o ide he ollowing kind o pieces: Fig. 1:Co e ing o he inpu space wi h an o e lap- ping deg ee o 2. inpu space ai1 ai2 0 1 ai3 L1L2L3L4L5 (3) whe e a,b,c,d a e cons an s. The memo y-based implemen a ion o p og am- mable piecewise mul ilinea con olle s equi es o e ie e he p og ammable pa ame e s om a memo- y and o implemen mul iplica ion and addi ion ope - a ions. A pa allel ealiza ion o hese ope a ions o e s he sho es p ocessing ime bu he la ges ci cui y. Fo ins ance, he memo y ha con ains he p og am- mable pa ame e s (a, ..., d, in Equa ion (4)) mus ha e 2uou pu buses. In he case o analog cu en -mode ci cui y, he addi ions can be pe o med by simply connec ing wi es; and he ollowing blocks a e e- qui ed: D/A con e e s (like p og ammable cu en mi o s), o con e and o scale he cons an s; and mul iplie s. The block diag am o his ype o ealiza- ion o he case o wo inpu s is shown in Figu e 3. The ci cui y can be educed by pe o ming he ope a ions sequen ially. Fo ins ance, ope a ions can be pe o med in 2us eps by using 1 adde , 1 mul ipli- e , and a memo y wi h 1 ou pu bus, as shown in Fig- u e 4 o he case o wo inpu s. 3.2. MFC-based app oach Ins ead o implemen ing di ec ly he exp ession o each ou pu piece, he MFC-based app oach imple- men s he di e en s ages o a uzzy in e ence mech- anism: uzzi ica ion, calcula ion o he ac i a ion de- g ees o he ules and compu a ion o a weigh ed a - e age. Ci cui y can be simpli ied i ce ain cons ain s a e imposed. In his sense, he membe - ship unc ions ha co e each inpu uni e se o dis- cou se usually o e lap each o he wi h a deg ee, α,o 2 o 3. This happens, o ins ance, when B-splines o deg ees 1 and 2 a e selec ed as membe ship unc ions. This means ha 2 o 3 MFCs pe inpu a e equi ed o gene a e he membe ship unc ions. Ano he con- s ain is ha he membe ship unc ions can be no - malized, ha is, hei sum is cons an (as shown in Figu e 1). In his case, α-1 MFCs pe inpu a e e- qui ed because he o he membe ship deg ee can be calcula ed wi h an addi ion. I no malized membe ship unc ions a e em- ployed and i he no malized p oduc o he mee -like ope a o is chosen as he connec i e ope a o , he de- nomina o o he weigh ed a e age is cons an , so ha no di ide is equi ed. I he membe ship unc ions do no o e lap, he ou pu alue is di ec ly he consequen unc ion and he e is any hing uzzy. In his case and i he conse- quen s a e cons an , he esul is a piecewise cons an in e pola o . I he o e lapping deg ee o membe ship unc- ions is 2, he inpu space is di ided in o (2M-1)ucells, whe e 2Mis he numbe o membe ship unc ions ha co e each inpu a iable. I he membe ship unc- ions a e linea (like hose in Figu e 1), he an eceden connec i e is he no malized p oduc o he mee -like ope a o , and he consequen s a e cons an , he esul - ing uzzy sys em is a piecewise mul ilinea in e po- la o . Fo ins ance, gi en wo inpu s, x1and x2, and using he no malized p oduc as an eceden connec- i e he ou pu piece is gi en by: (4) Fig. 2:G aphical use in e ace o x l. ypx1x2 ,()ax1x2bx2cx1d+++= Fig. 3:Memo y-based pa allel cu en -mode eal- iza ion o a piecewise mul ilinea con olle . cx1+d ax1+b 1 selec ion o he inpu cell pa ame e s in pa allel scaling ope a ion p oduc and sums A/D A/D D/A D/A D/A D/A x1 x2 y N N× Memo y o 22N • 22 c wo ds d b a (22N pieces) D/A Memo y o 22N • 22 wo ds d, c, b, a A/D x1 N A/D x2 MUX y coun e × + 1 Fig. 4:Memo y-based sequen ial ealiza ion o a piecewise mul ilinea in e pola o . selec ion o he inpu cell pa ame e s in se ies p oduc and sums (22N pieces) ypx1x2 ,()cRRµR1µR2 cRL µR1 µR1µR2 –()++= cLL 1µR1 –µ–R2 µR1µR2 +()cLR µR2 µR1µR2 –()+ whe e µRi and 1-µRi a e he wo non-ze o membe - ship deg ees o he inpu xi. I he minimum ope a o is chosen as he an eced- en connec i e, he denomina o o he weigh ed a e - age is no cons an , a di ide is equi ed, and a piece- wise nonlinea in e pola ion is pe o med. Simila o he memo y-based app oach, his MFC- based app oach equi es also mul iplica ions be ween wo a iables and o e ie e 2ucons an s om a memo y. An impo an di e ence is ha he numbe o wo ds o s o e is now 2M•u, while i is 2(L+1)•uin he memo y-based app oach, conside ing inpu space pa i ions o (2M-1)uand 2L•ucells, espec i ely. This means ha , o equal inpu space pa i ions, he mem- o y size in he MFC-based app oach is almos hal o he memo y size in he o he app oach. The eason is ha eachwo do hememo y in he MFC-based s a - egy is used by 2udi e en cells while in he o he ap- p oach i is used by only 1 cell. The cos o pay o his memo y educ ion is o include se e al mul iplexe s and, in his case, 1 MFC block pe inpu a iable. A pa allel cu en -mode ealiza ion ollowing his MFC-based s a egy is shown in Figu e 5 o he case o a piecewise bilinea in e pola ion. In a pa allel e- aliza ion, he memo y o 2M•uwo ds is di ided in o 2u pa s, each one con aining 2(M-1)u wo ds ha a e ne - e equi ed simul aneously. Mul iplexe s ha e o be added o selec which o he 2upa s p o ides each o he 2uwo ds equi ed [7]. The ci cui y can be e- duced by sequen ializing he ope a ions. Fo ins ance, ope a ions can be pe o med in 2us eps by using 1 ac- cumula o , 1 mul iplie , and a memo y wi h 1 ou pu bus [6]. The e a e h ee basic app oaches o implemen he MFCs. One app oach is o gene a e all he membe - ship unc ions o a a iable by means o a memo y. This is he mos e sa ile app oach because i allows di e en shapes o all he membe ship unc ions (bell-shaped, iangula , apezoidal, e c.). A second app oach is o gene a e he same shape o all he membe ship unc ions o an inpu a iable by means o a memo y (in his case, he i s ope a ion is o iden i y he inpu in e al o which he inpu belongs). The hi d app oach is o gene a e he same shape o all he membe ship unc ions o an inpu a iable by means o an a i hme ic block (again he inpu in e al o which he inpu belongs has o be iden i ied i s ly). Examples o a i hme ic MFCs a e cu en -mode ana- log MFCs o digi al MFCs ha gene a e iangula membe ship unc ions and ansconduc ance-mode analog MFCs, based on di e en ial pai s, ha gene - a e bell-shaped membe ship unc ions [6]. The en i onmen X uzzy has a ool named x hdl which s a s om he high-le el speci ica ion o he uzzy sys em and p oduces a VHDL desc ip ion. This ool is in ended o au oma ically syn hesizing piece- wise nonlinea in e pola o s (wi h a minimum ope a- o as an eceden connec i e) ha ollows a sequen ial a chi ec u e and ha implemen he MFCs wi h mem- o ies o wi h a i hme ic ci cui s. The code gene a ed by x hdl can be used o implemen ing he uzzy sys- em as an ASIC o as a Xilinx FPGA. The g aphical use in e ace o x hdl is shown in Figu e 6. 4. S a egies o he lea ning mechanism Typical neu al lea ning mechanisms a e supe - ised, ha is, hey employ a se o nume ical inpu alues and hei desi ed ou pu alues, and he objec- i e is o minimize he e o be ween he ac ual and he desi ed ou pu o he gi en inpu ec o s. A/D A/D D/A q x1 x2y ND/A D/A D/A × µR1 µR2 MFC MFC Fig. 5:MFC-based pa allel cu en -mode ealiza ion o a piecewise mul ilinea uzzy sys em wi h 4•22N ules. MUX MUX MUX MUX cRR cRL cLR cLL Memo y o 22N • 22 wo ds (22N • 4 pieces) Fig. 6:G aphical use in e ace o x hdl. 4.1. O -chip lea ning Two ac o s a e de e mina i e when selec ing an adequa e s a egy o implemen he lea ning mecha- nism. One ac o is he ype o applica ion owa ds which he neu o- uzzy sys em is add essed. S a ic ap- plica ions, like he modeling o s a ic sys ems, em- ploy uzzy sys ems whose knowledge base does no change wi h ime. Hence, he lea ning p ocess can be pe o med o chip and only he in e ence p ocess needs obein eg a edonsilicon.In hiscase,asecond ac o o be conside ed is he applica ion ange o he ci cui . I i is concei ed o be dedica ed o a speci ic applica ion, he lea ning p ocess can be pe o med p io o he ab ica ion o he chip and he lea n uzzy sys em can be in eg a ed in a non-p og ammable de- ice, which is he leas cos ly solu ion. I he ci cui is going o be applied o di e en asks, i should be p o- g ammable. In his case, he lea ning p ocess is ca - ied ou p io o he use o he chip and he lea n pa- ame e s a e downloaded o he chip be o e i s ope a- ion. A p ecise emula ion o he uzzy in e ence ha dwa e is e y impo an o he e ec i eness o he o -chip lea ning. Fo his pu pose, we ha e de el- oped a CAD ool named mcsim ha simula es a a be- ha io al le el he pe o mance o he uzzy in e ence ha dwa e. Gi en a desi ed inpu -ou pu mapping o ep oduce, his ools allows: (a) o compa e he ou pu p o ided by he di e en VLSI s a egies o he in- e ence mechanism depending on he inpu pa i ions, he esolu ion o he building blocks employed (mem- o ies and compu ing blocks), he ypes o MFCs and connec i e ope a o s (in he case o an MFC-based app oach), and (b) o ind he adequa e inpu pa i- ions and he adequa e alues o he pa ame e s ha de ine he ou pu pieces, aking in o accoun he eso- lu ion o he building blocks. As an example, Figu e 7 illus a es he esul s ob- ained wi h mcsim when o -chip adjus ing di e en designs o a uzzy in e ence chip o app oxima e he ollowing su ace (Figu e 7a): (5) The uzzy in e ence chips simula ed ollow an MFC-based app oach, implemen 3x5=15 ules, and employ consequen s wi h an 8-bi esolu ion. Figu e 7b shows he simula ed ou pu p o ided by a piece- wise linea digi al ealiza ion which employs he mee -like ope a o as connec i e and MFCs imple- men ed by memo ies wi h wo ds o 3 bi s. Figu e 7c illus a es he ou pu o an analog piecewise nonlinea ealiza ion which employs he p oduc as connec i e and ansconduc ance-mode MFCs wo king in s ong in e sion. In his example, i can be seen ha digi al compu ing blocks in oduce quan iza ion e o s ha usually domina e he app oxima ion e o . 4.2. On-chip lea ning The e is ano he ype o applica ions o which a dynamically changing knowledge base is needed. Examples o his ype o applica ions a e iden i ica- ion and modeling o non-linea dynamic sys ems, adap i e p edic ion o ime se ies, adap i e noise can- cella ion, adap i e con ol, e c. In hese cases, he neu o- uzzy sys ems employed a e called adap i e uzzy sys ems because hey adap hei knowledge base o ma ch he new si ua ion, hus eso ing o he use o he lea ning mechanism as hey a e ope a ing. Two app oaches can be used o hese applica ions. One o hem is o implemen he lea ning mechanism on chip oge he wi h he in e ence mechanism. This is he easible solu ion when equi emen s o low powe consump ion, embedded ope a ion (low a ea occupa ion), and eal- ime pe o mance apply no only o he in e ence engine bu also o he lea ning loop [6]. The ool mcsim also allows he use o emula e he beha io o a neu o- uzzy chip wi h on-chip lea n- ing mechanisms: weigh pe u ba ion o an eceden pa ame e s and g adien -descen o he single on al- ues o he consequen s. z 0.5 1 2πx()2πy()cossin+()= 0 0.5 10 0.5 1 0 0.5 1 (a) 0 0.5 10 0.5 1 0 0.5 1 (b) 0 0.5 10 0.5 1 0 0.5 1 (c) Fig. 7:Simula ed pe o mance o di e en VLSI neu o- uzzy sys ems app oxima ing he su ace shown in (a). RMSE: 10.5 % RMSE: 5.4 % 4.3. Chip-in- he-loop lea ning The hi d app oach o implemen he lea ning mechanism is known as chip-in- he-loop aining and can be applied i he chip is p og ammable. This app oach elies on a hos compu e which p o ides he inpu aining ec o s o he chip, compa es he desi ed ou pu ec o s wi h he ou pu gene a ed by he chip, and ep og am adequa ely he chip. Hence, he compu e mus be p o ided wi h a da a acquisi ion ca d, as shown in Figu e 8. A CAD ool named x lab allows he designe con- igu ing he da a acquisi ion ca d, de ining he inpu and ou pu signals, and moni o ing he uzzy in e - ence chip [6]. Figu e 9 shows he main window o he x lab g aphical use in e ace as well as he inpu /ou - pu con igu a ion window. 5. Conclusions Di e en s a egies o implemen ing he in e - ence and lea ning mechanisms o uni e sal app oxi- ma o neu o- uzzy sys ems ha e been desc ibed and compa ed. The VLSI s a egies o he in e ence mechanism di e in he ype o ha dwa e esou ces employed (mo e use o memo y agains compu ing blocks o ice e sa) and in he sys em pe o mance achie ed (mo e lexibili y agains simplici y o ice e sa). Piecewise cons an , linea , and non-linea be- ha io ha e been discussed, and analog, digi al, and mixed-signal ealiza ions ha e been illus a ed. The adequa e implemen a ion s a egy o he lea ning mechanism depends on he ype o applica ion. Fo o -chip o chip-in- he-loop lea ning s a egies, he lea ning mechanism is implemen ed by a hos compu- e . Di e en CAD ools (x l,x hdl, mcsim, and x lab), mos o hem cu en ly in eg a ed in o he X uzzy 2.0 de elopmen en i onmen , ha e been de- eloped o assis he designe in he ha dwa e imple- men a ion o neu o- uzzy sys ems as FPGAs o ASICs. Re e ences [1] D. R. López, C. J. Jiménez, I. Ba u one, A. Ba iga, S. Sanchez-Solano, “X uzzy: a design en i onmen o uzzy sys ems”, P oc. 7 h In . Con . on Fuzzy Sys ems, pp. 1060-1065, Ancho age, May 1998. [2] J.-S. R. Jang, C.-T. Sun, "Func ional equi alence be- ween adial basis unc ion ne wo ks and uzzy in e - ence sys ems", IEEE T ans. Neu al Ne wo ks, ol. 4 (1), pp. 156-159, 1993. [3] X.-J. Zeng, M. G. Singh, “App oxima ion accu acy analysis o uzzy sys ems as unc ion app oxima o s”, IEEE T ans. on Fuzzy Sys ems, ol. 4 (1), pp. 44-63, Feb. 1996. [4] Ro a i, R., Vi ua i, M., Linea and uzzy piecewise- linea signal p ocessing wi h an ex ended DSP a chi- ec u e, in P oc. IEEE In . Con e ence on Fuzzy Sys- ems, pp. 1082-1087, Ancho age, 1998. [5] Ma as, J., Ga cía de Vicuña, L., Cas illa, M., A syn he- sis o uzzy con ol su aces in CMOS echnologies, in P oc. IEEE In . Con e ence on Fuzzy Sys ems, ol. 2, pp. 641-647, Ba celona, 1997. [6] Ba u one, I., Ba iga, A., Sánchez-Solano, S., Jiménez- Fe nández, C. J., López, D. R., Mic oelec onic design o uzzy logic-based sys ems, CRC P ess, 2000. [7] Ba u one, I., Ba iga, A., Sánchez-Solano, S., Hue as, J. L., “Mixed-Signal Design o a Fully Pa allel Fuzzy P ocesso ”, Elec onics Le e s, ol. 34 (5), pp. 437- 438, Ma ch 1998. Fig. 8:Block diag am o chip-in- he-loop lea ning. moni o ing da a acquisi ion and lea ning boa d uzzy in e ence chip Fig. 9:G aphical use in e ace o x lab