Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology

O se -Compensa ed Compa a o wi h Full-Inpu Range in 150nm FDSOI CMOS-3D Technology M. Su´a ez and V.M. B ea Dep . o Elec onics and Compu e Science Uni e si y o San iago de Compos ela San iago de Compos ela E-15706, Spain Email: manuel.sua ez.cam[email p o ec ed] Ca los Dom´ınguez Ma as*, Rica do Ca mona** Gus a o Li˜n´an** and ´ Angel Rod ´ıguez-V´azquez** *AnaFocus **Ins i u o de Mic oelec ´onica de Se illa (IMSE-CNM) Se illa, Spain Abs ac —This pape add esses an o se -compensa ed com- pa a o wi h ull-inpu ange in he 150nm FDSOI CMOS- 3D echnology om MIT- Lincoln Labo a o y. The compa a o discussed he e makes pa o a ision sys em. I s a chi ec u e is ha o a sel -biased in e e wi h dynamic o se co ec ion. A simula ion le el, he compa a o can each a esolu ion o 0.1mV in an a ea o app oxima ely 220µm2wi h a ime esponse o less han 40ns and a s a ic powe dissipa ion o 1.125µW. I. INTRODUCTION Image s and Vision sys ems a e among he mos di icul challenges o mixed-signal design. The design o imaging sys ems (senso s + eadou + da a con e sion + con olle + d i e s) on CMOS chips has been making good p og ess du ing he las decade [1], [2], [3], [4]. The main design a ge o CMOS imaging chips is ep oducing images wi h gi en accu acy and speed. The a ge o a ision sys em is di e en . Simila o image s, hey ha e 2-D ligh in ensi y maps as inpu s. Howe e , hei ou pu s a e no images, bu eac ion commands. Vision applica ions equi e o comple e he ull “sense →p ocess →analyze →make decision” cycle. I in ol es la ge amoun o da a, especially in applica ions whe e high- esolu ion o high ame- a e a e essen ial. Making a eal- ime decision, e.g. o con olling an au onomous mo ing de ice, also equi es low la ency om he sys em, which makes he analysis o he la ge inpu da a se e en mo e demanding. The indus ial s a e-o - he-a conside s ision sys ems as seeing compu e s o compu e s ha see. This is e lec ed on he a chi ec u e ypically used o hem, namely: an image (image senso ) o acqui e and digi ize he senso y da a and a hos p ocesso o handle his huge amoun o aw da a. Such b u e- o ce app oach does comple ely igno e he speci ics o he da a, he ways how in e es ing pieces o in o ma ion eme ge om he da a, and hence esul s in highly ine icien sys ems. No only con en ional compu e a chi ec u es a e inadequa e. Con en ional algo i hmic solu ions used in hese a chi ec u es a e also inadequa e. This ac has been highligh ed in a e y ecen pape published in Vision Sys em Design [5]. I s a es ha b u e o ce pa e n ma ching, he con en ional app oach adop ed by many sys em de elope s, is no he igh ool in many applica ions. Ins ead, a majo i y o sma came a applica ions can be sol ed using only a small numbe o image p ocessing algo i hms ha can be lea ned quickly and used e y e ec i ely. Du ing he las ew yea s au ho s ha e wo ked on mapping hese simple algo i hms ( h esholds, blob analysis, edge de ec ion, a e age in ensi y, bina y ope a o s, ) on o dedica ed compu e ha dwa e a chi ec u es composed o simple p ocesso s wi h mos ly local in e ac ions. Di e en sys em-on-chip solu ions ha e been de ised and ealized on con en ional single-wa e CMOS echnologies [6], [7], [8]. These chips consis o 2-D a ays o mul i- unc ional pixels which pe o m ull pa allel-p ocessing o he incoming image low o allow e y high ope a ion speed. Howe e , a d awback o his a chi ec u al solu ion is ha he ill ac o dec eases hence impac ing he spa ial esolu ion and he op ical sensi- i i y. This d awback can be p ecluded by eso ing o he use o 3D in eg a ion echnologies and spli ing he mul i- unc ional ea u e o he pixels among se e al laye s: o senso s, o analog ead-ou and mixed-signal p e-p ocessing; o memo y and o digi al p ocessing. In such an a chi ec u e, he he ein epo ed compa a o plays he signi ican ole o making he ansi ion be ween images and digi al codes and hence be ween he laye s loca ed nea o he senso s and hose loca ed nea o he digi al p ocesso . This pape in oduces an o se -compensa ed compa a o wi h ull-inpu ange in he 150nm FDSOI CMOS-3D ech- nology om MIT-Lincoln Labo a o y. Sec ion II ou lines he challenges in he design o he ision a chi ec u e and he compa a o . Sec ion III add esses he compa a o i sel . Finally, he main conclusions om he wo k a e d awn. II. SYSTEM ARCHITECTURE, PIXEL AND COMPARATOR CHALLENGES Fig. 1 shows a schema ic ep esen a ion o a gene ic 3D a chi ec u e o ision. In ou case, we ha e ou laye s, namely: one senso laye which is bump bounded o a h ee- ie s uc u e composed o a mixed-signal laye (Tie 3), a memo y bu e (Tie 2) and a digi al p ocessing laye . The las h ee laye s a e in e connec ed ia Th ough-Silicon-Vias wi h 3µm×3µm pi ch. Fig. 2 shows a block diag am o Fig. 1. A gene ic 3D a chi ec u e o a ision sys em. Fig. 2. Block diag am o a cell in he mixed-signal laye o he ision sys em whe e he he ein epo ed compa a o is alloca ed. each cell in he mixed-signal laye whose unc ions a e he ollowing: •In e acing a pho odiode h ough a ans-impedance am- pli ie . •Analog s o age o di e en samples o he inpu signal as needed o pe o m mul i-scale image p ocessing. •Vol age- o- ime ans o ma ion by compa ing pixel he inpu ol age p o ided by he ans-impedance ampli ie o a digi ally-codi ied amp. •Spa ial il e ing o he inpu image o ob ain he in o ma- ion needed o ex ac mul iple scales. The a ge is an a chi ec u e sui able o ision applica ions. The pixel-le el pa allelism wi h pixel pe cell assignmen is key o achie e his goal, leading o a mo e compac , less powe -hung y and as e sys em han solu ions based on con en ional compu e s. Ne e heless, he challenges in he design low abound. Focussing on he compa a o shown in Fig. 2, he ision sys em imposes a se o cons ain s: •The cell should be as small as possible in o de o a ain a high esolu ion in a compac a ea. In ou design, he a ge ed a ea o a cell is 50µm×50µm. The compa a o canno occupy mo e han 15µm×15µm. •In e ms o inpu ange, he la ge he be e , as i makes i easie he design o i s d i ing blocks ( he ans- impedance ampli ie , o LAM memo ies in Fig.2). •In e ms o esolu ion, 8 bi s a e needed. The ans- impedance ampli e de e mines ha hose 8 bi s ha e o be eached wi hin 800mV, wha o ces a esolu ion o 3mV in he compa a o . •The compa ison ime is gi en by he a e a which he ans-impedance ampli ie p o ides he signal o be con e ed. Such a ime is a ound 400ns. •In he sea ch o a ba e y-ope a ed ision sys em, he powe dissipa ion has o be minimized oo. III. COMPARATOR DESIGN A. A chi ec u e A i s axonomy o compa a o s so s hem ou in disc e e- and con inuous- ime compa a o s [9]. The compa a o in o- duced he e belongs o he o me ype. Many a chi ec u es a e possible o ealize a con inuous- ime compa a o . A chi ec u es wi h inpu di e en ial pai s combined wi h ou pu cu en mi o s a e posed as he mos s aigh o wa d app oach. Many opologies a e possible he e. Ne e heless, in o de o each a wide inpu ange, a comple- men a y inpu di e en ial pai , i.e. a PMOS and an NMOS di e en ial pai , a e needed. Also, in o de o ha e enough esolu ion, (in ou case below 3mV), cascode opologies as ou pu cu en mi o s in conjunc ion wi h o se cancella ion echniques a e a mus . All he abo e leads o cumbe some ci cui s, making i di icul o comply wi h he a ea cons ain on he compa a o (less han 15µm×15µm). Ano he amily o compa a o s u ilize he in e e as he undamen al building block. A pa icula ealiza ion is he so-called sel -biased in e e . Fig. 3 displays i s schema ic iew. The ci cui implemen s ol age compa ison wi h o se compensa ion h ough dynamic biasing. The ci cui needs wo non-o e lapped clock signals. Du ing he i s phase, when he swi ch con oled by phiR is on and he one d i en by phiC is o , he alue Vin1−VQP is s o ed be ween he capaci o pla es. VQP means he quiescen (also known as swi ching) poin o he in e e . This is he alue eached when he inpu and he ou pu a e sho ed oge he . Du ing he second phase, when phiR is o and phiC is on, he compa ison be ween Vin1and Vin2occu s. The sampling o VQP gua an ees ha he compa ison is pe o med ega dless i s exac alue, wha ideally makes he compa a o insensi i e o misma ch. The sign o Vin1−Vin2de e mines i he ou pu o he compa ison will be a he igh o a he le o he quiescen poin o he in e e . The compa a o esolu ion, i.e. he minimum de ec able di e en ial signal a i s inpu , is also enhanced wi h se e al gain s ages in cascade. This is o mula ed in Eq. (1). Vin1 Vin2 phiR phiC C phiR ou Fig. 3. Sel -biased in e e as compa a o . ∆s=|Vo | es +VDD/Y i ksi (1) The pa ame e ksi is he gain o e e y s age, exp essed as he p oduc o i s ansconduc ance and i s ou pu impedance: ksi =gmi. oi. The o se is kep a a esidual alue. On he o he hand, he high subs a e esis i i y o he SOI echnology keeps subs a e coupling and la ch-up e ec s a negligible le els. Thus in he SOI echnology, he a ia ions caused by he digi al ci cui s in he sensi i e analog nodes in a mixed-signal design a e e y low when compa ed o he con en ional bulk CMOS echnology wi hou any special echnique like gua d ings o di e en ial opologies. B. T ansis o Realiza ion in 150nm FDSOI CMOS Technology The 150nm FDSOI CMOS-3D echnology om MIT- Lincoln Labo a o ies o e s esis o s and capaci o s as p imi- i es o design. Besides, wo ypes o ansis o s a e a ailable: ansis o s wi h low h eshold ol age (l ) and wi h medium h eshold ol age (m ). Fig. 4 depic s h ee possible ansis o ealiza ions o he in e e o Fig. 3. Fig. 5 shows simula ions un on he h ee ci cui s. The le hand-side igu e displays he dc esponse o he h ee implemen a ions. The igh hand-side igu e shows he gain a ound he quiescen poin o e e y in e e . The ansis o dimensions a e hose labeled on Fig. 4. Such sizes, gi en in mic ons, ha e been se o achie e high gain. The gain o an SOI con en ional CMOS in e e is lowe han ha ob ained on bulk CMOS. The eason is ound in he loa ing-body e ec s o he SOI echnology [10]. The high elec ic ields nea he d ain gene a ed wi h high Vds ol ages p oduce impac ioniza ion. Fo an NMOS, he new gene a ed elec ons a e collec ed a he d ain e minal. The new gene a ed holes a e accumula ed in he loa ing-body o he SOI. The lack o a body e minal p e en s he holes om lowing ou o he body. When he numbe o holes is su icien ly high, he po en ial body inc eases as much as o make he holes low in o he sou ce e minal. As a consequence, he e appea s a sha p inc ease in Ids, dec easing he ou pu impedance ( o), and hus he gain ac o ks=gm. o. The sha p inc ease o Ids, known as he kink e ec , occu s when Vds is su icien ly high. This is he case o con en ional CMOS in e e s, whe e alues abo e he Vds needed o he kink e ec o happen a e eached. S acked ansis o s (e.g. cascode opologies) dec ease he Vds ol age swings in he ansis o s, a oiding he kink e ec and enhancing he ou pu impedance, hence he gain ac o ks=gm. o. The simula ions shown in Fig. 5 show ha he pa ame e ks=gm. ois e y low in he 150nm FDSOI echnology o a con en ional CMOS in e e . The gain is Fig. 4. Th ee ansis o -le el ealiza ions o he in e e o Fig. 3. Le o igh : he dual-cascode, he diode-connec ed and he classical wo- ansis o in e e . Fig. 5. Simula ion esul s on he h ee di e en al e na i es displayed on Fig. 4 o he in e e o Fig. 3. imp o ed wi h s acked ansis o s in he diode-connec ed and he dual-cascode in e e s. The la e does no only yield he highes gain (a ound 1.8×103), bu i also p oduces ou pu s much close o he logic le els, making i he choice o he in e e ealiza ion o Fig. 3. Ou compa a o makes pa o an 8-bi single slope A/D con e e . I s unc ion is o compa e he signal o be con e ed (V e ) wi h a amp (V amp). Fig. 6 ske ches he conc e e e- aliza ion o ou compa a o . I wo ks wi h he bo om-sampling echnique, educing he e o s caused by clock eed h ough and cha ge injec ion. In so doing, he eedback NMOS swi ch con oled by phiR goes om HI o LO sligh ly be o e he ansmission ga e d i en by phiRD. Subsequen ly, when bo h phiR and phiRD a e LO, phiC goes HI, and he compa ison akes place. Wi h his echnique he cha ge injec ion and eed h ough e o s p esen in he ci cui come only om he eedback swi ches. The wo NAND ga es a e used as addi ional gain s ages. They a e implemen ed in complemen a y logic. Besides, he wo NAND ga es allow o ex e nal con ol o e he end o compa ison (end o A/D con e sion) wi h he swi ching o EOC. Du ing he ese , when phiC is se o LO, he ou pu om he i s NAND goes HI ega dless he ou pu om he i s gain s age, leading o a negligible dc powe dissipa ion. Likewise, wi h he signal End−Ramp se o LO, he s a ic powe dissipa ion in he second NAND ga e and he subsequen in e e comes om leakage cu en s only. The ansmission ga es allow o ull-inpu ange, om phiC End_Ramp EOC EOC Dual−Cascode In e e phiR phiRD 0.6/0.2 0.6/0.6 phiRD phiRD phiC phiC V e V amp C Fig. 6. Compa a o o he 3D mul i-laye ision a chi ec u e. gnd o VDD (1.5V). The eedback swi ches a e ealized wi h NMOS ansis o s. The eason is ha he quiescen poin is 500mV (see Fig.4), hus an NMOS swi ch su ices o ansmi such a ol age. The wo NMOS swi ches o he sel -biased in e e a e o balance he ade-o be ween cha ge injec- ion/ eed h ough and leakage cu en s. They a e sized o keep a good enough ade-o be ween cha ge injec ion/ eed hough e o s (need o low a ea) and low leakage (need o a low W/L a io). The use o m ansis o s in all he swi ches and ansmission ga es keeps leakage cu en s a a negligible le el. C. Pe o mance Da a The pa ame e C is key o achie e a high pe o mance compa a o . La ge C alues make cha ge injec ion and eed h ough e o s be low. Thus, i is possible o ha e be e esolu ion wi h la ge C alues. Ne e heless, la ge C alues gi e la ge a eas and longe ese cycles. The designe should choose he minimum possible C alue. In ou compa a o , C=150 F is he minimum alue capable o eaching 8 bi s o esolu ion in he single-slope A/D con e e , (3 mV in he compa a o wi hin a ange o 800mV). The alue o C=150 F leads o an a ea o less han 220µm2. The esponse ime gi es ise o ano he challenge h ough he esolu ion-speed ade-o gi en by Eq. (2). VDD = ∆d.kd(Tc)(2) ∆dis he dynamic esolu ion, kd he dynamic gain, and Tc he compa ison ime. Eq. (2) s a es ha o a compa a o o each a highe esolu ion, (smalle ∆d alues), highe dynamic gains (kd) a e needed. The compa a o needs a ce ain ime Tc o a ain such gains. Fig. 7 shows he speed- esolu ion ade-o o C=150 F. As expec ed, be e esolu ions lead o longe Tc’s. A simula ion le el, ou compa a o eaches a esolu ion o 0.1mV in less han 40ns. Tcis measu ed as he ime i akes he compa a o o es o e a logic le el s a ing om he biasing poin o he sel -biased in e e . The ese ime, i.e. he ansi ion om a logic le el back o he biasing poin , akes a ound 130ns. Usually, a new compa ison occu s a e a new ese cycle. Ne e heless, in he A/D con e e i is also possible o pe o m 256 compa isons wi h only one ese cycle. The ac ha one o he inpu s ( he amp) o he compa a o be a ying leads o an inc ease in Tc. This ime is also he wid h o e e y ol age s ep o he amp, which was ound o be 150ns. The s a ic powe in he compa a o comes mainly om he dual-cascode in e e , consuming 0.75µA, hence 1.125µW. Fig. 7. Resolu ion-speed ade-o o he compa a o wi h C=150 F. The s a ic powe in he NAND ga es and he inal in e e comes only om he leakage cu en s, being negligible. IV. CONCLUSION This pape has add essed he design o an o se - compensa ed compa a o wi h ull-inpu ange in he 150nm FDSOI CMOS-3D echnology om he MIT-Lincoln Labo a- o y. The compa a o makes pa o an 8-bi single-slope A/D con e e on a ision chip. Such a chip has been submi ed o ab ica ion in Oc obe 2009. The compa a o is implemen ed wi h a sel -biased in e e using dynamic biasing o enhance esolu ion as he i s s age. Two mo e gain s ages ealized wi h NAND ga es a e added in o de o enhance esolu ion, o sho en he compa ison ime, and o con ol he end o compa ison. The in e e o he i s s age is ealized wi h a dual-cascode opology due o he low alue o he pa ame e ks=gm. oin he a ge ed echnology. In o de o keep he esidual o se a a low alue, he bo om-sampling echnique along wi h m ansis o s o implemen ing swi ches ha e been employed. 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