Modulation and Control Independent Dead-Zone Compensation for H-Bridge Converters: A Simplified Digital Logic Scheme

Depósito de investigación de la Universidad de Sevilla https://idus.us.es/ This is an Accepted Manuscript of an article published by IEEE Transactions on Industrial Electronics available at: 10.1109/TIE.2024.3370975 “© 2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other Works” IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Modulation and Control Independent Dead Zone Compensation for H-Bridge Converters: A Simplified Digital Logic Scheme Hongjian Lin, Senior Member,IEEE, Changsong Cai, Senior Member,IEEE, Junyu Chen, Member,IEEE, Yuan Gao, Member,IEEE, Sergio Vazquez, Fellow,IEEE and Yunwei Li, Fellow,IEEE Abstract—The H-bridge (HB) converters are essential components in various power typologies, offering dual energy flow, increasing power density, and enhancing extensibility. For the HB converters, the dead zone plays a crucial role in avoiding power semiconductors against shoot-through phenomenon in the phase leg of a HB converter. However, it also negatively affects the quality of the output AC currents, impacting system performance. This letter introduces a simplified digital logic-based scheme that effectively compensates for the dead zone in HB converters. Initially, the scheme examines the repercussions of dead zones in HB converter. Subsequently, it adjusts pulse width modulation (PWM) signal waveforms by either delaying the leading edge or the lagging edge for the dead-zone compensation, irrespective of the control and modulation methods employed. Furthermore, extensibility of the proposed scheme to other power converters such as a neutral-point-clamped (NPC) converter is discussed. The effectiveness of the proposed scheme is validated by experimental results. Index Terms—H-bridge (HB) converter, dead-zone compensation, digital logics, and pulse width modulation (PWM) phase shift. I. INTRODUCTION THE H-bridge (HB) power converters are vital components in various power systems, enabling dual energy flow, increasing power density, and providing enhanced flexibility [1]–[5]. The dead zone within an HB converter is critical as it prevents simultaneous conduction of power semiconductors in the same phase leg, but it also distorts the current waveform, lowering power quality [6]–[9]. Therefore, developing effective dead zone compensation methods is essential. To mitigate the effects of the dead zone, numerous schemes have been devised, broadly falling into categories of auxiliary hardware-based, control-based, and modulation-based dead zone compensation. The hardware-based dead zone compensation schemes outlined in [10], [11] address dead zone impact on switching devices by integrating auxiliary hardware and circuits, like auxiliary commutation branches, into the converter. However, the adoption of such auxiliary hardware and circuit solutions introduces additional costs, losses, and necessitates extra control methods. In contrast, control and modulation-based dead zone compensation schemes demonstrate favorable attributes in terms of economic and power efficiency, as well as suitability and flexibility, as evidenced in literature [12]–[19]. Among these, the control-based dead zone compensation schemes detailed in [12], [13] integrate compensated voltages into modulation signals to synthesize a composite modulation signal with minimal total harmonic distortion (THD) of the AC current when dead zones affect the switching devices. However, complete elimination of the dead zone impact remains a challenge. Moreover, schemes in [14], [15] manipulate triangle waveforms or modulation waveforms, while the approach in [16] involves chopping PWM signals to entirely eliminate the dead zone impact. These schemes, though effective, entail intricate control loops and may exhibit reduced reliability. Adjustments to modulation waveforms are required to decompose the phaseleg of the converter into two basic switching cells, and accurate detection of the zero-crossing point of the AC current is crucial to avoid shoot-through risks within the same phase leg that could lead to the breakdown of switching devices. In an effort to advance dead zone compensation schemes, the space vector concept is further developed in references [17], [18] owing to its inherent flexibility. Additionally, references [19] and [20] enhance reference vector synthesizing methods tailored to specific targets, thereby altering PWM signals and eliminating dead zone impact in converters. Despite the promising performance of the schemes in [19], [20], their industrial application is somewhat limited due to digital implementation involving complex arithmetic operations. Furthermore, their suitability is constrained as these schemes are specific to certain topologies. This letter presents a modulation and control independent compensated dead zone scheme based on digital logic operations for HB converters. The proposed scheme only leverages the current polarity to determine the phase shift of the PWM signals using digital logic operations. Additionally, extensibility of the proposed dead zone compensation scheme to other power converters such as a neutral-point-clamped (NPC) converter is discussed and demonstrated. II. PROPOSED DEAD ZONE COMPENSATION SCHEME FOR AN HB CONVERTERS To illustrate the proposed scheme in a straightforward manner, an example in the context of a single-phase HB converter is proposed in this letter. Fig. 1 describes the structure and typical current flowing path of the single-phase three-level HB converter. T1to T4represent the four switching devices, while g1to g4correspond to the PWM signals. D1to D4are the freewheeling diodes connected accordingly. Esymbolizes the DC voltage source, while iSN and uasignify the AC current and voltage, respectively. By referring to Fig. 1, it becomes This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3370975 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS (a) isN > 0 and {1,0,0,1}: (Level “1”)(b) isN > 0 and {1,0,0,0}: (Level “0”)(c) isN > 0 and {1,1,0,0}: (Level “0”) isN < 0 and {1,1,0,0}: (Level “0”) ua ua EE D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 ua ua D4 (h) isN < 0 and {0,1,0,0}: (Level “0”) D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 EE (h) isN < 0 and {0,1,0,0}: (Level “0”) D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 E D4 (h) isN < 0 and {0,1,0,0}: (Level “0”) D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 E (i) D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 isN < 0 and {0,1,1,0}: (Level “-1”) ua ua EE (i) D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 isN < 0 and {0,1,1,0}: (Level “-1”) ua E (f) D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 isN < 0 and {1,0,0,1}/ {1,0,0,0}: (Level “1”) ua ua EE ua ua D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 EE ua ua D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 EE ua ua D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 Eua D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 EE (g) D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 E (g) D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 E (g) (d) isN > 0 and {0,1,1,0}: (Level “-1”) D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 EE ua ua (d) isN > 0 and {0,1,1,0}: (Level “-1”) D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 Eua isN > 0 and {0,1,0,0}: (Level “-1”) D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 EE ua ua (e) (a) isN > 0 and {1,0,0,1}: (Level “1”)(b) isN > 0 and {1,0,0,0}: (Level “0”)(c) isN > 0 and {1,1,0,0}: (Level “0”) isN < 0 and {1,1,0,0}: (Level “0”) ua E D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 ua D4 (h) isN < 0 and {0,1,0,0}: (Level “0”) D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 E (i) D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 isN < 0 and {0,1,1,0}: (Level “-1”) ua E (f) D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 isN < 0 and {1,0,0,1}/ {1,0,0,0}: (Level “1”) ua E ua D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 Eua D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 Eua D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 E (g) (d) isN > 0 and {0,1,1,0}: (Level “-1”) D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 Eua isN > 0 and {0,1,0,0}: (Level “-1”) D4 D2 isN T1 T3 T2 T4 g2 g4 D1 D3 g1 g3 Eua (e) Fig. 1. Current flowing paths of HB converter based on different current polarities and switching states. evident that different PWM signals and isN polarities lead to distinct AC current paths. For instance, in Fig. 1(a), when isN>0 and {g1,g2,g3,g4}={1, 0, 0, 1}, the isN current flows from Eto T1and subsequently returns from T4. According to Fig. 1, let’s consider three cases where the PWM signals for the AC voltage E, 0, and -Eare {1,0,0,1},{1,1,0,0}, and {0,1,1,0}, respectively, i.e., correspondingly normalized as levels “1”, “0”, and “-1”, as shown in Figs. 1 and 2. In the absence of a dead zone, these PWM signals generate the AC voltage waveform depicted in Fig. 2(d). However, if isN>0 and a dead zone is introduced, the PWM signal with the dead zone is represented as Fig. 2(b), resulting in the AC voltage waveform shown in Fig. 2(e), which exhibits noticeable degradation compared to Fig. 2(d). Nevertheless, an interesting observation arises when the PWM signals of g1and g4shift by one dead zone, i,e, (Td), while the leading edges of g2and g3shift by two dead zones, with the falling edges remaining unchanged, as shown in Fig. 2(c). In this scenario, the extra PWM signals, {1,0,0,0}and {0,1,0,0}to yield the AC voltages 0 and -E when isN>0 are generated, respectively. The current flowing paths to demonstrate the AC voltages by these PWM signals are shown in Figs. 1(b) and 1(e). It is evident that the resulting AC voltage waveform in Fig. 2(f) after enabling shift of the PWM signals in Fig. 2(c), performs identically to that in Fig. 2(d). Conversely, on the right side of Fig. 2, when isN<0, as illustrated in Fig. 2(c), shifting the leading edges of g1and g4by two dead zones while preserving the position of their falling edges, and entirely shifting the waveforms of g2and g3 by one dead zone generates the extra PWM signals {1,0,0,0} and {0,1,0,0}. These PWM signals yield the AC voltages E and 0, respectively when isN<0, as shown in Figs. 1(f) and g1 g2 1 0 0 g3 1 g4 1 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 E ua00E -E uaE0-E 0E 0-E0E 1 1 1 1 11 1 1 1 1 00 00 0 0 0 0 0 0 0 0 0 000 0 0 0 0 11 1 1 11 1 1 11 g1 g2 g3 g4 g1 g2 1 0 0 g3 1 g4 1 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 g1 g2 g3 g4 E ua00E uaE00E E00E 1111 11 1 1 11 00 00 00 0 0 0 0 0 0 000 000 111 1 1 1 g1 g2 g3 g4 0 (a) g1 g2 g3 g4 (b) (c) (d) (e) (f) -E ua 1 01 -E isN>0 isN<0 ua Td TdTd Td Td Td Td 2Td TdTd Td TdTdTd Td E Td Td Td Td 2Td Td Td 2Td Td TdTdTd Td -E g1 g2 1 0 0 g3 1 g4 1 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 E ua00E -E uaE0-E 0E 0-E0E 1 1 1 1 11 1 1 1 1 00 00 0 0 0 0 0 0 0 0 0 000 0 0 0 0 11 1 1 11 1 1 11 g1 g2 g3 g4 g1 g2 1 0 0 g3 1 g4 1 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 g1 g2 g3 g4 E ua00E uaE00E E00E 1111 11 1 1 11 00 00 00 0 0 0 0 0 0 000 000 111 1 1 1 g1 g2 g3 g4 0 (a) g1 g2 g3 g4 (b) (c) (d) (e) (f) -E ua 1 01 -E isN>0 isN<0 ua Td TdTd Td Td Td Td 2Td TdTd Td TdTdTd Td E Td Td Td Td 2Td Td Td 2Td Td TdTdTd Td -E Td 2TdTd Td g1 g2 1 0 0 g3 1 g4 1 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 E ua00E -E uaE0-E 0E 0-E0E 1 1 1 1 11 1 1 1 1 00 00 0 0 0 0 0 0 0 0 0 000 0 0 0 0 11 1 1 11 1 1 11 g1 g2 g3 g4 g1 g2 1 0 0 g3 1 g4 1 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 g1 g2 g3 g4 E ua00E uaE00E E00E 1111 11 1 1 11 00 00 00 0 0 0 0 0 0 000 000 111 1 1 1 g1 g2 g3 g4 0 (a) g1 g2 g3 g4 (b) (c) (d) (e) (f) -E ua 1 01 -E isN>0 isN<0 ua Td TdTd Td Td Td Td 2Td TdTd Td TdTdTd Td E Td Td Td Td 2Td Td Td 2Td Td TdTdTd Td -E Td 2TdTd Td Fig. 2. PWM signal waveforms of HB converter under different current polarities. (a) Ideal PWM waveforms, (b) PWM waveforms subsequent to dead-zone modulation, (c) PWM waveforms subsequent to deadzone compensation, (d) Ideal AC voltage, (e) AC voltage subsequent to dead-zone modulation, and (f) AC voltage subsequent to dead-zone compensation. Proposed dead-zone compensation scheme in Fig. 3(a) and (b) g1c g2c g3c g4c Closed-loop control mode Power converters in Fig.1 g1 g2 g3 g4 isN uaref (c) SPWM in [5] SPWM in [5] SVPWM in [7] (10) (01) (00) (11) SVPWM in [7] (10) (01) (00) (11) uaModulation module isN<0 z^(-Td) OR z^(-Td)z^(-Td) g3c isN>0 AND AND g1c g1c g1 g1 z^(-Td) AND z^(-Td)z^(-Td) g4c AND AND g2c g2c g2 g2 z^(-Td) AND z^(-Td)z^(-Td) g4c AND AND g2c g2 (a) z^(-Td) OR NOT z^(-Td)z^(-Td) g4c AND AND g2 g2 g2c g2c z^(-Td) OR NOT z^(-Td)z^(-Td) g4c AND AND g2 g2c z^(-Td) AND z^(-Td)z^(-Td) g3c AND AND g1 g1 g1c g1c (b) NOT NOT NOT Proposed dead-zone compensation scheme in Fig. 3(a) and (b) g1c g2c g3c g4c Closed-loop control mode Power converters in Fig.1 g1 g2 g3 g4 isN uaref (c) SPWM in [5] SVPWM in [7] (10) (01) (00) (11) uaModulation module isN<0 z^(-Td) OR z^(-Td)z^(-Td) g3c isN>0 AND AND g1c g1 z^(-Td) AND z^(-Td)z^(-Td) g4c AND AND g2c g2 (a) z^(-Td) OR NOT z^(-Td)z^(-Td) g4c AND AND g2 g2c z^(-Td) AND z^(-Td)z^(-Td) g3c AND AND g1 g1c (b) NOT NOT NOT Fig. 3. The overall dead-zone compensation block diagram. (a) and (b) Flowchart of the proposed dead-zone compensation scheme, and (c) The overall zone-zone compensation closed-loop control diagram. 1(h). The shift of these PWM signals leads to an uawaveform in Fig. 2(f) identical to that in Fig. 2(d). Drawing upon Figs. 1 to 2, the comprehensive dead-zone compensation scheme is summarized in Fig. 3, which relies on the current polarities and PWM signals. The underlying principle of this scheme is outlined as follows. In the initial stage, when isN>0 as depicted in Fig. 3(a), the signal g1or g2necessitates a one-dead zone shift, which is accomplished through the ”OR” operation. Subsequently, the complementary signal of g1or g2is generated using the ”NOT” operation. Both the final signal of g1or g2and its corresponding signal are shifted by one dead zone and subjected to respective ”AND” operations. This process results in the signal g1c or g2c, which represents g1or g2after undergoing dead-zone compensation. The complementary signal of g1or g2is defined as g3c or g4c depending on the specific topology feature. For instance, in the case of HB converter, g3or g4serves as the complementary signal of g1or g2, making g3c or g4c the complementary signal of g1c or g2c. This same conclusion holds true for the scenario when isN<0, as depicted in Fig. 3(b). Fig. 3(c) illustrates the overall dead- This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3370975 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS E/2 N D2 D1 D3 D4 D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 D6 D5 D7 D8 D6 D5 D7 D8 g6 g5 g7 g8 T6 T5 T7 T8 DL1 DL2 DR1 DR2 E/2 { Left phase leg Right phase leg { E/2 N D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 D6 D5 D7 D8 g6 g5 g7 g8 T6 T5 T7 T8 DL1 DL2 DR1 DR2 E/2 { Left phase leg Right phase leg { Fig. 4. The NPC converter [21]. (a) isN > 0, {1,1,0,0}: (Level “1”) E/2 isN N D2 D1 D3 D4 D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 E/2 E/2 isN N D2 D1 D3 D4 D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 isN > 0,{0,0,1,0}/{0,0,1,1}: (Level “-1”) (c) E/2 (b) isN > 0 , {0,1,0,0}/{0,1,1,0}: (Level “0”) E/2 N D2 D1 D3 D4 D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 E/2 N D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 (b) isN > 0 , {0,1,0,0}/{0,1,1,0}: (Level “0”) E/2 N D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 E/2 isN (b) isN > 0 , {0,1,0,0}/{0,1,1,0}: (Level “0”) E/2 N D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 E/2 isN (d) isN < 0, {1,1,0,0}/{0,1,0,0}: (Level “1”) E/2 isN N D2 D1 D3 D4 D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 (e) isN < 0, {0,1,1,0}/{0,0,1,0}: (Level “0”) E/2 isN N D2 D1 D3 D4 D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 E/2E/2 (f) isN < 0, {0,0,1,1}: (Level “-1”) E/2 isN N D2 D1 D3 D4 D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 E/2 (a) isN > 0, {1,1,0,0}: (Level “1”) E/2 isN N D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 E/2 E/2 isN N D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 isN > 0,{0,0,1,0}/{0,0,1,1}: (Level “-1”) (c) E/2 (b) isN > 0 , {0,1,0,0}/{0,1,1,0}: (Level “0”) E/2 N D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 E/2 isN (d) isN < 0, {1,1,0,0}/{0,1,0,0}: (Level “1”) E/2 isN N D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 (e) isN < 0, {0,1,1,0}/{0,0,1,0}: (Level “0”) E/2 isN N D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 E/2E/2 (f) isN < 0, {0,0,1,1}: (Level “-1”) E/2 isN N D2 D1 D3 D4 g2 g1 g3 g4 T2 T1 T3 T4 DL1 DL2 E/2 Fig. 5. Current flowing paths of the left phase leg of the NPC converter based on different current polarities and switching states. zone compensation closed-loop control diagram. With respect to Fig. 3(c), the proposed dead-zone compensation scheme shifts the phases of the PWM signal combination {g1,g2,g3, g4}by the manner in Figs. 3(a) and 3(b) to obtain the postcompensated PWM signal combination {g1c,g2c,g3c,g4c}to drive the switching devices in Fig. 1. According to Fig. 3, the proposed scheme is independent of control and modulation methods since it is activated after the period when the PWM signals i.e., {g1,g2,g3,g4}are outputted. III. EXTENSIBILITY DISCUSSION OF THE PROPOSED DEAD ZONE COMPENSATION SCHEME Based on the discussion in Section II, this section extends the proposed dead zone compensation scheme to apply in a multilevel converter. A five-level NPC converter is exemplified, as shown in Fig. 4 [21]. Based on Fig. 4, T1to T8are eight switching devices along with the corresponding switching driving signals g1to g8.D1and D8are eight freewheeling diodes. DL1,DL2,DR1 and DR2 are four clamped diodes. Nis the clamped point. Referring to Fig. 4, the symmetric structure of the NPC converter dictates that the analysis of the proposed dead-zone scheme, when applied to the left phase leg, mirrors that of the right phase leg in the NPC topology depicted in Fig. 4 except opposite detection of the AC current polarity. Consequently, the illustrated paths of current flow in the left phase leg are (1. MOSFETs: STW42N65M5) (2. DC capacitor: 350 V, 1000 uF) 3. Signal processing board (4. Driver board: IXDN609PI) (5. Auxiliary source: 65 W, 12 V) 6. Radiator 1 2 5 3 4 6 1 2 5 3 4 6 Fig. 6. Experimental prototype and the verification parameters. exemplified in Fig. 5. As evidenced by Fig. 5, switching devices T1and T3function as complementary switching devices, akin to switching devices T2and T4in the left phase leg of the NPC converter, which is identical to the HB converter. The difference is that the PWM signal combination of the left phase leg of the NPC converter outputting the level “1” is {1,1,0,0}, as shown in Fig. 5(a), yet the HB converter outputs the level “1” by the PWM signal combination {1,0,0,1}, as shown in Fig. 1(a) and Fig. 2. Drawing the experience from Fig. 2, in terms of the NPC converter to achieve the dead zone compensation, the PWM signals of g1and g2shift by one dead zone, while the leading edges of g3and g4shift by two dead zones, with the falling edges remaining unchanged for the left phase leg of the NPC converter. Expanding on Figs. 4 and 5, the proposed dead-zone compensation scheme is extended within the NPC converter. It is affirmed that this dead zone compensation scheme shown in Fig. 3, can be easily applied to any other converters wherein the converter structure analysis aligns with or similar to that of the HB converter regardless of the intricacies of the control and modulation techniques. IV. EXPERIMENTAL AND COMPARATIVE RESULTS A. Experimental Results To verify the effectiveness of the proposed dead-zone compensation scheme, a scale-down experimental prototype and the verification parameters are presented in Fig. 6. The sampling frequency is 10 kHz and the switching frequency is 5 kHz. The dead zone Tdis equal to 5 µs. Fig. 7 provides the results corresponding with Fig. 2 to derive the single-phase HB converter with different control and modulation combinations under the closed-loop control mode, as shown in Fig. 8. Figs. 8(a) and 8(b) present the AC current results obtained from the HB converter with PI controller combining SPWM modulation without and with dead-zone compensation by the proposed scheme, respectively. The total harmonic distortion (THD) of the AC currents exhibits 3.15% and 1.47% without and with employing the proposed scheme. Similarly, in terms of other combinations, i.e., (PR controller plus SPWM, as shown in Figs. 8(c) and 8(d)), (PI controller plus SVPWM, as shown in Figs. 8(e) and 8(f)), (PR controller plus SVPWM, as shown in Figs. 8(g) and 8(h)), the similar results with Figs. 8(a) and 8(b) in reducing the THD of AC current to 1.39%, 1.43%, and 1.38% are performed. From these verification results, the proposed dead-zone compensation scheme is capable of any control and modulation methods to confirm its independence of modulation and control methods. This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3370975 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS g1 g2 g3 g4 g1 g2 g3 g4 g1 g2 g3 g4 g1 g2 g3 g4 ua ua ua g1 g2 g3 g4 g1 g2 g3 g4 Td Td 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 0 -E 0 0 -E 0 0 0 0 0 0 0 0 -E 0 0 -E 0 -E -E 0 -E -E 0 0 0 -E 0 0 -E 0 0 0 0 0 0 0.06995 0.07 0.07005 0.0701 0.070150.06995 0.07 0.07005 0.0701 0.07015 E 0 0 E 0 0 0 0 E 0 0 E (a) (b) (c) (d) (e) (f) (g) (a) (b) (c) (d) (e) (f) (g) Fig. 7. PWM signals and the AC voltage of the HB converter. (a) The ideal PWM signals, (b) PWM signals without dead-zone compensation, (c) PWM signals with dead-zone compensation, (d) The ideal AC voltage, (e) The AC voltage without dead-zone compensation, (f) The AC voltage with dead-zone compensation, and (g) The zoom-out AC voltage of (f). Corresponding to Figs. 8(a) to 8(h), Figs. 9(a) to 9(h) demonstrate the proposed dead zone compensation scheme in the NPC converter with different control and modulation scheme combinations. In order to present the impact of the dead zone and effectiveness of the proposed dead zone compensation scheme, the dead zone of the NPC converter is intentionally set equal to 15 µs, larger than that of HB converter. Similar to Figs. 8(a) to 8(h), the proposed dead zone compensation scheme is effective in the NPC converter. The THD of the AC current is reduced in all the scenarios. Therefore, Figs. 9(a) to 9(h) demonstrate the extensibility and independence on control and modulation of the proposed scheme. B. Comparative Results In this subsection, two tables, namely Table I and Table II are illustrated for a comprehensive comparison between the proposed dead-zone compensation scheme and state-of-the-art schemes in different aspects. Table I facilitates a fair assessment of digital resource utilization across various dead-zone compensation schemes. Notably, upon examination of the digital resource utilization aspect, other schemes in [12], [13], [16], [19], and [20] employ additional control loops or specialized modulation techniques involving intricate calculations, resulting in heightened hardware resource consumption. In contrast, the proposed dead zone compensation scheme relies on a few logical operations, demonstrating superior speed with a required time of 132 ns and exceptional hardware efficiency, utilizing a mere 5632 memory bytes outperforming existing state-of-the-art schemes in these critical aspects. Table II conducts a comprehensive comparison between the proposed dead-zone compensation scheme and a state-of-the- THD: 2.99% THD: 1.39%(c) (d)1A/div 1A/div THD: 3.12% THD: 1.43% (f)(e) 1A/div1A/div THD: 2.93% THD: 1.38% (h)(g) 1A/div1A/div THD: 3.15% THD: 1.47%(a) (b)1.5A/div 1.5A/div THD: 2.99% THD: 1.39%(c) (d)1A/div 1A/div THD: 3.12% THD: 1.43% (f)(e) 1A/div1A/div THD: 2.93% THD: 1.38% (h)(g) 1A/div1A/div THD: 3.15% THD: 1.47%(a) (b)1.5A/div 1.5A/div Fig. 8. The AC current of the HB converter with different control and modulation combining closed-loop control methods: (a) and (b) The PI controller combining SPWM modulation without and with deadzone compensation, respectively, (c) and (d) The PR controller combing SPWM modulation without and with dead-zone compensation, respectively, (e) and (f) The PI controller combining SVPWM modulation without and with dead-zone compensation, respectively, (g) and (h) The PR controller combing SVPWM modulation without and with dead-zone compensation, respectively. THD: 2.21% THD: 1.01%(c) (d)1A/div 1A/div THD: 2.35% THD: 1.03% (f)(e) 1A/div1A/div THD: 2.46% THD: 1.12% (h)(g) 1A/div1A/div THD: 2.63% THD: 1.28%(a) (b)1.5A/div 1.5A/div Fig. 9. The AC current of the NPC converter with different control and modulation combining closed-loop control methods: (a) and (b) The PI controller combining SPWM modulation without and with dead-zone compensation, respectively, (c) and (d) The PR controller combing SPWM modulation without and with dead-zone compensation, respectively, (e) and (f) The PI controller combining SVPWM modulation without and with dead-zone compensation, respectively, (g) and (h) The PR controller combing SVPWM modulation without and with dead-zone compensation, respectively. art dead-zone scheme in implementation structure. Specifically, the schemes outlined in [12] and [13] employ compensated voltages to adjust modulation waveforms, effectively mitigating the dead-zone impact on three-phase converters. In contrast, the scheme presented in [16] integrates an additional control loop within the double second-order generalized integrator frequency-locked loop (DSOGI-FLL) to detect the zerocrossing point of the AC current, involving intricate control operations. Meanwhile, [19] and [20] leverage the space vector concept to determine switching actions and modify modulation waveforms for dead-zone compensation, necessitating complex multiplication, division, and trigonometric operations, thereby increasing hardware resource utilization. In contrast, the proposed scheme relies on straightforward logic operations This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3370975 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS TABLE I COMPREHENSIVE COMPARATIVE RESULTS BETWEEN THE PROPOSED SCHEME AND THE EXISTING STATE-OF-THE-ART SCHEMES IN DIGITAL RESOURCE UTILIZATION Schemes Logical cell Dedicated logic register Combinational functions Time required (ns) Memory bytes [12] 1718 1376 1101 198 17920 [13] 2193 1488 1342 264 19205 [16] 3053 2164 2288 429 15232 [19] 6791 5613 3594 561 37688 [20] 6944 5786 3620 594 43832 Proposed 1090 644 1067 132 5632 TABLE II COMPREHENSIVE COMPARATIVE RESULTS BETWEEN THE PROPOSED SCHEME AND THE EXISTING STATE-OF-THE-ART SCHEMES IN THE IMPLEMENTATION STRUCTURE Schemes Control Modulation Approach [12] √— Voltage signal compensation [13] √— Trapezoidal voltage compensation [16] √— PWM chop signal compensation [19] — √Space vector-based [20] — √Space vector-based The proposed — — Simple digital logic The signs “−” means “Independent”, “√” means “Dependent”. applied to the switching signals, independent of intricate control and modulation techniques. This characteristic allows for the adoption of simple control and modulation alternatives, simplifying the implementation process. Furthermore, the proposed scheme exhibits versatility, extending its applicability to various topologies such as multilevel converters. The incorporation of simple logic operations for these topologies underscores the high extensibility of the proposed scheme. V. CONCLUSION A simple digital logic-based dead-zone compensation scheme is proposed for typical single-phase HB converters in this letter. The scheme delays the phase position of the switching driving signals based on the current polarity without any zero-crossing detection. The key advantages of the proposed scheme can be summarized as follows: 1) It operates independently of any modulation and control schemes, employing the logic operations. 2) It is compatible with different types of power semiconductors. 3) It can be easily extended to other topologies, such as multilevel converters by repeatedly employing these simple logic operations. REFERENCES [1] S. Vazquez, P. Acuna, R. P. Aguilera, J. Pou, J. I. Leon, and L. G. Franquelo, “DC-Link Voltage-Balancing Strategy Based on Optimal Switching Sequence Model Predictive Control for Single-Phase H-NPC Converters,” IEEE Trans. on Ind. Electron., vol. 67, no. 9, pp. 7410– 7420,2020. [2] A. Sanchez-Ruiz, M. Mazuela, H. Fernandez-Rebolleda, S. Ceballos, A. Perez-Basante, I. Ibanez-Hidalgo, M. Zubiaga, J. Pou, N. Beniwal, and G. Konstantinou, “DC-Link Neutral Point Control for 3L-NPC Converters Utilizing Selective Harmonic Elimination PWM,” IEEE Trans. on Ind. Electron., vol. 69, no. 9, pp. 8633–8644,2022. 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This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2024.3370975 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.