FPGA-based implementation of a fuzzy motion adaptive de-interlacing algorithm

FPGA-based implemen a ion o a uzzy mo ion adap i e de-in e lacing algo i hm P. B ox, S. Sánchez-Solano and I. Ba u one Ins i u o de Mic oelec ónica de Se illa, IMSE-CNM (CSIC) Edi icio CICA, A . Reina Me cedes s/n, 41012 Se illa, SPAIN Phone: +34955056666, Fax: +34955056686, E-mail: {b ox|san iago|lumi}@imse.cnm.es Abs ac - This pape su eys he ha dwa e imple- men a ion o a de-in e lacing algo i hm on Field-P o- g ammable Technology o eal- ime p ocessing. The algo i hm p esen ed e alua es he le el o mo ion a each pixel, and de e mines he in e pola ion be ween a spa ial and a empo al me hod acco ding o he p esence o mo ion. To achie e i he algo i hm employs an hie a chi- cal s uc u e wi h h ee simple uzzy sys ems. The i s one pe o ms a se o uzzy ules o apply easoning in o de o de ec mo ion; he second one selec s he mos con enien di ec ion o implemen an edge-dependen line a e age me hod; and he hi d one is used o choose he mos adequa e empo al me hod. The ha dwa e implemen a ion o his algo i hm combines pipeline a chi ec u e wi h a pa allel p ocessing o uzzy ules o accele a e he compu a ion. As esul an e icien implemen a ion is de eloped in e ms o compu- a ional ime and ha dwa e cos . I. INTRODUCTION Cu en FPGA de ices include look-up ables, egis e s, mul iplexe s, and dis ibu ed and block mem- o y, as well as speci ic ci cui y o as adde s, mul i- plie s, and I/O p ocessing. This cha ac e is ic, oge he wi h a comple e and unlimi ed ep og amming capabil- i y, ha e made FPGAs become key componen s in implemen ing high pe o mance DSP sys ems in ecen yea s, especially in he a eas o digi al communica- ions, ne wo king, ideo and imaging. Se e al ools ha e been de eloped in o de o acili a e he design o FPGA-based DSP designs. The p esen ed design low u ilizes one o hese ools called Sys em Gene a o , a sys em le el ool de eloped by Xilinx (XSG)[1]. This pape desc ibes he design and implemen a- ion o an algo i hm o ideo de-in e lacing. This ype o algo i hms a e cu en ly in demand by a wide numbe o de ices, such as HDTVs, DVDs, p ojec o s, e c., ha equi e a p og essi e scanning o ma . In e - lacing was in oduced by TV indus y as he mos e i- cien me hod o educe ansmi ed in o ma ion. I consis s o hal ing ideo bandwid h by elimina ing lines, acco ding o he o de in which ames a e sen . F ames wi h odd numbe s only con ain he odd lines o he image whe eas ames wi h e en numbe s only con ain he e en lines. A comple e ame con aining odd and e en lines can be calcula ed a he ecei e using he in e pola ion echniques p o ided by de-in e lacing me hods [2]. The pape is o ganized as ollows. A b ie desc ip- ion o he algo i hm is expounded in Sec ion II. The s a egy o algo i hm implemen a ion is explained in Sec ion III. Implemen a ion esul s a e p esen ed in Sec ion IV. Finally, he main conclusions a e ou lined in Sec ion V. II. ALGORITHM STUDY Among de-in e lacing algo i hms, mo ion adap- i e algo i hms o e a good ade-o be ween cos and quali y [3]. This kind o algo i hms combines a spa ial me hod, , and a empo al me hod, , acco ding o he p esence o mo ion. They a e based on he idea ha empo al in e pola ion is e y sui able o s a ic a eas, while spa ial in e pola ion is mo e adequa e when he le el o mo ion is high. The algo i hm implemen ed he ein uses uzzy logic o in e pola e be ween and de-in e lacing me hods. I uses as inpu sys em an e alua ion o mo ion, which is calcula ed as he bi-dimensional con- olu ion o a di e ence ma ix o luminance al- ues om consecu i e ields o he sequence: (1) whe e a e he con olu ion weigh s and a e he ollowing alues (see Fig.1): (2) ISIT ISIT H() mo ion ΣCij Hij ΣCij ------------------------------ 242 H11 H12 H13 T 8 --------------------------------------------------------------- == Fig. 1: Pixels in ol e in he calcula ion o mo ion. B0 X0 E0 X B E Xn ( -1) In e pola ed line T ansmi ed line ( ) Sequence o de ( +1) Cu en pixel Cij,() Hij,() H11 BB 0 – 2 ------------------- =H12 XnX0 – 2 ---------------------- =H13 BB 0 – 2 ------------------- = Di e en sizes o ma ices and ha e been s udied o achie e a good ade-o be ween he esou ces equi ed and he quali y o mo ion measu e- men ob ained [4]-[5]. The selec ed ma ices, as can be seen in exp ession (1), only includes neighbo s in e - ical di ec ion since a wide numbe o simula ion sequences shown a non-decisi e in luence o ho izon- al neighbo s. Analyzing he alues o ma ix in exp ession (2), i can be seen ha is necessa y he use o in e po- la ed alues calcula ed in he p e ious ield ( in Fig.1). To calcula e he i s p og essi e ame he spa- ial me hod is applied. The in luence o mo ion in selec ing he con ibu- ion o each in e pola o is e alua ed by conside ing he ules in Table 1. The uzzy concep s small (S), la ge (L) and medium (M), used in he ulebase a e modeled acco ding o he membe ship unc ions shown in Fig.2. Using he Fuzzy Mean as de uzzi ica- ion me hod, he new pixel alue is calcula ed as ol- lows: (3) whe e is he ac i a ion deg ee o ule . and a e linea coe icien s being i s sum equal o one (). Ou p oposal in oduces wo main no el ies o e con en ional mo ion adap i e me hods. The i s one is he use o uzzy ins ead o c isp alues o de ine di - e en mo ion le els. This p o ides a mo e obus mo ion de ec ion since h eshold alues usually p o- duce w ong decision in a eas whe e he decision is unclea . The second one is he inclusion o a hi d ule ha inc eases he in e pola ion capabili y o he uzzy sys em. Rulebases wi h up o i e ules ha e been ana- lyzed in [6]. Ne e heless, he base wi h h ee ules p o ides he mos a ac i e solu ion in e ms o ha d- wa e esou ces and quali y o he in e pola ed image [6]. Mo eo e , he p oposed algo i hm also used wo simple uzzy sys ems o calcula e he and in e - pola ion modes. The p oposal o he spa ial in e pola- ion pe o ms an edge-adap i e in e pola ion by analyzing he i e p ede e mined di ec ions (a1,a,b,c,c1) shown in Fig.3(a) [7]. The ules o he Table in Fig.3(b) selec he mos adequa e di ec ion o apply he a e age o luminance alues. The uzzy con- cep s e y la ge (VL), la ge (L), small (S) and e y small (VS) used in he ulebase a e de ined by he membe ship unc ions shown in Fig.3(c). The inal esul is gi en by: (4) HC TABLE 1. Rulebase o in e pola ion selec ion i hen 1) mo ion is S IS 2) mo ion is L IT 3) mo ion is M λIT+δIS H B0E0, IS Xα1ITα2ISα3 λ IT δ IS+()++= α iiλδ λδ+1= ISIT Fig. 2: Membe ship unc ions used in he ulebase o in e pola ion selec ion. 1 0 S (small)M (medium)L (la ge) µmo ion mo ion 0.5 8.5 72.5 Fig. 3: (a) Pixels in ol e in he calcula ion o he spa ial in e pola o . (b) Rulebase o selec he spa ial in e pola ion acco ding o he p esence o edges. (c) Membe ship unc ions o he uzzy concep s used in he ulebase. X C1 BC A1 F1 A D1DEF ( ) Sequence o de (a) IS=(C1+D1)/2a1is VL and a is VL and b is L and c is L and c1is S 5) IS=(A+F+C+D)/4a is VS and b is L and c is VS3) IS=(C+D)/2a is L and b is L and c is S2) IS=(B+E)/2o he wise6) IS=(A1+F1)/2a1is S and a is L and b is L and c is VL and c1is VL 4) IS=(A+F)/2a is S and b is L and c is L1) heni IS=(C1+D1)/2a1is VL and a is VL and b is L and c is L and c1is S 5) IS=(A+F+C+D)/4a is VS and b is L and c is VS3) IS=(C+D)/2a is L and b is L and c is S2) IS=(B+E)/2o he wise6) IS=(A1+F1)/2a1is S and a is L and b is L and c is VL and c1is VL 4) IS=(A+F)/2a is S and b is L and c is L1) heni 1 0 µa a (b) (c) a=|A-F| a1=|A1-F1| b=|B-E| c=|C-D| c1=|C1-D1| SL 4 20 52 68 VL ( e y la ge) VS ( e y small) IS ISβ1 AF+ 2 ------------- ⎝⎠ ⎛⎞ β2 CD+ 2 -------------- ⎝⎠ ⎛⎞ β3 ACDF+++ 4 ---------------------------------- ⎝⎠ ⎛⎞ ++ += β+4 A1F1 + 2 -------------------- ⎝⎠ ⎛⎞ β5 C1D1 + 2 --------------------- ⎝⎠ ⎛⎞ β6 BE+ 2 ------------- ⎝⎠ ⎛⎞ ++ whe e is he ac i a ion deg ee o he ules in he Table o Fig.3(b). To selec he bes choice o empo al in e pola ion ano he uzzy sys em is used. I makes a decision depending on he simila i y be ween wo consecu i e ields, gi en by he ollowing exp ession: (5) The pixels used in exp ession (5) a e shown in Fig.4(a). The ulebase akes a decision using a uzzy ansi ion o dis inguish which pixel is he mos ade- qua e: he pixel in he p e ious o in he nex ield (see Table o Fig.4(b)). The uzzy de ini ions used in he ulebase a e shown in Fig.4(c) and he esul o is calcula ed as ollows: (6) whe e is he ac i a ion deg ee o he ules in he Table o Fig.4(b). III. ALGORITHM IMPLEMENTATION WITH XSG Ad ances in VLSI echnologies ha e encou aged a apid g ow h in capaci y and pe o mance o FPGAs. On he o he hand, he econ igu a ion capabili y o FPGAs allows adap ing i s ha dwa e esou ces o a speci ic p ocessing sys em. This abili y oge he wi h he de elopmen o powe ul design ool such as XSG, which conside ably educes he o e all sys em de el- opmen ime, ha e made FPGAs as one o he mos a ac i e solu ion o de elop apid p o o ypes o dig- i al signal p ocessing (DSP) applica ions. The ollow- ing subsec ions desc ibe he implemen a ion o he de-in e lacing algo i hm p oposed in his pape . A. Design speci ica ions The expe imen al se -up is con igu ed using a XUP Vi ex-II P o De elopmen boa d [8].I is an ad anced ha dwa e pla o m ha con ains a Vi ex-II P o FPGA su ounded by pe iphe al componen s ha can be used o c ea e a complex sys em. This boa d inco po a es expansion connec o s han can be used o connec a ideo cap u e boa d. This de ice ac s as an in e ace be ween a ideo sou ce such as camco de , VCR, CCD came a, e c. and he boa d. The ideo decode boa d is cen e ed on he ADV7183B ideo decode chip om Analog De ices, which can de ec s anda d analog baseband ele ision signals (NTSC, PAL and SECAM) and p o ides an ou pu digi al ideo signal. This con e sion is ealized acco ding o he ITU-R BT 656 ecommenda ion om he In e na ional Telecommunica ion Union (ITU), and is independen o he s anda d (NTSC, PAL o SECAM). This ecommenda ion desc ibes an in e ace in which he code wo ds ha desc ibe he ideo signal a e ansmi ed in he o m o eigh bi s a 13.5MHz. This o ces he sys em o compu e a new in e pola ed pixel alue a 27MHz. B. Sys em design wi h XSG Cu en FPGAs inco po a e la ge amoun s o block RAMs esou ces. Pa icula ly, he design is de eloped on he Vi ex-II P o XC2VP30, which con ains 136 block RAMs (BRAMs) and a o al memo y o 2,448 Kb [9]. Each block RAM buil in o he FPGA can be used wi h a con igu able dep h and wid h da a. Due o he sys em equi emen s he design implemen s BRAMs wi h an 8-bi wo d wid h and a pa ame ic memo y dep h (i is adap i e wi h he o ma o he ideo sequence). To de elop he uzzy sys em ha e alua es mo ion and selec s he in e pola ion me hods h ee ield mem- o ies a e equi ed: a i s one o he p e ious ield ( -1), a second one o he cu en ield ( ), and a hi d one o s o e he calcula ed alues o he p e ious ield (see Fig.1(a)). Block memo ies which implemen ield memo ies βi simila i y x y ,,() BB 0 –EE 0 –+ 2 --------------------------------------------- = X0 Xn IT ITγ1X0γ2X+n = γi Fig. 4: (a) Pixels in ol e in he calcula ion o he empo al in e pola o . (b) Rulebase o selec he empo al in e pola o (c) Membe ship unc- ions o he uzzy concep s used in he ulebase. 1 0 SL µsimila i y simila i y (a) (c) B0 E0 X B E ( -1) ( ) Sequence o de X0 9.5 2) simila i y is L IT=Xn 1) simila i y is S IT=X0 i hen 2) simila i y is L IT=Xn 1) simila i y is S IT=X0 i hen 1.5 (b) Fig. 5: Block diag am o he ield memo ies. Each ield memo y p o ides al e na ely he p e ious (whi e box) o cu en (g ey box) ield. CLK DATA ADDR WE EN FIELD MEMORY DATA OUTPUT FIELD MEMORY DATA OUTPUT 46 p 1 24 2 55 33 11 Field ou pu Field ou pu NOT ( -1) and ( ) a e con igu ed in o ‘ ead a e w i e mode’. The implemen a ion is pe o med enabling he w i e mode in one o he ield memo ies, and disabling i in he o he . The e o e, bo h modes a e complemen- a y and his causes ha he cu en ield con inuously changes om one ou pu ield memo y o he o he as shown in Fig.5. A con ol signal is used o iden i y he cu en ield. The implemen a ion o he ield memo y o s o e he in e pola ed pixels is ealized ollowing wo di e - en s a egies. BRMAs and he use o a dis ibu ed memo y, which employs slices o he FPGA. Bo h al e na i es a e p esen ed in Sec ion IV. Fo he wo i s de-in e laced ields, his ield memo y s o es he alues calcula ed by he in e pola o . Fo he es o he ields, he p e iously calcula ed ield is used. XSG ool is in eg a ed in o he Simulink en i on- men . I consis s o a Simulink lib a y, called Xilinx blockse , and so wa e o ansla e a Simulink model in o a ha dwa e ealiza ion o he model desc ibed in VHDL language. Fig.6 shows he XSG design o implemen L membe ship unc ion (see Fig.2). The membe ship unc ions used in he es o ulebases a e implemen ed in a simila way. No e om he ules o he Table in Fig.3(b) ha he an eceden s a e connec ed wi h and connec i es. The minimum ope a o is selec ed o he implemen a ion o hese connec i es. Mode n FPGA de ices also inco po a e embedded mul iplie blocks [9]. The inpu s o hese embedded mul iplie blocks can be up o 18 bi s wide, and he ou - pu up o 36 bi s. They a e op imized o high-speed ope a ions and ha e a lowe powe consump ion com- pa ed o a mul iplie implemen ed in slices. Besides, he use o he embedded mul iplie s lea es ee slices in he FPGA ha can be employed o implemen o he esou ces. Ou design uses wel e o hese mul iplie s o pe o m he exp essions in (3), (4) and (6). The inpu s o he block ha implemen s he uzzy sys em o calcula e , a e aken om he ou pu o he cu en ield memo y ( ). Ten luminance alues a e necessa y o compu e he i e inpu s (a1,a,b,c,c1) o he sys em (see Fig.3(a)). A line bu e and eigh egis e s a e used o achie e he equi ed luminance alues as shown in Fig.7. XSG p o ides wo ways o implemen a line bu e , using delay blocks o speci ic Vi ex-II line bu e s [1]. The delay block is a shi egis e o con igu able leng h. Da a p esen ed a he inpu will appea a he ou pu a e a use speci ied numbe o sample pe iods. The Vi ex-II line bu e block delays a sequen ial s eam o pixels by he speci ied bu e dep h. I is op imized o he Vi ex-II amily since i uses he ‘ ead be o e w i e’ op ion on he unde lying Single Po RAM block. Bo h op ions ha e been used in he design implemen a ion as shown in Sec ion IV. IV. IMPLEMENTATION RESULTS The pe o mance o he p oposed algo i hm has been analyzed by de-in e lacing s anda d ideo sequences. The ideo sequences conside ed ha e widely been used as benchma ks in ideo p ocessing applica ions. The in e laced ideo da a ha e been ob ained om hese p og essi e sequences by elimi- na ing lines. The peak signal- o-noise a io, which is called PSNR, has been employed as igu e o me i o compa e he quali y be ween he ob ained in e pola ed ames and he o iginal ones. I is de ined as ollows: IS Fig. 6: XSG design o implemen he uzzy concep L. Fig. 7: Block diag am o ob ain he en pixel alues shown in Fig.3(a). DATA OUTPUT LINE BUFFER R-1 A1 AC1 F1 R-1 BC R-1 R-1 R-1 D1 D R-1 EF R-1 R-1 IS (7) whe e MSE is he mean squa ed e o be ween he o ig- inal and he econs uc ed image. The p oposed algo i hm has also been compa ed wi h o he de-in e lacing algo i hms wi h less o simi- la compu a ional cos : ou spa ial me hod such as line doubling, line a e age, and con en ional ELA using 3+3 and 5+5 aps; he simples empo al de-in e lacing algo i hm called ield inse ion, and wo e ico- em- po al il e ing wi h wo and h ee ields [2]; and, inally, o he uzzy mo ion adap i e algo i hms epo ed in [10] and [11]. Table 2 shows he a e age PSNR ob ained when de-in e lacing i y ields o se en ideo sequences. As i can be seen, he p oposed algo i hm achie es he be e esul s. All he algo- i hms p esen ed in Table 2 ha e been coded in Ma lab, and hese esul s co espond o i s execu ion using dou- ble-p ecision. This sec ion also con ains implemen a ion esul s in e ms o de ice u iliza ion, ha is, ha dwa e esou ces om FPGA used in he implemen a ion, and also he maximum equency achie ed by he design o compu e a new pixel alue. The XSG blocks which compose he design ha e been de ined using pa ame ic alues, ha is, hei dimensions a e non- ixed and a e con igu ed wi h a - iables om he inpu wo kspace. This p o ides a design wi h a high econ igu abili y deg ee so as o wo k wi h di e en ideo sequence o ma s. Fo ins ance, Table 3 shows a summa y o FPGA u iliza- ion using QCIF (176x144) and CIF (352x288) o - ma s. The designs use Vi ex-II line bu e s blocks o implemen line bu e s and BRAMs o implemen he h ee ield memo ies. As i can be seen in Table 3, he p ocessing o a highe o ma mainly implies a high inc ease o he numbe o BRAMs, whe eas he es o esou ces ise mode a ely. Ob iously, he numbe o embedded mul iplie s used o implemen he exp es- sions (3), (4) and (6) a e he same. Table 4 shows he implemen a ion esul s when he Vi ex-II line bu e blocks a e subs i u ed o delay blocks. This educes he numbe o BRAMs since each line bu e equi es one BRAM a expense o a sligh inc ease in he numbe o slices: 1.23% (QCIF) and 2.58% (CIF). Finally, he ield memo y o s o e he in e pola ed pixel alues is implemen ed using dis ibu ed memo y ins ead o BRAMS. The esul s showed ha his op ion is no e icien since i implies a la ge inc ease o he numbe o slices in o he FPGA. The design o he QCIF o ma almos equi es 90% o slices whe eas he e is no enough slices in o he XC2VP30 FPGA o implemen he algo i hm o he CIF o ma . Finally, implemen a ion esul s o he uzzy sys ems o calcu- la e he spa ial and empo al in e pola o a e shown in Table 5. The algo i hm implemen a ion can be e alua ed om esul s ob ained in he Simulink en i onmen o by modeling he VHDL desc ip ion gene a ed by XSG PSNR 20 255 MSE ---------------- ⎝⎠ ⎛⎞ log = TABLE 2. PSNR alues in (dBs) o di e en de-in e lacing me hods Sequence Fo ma Missa CIF Pa is CIF T e o CIF Salesman CIF News QCIF Mo he QCIF Ca phone QCIF Line Doubling 36.44 23.61 31.05 29.75 25.18 31.81 28.25 Line A e age 40.47 26.67 35.04 33.53 29.25 35.94 32.61 ELA 3+3 39.49 25.53 34.11 32.11 26.63 35.39 32.65 ELA 5+5 38.56 24.64 33.31 30.17 25.92 34.2 31.51 Field Inse ion 38.36 29.86 34.36 36.17 33.13 36.14 30.34 VT 2 ields 40.25 30.73 36.61 36.54 35.46 39.61 34.08 VT 3 ields 40.52 31.37 37.16 36.95 35.67 40.89 34.54 Technique in [10] 40.01 33.12 35.38 37.62 34.73 39.49 32.27 Technique in [11] 40.18 35.28 36.69 38.29 37.51 41.87 34.78 P oposal 40.81 35.87 37.63 38.35 38.78 42.11 35.09 TABLE 3. Implemen a ion esul s in e ms o ha dwa e esou ces o he comple e p oposed algo i hm. The design uses Vi ex-II line bu e s and BRAMs o implemen ield memo ies Fo ma Sequence Numbe o slices Numbe o slices Flips Flops Numbe o 4-inpu look-up ables (LUTs) Numbe o BRAMs Numbe o embedded mul iplie s QCIF 1357 (9.91%) 1505 (5.49%) 1306 (4.76%) 35 (25.73%) 12 (8.82%) CIF 1490 (10.87%) 1550 (5.65%) 1515 (5.53%) 92 (67.64%) 12 (8.82%) wi h he ModelSim ool om Men o G aphics. The a e age PSNR alue o ‘Salesman’ sequence is 37.71 dBs, whe eas o he ‘Mo he ’ sequence is 40.35 dBs. As i can be seen om he esul s in Table 2, e o s a e highe o he ha dwa e implemen a ion because o he algo i hm desc ibed in Ma lab wo ks wi h double-p e- cision numbe s (64-bi s). The design which implemen s he algo i hm com- bines pipeline a chi ec u e wi h a pa allel p ocessing o uzzy ules o accele a e he compu a ion. As esul , a new pixel alues is in e pola ed each 9.61 ns (104.04 MHz). The e o e he design o e comes he iming con- s ain s o eal- ime p ocessing. V. CONCLUSIONS This pape p esen s he ha dwa e implemen a ion o a de-in e lacing algo i hm on a Vi ex-II P o FPGA. The algo i hm uses h ee simple uzzy sys ems o in e - pola e he non- ansmi ed lines o ideo signals. One uzzy sys em is used o decide he con ibu ion o spa- ial ( ) and empo al ( ) in e pola o s acco ding o he p esence o mo ion. O he uzzy sys em is used o calcula e he in e pola o , which is adap i e wi h he exis ence o edges in he image. Finally, he hi d uzzy sys em calcula es he mos adequa e in e pola o . The h ee uzzy sys ems u ilize simple uzzy ulebases, which a e implemen ed in pa allel o accele a e he compu a ion. The s a egy o implemen a ion employs pipeline a chi ec u e and p o ides a new in e pola ed pixel in a clock pe iod. As a esul , an e icien imple- men a ion o he algo i hm in e ms o p ocessing ime and ha dwa e cos is achie ed. REFERENCES [1] Xilinx Inc., “Xilinx Sys em Gene a o o DSP ( 9.1.01) Use ’s Guide”, Ma ch 2007. Web add ess o download: h p://www.xilinx.com/suppo /sw_manuals/sysgen_ug.pd . [2] G. de Haan and E. B. Belle s, “De-in e lacing: an o e iew,” in P oc. o he IEEE, Sep. 1998, pp. 1839–57. [3] A. M. Bock, “Mo ion adap i e s anda ds con e sion be ween o ma s simila ield a es,” Signal P ocessing: Image Communica ion, ol. 6, no. 3, pp. 275–80, Jan. 1994.. [4] P. B ox, I. Ba u one, S. Sánchez-Solano, J. Gu ié ez-Ríos and F.Fe nández-He nández, “A uzzy edge-dependen mo ion adap i e algo i hm o de-in e lacing,”Fuzzy Se s and Sys ems. Special Issue: Image P ocessing, ol. 158, no. 3, pp. 337–347, Feb. 2007. [5] P. B ox, I. Ba u one and S. Sánchez-Solano, “A uzzy mo ion adap i e algo i hm o in e laced- o-p og essi e con e sion,” in P oc. o In o ma ion P ocessing and Man- agemen o Unce ain y in Knowledge-Based Sys ems (IPMU), Jul, 2006. [6] P. B ox, I. Ba u one and S. Sánchez-Solano, “Fuzzy mo ion adap i e algo i hm o ideo de-in e lacing,” in P oc. o In e na ional Con e ence on Knowledge-Based and In elli- gen In o ma ion and Enginee ing Sys ems (KES), Oc , 2006. [7] P. B ox, I. Ba u one and S. Sánchez-Solano, “A uzzy edge-dependen in e pola ion algo i hm,” in So Compu ing in Image P ocessing: Recen Ad ances. Heidelbe g, Ge - many. Sp inge , 2007. [8] Xilinx Inc., “Xilinx Uni e si y P og am Vi ex-II P o De el- opmen Sys em UG069 ( 1.0)”, Ma ch 2005. h p://www.xilinx.com/uni /xup2 p.h ml [9] Xilinx Inc., “Vi ex-II P o and Vi ex-II P o X FPGA Use Guide UG012 ( 4.1)”, Ma ch 2007. Web add ess o down- load: h p://www.xilinx.com/b docs/use guides/ug012.pd [10]D. Van de Ville, W. Philips and I. Lemahieu, “Fuzzy-based mo ion de ec ion and i s applica ion o de-in e lacing,” in Fuzzy echniques in image p ocessing. Book Se ies o S ud- ies in Fuzziness and So Compu ing, 2000. [11]J. Gu ié ez-Ríos, F. Fe nández-He nández, J. C. C espo and G. T e iño, “Mo ion adap i e uzzy ideo de-in e lacing me hod based on con olu ion echniques,” in P oc. o In o - ma ion P ocessing and Managemen o Unce ain y in Knowledge-Based Sys ems (IPMU), Jul, 2004. TABLE 4. Implemen a ion esul s in e ms o ha dwa e esou ces o he comple e p oposed algo i hm. The design uses delays blocks o implemen line bu e s and BRAMs o implemen ield memo ies Fo ma Sequence Numbe o slices Numbe o slices Flips Flops Numbe o 4-inpu look-up ables (LUTs) Numbe o BRAMs Numbe o embedded mul iplie s QCIF 1526 (11.14%) 1855 (6.77%) 1294 (4.72%) 32 (23.52%) 12 (8.82%) CIF 1843 (13.45%) 2271 (8.27%) 1506 (5.49%) 89 (65.44%) 12 (8.82%) ISIT IS IT TABLE 5. Implemen a ion esul s in e ms o ha dwa e esou ces o he uzzy sys ems o calcula e he spa ial and empo al in e pola o In e pola o Fo ma Sequence Numbe o slices Numbe o slices Flips Flops Numbe o 4-inpu LUTs Numbe o embedded mul iplie s Spa ial QCIF 579 (4.22%) 659 (2.41%) 639 (2.33%) 6 (4.41% Spa ial CIF 721 (5.27%) 1073 (3.92%) 1016 (3.71%) 6 (4.41%) Tempo al QCIF 72 (0.52%) 64 (0.23%) 58 (0.21%) 2 (1.47%) Tempo al CIF 72 (0.52%) 64 (0.23%) 58 (0.21%) 2 (1.47%)