Hardware Implementation of Differential Oscillatory Neural Networks Using VO 2-Based Oscillators and Memristor-Bridge Circuits

fnins-15-674567 July 12, 2021 Time: 17:47 # 1 ORIGINAL RESEARCH published: 16 July 2021 doi: 10.3389/fnins.2021.674567 Edited by: Georgios Ch. Sirakoulis, Democritus University of Thrace, Greece Reviewed by: Can Li, The University of Hong Kong, Hong Kong Alon Ascoli, Technische Universität Dresden, Germany *Correspondence: Bernabé Linares-Barranco [email protected] Specialty section: This article was submitted to Neuromorphic Engineering, a section of the journal Frontiers in Neuroscience Received: 01 March 2021 Accepted: 15 June 2021 Published: 16 July 2021 Citation: Shamsi J, Avedillo MJ, Linares-Barranco B and Serrano-Gotarredona T (2021) Hardware Implementation of Differential Oscillatory Neural Networks Using VO2-Based Oscillators and Memristor-Bridge Circuits. Front. Neurosci. 15:674567. doi: 10.3389/fnins.2021.674567 Hardware Implementation of Differential Oscillatory Neural Networks Using VO2-Based Oscillators and Memristor-Bridge Circuits Jafar Shamsi, María José Avedillo, Bernabé Linares-Barranco*and Teresa Serrano-Gotarredona Instituto de Microelectrónica de Sevilla (CSIC), Universidad of Sevilla, Seville, Spain Oscillatory Neural Networks (ONNs) are currently arousing interest in the research community for their potential to implement very fast, ultra-low-power computing tasks by exploiting specific emerging technologies. From the architectural point of view, ONNs are based on the synchronization of oscillatory neurons in cognitive processing, as occurs in the human brain. As emerging technologies, VO2and memristive devices show promising potential for the efficient implementation of ONNs. Abundant literature is now becoming available pertaining to the study and building of ONNs based on VO2 devices and resistive coupling, such as memristors. One drawback of direct resistive coupling is that physical resistances cannot be negative, but from the architectural and computational perspective this would be a powerful advantage when interconnecting weights in ONNs. Here we solve the problem by proposing a hardware implementation technique based on differential oscillatory neurons for ONNs (DONNs) with VO2-based oscillators and memristor-bridge circuits. Each differential oscillatory neuron is made of a pair of VO2oscillators operating in anti-phase. This way, the neurons provide a pair of differential output signals in opposite phase. The memristor-bridge circuit is used as an adjustable coupling function that is compatible with differential structures and capable of providing both positive and negative weights. By combining differential oscillatory neurons and memristor-bridge circuits, we propose the hardware implementation of a fully connected differential ONN (DONN) and use it as an associative memory. The standard Hebbian rule is used for training, and the weights are then mapped to the memristor-bridge circuit through a proposed mapping rule. The paper also introduces some functional and hardware specifications to evaluate the design. Evaluation is performed by circuit-level electrical simulations and shows that the retrieval accuracy of the proposed design is comparable to that of classic Hopfield Neural Networks. Keywords: oscillatory neural networks, relaxation oscillators, coupled oscillators, vanadium dioxide, memristor, Hopfield Neural Network, associative memory Frontiers in Neuroscience | www.frontiersin.org 1July 2021 | Volume 15 | Article 674567 fnins-15-674567 July 12, 2021 Time: 17:47 # 2 Shamsi et al. Hardware Implementation of Differential ONNs INTRODUCTION Brain efficiency in cognitive processing relies on an architecture made up of distributed processors (neurons) and memories (synapses). Inspired by this brain architecture, novel cognitive processing paradigms are now being developed which go beyond the Von Neumann model. In addition to architecture, the devices employed also play a significant role in power and area efficiency. In this regard, emerging low power and compact devices constitute alternative resources useful for developing efficient cognitive processors. Synthetic neural networks (NNs) have been under development for more than 50 years. Different types of NNs have been introduced, differentiated by their neuron types and data representation. Examples include classic artificial neural networks (ANNs) (Jain et al., 1996), spiking neural networks (SNNs) (Paugam-Moisy and Bohte, 2012), and oscillatory neural networks (ONNs) (Izhikevich, 1997). In classic ANNs, neurons are the simplest biological computing units that accumulate weighted input values prior to the application of an activation function to obtain the output value. In these neural networks, data representation is based on binary or real numbers. In SNNs, which have more biological features, spiking neurons receive and generate spikes, the spiking time or frequency of which is exploited for processing. In ONNs, an oscillator acts as a neuron, and the oscillator phase is the main characteristic used for processing. Like coupled oscillators, neurons process information by synchronizing. It has been hypothesized that synchronization plays an important role in cognitive processing (Gupta et al., 2016). Similarly to synapses, coupling functions describe the connections between the oscillators (Stankovski et al., 2015). A coupling function determines how one oscillator will affect another. With regard to hardware, emerging devices such as vanadium dioxide (VO2) (Velichko et al., 2017) and memristors (Strukov et al., 2008) make it feasible to implement oscillators and coupling functions efficiently. VO2devices have been exploited to design compact nano-scale, low power oscillators (Parihar et al., 2015; Shukla et al., 2015;Velichko et al., 2017;Raychowdhury et al., 2019;Corti et al., 2020a). A basic VO2oscillator circuit can be made by a series connection of a VO2device and a resistor or a CMOS transistor (Corti et al., 2020b). As coupling components, resistors and/or a capacitors are typically used to interconnect the oscillators. Resistively and capacitively coupled oscillators have shown their potential for processing tasks, such as image recognition (Corti et al., 2018) or vertex coloring (Weiher et al., 2021). For the case of a pair of VO2oscillators, when a pure resistor is employed for coupling them, increasing the connectivity strength (decreasing the resistance) tends to put the oscillator pair in phase, while for capacitively coupling, increasing the coupling capacitance tends to put the oscillator pair in anti-phase (Parihar et al., 2015). Although parallel resistors and capacitors make it easier to form a different phase difference between a coupled oscillator pair, it is not so easy to adjust the connection strength. Moreover, a capacitor usually consumes a large area of the hardware. For implementing adjustable connections, the memristor is a convenient device (Li et al., 2018; Sung et al., 2018;Camuñas-Mesa et al., 2019), as its non-volatile resistance can be adjusted to the desired value. However, the implementation of negative and zero weights is an issue. One proposed method is to use an extra memristor crossbar array to implement negative weights (Alibart et al., 2013;Molahasani Majdabadi et al., 2020). It is also possible to achieve both in phase and in anti-phase oscillations in a pair of coupled VO2 oscillators using a single resistor as a coupling component (Corti et al., 2020a). In this method, a specific range of resistances (high resistance) puts the oscillator pair in anti-phase, while low resistances puts it in phase. Therefore, high resistance ranges and low resistance ranges could be equivalent to using negative and positive weights, respectively. However, this has only been studied for small size of ONNs, and scaling up to arbitrary size needs further research. Here we propose another method, in which oscillatory neurons are made of pairs of VO2oscillators, coupled to be in anti-phase. This way, each neuron provides two differential outputs in anti-phase, and these differential oscillatory neurons are interconnected with adjustable positive- or negative-weight memristor-bridge circuits (Adhikari et al., 2012;Shamsi et al., 2017) to implement differential oscillatory neural networks (DONNs). First, a differential oscillatory neuron based on VO2 devices is proposed to benefit from its differential outputs with anti-phase signals. The oscillatory neurons’ differential output allows the memristor-bridge circuit to implement positive, negative, and zero weights. Differential oscillatory neurons are then interconnected through memristor-bridge circuits to form a Hopfield-type architecture (Hopfield, 1982) as an associative memory. The synaptic weights are calculated using the standard Hebbian rule and mapped to the memristors’ resistances in the memristor-bridge circuits. Simulation results demonstrate the pattern retrieval capability of the proposed architecture. To the best of our knowledge, this is the first attempt to introduce and implement differential oscillatory neural networks (DONNs). The main contribution of this paper is the integration of differential oscillatory neurons and memristor-bridge circuits to implement DONNs. Our study also introduces several criteria which can be used to evaluate and compare different implementations of ONNs. The rest of the paper is organized as follows. Section “Methods” describes the architecture of DONNs, including a brief introduction to ONNs, VO2devices, and memristors. Section “Differential oscillatory neural networks (DONNs)” looks at circuit designs for DONNs. A differential oscillator neuron is proposed and the memristor-bridge circuit is introduced as an inter-neuron coupling function. The differential oscillatory neurons and memristor-bridge circuits are then combined to implement fully connected DONNs. Section “Evaluation Method” introduces some design specifications as design criteria for evaluating our design, and Section “Results” provides evaluation and simulation results, followed by some conclusions. METHODS Oscillatory Neural Networks An ONN is a dynamic system that comprises weakly connected oscillatory neurons and is described through Frontiers in Neuroscience | www.frontiersin.org 2July 2021 | Volume 15 | Article 674567 fnins-15-674567 July 12, 2021 Time: 17:47 # 3 Shamsi et al. Hardware Implementation of Differential ONNs Ordinary Differential Equations (ODEs) (Izhikevich, 1997; Nakao, 2016). ˙xi=fi(xi)+ n X j=1 wijgij(xi,xj), i=1,2, ..., n(1) where nis the number of the oscillatory neurons and xiis the state vector of oscillatory neuron i(xi∈Rm,m≥2), which is a function of its phase1. Function fi(xi) describes the dynamic behavior of the oscillatory neuron iand is usually formulated using m-dimensional differential equations. Parameter wij is the weight between oscillatory neurons iand j.gij(xi,xj) is the coupling function that shows the effect of oscillatory neuron jon oscillatory neuron i. The weights, wij, and the coupling function, gij(xi,xj), are crucial factors in oscillatory neural networks’ behavior. From the hardware perspective, oscillator function fi(xi) can be implemented using both harmonic and relaxation oscillators. In this paper, a relaxation oscillator based on VO2devices is used. On the other hand, different coupling functions have been introduced in literature, such as a sinus function in the Kuramoto model (Acebrón et al., 2005) and a phase detector in PLL-based oscillators (Hoppensteadt and Izhikevich, 2000). One of the most straightforward coupling functions in terms of implementation is diffusive coupling, where gij(xi,xj)=(xjxi) (Stankovski et al., 2015). The diffusive coupling function is implemented by connecting the oscillatory neuron outputs via resistors (memristors), creating what is known as resistively coupled oscillatory neurons (Corti et al., 2020a). Moreover, using a mapping method, the weights wij are mapped to resistance values Rij. Using VO2-based oscillatory neurons and memristive devices, all elements of an oscillatory neural network can therefore be implemented. The following subsections summarize the main features and models of VO2and memristor devices. Vanadium Dioxide (VO2) Device Model A VO2device2is a two-terminal device based on a phase change material that presents insulator-to-metal (IMT) and metal-to- insulator transitions (MIT) (Velichko et al., 2017). The transition is temperature-driven, caused by the joule heating in the presence of an applied voltage. Increasing the device temperature causes a change from a high resistance (RH) state to a low resistance (RL) state and vice versa. Although the temperature of the device is the main factor that causes the transitions, device behavior is also shaped by the applied voltage. In (Maffezzoni et al., 2015), a SPICE model for VO2devices is introduced where the transitions are related to a high voltage VHand a low voltage threshold VL. When an increasing applied voltage reaches VH, the resistance changes from its high resistance value RH= 1/GLto its low resistance value RL= 1/GH. When a decreasing applied voltage drops below VL, 1Note that this mathematical phase-based representation method results in an overall dynamical description, which ressembles that of traditional non-oscillatory ANNs. 2Although VO2devices are negative differential resistance (NDR) devices, they can also be considered as volatile memristors capable of producing oscillatory circuits (Yi et al., 2018), as done throughout the present paper. a transition from the low resistance state to the high resistance state occurs. The time constant of the transitions is τ. This model is compatible with fabricated VO2devices, making it a reliable model for SPICE simulations. Although it is a compact SPICE model, it makes use of a discontinuous nonlinear function, which may yield convergence problems when simulating large scale circuits. To prevent this problem, we introduce here an equivalent mathematical macro model that uses a continuously differentiable nonlinear function, as follows: ˙g=K τ−g+GH+GL 2+GH−GL 2×S(v,g)(2) where, Sv,g=tanh A.(VH−VL).v−VL VH−VL −g−GL GH−GL (3) Variables gand vare the conductance and voltage of the VO2 device, respectively. Parameter Ais a large constant value, and the other parameters are the main parameters of a VO2device. Parameter Kis a fitting parameter to match this mathematical model with the original SPICE model. A basic circuit of a VO2-based oscillator was simulated to compare the proposed mathematical model with the Maffezzoni SPICE model (see Figure 1A). The differential equation of the circuit is given by: ˙v=1 C.−Gs+gv+Gs.Vdd ˙g=G(g,v)(4) where G(g,v) is given by the right-hand expression in Eq. (2). Figure 1B shows the simulation results of the proposed mathematical model matching very well with Maffezzoni’s SPICE model. Memristor Model A memristor is a two-terminal resistive device whose resistance is adjustable. It is typically used as an analog memory that can be both non-volatile or volatile (Ohno et al., 2011;van den Hurk et al., 2014;La Barbera et al., 2015;Wang et al., 2017;Ascoli et al., 2021). In addition, the adjustability of non-volatile memristors and their nanoscale size make them attractive candidates to implement massive adjustable synaptic circuits, especially with crossbar structures. In some models, the memristor behavior is described by using one positive and one negative threshold voltages (−| Vn| and Vp) (Ascoli et al., 2013;Krestinskaya et al., 2020). In memristors with counterclockwise switching, when the applied memristor voltage is larger than the positive threshold voltage Vp, the resistance of the memristor decreases. On the contrary, in memristors with clockwise switching, applying a voltage larger than Vpcauses an increase in resistance, while the resistance decreases when the applied voltage is less than −|Vn| (Min and Cho, 2021).With an applied voltage between −|Vn| and Vp, the resistance remains constant. The operational phases of a memristor are usually known as programming and operating phases (Shamsi et al., 2018). In the programming phase, the amplitude of each positive (negative) Frontiers in Neuroscience | www.frontiersin.org 3July 2021 | Volume 15 | Article 674567 fnins-15-674567 July 12, 2021 Time: 17:47 # 4 Shamsi et al. Hardware Implementation of Differential ONNs FIGURE 1 | (A) A basic oscillator circuit. (B) Simulation of the basic oscillator with Maffezzoni’s SPICE model and the proposed mathematical model. The simulation parameters are VH=2,VL=1,RL=1k,RH= 100 k,τ= 30 ns, and K= 6. voltage pulse, applied across the memristor, is set to some predefined value larger than the modulus of the memristor threshold voltage Vp(| Vn|). Depending on the number, polarity, height and width of the pulses, the resistance is adjusted. On the other hand, in the operating phase, the maximum and minimum peaks of the pulses are within the intervals between the upper and lower threshold voltages, so there is no resistance change. This paper focuses on the operating phase of the memristor as a non-volatile synaptic circuit. We thus consider a memristor as a constant resistor, and weights are mapped to the resistance values. Consequently, throughout this paper we consider that memristor terminal voltages never exceed the threshold voltages. Resistance range and threshold voltages are closely related to the materials used in memristor fabrication (Hadiyawarman et al., 2018), which therefore constitute important factors for memristor-based circuit designs. In this paper, the threshold voltages and the resistance ranges are assumed to meet the needs of our design. Specifically, we assume that maximum voltages across the memristors are never larger than the high threshold voltage VHof the VO2devices. Also, some relations for defining a valid range of resistances are introduced in subsection “Circuit Design Method.” Differential Oscillatory Neural Networks (DONNs) In this study, differential oscillatory neurons and memristorbridge circuits are combined to implement a fully connected DONN, similar to a classic (non-oscillatory) Hopfield neural network. The proposed neural network circuit, shown in v 1 v 2 v 3 v ... ab cd +- a b c d + - + - + - + - v p N v N n N FIGURE 2 | Hardware architecture of the fully connected DONN. Differential neurons are implemented with a pair of VO2oscillators, oscillating in anti-phase. Synapses are implemented using memristor-bridge circuits. Figure 2, is used as an associative memory. The following subsections describe the differential oscillatory neurons and memristor-bridge circuits used as the basic blocks of the DONN. Differential Oscillatory Neuron Circuit Figure 3A shows the circuit of the proposed differential oscillatory neuron which generates two anti-phase signals. It comprises two single-ended oscillators connected to each other through a capacitor. The coupling capacitor forces the singleended oscillators to be in anti-phase, in which they produce differential signals. To get anti-phase waveforms, the coupling capacitor Cc should be much lower than C(Cc < < C) Frontiers in Neuroscience | www.frontiersin.org 4July 2021 | Volume 15 | Article 674567 fnins-15-674567 July 12, 2021 Time: 17:47 # 5 Shamsi et al. Hardware Implementation of Differential ONNs FIGURE 3 | (A) Proposed differential oscillatory neuron (Cp=Cn=C). (B) Simulation of the differential oscillatory neuron with power-on delay initialization; The positive and negative voltage sources were applied at t=2.5 µs and t=3µs, respectively. Bottom figure shows the current through the capacitors. (Parihar et al., 2015). However, when Cc > > Cthe outputs tend to be in phase. In addition, when Cc =Cthe output signals do not increase monotonically causing distorted output signals (Parihar et al., 2015). The following equations describe the dynamics of the differential oscillatory neuron. ˙vp=1 C+CC−Gs+gpvp+CC.˙vn+Gs.Vdd ˙vn=1 C+CC−Gs+gnvn+CC.˙vp+Gs.Vdd ˙gp=Ggp,vp ˙gn=Ggn,vn (5) where indexes pand nindicate the corresponding branch pand n, respectively. The starting point for exploiting a DONN is the initialization phase, in which an input pattern is applied to the DONN. The power-on delay method can be used to initialize the differential oscillatory neuron (Corti et al., 2020b). In this method, the power supplies of the single-ended oscillator branches are applied in a power-on sequence with a specific delay. Given an input value, the power supply is applied to one of the branches first, and then, after a given time, to the second branch. For binary values, the delay time should be half of the oscillators’ period. For instance, when the binary value is 1, the power supply is applied to the positive branch first, and then, after one half period, to the negative branch. Figure 3B shows the simulation results of a differential oscillatory neuron for which the period is 1 µs and the delay between the applied power supplies is 0.5 µs. The output voltages are anti-phase shown in the middle of Figure 3B. In our design, parameters C,CC, Rs,and Vdd were calculated using relations that satisfy the operating conditions of the DONN circuit (see subsection “Circuit Design Method”). Some relations are necessary to ensure the VO2devices are biased in their negative resistance region to guarantee the respective branches perform as oscillators. Using these relations, parameters Rs and Vdd are calculated. Other relations are used to calculate parameters Cc and C. Details of the operating conditions are provided in subsection “Circuit Design Method.” Synaptic Memristive-Bridge Circuit As an analogy of the Wheatstone bridge, the memristor-bridge is introduced to implement a synaptic circuit capable of providing Frontiers in Neuroscience | www.frontiersin.org 5July 2021 | Volume 15 | Article 674567 fnins-15-674567 July 12, 2021 Time: 17:47 # 6 Shamsi et al. Hardware Implementation of Differential ONNs + v 1 - + v2 - R 1 R 2 R 3 R 4 vp vn i i vp vn j j gd ij g d ij gc ij g c ij A B FIGURE 4 | (A) Memristor-bridge circuit. (B) Equivalent circuit of two differential oscillatory neurons coupled through one memristor-bridge circuit. positive, negative, and zero weights (Figure 4A;Adhikari et al., 2012). Being a four-terminal circuit makes it appropriate for differential structures. However, it is also used in single-ended neural networks (Jackson et al., 2016;Shamsi et al., 2017). Figure 4B shows the equivalent circuit with two differential oscillatory neurons coupled by the memristor-bridge circuit. The following conditions are required to implement a symmetric coupling function. gd ij =1 R1 =1 R4 (6) gc ij =1 R2 =1 R3 (7) where superscript dstands for “direct” path (positive with positive or negative with negative), while superscript cstands for “crossed” path (positive with negative, and vice versa). Conductance gd ij is located between the positive branches (negative branches), tending to put positive branches (negative branches) in phase. When the positive branches (negative branches) are in phase, then the two differential oscillatory neurons are considered in phase. On the other hand, conductance gc ij is located between a positive and a negative branch, thus tending to put them in phase while the positive branches (negative branches) are anti-phase. When the positive branches (negative branches) are anti-phase, then the two differential oscillators are considered as anti-phase. Considering the values of gd ij and gc ij, differential oscillatory neurons tend to be in phase (anti-phase) when gd ij >gc ij (gd ij <gc ij). In this regard, it is possible to implement a coupling circuit with a positive (if gd ij >gc ij), negative (if gd ij <gc ij), or zero (if gd ij =gc ij ) weight. It also worth mentioning that the maximum voltage across a memristor is kept less than VH. Suppose that a memristor is connected to the output nodes of two VO2devices from two distinct differential oscillatory neurons. Therefore, the maximum voltage across the memristor will be | VH−VL|. However, during the initialization Vdd is applied with a delay to a branch that may increase the voltage of one terminal of the memristor up to VH, while the voltage of the other terminal is around zero. Thus, the maximum voltage across a memristor will in general be less than VH. The following subsection reviews the standard Hebbian rule used to calculate the synaptic weights. A mapping method is also introduced to map the synaptic weights to the conductance values gd ij and gc ij . Training and mapping rules A training rule is used to store patterns in neural networks, adjusting the synaptic weights accordingly. Once the weights are known, we propose a mapping rule to obtain the physical resistances for the memristor-bridge synapses. To store patterns in the DONN, we use the Hebbian rule to calculate the weights. wij =1 L P X k=1 bk ibk ji,j∈ {1,2,3, . . . , L}(8) where Pis the number of stored patterns and Lis the number of pixels in each pattern (which is equal to the number of neurons in the DONN). Elements biand bjof all stored patterns are used to calculate the weight wij. We propose here the following rules to map the sign and value of the above weights to the memristors’ resistances. Weights wij are mapped to the gij values using the following relation. Mapvalue :gij =     g0 1+β×P× 1 wij norm ,wij 6= 0 g0 1+β×P,wij =0 (9) where g0is the maximum conductance (inverse the minimum resistance) of the memristors. Parameter βis a small positive value (e.g., 0.2) that controls the mapping range for conductance gij. A larger value for βprovides a larger range for conductance gij. Value 1/wijnorm is the Min-Max normalization of |1/wij|. In order to obtain the Min-Max normalization, the following relation is used.  1 wij norm = 1 wij −min max −min (10) where min and max are the minimum and maximum values of |1/wij|among all non-zero weights, respectively. The following mapping rule was also used to map the weight signs to resistance values gd ij and gc ij. Mapsign :     αgd ij =gc ij =gij,wij <0 gd ij =αgc ij =gij,wij >0 αgd ij =αgc ij =gij,wij =0 (11) where α>1 is a constant value. The design parameters of the memristor-bridge are wij,α, β, and g0. Parameter g0will be obtained based on correctly Frontiers in Neuroscience | www.frontiersin.org 6July 2021 | Volume 15 | Article 674567 fnins-15-674567 July 12, 2021 Time: 17:47 # 7 Shamsi et al. Hardware Implementation of Differential ONNs Cc VO2 Rs VDD C VO2 Rs VDD C i CC × (N-1) VO2 Rs VDD C VO2 C × (N-1) gij VO2 Rs VDD C × (N-1) gij vj Cgvo2(N-1)× gij Gs VDD × gs(N-1)gij× v j i C i C X v p v n ii ABC D FIGURE 5 | Simplification of the DONN. (A) The DONN from the viewpoint of one of the differential oscillatory neurons connected to the other (N−1) ones. (B) The circuit as simplified by ignoring the current iCC, and assuming that the oscillatory neurons are either in phase or in anti-phase. (C) Replacement of the (N−1) oscillatory neurons with voltage sources. (D) Norton equivalent of the simplified circuit. functioning hardware, as explained next in subsection “Circuit Design Method.” Section “Results” then illustrates how the DONN performance depends on parameters αand β. Circuit Design Method As a starting point, design relations are extracted to calculate circuit parameters by analyzing the fully connected DONN circuit (Figure 2). Figure 5A shows the circuit from the viewpoint of a single differential oscillatory neuron coupled to other (N−1) differential oscillatory neurons. The dynamics of the former differential oscillatory neuron is described by: ˙vp i=1 C+CCh−Gs+gp ivp i+CC.˙vn i+Gs.Vddi+ N P j=1 ip ij ˙vn i=1 C+CCh−Gs+gn ivn i+CC.˙vp i+Gs.Vddi+ N P j=1 in ij ˙gp i=Ggp i,vp i ˙gn i=Ggn i,vn i (12) Where ip ij and in ij are the currents from oscillatory neuron jto the positive and negative branch of oscillatory neuron i, respectively: ip ij =gd ij(vp j−vp i)+gc ij(vn j−vp i) in ij =gc ij(vp j−vn i)+gd ij(vn j−vn i)(13) In order to guarantee that each VO2device branch operates as an oscillator, the following condition is imposed: •Each VO2device operates in its negative resistance region: VMax >VHand Vmin <VL, where VMax (Vmin) is the maximum (minimum) output voltage if IMT (MIT) does not occur in the VO2device. This condition guarantees that the voltage of the oscillators do not reach stable points, resulting in permanent oscillation (Raychowdhury et al., 2019). The DONN circuit is analyzed next to extract relations for VMax and Vmin. For the analysis, and to simplify the circuit, some assumptions are considered. First, we consider a single point for analysis where the voltage of the positive branch of a differential oscillatory neuron is either at its maximum or minimum value. Regarding the assumption C>> CC, the share of current iCC in the total current iCis considered negligible. For instance, the current of capacitor C (in positive and negative branches) and CCare shown at the bottom of Figure 3B. When the voltage of the positive branch is at its maximum value, immediately before the jump, the current through capacitors Cpand CCare 71 and 7.5 µA, respectively. Also, when the voltage of positive branch is at its minimum value, immediately before the jump, the current through capacitors Cpand CCare 686 and 76 µA, respectively. Thus we omit capacitor Cc. It is also assumed that the differential oscillatory neurons with respect to each other are either in phase or in antiphase. When two differential oscillatory neurons are in phase, the voltage of their positive branches (negative branches) is equal. Therefore, the current through the memristors between the positive branches (negative branches) is zero. Similarly, when in anti-phase, the current through the memristors between a positive and a negative branch is zero, as well. In this regard, the circuit is simplified, as shown in Figure 5B. The simplified circuit is a single-ended oscillator connected to the other (N−1) singleended oscillators. We are also able to replace the (N−1) singleended oscillators with (N−1) voltage sources, which generate the same signals than the respective single-ended oscillators (Figure 5C). The circuit is now simple enough to be analyzed easily. The Norton equivalent circuit is shown in Figure 5D. We use next some worst-case operating conditions to extract design relations. In other words, relations are extracted for the most difficult operating conditions to ensure that the calculated parameters are valid for all conditions. Frontiers in Neuroscience | www.frontiersin.org 7July 2021 | Volume 15 | Article 674567 fnins-15-674567 July 12, 2021 Time: 17:47 # 8 Shamsi et al. Hardware Implementation of Differential ONNs Consequently, parameters GH,GL,VH, and VLare used in the analysis so that the worst-case conditions are satisfied. In this regard, the maximum (minimum) voltage at node Xin Figure 5D is obtained for the charging (discharging) period. Then, parameters GH,GL,VH, and VLare used to find the minimum (maximum) voltage of the charged (discharged) capacitor after the charging (discharging) period, which should be larger (smaller) than VH(VL). It worth mentioning that IMT (MIT) in VO2devices occurs before reaching the maximum (minimum) voltage of the capacitor/VO2devices, consequently causing permanent oscillation. Vp Max =GsVdd +g(N−1)VL Gs+GL+(N−1)g>VH(14) Vp min =GsVdd +g(N−1)VH Gs+GH+(N−1)g<VL(15) These relations are used to calculate the values for GSand g0. In this regard, we first use relations with N= 1 to find a range for Gs and a value in this range is selected for Gs. Afterward, using the same equations with the selected value of Gs and the number of differential oscillatory neurons N, a range for gis obtained. The maximum value of this range is used as g0. Finally, we substitute all parameters in the equations to verify whether the selected values are valid. Otherwise, the same procedure is repeated with a new value for Gs. The values for Cand CCare other design parameters that need to be considered. It is worth mentioning that a large coupling capacitance value provides strong coupling. On the other hand, a large value for the Cc/C ratio causes degradation of the waveform shapes, resulting in deviations from ideal anti-phase waveforms for differential oscillatory neurons (Parihar et al., 2015). Strong coupling therefore has to be traded off against ideal anti-phase waveforms. In this paper, the following relation between Cand CCis used. Cc≈0.1×C(16) Also, the oscillator period relation is used to calculate Cand CC (Corti et al., 2020a). T=C∗× 1 GL+Gsln Vmax −VL Vmax −VH +1 GH+Gsln Vmin −VL Vmin −VH (17) where Vmax =GsVdd GL+Gsand Vmin =GsVdd GH+Gs. Parameter C∗is the capacitance at the output nodes of the differential oscillatory neurons and is approximately considered as C∗≈C+Cc. In the relations mentioned earlier, the input parameters were Vdd (voltage supply of the circuit), VH(high threshold voltage of the VO2device), VL(low threshold voltage of the VO2device), GH (high conductance value of the VO2device in the metallic state), GL(low conductance value of the VO2device in the insulator state), and N(the number of neurons in the neural network). Functional Retrieval Rate Synchronization level Stability rate Convergence cycle Hardware Area overhead Power consumption Frequency FIGURE 6 | Functional and hardware specifications for evaluating the design. Evaluation Method Figure 6 shows the specifications used to evaluate our design. These specifications are classified into two categories: functional and hardware specifications. The functional specifications are defined as follows: •Retrieval rate is defined as a value in the range of [0 1] that shows the ratio of correct retrieved patterns to all applied patterns: RET =#correct retrived patterns #all patterns (18) •Synchronization level is defined to measure how many differential oscillatory neurons (neurons3) are synchronized either in phase or in anti-phase. For an input pattern p, the synchronization level is a value in the range of [0 1] that is related to the average deviations between synchronized signals in a period c: SYNp(c)=<1 N N X i=1 m(PTi(c)−PTref (c)) > (19) The SYNp(c) value shows the synchronization level at cycle c, which is related to the time difference between the peak time of signal iat cycle c,PTi(c), and the peak time of the reference signal PTref (c) (the signal of positive branches vp iare used for calculations). Function m = m(1t) maps a time difference 1tto a value between 0 to 1 (see Figure 7). It is worth mentioning that time difference 1tis equivalent to phase difference. According to function m(), synchronization level SYNp(c) is maximum when the neurons are either in phase (1t = 0 or 1t = ±T) or in anti-phase (1t = ±T/2). When the neurons are not exactly in phase or in anti-phase, a value less than 1 is assigned depending on the phase difference. For instance, the worst case in terms of synchronization corresponds to the phase difference T/4. •Stability rate is defined as a value in the range of [0 1] which is the number of applied patterns resulting in stable outputs divided by all applied patterns: STB =#patterns resulting in a stable output #all patterns (20) 3In the following, the word “neuron” is used for “differential oscillatory neurons.” Frontiers in Neuroscience | www.frontiersin.org 8July 2021 | Volume 15 | Article 674567 fnins-15-674567 July 12, 2021 Time: 17:47 # 9 Shamsi et al. Hardware Implementation of Differential ONNs FIGURE 7 | Function m = m(1t) used to map a time difference to a value between 0 and 1. Output stability for an applied pattern is defined based on the average SYNp(c) for all signals in the last few cycles. When this average value is larger than 0.9, the output is considered as a stable output. •Convergence cycle is defined as the number of cycles 9 required to converge to a pattern: CON =9(21) where, SYNp(9)>0.9×Max∀c>9{SYNp(c)}(22) When the output converges to a pattern, the synchronization level is larger than 90% of the maximum synchronization level in subsequent cycles. In addition to the functional specifications, some hardware specifications are also considered to evaluate the design, such as power consumption per neuron, frequency, and area overhead. RESULTS This section describes the evaluation of the design. A DONN with 15 neurons is first simulated to show how DONNs work4. A comprehensive evaluation is then provided to show the performance of DONNs. Operation of a DONN A DONN with N= 15 neurons (differential oscillatory neurons) was designed to illustrate the concepts underlying the functional specifications and operation of the DONN. The design relations Eqs. (14)-(17) and the input parameters (the number of neurons N, oscillation frequency f, supply voltage Vdd, and VO2parameters) were used to calculate the circuit parameters. First, Eqs. (14)-(15) were used to calculate values for g0and Gs. The values for Cand CCwere then computed using relations Eqs. (16)-(17). After that, the synaptic weights were calculated with the standard Hebbian rule to store the three patterns shown in Figure 8A. Each pattern has 15 pixels and each pixel value at any time is represented by the phase of one of the 15 neurons (each made of two physical VO2 oscillators in antiphase) with respect to the reference neuron. The rules in Eqs. 4A presentation with a general overview of DONN is provided in the Supplementary Material section. (9) and (11) were then used to map the weights to the physical synaptic resistance with α= 1.8 and β= 0.2. A summary of the parameters for this design is shown in Table 1. Figure 8B shows simulation results for an applied input pattern. The voltage of the positive branches can be seen in the top sub-figure. Input patterns are applied by setting a specific initial phase for each neuron. The initial phases of the neurons were set by powering up first the positive branch and then the negative branch of each neuron associated to the white pixels. In contrast, for black pixels, the positive branch was powered up after the negative branch. On the other hand, in order to extract the value of pixel i(or neuron i) for a specific cycle, the time difference between the voltage peak of the positive branch in neuron iwith respect to a reference voltage peak (e.g., the voltage of the positive branch in neuron 1) is measured. For each neuron, if the time difference is zero (half of the period), then a white (black) pixel value is assigned. In Figure 8B (bottom figure) the 1st cycle pattern (which is not among the stored patterns in Figure 8A) is shown. It can be seen that it resembles the input pattern. The same figure also shows the synchronization level during the convergence period. The minimum synchronization level corresponded to a moment in which the deviation between the signals was maximum. The maximum synchronization level occurred when the neurons were either in phase or in anti-phase. The convergence cycle for this pattern was 15 cycles. Figure 8C shows another simulation of unstable neural network behavior in which the mapping parameter αwas a large value (α= 106). For this value, gc ij (gd ij) was a negligible value for positive (negative) weights (see the mapping rule). For zero weights, gc ij and gd ij were negligible values in comparison to g0and memristors can be considered as open circuits. The simulation results show that the output was unstable for the input pattern (Figure 8C). The synchronization level changed periodically, and the evolution of the pattern shows that the retrieved pattern periodically changed from one pattern (pattern 0) to another (pattern 2). Performance of DONNs The DONN was evaluated with different numbers of neurons Nusing random orthogonal or semi-orthogonal patterns. The hamming distance between orthogonal patterns is exactly half the length of the patterns (number of neurons), while, for Frontiers in Neuroscience | www.frontiersin.org 9July 2021 | Volume 15 | Article 674567