High-voltage compliant neurostimulator with on-chip power management in standard CMOS technology

High-Voltage Compliant Neurostimulator With On-Chip Power Management in Standard CMOS Technology Memoria presentada por DAVID PALOMEQUE MANGUT para la obtención del Grado de Doctor por la Universidad de Sevilla. Directores MANUEL DELGADO RESTITUTO ÁNGEL RODRÍGUEZ VÁZQUEZ Tutor ÁNGEL RODRÍGUEZ VÁZQUEZ Sevilla, 2022 Tesis doctoral High-Voltage Compliant Neurostimulator With On-Chip Power Management in Standard CMOS Technology Programa de Doctorado en Ciencias y Tecnologías Físicas Universidad de Sevilla Autor David Palomeque Mangut Graduado en Ingeniería Electrónica y Automática (Rama Industrial) Máster en Investigación en Ingeniería y Arquitectura (Rama Industrial) Director Manuel Delgado Restituto Investigador Científico Instituto de Microelectronica de Sevilla (IMSE) Consejo Superior de Investigaciones (CSIC) Director y Tutor Ángel Rodríguez Vázquez Catedrático de Universidad Departamento de Electrónica y Electromagnetismo Universidad de Sevilla (US) Instituciones Universidad de Sevilla (US) Consejo Superior de Investigaciones Científicas (CSIC) Centro Nacional de Microelectrónica (CNM) Instituto de Microelectrónica de Sevilla (IMSE) | Agradecimientos Acknowledgments La realización unas Tesis Doctoral suela comenzar con mucha ilusión y ganas. Después, llegan el estrés, las jornadas interminables y las alegrías entremezcladas con frustraciones. Al final, si todo va bien, el Doctorando reconoce el gran aprendizaje y el logro que conlleva la realización de una Tesis. Además del trabajo personal llevado a cabo por el Doctorando, en cualquier Tesis hay una dimensión colectiva, una serie de personas sin cuya participación no podría salir adelante el trabajo. En estas líneas reconozco a las personas que han hecho posible esta Tesis Doctoral. Mis logros son, sobre todo, mérito de mis padres, que son una fuente inagotable de apoyo, cariño y comprensión. Ellos me inculcaron la importancia del estudio. Además, durante mi niñez, adolescencia y el principio de mi adultez, se encargaron de que mis únicas preocupaciones fueran crecer como persona y cumplir con mis objetivos académicos y profesionales. Tampoco sería quien soy si no fuera por la influencia de Sergio: mi hermano, colega y amigo, con el que siempre tengo conversaciones muy estimulantes. ¡Gracias a los tres! Esta Tesis también ha salido adelante gracias a Irene, que me ha escuchado, me ha entendido, me ha dado cariño y me ha enseñado otras maneras de ver el mundo. Es, además, una excelente Ingeniera de la que aprendo todos los días. Con ella todo es mucho más fácil. Gracias. La vida tendría poco sentido sin rodearse de buenos amigos, y yo tengo la suerte de contar con Alex, Antonio, Borja A., Borja N., Fidel, Fran, Javi, Jaime, Miguel, Nacho, Nico, Pablo G., Pablo M. y tantos otros. Gracias por las risas y por estar ahí. Agradezco especialmente su apoyo a Jaime, que conoce de primera mano las dificultades del mundo de la investigación y con el que llevo años teniendo grandes conversaciones y pasando muy buenos ratos. Quiero poner en valor también a la comunidad de investigadores/as predoctorales del Instituto de Microelectrónica de Sevilla (IMSE). Aunque la situación mejora progresivamente gracias a colectivos como “FPU Investiga” o “Red de Doctorand@s del CSIC”, en general, el trabajo de un Doctorando no está justamente remunerado ni reconocido. Esto da aún más relevancia al hecho de que los/as investigadores/as predoctorales del IMSE son personas con un enorme conocimiento técnico y que no dudan en invertir horas de su tiempo en ayudar al resto de compañeros y compañeras. Así, esta Tesis no habría sido posible sin Norberto, Franco, Valentín, Antonio, Rubén, Rafa, José Luis y Carlos D. Todos ellos son muy buenos diseñadores de circuitos integrados y mejores colegas. Quiero hacer una mención especial a Norberto, con el que compartí (muchos) momentos de estrés y apoyo mutuo. También quiero agradecer su apoyo y compañerismo a Juan, Pablo P., Manu, Pablo F., Marco, Virginia y Kourosh. Tener buenos supervisores puede facilitar mucho la vida de un Doctorando. Agradezco al Prof. Ángel Rodríguez todas las conversaciones de carácter técnico, docente y formativo que tuvimos durante mi colaboración como docente en una asignatura coordinada por él. Aprendí mucho de ellas. También su labor como Director y Tutor de esta Tesis Doctoral. Agradezco al Dr. Manuel Delgado, Director de esta Tesis Doctoral, su supervisión durante estos cuatro años. Por último, quiero mencionar al Prof. Juan Antonio Leñero, que siempre fue muy amable y del que aprendí sobre fotodiodos CMOS todo lo que se refleja en esta Tesis. I would also like to thank Prof. Alexander Schmid for his supervision when I was a Guest PhD Student at Swiss Federal Institute of Technology Lausanne (EPFL). Besides his kindness in welcoming me into his research group, his guidance in the field of inductive links for neural implants was fundamental for me to having a fruitful stay. I also thank Ph.D. Student Mohammad Javad Karimi for his kindness and for the technical discussions in a field in which he is becoming an expert. Por último, agradezco al Ministerio de Universidades del Gobierno de España la financiación, dentro del programa para la Formación del Profesorado Universitario (FPU), de mi contrato predoctoral durante la mayor parte de esta Tesis (FPU18/00247) y de mi estancia de 3 meses en EPFL (EST21/00407); a la Universidad de Sevilla la financiación, dentro del VI Plan Propio de Investigación, de mi contrato predoctoral durante varios meses; a la USA Office of Naval Research la financiación de los proyectos con referencias N00014-14-1-355 y N00014-19-12156; al Ministerio de Economía, Industria y Competitividad del Gobierno de España la financiación del proyecto con referencia TEC2016-80923-P; y al Ministerio Ciencia e Innovación del Gobierno de España por la financiación del proyecto con referencia PID2019-110410RB-I00. | Abstract This thesis is devoted to the design and development of Application-Specific Integrated Circuits (ASICs) in a standard 1.8V/3.3V CMOS process towards the implementation of a neural stimulator with high compliance voltage, which is a fundamental part of the neural implant that is being developed in this research group. Thus, most of this work deals with circuitlevel and block-level techniques for the design and implementation of highvoltage-tolerant circuits in standard CMOS technologies, in the context of implantable systems. Besides, this thesis preliminary addresses the wireless powering of the neural implant, including: (1) light harvesting with solar cells implemented on a standard CMOS technology and (2) the design and optimization of inductive links for wireless transfer of power and data to/from the neural implant. Two ASICs were designed an fabricated. One includes the neural stimulator front-end and the power management unit. The other implements a CMOS solar cell with a novel stacked-diode configuration. Experimental results of both ASICs are shown and discussed. Summarising: (1) the neural stimulator front-end delivers currents up to 2.08mA and has a compliance voltage of roughly 12.5V; (2) the output voltage of the DC-DC converter in the power management unit ranges from 4.2V up to 13.2V, from a 3V input source; (3) overall peak efficiency is close to 50%; and (4) the measured peak power generation of the CMOS solar cell was around 18 µWmm−2. Regarding the design and optimization of inductive Wireless Power and Data Transfer (WPDT) systems, a topology for the transmission of mW- power and Mbps-data over a single pair of coils was designed and simulated at the block-level. This topology shows promising results towards the implementation of a millimeter-sized wirelessly-powered neural implant with moderate power consumption and moderate data transmission rate. | Contents List of figures i List of tables iii Acronyms v Objectives, contributions, and thesis structure ix 1 Fundamentals of Neural Stimulation 1 1.1 Introduction ............................ 1 1.2 The Electrode-Tissue Interface (ETI) .............. 2 1.2.1 Faradaic and non-faradaic charge transfer ....... 2 1.2.2 Electrochemical reversal ................. 3 1.3 Efficacious and safety of electrical neural stimulation ..... 3 1.4 Optogenetic stimulation ..................... 5 1.4.1 Opsins used in optogenetic neural stimulation ..... 5 1.4.2 Light interaction in cerebral cortex ........... 6 2 Literature Review of Neural Stimulators 9 2.1 An introduction to neural stimulators from an electrical perspective .............................. 9 2.1.1 Types of neural stimulators ............... 9 2.1.2 Optical Neural Stimulators ............... 12 2.2 Literature review ......................... 13 3 Wireless Power and Data Transfer 19 3.1 CMOS photovoltaic cell ..................... 19 3.1.1 Introduction ....................... 19 3.1.2 Photodiode operation .................. 20 vi | vii Acronyms AP Action Potential. 6, 7 ASIC Application-Specific Integrated Circuit. , i, xii, xiii, xv, 13, 68, 69, 79 ASK Amplitude-Shift Keying. 27, 31, 32, 33 CCS Current-Controlled Stimulator. i, 9, 10, 11, 12, 13, 14, 15, 16 CE Counter Electrode. 1, 5 CP Charge-Pump. 36, 37, 40, 41, 42, 43, 44, 52, 54 DAC Digital-to-Analog Converter. , 14, 47, 48, 64, 66, 67 DBS Deep-Brain Stimulation. 1, 5 DDT Downlink Data Transmission. ii, 31, 33 DNL Differential Non-Linearity. ii, 69, 70 DNW Deep N-type Well. 20, 21, 41 ECS Electrical-Cortical Stimulation. 1, 2, 5 ENS Electrical Neural Stimulator. 13, 64 ETI Electrode-Tissue Interface. , i, xi, 1, 2, 4, 5, 10, 13, 14, 16, 35, 61, 62 HCVC High Compliance Voltage Cell. ii, xii, 64, 65, 66, 67, 73 HV High-Voltage. ii, xii, xiii, 16, 36, 59, 63, 64, 74 HV-NSFE High-Voltage Neural Stimulator Front-End. xii, 61, 68, 69, 78 viii HV-SCRC High-Voltage Switched-Capacitor Regulated DC-DC Converter. ii, xii, xv, 35, 36, 43, 44, 45, 46, 47, 51, 52, 53, 54, 58, 64, 68, 69, 72, 73, 78, 79 HV-FLS High-Voltage Floating Level Shifter. ii, 38, 39, 40, 41, 42, 53, 54, 55, 68 INL Integral Non-Linearity. 69, 70 LED Light-Emitting Diode. 12 LSB Least-Significant Bit. 70 LSK Load-Shift Keying. i, 27, 28, 29, 31, 33 LUT Look-Up Table. 51, 52 LV Low-Voltage. xii, 59, 74 MIM Metal-Insulator-Metal. 24, 41, 48 MOM Metal-Oxide-Metal. 37 ND N-type Diffusion. 21, 24 ONS Optical Neural Stimulator. 13 OTA Operational Transconductance Amplifier. 49 PBS Phosphate-Buffered Saline. , iii, 69, 74 PS P-type Substrate. 21 PTAT Proportional To Absolute Temperature. 49 PW P-type Well. 21, 24 SCS Switched-Capacitor Stimulator. 9, 10, 11, 12, 16 SPI Serial-Peripheral Interface. 51 TC Temperature Coefficient. 49, 50 ix UDT Uplink Data Transmission. i, 26, 27, 28, 31, 33 VCO Voltage-Controlled Oscillator. 37, 48, 49 VCR Voltage Conversion Ratio. 35, 36 VCS Voltage-Controlled Stimulator. 9, 10, 11, 12, 16, 17 WE Working Electrode. 1, 5 WPDT Wireless Power and Data Transfer. , i, 14, 19, 25, 26, 27, 28, 30 x | xi Objectives, contributions, and thesis structure This chapter outlines the objectives posed at the beginning of this thesis, the contributions made to fulfill those objectives, and the thesis structure. Objectives Studying neuronal circuits at cellular level for the understanding of brain functions is a challenging endeavor which requires neural interfaces. These neural interfaces perform two tasks. First, they record the neural activity of the target brain area. Second, they stimulate that brain area in order to modulate neural activity. Thus, the efficacy of neural interfaces ultimately depends on their ability to trigger a functional response in the target tissue by inducing a flow of current between two or more electrodes. This is typically done by applying a series of biphasic current pulses with cathodic and anodic phases whose amplitudes and durations are adjusted to result in an overall zero net charge in the tissue. A major concern in the implementation of stimulators is the impedance at the Electrode-Tissue Interface (ETI). Such impedance depends on the geometry and materials of the electrodes; the physiological parameters of the tissue; and the degree of electrical contact at the stimulation zone. Further, the interface is not stationary in nature and the impedance changes throughout the life cycle of the implant. These factors make that the stimulation currents practically range from some tens of µA up to some mA and that the voltage compliance of the current drivers vary from a few volts up to over 10V. The main objective of this thesis was thus the design and development of a neural stimulator with wide stimulation current range and high compliance voltage. xii Besides, the neural interface in which the stimulator shall be included should be highly power efficient for two reasons. First, high power consumption translates to high power dissipation in the form of heat, which is undesirable in the context of implantable systems. Second, the neural interface shall be powered through an wireless power link so as to avoid wires, thus minimizing the risk of infection. The specifications of that wireless power link should be relaxed as much as possible so as to reduce its size and complexity. Another objective of this thesis was to investigate and propose circuit solutions to implement the mentioned high compliance voltage, highly efficient, neural stimulator in a standard 1.8V/3.3V CMOS process. Implementing it in such process instead of using a High-Voltage (HV) CMOS technology was mandatory in order to avoid time-consuming migration of previously designed Low-Voltage (LV) circuitry [1], [2]. Last, this thesis was meant to preliminary explore the possibilities regarding the wireless transfer of both power and data to/from the neural implant by means of inductive links and CMOS solar cells.. Contributions This thesis introduces several innovative solutions both at the circuit-level and block-level in the field of mixed-signal ASIC design, including: • A high-voltage-tolerant versatile charge-pump cell has been designed and implemented. It can operate under three different modes: PUMP, PASS, and DISABLE. This enabled the design of a programmable charge-pump array, which is the core of the proposed High-Voltage Switched-Capacitor Regulated DC-DC Converter (HV-SCRC). • A High-Voltage Neural Stimulator Front-End (HV-NSFE) with roughly 12.5V compliance voltage has been proposed [3]. Circuit-level contributions include a High Compliance Voltage Cell (HCVC) which adapts its equivalent impedance in order to withstand large voltages or act as a closed switch, as needed. • A high-voltage-tolerant floating level-shifter with charge refreshing has been designed [4], [5]. This cell is extensively used in the High-Voltage Neural Stimulator Front-End (HV-NSFE) and the HV-SCRC. Its fundamental features are: high-voltage tolerant operation, tracking of the low-supply rail, and handling of non-periodical input signals. xiii 5 mm (a) (b) 2 mm 5 mm 2.5 mm Figure 1: Microphotographs of two ASICs implemented in this thesis. (a) CMOS solar cell. (b) Neural stimulator. • A novel stacked-photodiode configuration was implemented and characterized. Its use in CMOS solar cells and CMOS image sensors was discussed [6]. • A novel inductive-link topology for the wireless transfer of Mbps-data and mW-power over a single pair of coils has been proposed [7]. It was electrically modeled at the system level. Simulation results have been shown an discussed. Experimental results shown in this thesis were obtained from two ASICs implemented in the TSMC 180nm 1.8V/3.3V CMOS process. On the one hand, Fig. 1(a) shows the microphotograph of the ASIC including a CMOS photovoltaic solar cell, which was characterised to determine if it is feasible to power the neural implant with light harvesting. In Chapter 3, the design and characterization of this ASIC is discussed. Further analysis and experimental characterization were carried out to evaluate the performance of the integrated photodiodes in the context of CMOS image sensors. However, since this lies out of the scope of this thesis, the interested reader is referred to [6] for more insights. On the other hand, Fig. 1(b) depicts the proposed neural stimulator with on-chip HV generation, whose design and implementation are discussed in Chapters 4 and 5. Furthermore, for the experimental validation of the neural stimulator, a complete firmware was developed for the nRF52832 microcontroller: ADC, UART, timers, and SPI modules were used for controlling the neural stimulator and measuring its xiv response, sending commands from a custom MATLAB GUI. The following publications cover most of the material presented in this thesis. • R. Gómez-Merchán, D. Palomeque-Mangut, J. A. Leñero-Bardallo, M. Delgado-Restituto, and A. Rodríguez-Vázquez, «A Comparative Study of Stacked-Diode Configurations Operating in the Photovoltaic Region», IEEE Sensors Journal, vol. 20, n.º 16, pp. 9105-9113, 2020. •D. Palomeque-Mangut, A. Rodriguez-Vazquez, and M. Delgado- Restituto, «A Wide-Range, High-Voltage, Floating Level Shifter with Charge Refreshing in a Standard 180 nm CMOS Process», IEEE 13th Latin America Symposium on Circuits and System (LASCAS), Puerto Varas, Chile, 2022, pp. 01-04. •D. Palomeque-Mangut, A. Schmid, Á. Rodríguez-Vázquez, and M. Delgado-Restituto, «Electrical Model of a Wireless mW-Power and Mbps-Data Transfer System Over a Single Pair of Coils», International Conference on PhD Research in Microelectronics and Electronics (PRIME), Sardinia (Italy), 2022. •D. Palomeque-Mangut, Á. Rodríguez-Vázquez, and M. Delgado- Restituto, «Experimental Validation of a High-Voltage Compliant Neural Stimulator Implemented in a Standard 1.8V/3.3V CMOS Process», accepted at the IEEE Biomedical Circuits and Systems Conference (BioCAS), Taipei (Taiwan), 2022. •D. Palomeque-Mangut, Á. Rodríguez-Vázquez, and M. Delgado- Restituto, «A High-Voltage Floating Level Shifter for a Multi-stage Charge-Pump in a Standard 1.8V/3.3V CMOS Process», accepted for publication at AEU - International Journal of Electronics and Communications, 2022. •D. Palomeque-Mangut, Á. Rodríguez-Vázquez, and M. Delgado- Restituto, «A Fully Integrated, Power-Efficient, 0.07-2.08 mA, High- Voltage Neural Stimulator in a Standard CMOS Process», accepted for publication at Sensors, 2022. •D. Palomeque-Mangut, Á. Rodríguez-Vázquez, and M. Delgado- Restituto, «A 4.2-13.2 V, On-Chip, Regulated, DC-DC Converter in a Standard 1.8V/3.3V CMOS Process», sent to AEU - International Journal of Electronics and Communications, 2022. xv Thesis structure This thesis work is structured as follows: • An introduction to fundamental concepts of neural stimulation is given in Chapter 1. • Chapter 2 discusses the fundamental electrical specifications of neural stimulators and presents a literature review of neural stimulators. • Chapter 3 presents the preliminary work carried out regarding the wireless transfer of power and data to/from the neural implant. First, the designed and implemented CMOS solar cell shown in Fig. 1(a) is discussed, including experimental results. Second, an inductive-link topology over a single pair of coils is proposed. In this case, simulation results are discussed. • In Chapter 4, the proposed HV-SCRC –included in the ASIC presented in Fig. 1(b)– is discussed. Experimental results are also given. • The proposed neural stimulator –i.e. the whole ASIC shown in Fig. 1(b)– is presented in Chapter 5, where experimental results are also shown and discussed. • Finally, Chapter 6 presents the conclusions of the thesis as well as an overview of the possible future works. 6 pulses of blue light can induce single Action Potential (AP) in neurons expressing ChR2. Besides, neural spiking activity can be light-driven with high precision at frequencies up to 30 spikes per second. Opsins with faster temporal kinetics have been developed for applications in which the goal is the extremely fast control of neural activity at high firing rates. Examples of these opsins are ChETA and ChEF/ChIEF [41], [42]. Spectrally shifted opsins Great effort has been put into the development of opsins with an excitation spectra different from blue. With such opsins, independent optical control of different populations of neurons can be achieved. Red-light activated opsins are particularly interesting because 1) the red wavelength interval (635 nm- 700 nm) does not overlap with the blue wavelength interval (450 nm-490 nm) and 2) red electromagnetic radiation enables deeper penetration into the tissue with reduced scattering than blue electromagnetic radiation. Thus, different opsins with red-shifted activation wavelength have been proposed [43], [44]. Opsins for inhibition of neural activity Inhibition of neural activity comprises the hyperpolarization of neuronal membrane in order to suppress AP. NpHR is a widely used halorhodopsin – light-gated ion pump– that hyperpolarize the neuronal membrane by pumping ions into the cell [45]. A series of revision were made in order to improve the performance of this opsin, leading to the development of eNpHR3.0 [46]. eNpHR3.0 has its maximum excitation at 590 nm and it thus can be driven by green, yellow or red light sources. However, there are two limitations when using light-gated pumps for inhibiting neural activity. First, these pumps are less efficient than excitatory channel opsins. In other words, the rate of ions per absorbed photon flowing through the channel is much higher in excitatory opsins than in the inhibitory ones [36]. Second, techniques used to increase the light sensitivity cannot be used in pumps in an efficient manner. 1.4.2 Light interaction in cerebral cortex There is another concern to think about when delivering light to the tissue: irradiance. Light irradiance is defined as the optical power or flux per unit area striking a surface. In this regard, there is a threshold that have to Chapter 1 | 7 be overcome in order to successfully evoke AP. In the case of ChR2, the irradiance threshold is ≈1mWmm−2[47]. When the light radiation strikes the neural tissue, a number of light-medium interactions occur. Thus, light intensity and propagation direction might change [48]. Among these interactions one can find reflection, refraction, absorption, and scattering. Even though the analysis of such interactions is outside the scope of this thesis, it is worth noting that absorption –the conversion of light into heat in the tissue– can lead to an increase in the neural tissue temperature. Since many physiological processes are sensitive to temperature, the amount of irradiance delivered has to be carefully set in order not to unwillingly alter brain function [49]. 8 |9 Chapter 2 Literature Review of Neural Stimulators This chapter introduces some fundamental concepts of neural stimulator from an electrical perspective and presents an analysis of state-of-the-art neural stimulators. 2.1 An introduction to neural stimulators from an electrical perspective In this section, neural stimulators are analysed from an electrical point of view. First, the major approaches for implementing neurostimulators are compared. Second, the importance of compliance voltage is highlighted. Third, particularities of optical neurostimulators are remarked. 2.1.1 Types of neural stimulators Fig. 2.1(a-c) show the three major approaches used for implementing neural stimulators: Voltage-Controlled Stimulator (VCS), Switched-Capacitor Stimulator (SCS), and Current-Controlled Stimulator (CCS). It also shows the load current, Iload, and load voltage, Vload, waveforms obtained during stimulation. In VCS, a stimulation voltage is directly applied to the neural tissue during a certain period of time. Alternatively, in SCS a previously charged capacitor 10 (a) (b) (c) Vstim Rstim Zload Vstim Rstim Cstim Zload Rstim Istim VDD Zload time Iload Vload Vstim Rs Rstim+Rs Vstim Rstim+Rs time Iload Vload Vstim Vstim Rs time Iload Vload VDD xIstim Rs Rstim Vstim Rstim Rstim+Rs Figure 2.1: Conceptual electrical schemes for the major approaches for neural stimulators. (a) Voltage-Controlled Stimulator (VCS), (b) Switched- Capacitor Stimulator (SCS), and (c) Current-Controlled Stimulator (CCS). is discharged through the neural tissue. Last, in CCS the current source draws a certain level of current from the supply voltage to the neural tissue. These approaches can be compared in terms of energy efficiency and precision at charge delivering. For that purpose, efficiency is defined as defined as the power delivered to the load, Pload, divided by the power drawn from the stimulator’s power source, Pstim η=Pload Pstim . (2.1) Besides, precision at charge delivering can be obtained from the definition of charge Qload =!Tstim 0 Iload(t)dt, (2.2) where Tstim corresponds to the stimulation time and Iload(t)is the instantaneous current delivered to the neural tissue. Next, (2.1) and (2.2) are particularized for the three types of electrical stimulators by modelling both the neural tissue and ETI with its electrical equivalent –shown in Fig. 1.1–, Chapter 2 | 11 but considering that Rf→∞for simplicity. The expression of efficiency of VCS is ηVCS =1−1 2 Rstim Rstim +Rs 1−exp "−2Tstim (Rstim+Rs)Cdl # 1−exp "−Tstim (Rstim+Rs)Cdl #≈Rs Rs+Rstim , (2.3) where Rsand Cdl are the extracellular fluid resistance and the doublelayer capacitance, as shown in Fig. 1.1. The approximation is valid for Tstim << (Rstim +Rs)Cdl. Since Rsis usually in the range of some kiloohms, efficiencies above 90% can be obtained for moderate values of Rstim. In the case of SCS, power efficiency is maximum when Cstim is discharged to the load. However, the efficiency when charging Cstim to Vstim is ηSCS =1−1 2 1−exp "−2Tc RstimCstim # 1−exp "−Tc RstimCstim #≈0.5, (2.4) where Tcis the charging time and the approximation holds for Tc>> RstimCstim. Regarding CCS, power efficiency was calculated assuming Rstim →∞for simplicity ηCCS =IstimTstim VDD $Rs+Tstim 2Cdl %. (2.5) Power efficiency in CCS depends on how close VDD is to Vload because the larger that voltage difference the larger the power losses at Istim –as depicted by the shaded region in Fig. 2.1(c)–. It is thus desirable to have a programmable voltage supply, VDD, in order to maximize power efficiency. The charge delivered by a VCS is Qstim,V CS =VstimCdl &1−exp $−Tstim (Rstim +Rs)Cdl %'≈VstimTstim Rstim +Rs , (2.6) where the approximation holds if Tstim << (Rstim +Rs)Cdl. Charge delivered is strongly dependent on Rs. The charge delivered by an SCS is Qstim,SCS =Vstim τSCS Rs&1−exp$−Tstim τSCS %', (2.7) 12 where τSCS =Rs·Cstim·Cdl/(Cstim +Cdl). The expression can be further simplified by assuming that Tstim << τSCS Qstim,SCS ≈VstimTstim Rs , (2.8) which shows that stimulation charge is also highly dependent on Rs. Finally, the stimulation charge in CCS is Qstim,CCS =RstimCdl &1−exp $−Tstim τCCS %', (2.9) where τCCS =(Rs+Rstim)·Cdl. Assuming that Tstim << τCCS Qstim,CCS =Rstim Rstim +Rs IstimTstim, (2.10) which shows that, even with moderate values of Rstim, stimulation charge is highly controlled in CCS. The analysis of these three approaches for electrical stimulation is summarized in Table 2.1. VCS achieves the best power efficiency but charge delivered is load-dependent. SCS has a 50% efficiency but the charge delivered is also load-dependent. Finally, CCS achieves load-independent charge delivery at the cost of a power efficiency which depends on the load, the stimulation current, and the supply voltage. Given these characteristics, most of the neural stimulators found in the literature implement CCS topologies in which most design effort is put into maximizing power efficiency. This thesis intends to make a contribution in this endeavour. 2.1.2 Optical Neural Stimulators Optical neurostimulation is carried out by driving a Light-Emitting Diode (LED) or a laser diode in order to deliver light to neural tissue. In either way, the neurostimulator must deliver a precise and constant light irradiance to Type Efficiency Precision at charge delivering Fully integrable VCS >90% Load-dependent Yes SCS 50% Load-dependent No CCS Load-dependent Load-independent Yes Table 2.1: Qualitative comparison of different electrical neurostimulation approaches. Chapter 2 | 13 1960 1970 1980 1990 2000 2010 2020 Publication year 0 1 2 3 4 5 Number of publications 104 Figure 2.2: Evolution of results appearing in PubMed’s search engine when aggregating results for “neural stimulation” and “neuromodulation”. neural tissue. Thus, they are usually implemented with the CCS approach, as shown in Fig. 2.1(c). Optical stimulation pulses are also delivered at frequencies below 1 kHz, and pulse widths can be well below 100 µs. However, in Optical Neural Stimulators (ONSs) charge balancing is not an issue anymore. Thus, the setting time constraints are less restrictive than in Electrical Neural Stimulators (ENSs). The neural stimulator here presented was designed to comply with electrical stimulation specifications, but it can also be used as an optical neural stimulator. 2.2 Literature review In the last decades, a vast amount of scientific literature related to neuromodulation has been published –see Fig. 2.2–. There is thus a need of implantable devices that health researchers can use for exploring and modulating the brain activity. Mixed-signal ASIC designers have been working on offering solutions for the design and development of integrated circuits that meet this need. In this regard, challenges in the design of cutting edge neural stimulators are: • Charge balance. Biphasic stimulation demands that the charge delivered during both stimulation phases is the same so as to have zero net charge stored at the ETI after a stimulation round [15]. 14 • Compliance voltage. The ETI depends on the geometry and materials of the electrodes; the physiological parameters of the tissue; and the degree of electrical contact at the stimulation zone [15]. Further, the interface is not stationary in nature and the impedance changes throughout the life cycle of the implant. These factors make that the voltage compliance of the neural stimulator front-end varies from a few volts up to over 10V. • WPDT. Wired transmission of power and data should be avoided in order to maximize the safety of the implant. The design of highlyefficient fully-implantable WPDT systems is a challenging topic which is experiencing a great development in the last decade [7], [50]–[57]. • Power efficiency. Power dissipation in the form of heat should be minimized for long-term safety of the implant. Besides, a wirelesslypowered implant should demand as little power as possible in order to relax the specifications of the wireless power supply and expand the autonomy of the implant. Both things depend on increasing neural stimulator’s power efficiency as much as possible. Neural stimulators with programmable power supply have been widely studied in the literature. In the case of CCS, they are usually implemented either with single or dual current sources, as shown in Fig. 2.3. Fundamental parts of these stimulator topology are: the current-steering Digital-to- Analog Converter (DAC), current mirror, switches, and DC-DC converter for generating VDDH. In [58], a CCS with on-chip voltage generator was proposed. It uses a single current source for delivering asymmetrical biphasic pulses. The circuit achieves a 11.5V compliance voltage, but it was implemented in a 180 nm HV CMOS process. Besides, the DC-DC converter has limited programmability and lacks a regulation loop. A high-voltage-tolerant neurostimulator with an on-chip regulated 5-stages charge pump was proposed in [59]. Implemented in a 180 nm 1.8V/3.3V CMOS process, the compliance voltage reaches 10 V. Nonetheless, power efficiency of the solution was not discussed. Besides, the stimulation current is fixed at 30 µA and charge balancing was not tackled. Another CCS with programmable power supply was presented in [60]. Implemented in a standard CMOS process, an on-chip voltage generator provides an adjustable voltage supply from 6.7V up to 12.3V. A dynamic gate biasing circuit that controls the state of some stacked transistors is proposed for having a compliance voltage up to 3×VDD. Nonetheless, the different Chapter 2 | 15 S0S1 VDDH VDD DAC H-bridge Tissue Current mirror Vb Iref SN-1 S 0 S 1 DAC S N-1 S0S1 VDDH (a) (b) VDD Current mirror Vb Vref Iref SN-1 S0S1 SN-1 S 0 S 1 S N-1 S 0 S 1 S N-1 Current mirror Current mirror DAC Tissue Figure 2.3: Current-Controlled Stimulator (CCS). (a) Single current source. (b) Dual current sources. power supplies needed for biasing the H-bridge do not adapt to VDDH. Thus, it is expected that the H-bridge shows a non-negligible on-resistance in situations with small VDDH, leading to lower power efficiency. A slightly different approach was followed in [61], where a Dickson ladder DC-DC converter was implemented to dynamically supply the neural stimulator front-end. The adiabatic solution permits charge recycling but no programmability for disabling unused stages of the Dickson ladder were devised. Besides, there is no regulation loop for locking the output voltage of the DC-DC converter to some reference value. It implements a single current source topology in which a discharging phase can be triggered to 22 Ipd Ipd,1 Ipd,2 Ipd,1+Ipd,2 Vpd Figure 3.3: Current-voltage curves of two parallel diodes operating simultaneously. [6] Operating with (3.3), it is easy to deduce that Voc,double =nUTln   Iph1 Is1 1+Iph2 Iph1 1+Is2 Is1 +1  .(3.4) Comparing (3.2) and (3.4), it is deduced that Voc,double >V oc,single when the ratio between diodes’ photocurrents and specific currents satisfies Voc,double >V oc,single ⇐⇒ Iph1 Iph2 <Is1 Is2 (3.5) The specific current value in an abrupt PN junction is given by this expression [87] Is=qWL $Dppn Lp +Dnnp Ln%,(3.6) where Wand Lare the diode dimensions; Dpand Dnare the holes and electrons diffusion coefficients, respectively; Lpand Lnare the holes and electrons diffusion lengths, respectively; and pnand npand the minority carriers concentration in the P- and the N-regions, respectively. Doping profiles were not disclosed by the foundry. The ratio between the specific currents can be considered constant in the photovoltaic region. Assuming similar doping profiles for the two PN- junctions, Is1>I s2, because D1is larger than D2. Finally, it must remarked that diodes photocurrent values in (3.4) depend on the incident light wavelength: while D2is more sensitive to shorter wavelengths, D1has a sensitivity peak at higher wavelengths [81], [88], [89]. Overall, if technological Chapter 3 | 23 Voc Cint Ipd PD Vth Vpd Vpd Vpd Vth time Cint Cint Ipd Ipd PD (a) (c) (b) Figure 3.4: Integrated test circuits to compare the two diode configurations performance. (a) Test circuit devised to gauge open circuit voltages (Voc). (b-c) Astable oscillator to compare the relative photocurrents values of each diode. [6] parameters are unknown, it is not direct to guess which diode configuration offers higher Voc without a previous experimental characterization. When the two diodes operate simultaneously in the photovoltaic region, the configuration shown in Fig. 3.2(b) is more efficient in terms of current generation. However, there may be situations in which one diode can be forward biased outside the photovoltaic region while the other one still operates in photovoltaic region. Fig. 3.3 shows this case, where the green line represents the total current of two parallel diodes with different I-V curves (blue and red lines). Note that, at Voc, the first diode generates the forward current of the second one. Thus, they can compete between them degrading the performance. Hence, the resultant Voc voltage has to be measured and analyzed to decide which diode configuration performs better. Two circuits were implemented to characterise both photodiode configurations. Fig. 3.4(a) shows a circuit to measure Voc, in which a buffer architecture with low offset, rail-to-rail operation and large current driving capability was chosen [90]. Fig. 3.4(b) shows an astable oscillator that pulses with a frequency proportional, fosc, to illumination [80] fosc ≈Ipd Cint ·Vth ,(3.7) where Cint =Cpd +Cpar accounts for all the parasitic capacitances at the input node of the comparator. Hence, if the two diode configurations gener- 24 (b)(a) 15 μm 0.98 mm 0.3 mm 2.1 mm 2.5 mm 30 μm Figure 3.5: (a) Chip microphotograph. The array of 7800 photodiodes with dimension of 15 µmx15 µm is highlighted in green. The array of 684 Metal- Insulator-Metal (MIM) capacitors with dimension of 30 µmx30 µm is highlighted in blue color. Test circuits depicted in Fig. 3.4 are surrounded by yellow lines. (b) Experimental setup devised to characterize both diode configurations. [6] ate pulses with the same frequency, the double diode is generating a higher current. 3.1.3 Experimental results Fig. 3.5(a) shows a micro-photograph of the test chip implemented in a standard 180nm 1.8V/3.3V CMOS process. It contains (1) an array of 7800 photodiodes –with the configuration shown in Fig. 3.2– with dimensions of 15 µmx15 µm and connected to an array of 684 MIM capacitors with dimensions of 30 µmx30 µm; and (2) test circuits shown in Fig. 3.4(a-b) for characterizing both diode configurations. Fig. 3.5(b) depicts the experimental setup used for the extensive characterization of both photodiode configurations. Fig. 3.6 shows both photodiode configurations’ open-circuit voltage for different illumination levels. For the two diode configurations, Voc depend logarithmically on Iph. Besides, Voc is always higher in the double diode configuration. It can thus be assumed that, for some wavelengths towards blue and green, the ND-PW top diode contributes positively with current Chapter 3 | 25 101102103104105 Illumination (lux) 200 300 400 500 Voc (mV) Single diode Double diode Figure 3.6: Open-circuit voltage, Voc, versus illumination. [6] values that decrease the current ratio Iph1/Iph2, satisfying the condition of (3.5) to achieve a higher Voc. This spectral response is consistent with prior results reported by several authors that have already studied the spectral sensitivity of these diodes separately [81], [88]. Under typical illumination values in indoor environments, Voc ranges between 300 mV and 400 mV. In outdoor environments on sunny days, Voc ∈[410,500] mV. For low illumination values, Voc tends to zero. Fig. 3.7 depicts current measurements performed. Since the light source was close to the chip, their temperature could affect the measurements. To avoid that, temperature was monitored with a thermometer and kept constant at 35,◦C during the experiment. Illuminance on sunny days ranges roughly between 30klux and 100klux, thus the 18 µWmm−2harvested at 79klux serve as a reference value of the amount of power that can be harvested in a standard CMOS process. Given these results, a 20 mm2CMOS solar cell mounted on the external unit of the neural interface might be enough for powering the implanted side when it not in stimulation mode. 3.2 Inductive Wireless Power and Data Transfer (WPDT) system This section is organised as follows. First, an introduction to inductive WPDT is given along with the main limitations of topologies with a single pair of coils. Second, the proposed topology of WPDT system is described. Third, simulation results of an electrical model are shown and discussed. 26 00.1 0.20.3 0.40.5 Photodiode voltage (V) (a) (b) -5 0 5 10 15 20 Power/Area ( W/mm2) 00.1 0.20.3 0.40.5 Photodiode voltage (V) -10 0 10 20 30 40 50 60 Ipd/Area ( A/mm2) 79 klux 39 klux 13.8 klux 0.8 klux Figure 3.7: Measurements on the photodiode array for different illumination values. (a) Current-voltage curves. (b) Power-voltage curves. [6] 3.2.1 Introduction WPDT systems are widely used in many applications such as Near-Field Communication (NFC) systems and Implanted Medical Devices (IMD) [91]– [93]. In the latter, the WPDT subsystem allows the implant to be powered and programmed without the need of wires, thus minimizing the risk of infection. In electrical neuro-modulators, currents from a few hundreds of microamperes up to some milliamperes must be delivered in multiple stimulation sites. Thus, the power demand of the system can range from under 1 mW up to tens of milliwatts. Besides, real time monitoring of neural activity requires sending data from the electrical neuro-modulator to the external unit at rates –i.e. UDT– above 1Mbps. To illustrate how WPDT can be performed over a single inductive link, a simplified system is shown in Fig. 3.8. For the sake of simplicity, the Chapter 3 | 27 V sV 2 1 C C 2 ZLSK RL SLSK L Zref 1 Eind L2 Figure 3.8: Simplified schematic of a resonant inductive WPDT system. Downlink data transfer is performed with ASK by changing the amplitude of Vs. Uplink data transfer is performed with LSK. [7] impedance seen by the secondary side of the inductive link is modelled as a resistance, RL. In such a system, power is transferred from the power source at a frequency fc; UDT is performed with Amplitude-Shift Keying (ASK) by changing the amplitude of Vs; and UDT is performed with LSK. This latter is commonly implemented by switching on and off either a capacitor or a resistor that is placed in parallel to the secondary coil. Finally, it is worth noting that, when implementing WPDT subsystems in IMDs, nearfield electromagnetic induction –or inductive coupling– is preferred over farfield electromagnetic induction because living tissue’s specific absorption rate increases with the frequency of the electromagnetic wave [94]. In such an arrangement, the voltage gain magnitude is ,,,, V2 Vs,,,, =RL ωcL1 1 k2 Q2 L Q2 L+1,(3.8) where kis the coupling factor and QLis the quality factor of the series association of L2and RL. It has been assumed that resonant inductors are tuned at ωc–i.e. ω−1 c=√C1L1=√C2L2– and that inductors are have no resistive losses –i.e. quality factor tends to infinity–. In LSK, the impedance seen by the inductive link’s secondary side is modified to change the value of the reflected impedance, Zref , –modeled as a resistor Rref and a capacitor Cref – at the primary side. This change in the reflected impedance is sensed and uplink data is demodulated. However, since the WPDT system is expected to continuously power an electrical neuro-modulator, the reflected impedance is also affected by the amount of power being demanded. To illustrate this effect, the reflected impedance is calculated both for ZLSK = RLSK and for ZLSK =(s·k2·C2)−1. In the first case, the reflected impedance 28 is Rref =k2L1 L2 (RL||RLSK )(3.9) Cref =1 ωck2L1 ,(3.10) This way, from Eq. 3.9 and as illustrated in Fig. 3.9a, the reflected resistance equally depends on RLand RLSK . Thus, the only way to perform reliable LSK is by keeping RLSK smaller than the smallest expected load resistance, thus negatively affecting power delivery. In the second case, the reflected impedance is Rref =k2ωcL1 QL(Q2 L+k2 2) Q2 L+(Q2 L+k2(k2−1))2(3.11) Cref =1 (kωc)2L1 Q2 L+(Q2 L+k2(k2−1))2 (Q2 L+k2 2)2−k2(Q2 L+k2 2),(3.12) Again, as depicted in Fig. 3.9b, reliable UDT would only be achieved by doing k2large, thus heavily detuning the resonant inductive link and affecting power delivery. The transmission of power to a variable load while simultaneously operating reliable UDT has been previously tackled in the literature. A WPDT system that transmits power and data over a single pair of coils was proposed in [54]. Even though power transferred reaches 10mW, the UDT rate is just 33.3kbps. Another proposed solution reports a power transmission of 111 µW and a UDT rate of 1Mbps [95]. However, the system relies on a complex arrangement of five coils. In [92], a WPDT system that selfregulates against load variations is proposed. It achieves up to 94mW of power delivered and up 5Mbps UDT rate. However, the system needs two bulky 40 µH inductors and a LSK demodulator that consumes 6.8mW. The electrical model of a WPDT system that allows simultaneous power and data transmission to a wide range of loads over a single pair of coils is presented in the next section. 3.2.2 Proposed WPDT system A simplified block diagram of the proposed WPDT system is shown in Fig. 3.10(a), including: a programmable step-down DC-DC converter performing ASK modulation, class-E power amplifier, LSK demodulator, resonant two-coils inductive link, LSK modulator, ASK demodulator, rectifier Chapter 3 | 29 0 200 400 600 800 1000 Load resistance ( ) 0 10 20 30 Reflected impedance ( ) Switch open Switch closed (a) 0 200 400 600 800 1000 Load resistance ( ) 0 50 100 150 Reflected impedance ( ) Switch open Switch closed (b) Figure 3.9: Reflected impedance magnitude variation under different load resistances with/without LSK. Parameters: L1=600nH, C1=229.6pF, L2=200nH, C2=688.9pF, k=0.1, and fc=13.56 MHz. (a) Resistive LSK (Rx=500Ω). (b) Capacitive LSK (k2=0.1). [7] and load adapter. Besides, a more detailed schematic of the load adapter block is presented in Fig. 3.10b. In this solution, the issue described in Section I is alleviated by implementing a Power Transfer Phase (PTP) followed by a Data Transfer Phase (DTP), according to the timing diagram depicted in Fig. 3.11. In the proposed load adapter block, capacitors CAand CBstore energy. During PTP, one capacitor is charged up at a constant current rate, Irect, which is directly sunk from the rectifier whereas during PTP no current is drawn from the inductive link. The load, IL, is always being powered by either one capacitor or another. There is no significant power transfer during DTP and, thus, data transmission can be done without affecting power delivery to the load nor consuming much power. The system takes advantage of the fact that microfarad capacitors with sub-mm footprints are commercially available, allowing mW-power and Mbps-data transmission 30 using only a single pair of coils. The constant current charging the capacitors must be larger than the maximum current expected to be drawn by the load. With this constraint, the capacitors are sized taking into account 1) the difference between the voltage at which a capacitor is considered to be charged, Vc1, and the voltage at which a capacitor is considered to be depleted, Vc2, and 2) the duration of PTP, TPTP. The expressions of TPTP and TDTP are TPTP =CA,B Vc1−Vc2 Irect (3.13) TDTP =CA,B(Vc1−Vc2)$1 IL−1 Irect %,(3.14) In this implementation, the load current ranges from 1mA up to 15mA, with an output regulated voltage of 2.5V. The chosen carrier frequency is 13.56 MHz. The selected storage capacitors have a capacitance of 4.7µF; the constant current drawn from the rectifier is 25mA; and the voltage difference in capacitors, Vc1−Vc2, is 0.3V. Thus, the PTP lasts 26.4µs or 357.98 periods of the carrier frequency whereas the DTP lasts from 17.6µs (238.66 periods) to 633.6µs (8591.6 periods). A longer DTP allows achieving larger bandwidth for data communication. There is thus a trade-off between the power demand and the achievable data transmission bandwidth. The rest of the system is modeled as follows. Regarding the inductive link, the primary coil is set to 600nH and the secondary coil to 200nH. Both coils’ quality factors are set to 40. Capacitors are sized to resonate at 13.56MHz (229.6pF and 688.9pF). Besides, we use an electrical model of a Class- E power amplifier (PA) for driving the primary side of the inductive link Power amplifier DC-DC Load adapter AC-DC Quantizer Peak detector Amp + LPF Amp + LPF Internal control logic External control logic V2 V rect V rect VLVL V A V B IL IL Irect C (a) (b) 1 Cm C2 C2 CACB SLSK SLA SLA S[0] LA S[4] LA S[1] LA S[3] LA S[2] LA 5b 5b 2b k2 L k 1 Lm fcL2 DDDT,out D LSK Demodulator ASK Demodulator UDT,out DDDT,in DUDT,in SLSK SASK SASK CLSK V DD,PA V PA V 1 VDD 2b 2b Quantizer 2b CLSK Skin/Air Figure 3.10: (a) Simplified block diagram of the proposed WPDT system. (b) Schematic of the load adapter block. [7] Chapter 3 | 31 time T PTP DTP PTP DTP IL PTP T DTP Irect VA VB V L V 0 C2 Irect VC1 Figure 3.11: Timing diagram of the load adapter block. [7] [96], [97]. The voltage supply of the PA, VDD,P A, originates from a programmable step-down DC-DC converter whose input is 3V and whose gain is programmed by the external control unit. The values of VDD,P A are 2V for the PTP and 1V for the DTP, obtaining a voltage amplitude of around 4.5V at the secondary side of the link in both phases. The AC-DC converter is modelled as a half-wave rectifier. Finally, uplink demodulator comprises a peak detector, low-pass filter, amplifier and 2-bits quantizer; and downlink demodulator includes a low-pass filter, amplifier and 2-bits quantizer. 3.2.3 Simulation results We built an electrical model of the proposed WPDT system in MATLAB Simulink, taking advantage of the Simscape Electrical and Stateflow toolboxes for implementing analog and digital blocks, respectively. First, we show power transmission to a 15mA load current. Results are shown in Fig. 3.12, where power and data transfer phases are highlighted. The WPDT system can deliver around 40mW of power to a load even when no significant power is drawn from the inductive link. Power consumption of circuitry at the secondary side during DTP was modelled with a 0.5mA load current. UDT with LSK modulation was proven by sending two bytes of data at 1Mbps meanwhile a 15mA load is powered. Results are depicted in Fig. 3.13. The main limitation for achieving higher data rates are both the carrier frequency and the hold time required by the LSK demodulator, which was modelled at roughly 0.7µs in this work. Two bytes of data were sent along with start/end of frame delimiters identifying the beginning and end of the data package. Finally, DDT with ASK modulation was tested by sending two bytes of 38 only 4 combinations are possible. Extensions for different number of rows, M, or columns, N, is straightforward, whenever the breakdown voltages of the CMOS process are not exceeded. In the selected process, the PN-junctions of PMOS and DNW-NMOS transistors have breakdown voltages above 14V, and transistors can withstand voltage differences of up to 3.3V. Consequently, the number of columns in the presented design has been set to M=4and the maximum input voltage has been set to 3V, to give some margin against transient spikes during switching. The voltage levels of Rand Chave to be adjusted according to the cell position in the array. Namely, it has to be guaranteed that the transformed variables are comprised between the input VCP,j−1, and the output, VCP,j of the cell (by construction, VCP,0=Vin, i.e., the input voltage of the array). This is done by means of HV-FLS [4], [106]. The schematic and symbol of a HV-FLS are shown in Fig. 4.3. Assuming the control signal EN is comprised between ground and Vin, the circuit generates a voltage-shifted M7 M7a M7b M9a M9b M10a M10b M8a M8b Vin V C4a C4b C5b C V1 V2 V3V5 V6 V4 EN EN EN 0 OUT INP INP INP EN OUT INP OUT HV-FLS 5a Vin Ψ1 Ψ3 Ψ4 Ψ Ψ1 Ψ2 Ψ2 1 M8a 2 M8b 4 M91 M10 2 C41.25 C51.25 Figure 4.3: Schematic and symbol of the HV-FLS for sliding configuration bits. The dimensions of the transistors and capacitors are given in µm and pF, respectively. All the transistors have a length of 0.35 µm. [4] Chapter 4 | 39 version, OUT, which swings from INP to Vin +INP. As capacitors C4x- C5x(xstands for aor b) are periodically refreshed with Ψ={ψk},k = 1,...,4, the circuit can tolerate non-periodical EN signals or variations of the shifting voltage, INP. The HV-FLS supports a wide range of INP values, exhibits a propagation delay of only 1.86ns, and its power consumption is 13.9µW (for INP =9.5V and fΨ=2.5MHz). The circuit consists of three main blocks: (1) a local HV-FLS (C5xand M7x), (2) a basic charge-pump (C4x,M9x, and M10x), and (3) a sample-and-hold C1C2C3C4 4-ph Clock gen clk Tclk 4-ph Clock gen 8Tclk 8 (a) (b) Cj Cj φ1 Φ1 Φj-1 Φj-1 Φj Φj φ2 φ3 Φ φ4 φj-1,1/2 φj-1,3/4 φ1/2 φj,1/2 φj,3/4 ψ1 Ψψ2 ψ3 ψ4 Vin Level Shifter Vin Level Shifter Φ2 Vin Level Shifter Φ3 Vin Level Shifter Φ4 Vin Level Shifter Figure 4.4: Timing diagram of the 4-phase clock signals Φ,Φjand Ψ. All the circuit elements are supplied at VDD, excepting the clock drivers that are biased at Vin. 40 (S&H) (transmission gates M8xand load capacitor). Complementary clock signals Ψ1and Ψ2are in-phase with signals Ψ3and Ψ4, respectively, with non-overlapping time margins at the rising and falling edges, as illustrated in 4.4(a). The local HV-FLS provides the input voltage, V3, of the S&H circuit. Signal V3is in-phase with Ψ1if the FLS input, EN, is in high state; otherwise V3 is in-phase with Ψ2. Accordingly, if EN is HIGH, V3≈Vin +INP and, Vin V in Vin V in C2b C1b C3b C2a C1a C3a M1a M1b M2a M2b M3a M3b M4a M4b M5a M5b M6a M6b Vcell,ij Ri VCP,j Vc,j VCP,j-1 fj,4 fij,1 fij,2 fij,4 Vcell,ij Vcell,ij Vcell,ij Ri fj,2 Ri fj,1 Ri fj,3 48 96 0.5 0.5 4 12.5 0.6 0.68 M1M2M3M4M5M6C1C2C3 HV-FLS Y VCP,j-1 Ri Vcell,ij Figure 4.5: Proposed cross-coupling CP cell with enhanced conduction main transistors. Similar comments as in Fig. 4.3 hold for dimensions and values. Chapter 4 | 41 otherwise, if EN is LOW, V3=INP. The charge pump generates two voltage-shifted versions of the clock signals Ψ3and Ψ4, named V5and V6, that drive the gates of transistors M8aand M8b, respectively. Also, it biases the bulk of M8band the deep n-wells of DNW-NMOS transistors. When Ψ3is HIGH (alt. Ψ4is LOW), voltage V3is sampled in the load capacitor. Otherwise, if Ψ3is LOW (alt. Ψ4is HIGH), the charge stored in the load capacitor is held. Note that the non-overlapping margins between Ψ1and Ψ3 (similarly between Ψ2and Ψ4) guarantee that signal sampling only occurs when V3is established. During the sampling phase, if the EN signal state is LOW (alt. HIGH), C5a (alt. C5b) stores the voltage level INP and C5b(alt. C5a) pumps charge to the load capacitor. On the other hand, during the holding phase, if the EN state is LOW (alt. HIGH), C5b(alt. C5a) stores the voltage level INP and C5a(alt. C5b) pumps charge to the load capacitor. Regardless of signal EN level, the capacitor C4a(alt. C4b) stores INP in the hold (alt. sampling) phase and the capacitor C4b(alt. C4a) pumps charge in the hold (alt. sampling) phase. Hence, the capacitors are refreshed at the frequency of the main clock. This allows to track time-varying shifting voltages INP and handle non-periodic input signals EN. Fig. 4.4(a) shows the timing diagram of clock Ψ, which is generated at the programming interface from the clk output of the regulation loop (see Fig. 4.1). Clock Ψis made 8×slower than Φby means of a clock divider to save power consumption. Fig. 4.5 shows the schematics of the CP core. It follows a cross-coupling architecture [107], [108]. Besides the main charge pumping stage (M1x- M2xand C1x), it includes two auxiliary charge-pump circuits (M3x-M4x and C2x-C3x) for boosting the conductivity of the core transistors; one HVFLS integrated within the CP cell for level-shifting the selection bits Ri and Cjto Vcell,ij; and switches (M5x-M6x). The flying capacitors (C1x-C3x) nominally have a capacitance of Cfly = 12.5pF. They are implemented with a single MIM structure in the cells located in the first and second columns of the array; however, the CPs in the third and fourth columns use two series-connected MIM capacitances to support higher voltages. DNW NMOS transistors were employed in the CPs. Fig. 4.6 shows the cascade circuit used for implementing the voltage-shifted column selection signals Vc,j from the configuration bit Cj,j =1,...,4. The circuit is implemented outside the CP array and employs both HV-FLS and digital buffers. The values of Vc,1−4for Na={1,2,3,4}are shown 42 Table 4.1: Values of the voltage-shifted column selection signals, depending on the number of stages enabled. Node Na=1 Na=2 Na=3 Na=4 Vout Vin +Vpump Vin +2·Vpump Vin +3·Vpump Vin +4·Vpump Vc,1Vin Vin Vin Vin Vc,2Vin Vin +VpVin +Vpump Vin +Vpump Vc,3Vin Vin +Vpump Vin +2·Vpump Vin +2·Vpump Vc,4Vin Vin +Vpump Vin +2·Vpump Vin +3·Vpump in Table 4.1, where Vpump is the voltage pump introduced by each enabled column. The clock signals Φj={φj,k},k =1,...,4employed by the CPs are shared by columns. They are derived from the non frequency-divided clock Φ represented in Fig. 4.4(a) using the circuit shown in Fig. 4.4(b). Note that the phases φj,k depend on the configuration bits Cj. Using the Delta blocks shown in Fig. 4.4(b), the phases φj,k are defined as: HV-FLS Y Vc,3 C4 Vc,4 Vc,3 VCP,3 HV-FLS Y Vc,2 C3 Vc,3 Vc,2 VCP,2 HV-FLS Y Vc,1 C2 Vc,2 Vc,1 VCP,1 C1Vc,1 Vin Figure 4.6: HV-FLS based generation of voltage-shifted column selection signals Vc,j from the configuration bit Cj,j =1,...,4. Chapter 4 | 43 Φj=-{φ1,φ 2,φ 3,φ 4},C j=1 {0,0,φ 1,φ 2},C j=0 (4.1) Also note that because of the cascaded synthesis of the clocks Φj,j = 1,...,4, they are slightly time delayed each other, regardless of the Cjvalues. This avoids that flying capacitors are charged at the same time, thus smoothing the current demand of the DC-DC converter [109]. Depending on whether the row and column of the CP cell are enabled or disabled, three different operation modes, denoted as PUMP, BYPASS, or DISABLED, can be defined. They are illustrated in Fig. 4.7 (only core transistors M1x-M2xare shown for clarity). •PUMP. In this mode (see Fig. 4.7(a)), the row and column of the cell are enabled, Vcell,ij =VCP,j−1and Vc,j =VCP,j−1. Hence, the cell operates as a cross-coupled CP in which core transistors (M1x-M2x) are switched on and off as illustrated in the figure, and switches (M5x- M6x) are off. The voltage Vpump,j pumped to the following j-th column of the array is given by Vpump,j =VCP,j −VCP,j−1 =Vin −IL 2MafclkCfly (4.2) where Cfly,Ma,VCP,i−1,Vin,fclk, and ILare, respectively, the value of the flying capacitor C1x, the number of active rows, the cell’s input voltage, the input voltage of the HV-SCRC, the pumping frequency, and the load current. Since the cells of the CP array are equally sized, the charge pumped from the input voltage source to the load is equally distributed among the flying capacitors, thus resulting in a constant pumping voltage, Vpump, across all cells. As Vpump decreases, the conduction resistance of M2xincreases, thus increasing the charge transfer time constant formed with the flying capacitors. When this time constant is comparable to the pumping clock period, charge is not fully transferred to the next stage, and the output voltage can not be properly regulated. In the proposed design, this performance limit is observable when Vpump,j drops below roughly 1 V. •BYPASS. In this mode (see Fig. 4.7(b)), the row of the cell is enabled but the column is disabled. This is done by permanently setting M2x on and by alternatively switching M1xon and off. In this case, Vcell,ij = 44 VCP,j−1and Vc,j =Vc,j−1. If the previous stage is in PUMP mode, Vc,j =VCP,j−2, otherwise, if it is in BYPASS mode, Vc,j =Vc,j−2. Note that the flying capacitors are tied to the cell output node to reduce voltage ripples. •DISABLED. In this mode (see Fig. 4.7(c)), the row of the cell is disabled and, regardless of the Cjvalue, the cell’s input and output voltages are isolated and flying capacitors contribute to reducing the ripple. In this case, Vcell,ij =VCP,j−1+Vin, and if the column is enabled, Vc,j =VCP,j−1, otherwise Vc,j =Vc,j−1. Assuming a general M×Narray architecture and neglecting conduction and switching losses in the CPs, the output voltage Vout of the HV-SCRC follows a saw-tooth waveform with period Th=Tclk/2 given by Vout(t)=V0−ReqIL+&1−$t Th−.t Th−1/%' IL Ceq (4.3) where *·+represents the floor function, V0=(Na+ 1)Vin,Nais the number of active columns in the array, and Req =Na 2MafclkCfly (4.4) Ceq =02M(N−Na+ 1) −Ma1Cfly +Cout (4.5) fij,1 fij,2 fij,3 fij,4 fij,3 fij,4 fij,1 fij,2 fij,3 fij,4 fij,1 fij,2 M1a M1b M2a M2b VCP,j-1 VCP,j M1a M1b M2a M2b VCP,j-1 VCP,j M1a M1b M2a M2b VCP,j-1 VCP,j Vin PUMP BYPASS DISABLED Ri = Vin Cj = Vin Ri = Vin Cj = 0 Ri = 0 Cj = Any (a) (b) (c) Figure 4.7: Simplified schematic of the proposed CP cell in its different states: (a) PUMP, (b) BYPASS, (c) and DISABLED. Clock phases are also shown. Chapter 4 | 45 Note that during the time interval [0,T h],Vout(t)can be interpreted as the voltage drop across an equivalent Req −Ceq series circuit, with the capacitor having an initial voltage V0, which is discharged by a current load IL. From (4.3), the average output voltage, Vout,avg, and the output ripple, ∆Vout, of the converter are, respectively, given by Vout,avg =V0−$Req +1 4fclkCeq %IL(4.6) ∆Vout =IL 2fclkCeq (4.7) For a given flying capacitance Cfly and output capacitor Cout,(4.6) shows that the voltage conversion ratio, VCR=Vout/Vin, is mainly determined by Na, however, it also depends on Maand fclk. Similarly, the output voltage ripple also depends on Na,Maand fclk, according to (4.7). This reliance on multiple parameters is key to expanding the operating range of the HVSCRC, as well as allowing different configurations for a given target. This is illustrated in Fig. 4.8 which shows the operation range segments (thick lines) for four different Maand Nacombinations in the Vpump vs. Vout(0) plane for an arbitrary case where Vin =3.0V and IL=0.5mA. The combinations 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Output voltage (V) 0 0.5 1 1.5 2 2.5 3 3.5 Na=1 Na=2 Na=3 Na=4 Ma=2 Ma=3 Pumping voltage (V) Ma=1 Ma=4 10 Vin fclk,min fclk,max Figure 4.8: Graphical representation of the converter operation range for different row/column configurations, assuming IL=0.5mA, Vin =3.0V. Top (alt. bottom) horizontal colored lines represent the achievable pumping voltage at maximum (alt. minimum) fclk for Ma=1,2,3,4. 46 are Ma=Na={1,2,3,4}. From (4.2) and (4.3), the segments follow the expression Vpump =Vout(0) −Vin Na (4.8) and the upper and bottom boundaries of each are obtained from (4.2) for the maximum and minimum values of the pumping clock frequency fclk generated by the regulation loop. As mentioned, the lower boundaries cannot be decreased below approximately 1V. Note from Fig. 4.8 that the segments cover different operation ranges, and there are output voltages which can only be accessed with one configuration. For instance, an output voltage of 4.3V is only achievable if Ma=Na=1, as shown in the plot. It can also be observed that the segments overlaps for given output voltages. For instance, an output voltage of Vout = 11.3V can be generated both with Ma=Na=3 and Ma=Na=4. This paves the way to select one configuration or another for a target output voltage based on considerations like power efficiency or voltage ripple. This is further illustrated in Fig 4.9, which shows the accessible output voltage regions of the converter in terms of the load current and the number of activated rows Ma={1,2,3,4}, assuming Na=4and Vin =3V. The overlaps between the different regions are clearly observable and it can also be seen that some operation points are only accessible from a single con- Load current (mA) Output voltage (V) 0 0.5 1 1.5 2 2.5 3 3.5 4 4 6 8 10 12 14 Ma=3 Ma=4 fclk,max fclk,min Ma=4 Ma=2 Ma=1 Ma=1 Ma=2 Ma=3 Figure 4.9: Graphical representation of the HV-SCRC’s operation range in terms of the load current and the number of activated rows for Na=4, Vin=3V. Chapter 4 | 47 figuration. For instance, Ma=1is the only possibility for generating a target output voltage V(0) = 10.5for load currents down to 0.1mA. This illustrates the advantages that row programming offers for extending the operation range of the converter – a non-programmable Ma=4implemen- tation would have require a load current of 0.5mA for the same output voltage–. The power losses of the array, not considered in (4.3), depend on the number of active cells and the fclk·Cfly product as [110], Ploss,tot =fclk·Cfly·(2·β·V2 in +Kinv)·Ma·Na.(4.9) where the first sum term accounts for the switching-losses due to the parasitic capacitances of the flying capacitors (they are estimated as a fraction β of the Cfly nominal value), and the second term represents the short-circuit losses of the flying capacitor drivers. This loss is modeled by parameter Kinv which depends on circuit dimensions and increases with the square of the input voltage, Vin. Equation (4.9) reveals that power losses increase with the pumping frequency. However, from (4.4) and (4.7), the equivalent output resistance and the output voltage ripple are both inversely proportional to fclk. Hence, there is a trade-off between power efficiency, achievable output voltage, and voltage ripple. A similar trade-off also holds if the number of active rows increases, i.e., power efficiency lowers but the converter output is smoother. Referring back to the graphical representation in Fig. 4.8, if a given target output voltage can be generated from two or more configurations, the one for which the operating point is closer to the lower limit of its feasibility segment gets a better energy efficiency. On the contrary, the configuration with an operating point closer to the upper limit obtains a better ripple behavior. These trade-offs will be further illustrated in Section III. 4.2.2 Regulation circuit It consists of a negative feedback loop which generates a clock signal that locks when the difference between a 1/10 scaled version of the HV-SCRC’s output and an internal voltage reference cancel out. Voltage scaling is implemented using a string of diode-connected PMOS transistors from the converter output to ground, and the voltage reference is obtained from a 4bits NMOS-based DAC –shown in Fig. 4.10(b)–. The output of the DAC is comprised within the range from 0.42mV to 1.32V at 60mV steps, and 54 0306090 120 150 180 Time (us) 5 8 11 14 Voltage (V) 0306090 120 150 180 Time (us) 3 5 7 9 11 Voltage (V)Voltage (V)Voltage (V) 0306090 120 150 180 Time (us) (a) (b) (c) (d) 2 4 6 8 0306090 120 150 180 Time (us) 2 3 4 5 6 N=1 ST4=0 V N=2 N=4 N=3 ST4=0 V ST4=3 V ST4=0 V ST3=0 V ST3=0 V ST3=3 V ST2=3 V ST2=0 V OUT=ST4,HV INP=ST3,HV OUT=ST3,HV INP=ST2,HV OUT=ST2,HV INP=Vin Figure 4.17: Experimental measurements with Vin=3 V, fclk=50MHz, Ma=4, and IL=3 mA. Columns are successively enabled. (a) Output voltage. (b-d)) Level shifting voltage supply and output voltage of the HV-FLS driving the fourth/third/second columns, respectively. shows the signals INP and OUT of the HV-FLS driving the fourth, third, and second CP columns, respectively, for the same time sequence of activated cells. Again, the level shifters update their outputs, Vc,2−4, according to the values previously discussed. When Nachanges, the signals settle after roughly 2µs. This delay is essentially dominated by the internal dynamics of the charge pumps, which are much slower than the HV-FLS blocks. Fig. 4.18 shows the response of the HV-SCRC and the HV-FLSs to a varying load current. In this case, Ma=Na=4, fclk=50MHz, and the load current changes from 0.5mA to 4mA within 50 µs. From top to bottom, the oscilloscope screenshot shows Vout,Vc,4,Vc,3, and Vc,2. The voltage difference between adjacent signals is always Vpump, as discussed in (4.2). However, Chapter 4 | 55 IL=0.5 mA 20 us Vout=Vin+4VP ST4,HV=Vin+3VP ST3,HV=Vin+2VP ST2,HV=Vin+VP IL=4 mA 2 V 6 V 10 V 14 V Figure 4.18: Experimental measurements for Vin=3V, Ma=Na=4, and fclk=50MHz. The load current is a 10kHz triangular wave from 0.5mA to 4mA. Vpump, and, hence, Vout varies with the load current. Namely, Vout changes from 13.6V –for a load current of 0.5mA– to 8V –under a load current of 4mA–. Even though the digital input of the floating level shifters do not change, thanks to the charge-refreshing topology, the HV-FLS successfully maintain their outputs Vc,2−4at the correct level. 4.3.2 Closed loop characterization In this setup, the pumping frequency of the CP array is internally controlled by the regulation loop; and the average output voltage, power efficiency, and output voltage ripple of the DC-DC converter are evaluated for all 16 possible values of VREF. Measurements are repeated for every combination of load currents (assuming discrete values of 0.5, 1.5, 3.5, and 4mA) and input voltages (assuming discrete values of 3.0, 2.7, and 2.4V). The surface plot of Fig. 4.19(a) illustrates the circuit behavior for a 3V input voltage. Row/column configurations have been selected for improving power efficiency. The DC-DC converter can deliver output voltages from 4.2 V up to 13.2V depending on the load current. For a 4mA load, the output voltage is 12.1V and the power efficiency is 65%. For loads larger than 1.5mA, the efficiency is above 50%. At lower values, the efficiency decreases to 35%. Fig. 4.19(b) illustrates the case for Vin =2.7V. The output voltage can be adjusted from 4.2V up to 13V and, hence, the VCR is comprised in the range 1.6-4.8V/V. The peak power efficiency is 66%, obtained when the circuit delivers around 40mW. Finally, Fig. 4.19(c) shows the operation for 56 (c)(b) V = 3 V in V = 2.7 V in V = 2.4 V in (a) Output voltage (V) Load current (mA) Load current (mA) Load current (mA) Output voltage (V) Output voltage (V) Efficiency (%) Efficiency (%) Efficiency (%) 30 14 40 12 50 4.5 10 60 3.5 70 82.5 61.5 0.5 4 30 14 40 12 50 4.5 10 60 3.5 70 82.5 61.5 0.5 4 30 14 40 12 50 4.5 10 60 3.5 70 82.5 61.5 0.5 4 Figure 4.19: Closed loop measurements. Power efficiency for (a) Vin =3.0V, (b) Vin =2.7V, and (c) Vin =2.4V. Vin =2.4V. The DC-DC converter outputs voltages from 4.2V up to 11.7V, and the efficiency stays above 40% in most of the operation points, reaching a local maximum of 67%, when driving a 4mA load current at 8.6V. Using the same setup, output voltage ripple is measured rather than power efficiency, and the corresponding surface plots are shown in Fig. 4.20. In the case Vin =3.0V, illustrated in Fig. 4.20(a), the peak voltage ripple is measured at 3.5mA load current and 11.4V output voltage, where a ratio ∆Vout/Vout,avg of 2.4% is obtained. In the case Vin =2.7V, shown in Fig. 4.20(b), the peak ratio decreases to 1.4%, obtained at 4mA load current and 10.4V output voltage. Finally, when Vin=2.4 V (case shown in Fig. 4.20(c)), the peak ∆Vout/Vout,avg ratio further decreases to 0.9%, measured for Vout=8.6V and IL=4mA. This decrease of the output voltage ripple with the input voltage can be explained through (4.2) and (4.7). Decreasing Vin increases the pumping clock frequency needed for reaching the target output voltage and, thus, ripples are smaller. As discussed in Fig 4.9, the programmability of the charge-pump array extends the low side of the load current operation range. This is experimentally confirmed in Fig 4.21, which shows the output voltage, Vout, for different Load current (mA) Output voltage (V) Ripple (mV) Load current (mA) Output voltage (V) Load current (mA) Output voltage (V) Ripple (mV) Ripple (mV) (c)(b) V = 3 V in V = 2.7 V in V = 2.4 V in (a) 14 20 40 12 4.5 60 10 3.5 80 82.5 100 61.5 0.5 4 14 40 80 12 4.5 120 10 3.5 160 82.5 200 61.5 0.5 4 20 14 60 100 12 4.5 140 180 10 3.5 220 82.5 260 61.5 0.5 4 Figure 4.20: Closed loop measurements. Output voltage ripple for (a) Vin = 3.0V, (b) Vin =2.7V, and (c) Vin =2.4V. Chapter 4 | 57 0 0.5 1 1.5 2 2.5 3 3.5 4 Load current (mA) 10 10.5 11 11.5 12 12.5 13 13.5 14 Output voltage (V) M Ma=1 Ma=2 Ma=3 Ma=4 a programmable Ma = 4 { { { { Figure 4.21: Closed loop measurements. Orange line represents the output voltage for Ma=4. Blue line represents the output voltage when Mais adapted to the load current. Vin =3.0V, VREF = ‘1010’,Na=4. load currents ranging from 0.1mA to 4mA at VREF = ‘1010’. The plot compares a case in which Ma=4to a case in which the number of activated rows is programmed according to the current load. Note that for currents below 0.5mA the converter with Ma=4is not able to regulate the targeted output voltage and large deviations occurs. Contrarily, when Ma is programmable, the circuit tolerates load currents as low as 0.1 mA with an average voltage deviation of 36mV. This is in agreement with Fig 4.9. Furthermore, as discussed in Sec. II and captured by (4.7), flying capacitors of disabled rows contribute to reducing the voltage ripple by increasing the equivalent capacitance, Ceq. Fig. 4.22(a) illustrates the use of the DC-DC converter together with the on-chip neural stimulator. It shows the output voltage response to a load current ILthat switches from 0.2mA to 2mA at a rate of 1kHz. During the transitions, the configuration of the CP array changes from Ma=1,Na=4 (for the low current level), to Ma=4,Na=3(for the high current level). Note that despite the large load change and the structural reconfiguration of the array, Vout variations remain below 0.3 V. Additionally, it can be observed that the regulation loop successfully stabilized the output voltage after around 6µs. Finally, Fig. 4.22(b) shows the output voltage transient response to a change in the target output voltage, VREF, for a load current of 1.5mA. Each 40 µs, the target voltage is changed from ‘0000’ to ‘1111’. The output voltage can reach the target within 5µs. 58 2 mA Vref=`1111´ Vref=`0000´ (a) (b) 0.2 mA ~0.3 V ~13 V ~13 V ~4.2 V Figure 4.22: (a) Response of Vout to a switching IL.(Ma,Na) is set to (1, 4) under IL=0.2mA and to (4, 3) under IL=2 mA. Vin=3 V, VREF = ‘1111’. (b) Response of Vout to a change in VREF.(Ma,Na) is set to (2, 1) for VREF = ‘0000’ and to (2, 4) for VREF = ‘1111’.Vin=3 V, IL=1.5 mA. 4.3.3 State-of-the-art comparison Table 4.2 summarizes the performance of the proposed HV-SCRC, together with other solutions proposed in the literature. Only a few reported HV DCDC converters implemented LV CMOS processes are fully implemented onchip [78], [101]–[103]. Compared to them, the proposed circuit can operate for different input voltages Vin ∈[2.4,3.0] V, obtains higher output power and the occupied area is smaller than the work achieving similar delivered power [102]. Moreover, the efficiency when delivering maximum power is among the highest of the fully-on-chip solutions. Finally, the output voltage gets regulated under a wide range of load currents and the regulation loop is able to stabilize the output voltage within a few microseconds when the load current switches abruptly. Chapter 4 | 59 [100] [101] [103] [102] [104] [78] This work Process 0.18 µm LV 0.35 µm LV 0.18 µm LV 0.18 µm LV 0.18 µm LV 65 nm LV 0.18 µmLV Vout (Vin)1.7-11.4V (1.8V) 7.5-16V (2.5V) 5-19.6V (3.3V) 3.3-12.6V (3.3V) 12.8V (2.8V) 11V (0.5V) 4.2-13.2 V 4.2-13.0 V 4.2-11.7 V Load current 0.1-1 mA 0.1-25 µA Up to 150 µA 0.5-3.5 mA 0.01-2 mA Up to mA 0.1-4 mA Maximum op. point 9.8V@1mA 11.5V@25 µA 17V@150 µA [email protected] 12.8V@1mA 11V@2mA 12.1 V@4mA 10.2 V@4mA 8.6 V@4mA Max. power (mW) 9.8 0.3 2.6 37.9 12.8 22 48.4 40.8 34.4 Efficiency at max. power 77% 32% 34% 60% 82% 31% 65% 66% 67% Area (mm2) - 0.07 0.06 2.87 - 0.04 2.10 Capacitors 1.2µF 18pF 26.4pF 400pF 9µF - 400 pF Fully on-chip No Yes Yes Yes No Yes Yes Regulated No Yes Yes Yes Yes Yes Yes Table 4.2: Performance comparison with previously reported HV DC-DC boost converters in LV CMOS process. 60 | 61 Chapter 5 High-Voltage Neural Stimulator Front-End Abstract In this chapter, the High-Voltage Neural Stimulator Front-End (HV-NSFE) shown in Fig. 1(b) is presented. In Section 5.1, the operation of a currentcontrolled biphasic stimulator is described, with an emphasis on the analysis of the compliance voltage and power efficiency. The architecture, components, and operation modes of the proposed HV-NSFE are described in Section 5.2. In Section 5.3, experimental results are presented and discussed. 5.1 Introduction Figures 5.1(a-b) show the simplified schematics of a monopolar neuronal stimulator and a bipolar neuronal stimulator, respectively. They essentially work in two alternating phases. First, an anodic phase of Tan duration is established to inject charge immediately around the stimulation electrode A. Then, a cathodic phase of Tca duration is set to restore the charge balance in the tissue prior to the stimulation. This is done to prevent charge accumulations that can lead to the generation of toxic chemicals or the corrosion of the electrodes [15]. Hence, if Istim,an and Istim,ca are the currents flowing through the ETI during the anodic and cathodic phases, the charges Qan =2Tan 0Istim,an dt and Qca =2Tca 0Istim,ca dt injected and extracted from the tissue, respectively, should have the same magnitude 62 Tissue I 0 + - drv Cdl Rct Rct Rs Cdl Idrv -Idrv VDDH VA VB Istim Tan Tint Tca Tdis (b) (d) (c) V VA VDDH VA VB VB stim Istim Tissue I + - drv Idrv (a) V VDDH stim I φan φan φan φca φdis φca φca stim Cdl,eq Rct,eq Rs VA VB VCdl,eq,an Vdrop Figure 5.1: (a-b) Simplified schematics of unipolar and bipolar electrical neural stimulators. (c) Electrical model of the ETI and lumped model. (d) Current and voltage stimulation waveforms. but different sign. Generally, the stimulation currents during the anodic and cathodic phases may have different waveforms and duration as long as |Qan|=|Qca|; however, in this work we consider a typical case in which such currents are pulses of the same duration, Tan =Tca and the same magnitude, |Istim,an|=|Istim,ca|=Idrv. Fig. 5.1(d) shows a simplified model of the equivalent impedance, ZL, between the stimulation nodes A and B in the schematics of Fig. 5.1(b) [15], [115]. Such impedance is given by ZL(s)=Rs+Rct,eq 1+s·Rct,eq·Cdl,eq ,(5.1) where Rsmodels the spreading resistance of the neural tissue, Cdl,eq =Cdl/2 takes into account the electrical double-layer capacitance at the ETI, and Rct,eq =2Rct is an equivalent charge transfer resistance that models the faradaic electrochemical reactions at the electrode surface [15]. The voltage between the electrodes A and B, Vstim(t)=|VA(t)−VB(t)|, during the anodic phase (a similar analysis can be done for the cathodic phase) is given by Vstim(t)=Idrv·Rs+VCdl,eq (t),(5.2) where t∈[0,T an]and VCdl,eq (t)is the voltage across the equivalent doublelayer capacitance given by, VCdl,eq (t)=Idrv·Rct,eq −(Idrv·Rct,eq +VCdl,eq,0)·exp$−t Rct,eq·Cdl,eq %,(5.3) where VCdl,eq,0is the VCdl voltage stored at the beginning of the pulse and τ=Rct,eq·Cdl,eq. Assuming that the time constant of the ETI is much Chapter 5 | 63 larger than the duration of the anodic phase, i.e. Tan ,τas it occurs in practice, the peak stimulation voltage between the electrodes at the end of the anodic phase (t=Tan) (preserved during the interphase delay period) can be approximated as, Vstim,pk ≈VCdl,eq,0+Idrv $Rs+Tan Cdl,eq %.(5.4) The efficiency ηstim of the neural stimulator during the anodic phase can be defined by the ratio between the energy delivered to the tissue and the energy supplied by the biasing voltage, VDDH. Hence, assuming again that Tan ,τ, the following expression is obtained ηstim =2Tan 0Vstim(t)·Idrv·dt 2Tan 0VDDH·Idrv·dt ≈Idrv VDDH ·$Rs+Tan 2·Cdl,eq %,(5.5) which shows that the efficiency depends on the load impedance and the pulse characteristics. Clearly, the efficiency increases by reducing the supply voltage VDDH up to the limit imposed by the peak stimulation voltage Vstim,pk in (5.4). On the other hand, for a given VDDH value, the efficiency and peak of the stimulation voltage decrease both with the amplitude and width of the current pulse and the stimulator may be forced to withstand a large voltage gap between the supply voltage and VA. These considerations are taken into account in the proposed design. Programming interface LS Clock gen charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump charge pump Charge-pump array charge pump Regulation loop x0.1 VCO DAC 1.8 V Vin Vin VDDH R C VREF Vc,4 Vc,3 Vc,2 Vc,1 1.8 V 5-bits DAC H-bridge driver H-bridge DC-DC Converter Stimulator Front-End IREF STIM DISCH Current mirror Figure 5.2: Block-level scheme of the proposed HV neural stimulator. 70 3 mm 3 mm 3 mm 3.3 mm Figure 5.8: Photography of the micro-electrode arrays for cortical optogenetic/electrical stimulation and neural recording. Optical stimulation array with one µLED ON is zoomed, while the electrical stimulation array is displayed in a micro-photography. Active stimulation/recording area occupies an area of roughly 3x3mm2. (a) (b) 00000 00010 00100 00110 01000 01010 01100 01110 10000 10010 10100 10110 11000 11010 11100 11110 IREF -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 DNL 00000 00010 00100 00110 01000 01010 01100 01110 10000 10010 10100 10110 11000 11010 11100 11110 IREF -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 INL Figure 5.9: Measured stimulation current’s DNL, as a fraction of one LSB for a 4.7kΩload and VDDH=11V. Maximum DNL and INL are 0.22LSB and -0.19LSB, respectively. the deviation of the response from the best-fit straight line [120]. It can deliver currents from 69µA up to 2.08mA with a Least-Significant Bit (LSB) current of approximately ILSB=65µA. Given that VDDH reaches 13.2V, the stimulator can deliver a current of 2.08mA to resistive loads close to 6.3kΩ. Chapter 5 | 71 Fig. 5.10 depicts the residual voltage and residual charge stored at the double-layer capacitance for different stimulation currents. The residual voltage was measured by delivering 200 biphasic stimulation rounds with anodic/cathodic and interphase phases lasting 200 µs. Voltage at Cdl,eq was sampled before the first stimulation round and after the 200-th stimulation round, then it was averaged. No discharging phase was triggered. The residual voltage remains below 1mV for most of the stimulation current range. Expressed as a percentage of the charge delivered during each stimulation phase, the residual charge is less than 0.1% for most of the stimulation current range. Fig. 5.11(a-b) illustrates the use of the discharging phase by electrode shorting to remove the residual voltage. A 2mA current is delivered with Tan/ca = Tint = 200 µs and VDDH=12V. On the one hand, Fig. 5.11(a) shows both electrodes’ voltage when no discharging phase is triggered. The 2mA current causes an instant 9.4V difference between electrodes when flowing through Rs=4.7kΩ. Besides, the voltage stored at Cdl,eq=330nF is 1.2 V, as expected by observing (5.3). Thus, after the anodic phase, both outputs remain halfway between VDDH and ground, with a 1.2 V difference between them. Then, after the biphasic stimulation, both electrodes remain at a voltage around 6V. In this point, the voltage difference between both outputs is in the range of milli-volts, as shown in Fig. 5.10. Hence, even with the zoomed screenshot, the residual voltage can not be accurately measured. On the other hand, Fig. 5.11(b) shows both electrodes’ voltage when a 100 µs electrode shorting phase is triggered, which discharges both electrodes to ground. A 0 0.4 0.8 1.2 1.6 2 Stimulation current (mA) 0 0.2 0.4 0.6 0.8 1 1.2 Residual voltage (mV) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 Residual charge (%) Figure 5.10: Measured residual voltage and residual charge stored at the double-layer capacitance Cdl with no discharging phase. Tan/ca=Tint=200 µs. 72 zoom of the electrode shorting phase is also included. Applying a discharging phase lasting more than 100 µs, the remaining residual voltage was below the LSB of the 12bits ADC used in the measurements. Fig. 5.11(c-e) depict the electrodes’ voltages and HV-SCRC’s output voltage, VDDH, in different scenarios. The area of regions shaded in red multiplied by the stimulation current represents energy losses at the stimulator front-end, as discussed in Fig. 5.1. Fig. 5.11(c) shows how the system handles the delivery of a stimulation current of roughly 2mA to the load, with VDDH=12.5V. The 9.4 V 1.2 V (a) (b) Electrode B 2 V 400 us STIM DISCHSTIM 9.4 V Electrode A Electrode B Electrode shorting 2 V 400 us Electrode A 1.2 V 40 us 10 mV VDDH 2 V 12.5 V 0.9 V 3.3 V 5.8 V 200 us VDDH 2 V 12.5 V 8.5 V 9.3 V 200 us Electrode A Electrode B Electrode A Electrode B VDDH 1 V 4.6 V 0.5 V 1.4 V 1.3 V 2.2 V 200 us Electrode A Electrode B 1.3 V 2.2 V 12.5 V 9.3 V Electrode A Electrode B 5.8 V Electrode B (c) (d) (e) 3.4 V 9.2 V 10 V 10 mV 40 us Figure 5.11: (a-b) Electrodes’ voltages when a 2mA stimulation current is delivered with/without electrode shorting phase. Tan/ca =Tint = 200 µs and VDDH=12 V. (c-e) Electrodes’ voltages and HV-SCRC’s output voltage at different stimulation timing and currents. Voltage drop between VDDH and stimulator’s output is shaded in red. Chapter 5 | 73 voltage at electrode A goes from 9.1V to 11.6V. The stimulator front-end is thus capable of delivering a high stimulation current with a dropout voltage below 1V while being supplied at a voltage 4 times higher than the nominal voltage supply of the technology. Fig. 5.11(d) shows how the system handles the delivery of a stimulation current of roughly 0.7mA to the load, with VDDH=12.5V. In this case, there is a large voltage drop from VDDH to the electrodes. However, as discussed in Section 5.2 the HCVC maintains the voltage across all devices below 3.3V. Fig. 5.11(e) illustrates how the programmability of VDDH improved power efficiency. The response of the system was measured again with Idrv=0.7mA, but VDDH was now set to 4.6V. With this current level, the neural stimulator can operate with a voltage drop of 0.5V. Biphasic stimulation rounds were delivered for all the stimulation current values. Fig. 5.12(a) shows the stimulation voltage at the end of the anodic phase, Vstim(t=Tan)and the HV-SCRC’s output voltage. The latter is programmed through the nRF52832 micro-controller. Fig. 5.12(b) depicts overall efficiency. Thus, DC-DC converter’s power efficiency in the operation points shown in Fig. 5.11(c-e) is 58%, 46%, and 45%, respectively. This way, measured overall neural stimulator’s efficiency, ηstim, was 48% at the operation point (VDDH,Idrv) equal to (12.5 V, 2 mA); 13% at (12.5 V, 0.7mA); and 36% at (4.6V, 0.7mA). (a) (b) 00.4 0.81.2 1.62 Stimulation current (mA) 0 2 4 6 8 10 12 14 Voltage (V) Vstim VDDH 00.4 0.81.2 1.62 Stimulation current (mA) 0 10 20 30 40 50 Efficiency (%) Figure 5.12: Electrical characterization. (a) Measured stimulation voltage at the end of the anodic phase and HV-SCRC’s output voltage. (b) Measured overall efficiency. 74 Electrode C VDDH 2 V 200 us 7.6 V Electrode A Electrode B Micro-electrode array Test PCB Electrochemical cell (a) (b) Figure 5.13: Electrodes’ voltages when a 2 mA stimulation current is delivered to the Phosphate-Buffered Saline (PBS) solution. 5.3.3 Validation with a PBS solution The neural stimulator was also characterized by immersing the custom µelectrode array into a PBS solution by means of an electrochemical cell, as depicted in Fig. 5.13(a). Fig. 5.13(b) shows the response when a 2 mA stimulation current is delivered between two electrodes separated roughly 600 µm away in the custom µelectrode array (A and B in the oscilloscope screenshot). Stimulation timing was configured as Tan=Tca=300 µs, Tint=250 µs, and Tdis=200 µs. VDDH is set at 7.6V during stimulation and decreased to roughly 6.6V between stimulation phases. From the curves of voltages at electrodes A and B, it can be seen that the response of the electrodes immersed in the PBS solution approaches a series resistance-capacitance circuit with Rs≈2.3kΩand Cdl,eq ≈550 nF. Electrode C, also shown in Fig. 5.13, is located in the vicinity of electrodes A and B. 5.3.4 State-of-the-art comparison Table 5.1 summarizes the performance of the proposed neural stimulator, along with other solutions proposed in the literature. Compared to the reported HV systems implemented in LV CMOS processes, the proposed neural stimulator achieves higher compliance voltage and wider VDDH than any other reported solution. Besides, lower area/channel than [60], [78] was achieved. Finally, when delivering 2mA of current, similar power efficiency as in [60] was obtained, whereas the 36% power efficiency obtained at 0.7mA stimulation current outperforms that reported in the mentioned work. Chapter 5 | 75 [60] [75] [78] [79] [62] This work CMOS Process 0.18 µm 1.8V/3.3V 0.18 µm 24V 65nm LV 0.25 µm 2.5V/5V/12V 0.18 µm 1.8V/3.3V 0.18 µm 1.8V/3.3V VDDH gen. 6.7-12.3V (4b) Up to 22.5V 11V 20V ±6V 4.2-13.2 V (4b) VDDH gen. area 1.5mm2Off-chip 0.04 mm21.64 mm2-2.1mm2 Stim. current 2.48mA (5b) 48.4µA (7b) 169.5µA (7b) 2mA (8b) 5 mA (6b) 3mA (4b) 2.08 mA (5b) Area/channel 1.5mm2-0.36 mm20.22 mm20.08 mm20.15 mm2 Compliance voltage 11V 21.3 V 11V 16.7V 3.6 V 12.5 V Max. Qres/Qstim 1.7% 0.03% - - 1.94% 0.12% Power efficiency 48% (2mA,10V) 32% (1mA,6.7V) -31% (2mA) 28% (1mA) - - 48% (2 mA,11.6 V) 36% (0.7 mA,4.6 V) Table 5.1: Performance comparison with previously reported HV neural stimulators. 76 | 77 Chapter 6 Conclusions In this thesis, the design of a high-voltage neural stimulator with on-chip power management has been presented. Besides, preliminary work regarding the wireless transmission of power and data to/from the neural implant was tackled. In the mixed-signal ASIC design field, novel circuit solutions for the implementation of a high-voltage tolerant circuits in a standard 1.8V/3.3V CMOS process were shown and discussed. Furthermore, the wireless transfer of power and data to/from the neural implant has been investigated. A remarkable innovation of this work relies in the wide range of voltage supplies that the neural stimulator front-end can handle: from 4.2 V up to 13.2V. For this purpose, a voltage-adaptive cell based on stacked transistors with dynamic gate biasing has been proposed. This cell can dynamically adjust its impedance in order to withstand large voltages or act as a closed switch, as needed. The generation of the front-end’s voltage supply and the biasing of the voltage-adaptive cell is done in an on-chip regulated switchedcapacitor DC-DC converter. The proposed regulated switched-capacitor DC-DC converter can output voltages from 4.2V up to 13.2V and deliver currents from 0.1mA up to 4mA. Efficiency, load current range, and load regulation were improved by implementing a novel charge-pump array. This topology allows the programming of the equivalent output resistance and equivalent output capacitance of the DC-DC converter with two additional parameters: the number of activated rows and the number of activated columns. This way, the operation range of the DC-DC converter is expanded. Besides, most of the operation points can be reached by either maximizing efficiency or maximizing output 78 voltage ripple, overall achieving a quite versatile circuit. At the circuit-level, a charge-pump cell which has three operation modes –PUMP, BYPASS, and DISABLED– has been proposed. This cell allows the implementation of the programmable charge-pump array. Besides, a floating level shifter with charge refreshing has also been proposed. This circuit was implemented in different sub-blocks of the DC-DC converter, as well as in the neural stimulator front-end. Its fundamental features are: high-voltage tolerant operation, tracking of the low-supply rail, and handling of non-periodical input signals. Implementing a system withstanding voltages 4 times higher than the nominal voltage involved several layout techniques and considerations. Some of them are listed here: • Distances between same-layer metal paths should be Ntimes larger than the minimum stated in the design rules of the technology, where Nis the maximum expected voltage difference between both metal paths divided by the nominal supply of the technology [121]. • Chip pads connected to internal high-voltage nodes shall not be connected to standard ESD I/O cells. Instead, custom high-voltage- tolerant ESD cells should be implemented. • Both the HV-SCRC and the HV-NSFE run currents over one milliampere. Thus, current densities have to be taken into account when drawing metal paths [122]. • Switched-capacitors implemented as MIM structures which are floating between high-voltage levels should not be placed above MOS devices. This might cause large charge injections to MOS devices. Concerning the wireless transfer of power and data, preliminary research were conducted in two fields: CMOS photovoltaic solar cells and inductive links. A CMOS photovoltaic solar cell with a novel stacked-diode configuration was designed, fabricated, and experimentally characterised. This work was done under the supervision of Prof. Juan Antonio Leñero and it allowed us to quantify the power that can be extracted from this standard 1.8V/3.3V CMOS process. Besides, the use of the stacked-diode configuration for CMOS image sensor applications was also investigated. In the inductive links field, a system topology for the Mbps-data and mW-power transfer over a single-pair of coils was proposed. This work was carried out at the Swiss Federal Institute of Technology Lausanne (EPFL), under the Chapter 6 | 79 supervision of Prof. Alexandre Schmid. This topology has the potential of overcoming the drawbacks of using a single-pair of coils while keeping the main advantage: its reduced size. 6.1 Future works Neural stimulator front-end’s area might be reduced by synthesising the digital control block instead of implementing it as a full-custom circuit. Also, long-term electrical characterization might be performed in order to check the ASIC’s temperature when delivering maximum stimulation currents. Finally, for implementing a multi-channel neural stimulator, different circuitlevel power saving techniques should be considered to minimize standby power consumption as much as possible. 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McGraw-Hill Professional Engineering. New York: McGraw-Hill, 2002. ! Interests Analog/Mixed-Signal ASIC Design — Embedded electronics! Experience Axelera AI – Mixed-Signal ASIC Designer — July 2022 to Present Seville Institute of Microelectronics (IMSE-CNM); Seville (Spain) – PhD Candidate (Analog/ Mixed-Signal ASIC Designer) — June 2018 to July 2022! "University of Seville; Seville (Spain) – Lecturer — October 2019 to June 2022! "Swiss Federal Institute of Technology Lausanne (EPFL); Lausanne (Switzerland) – Guest PhD Student — September 2021 to December 2021"! "! "BioBee Technologies S.L.; Badajoz (Spain) – R&D Electronic Engineer — January 2018 to March 2018! "University of Extremadura; Badajoz (Spain) – Junior Analog ASIC Designer — January 2016 to December 2017! "University of Extremadura; Badajoz (Spain) – Research Scholar – September 2015 to November 2015! Education"University of Seville; Seville (Spain) – PhD in Electronic Physics (Mixed-Signal IC Design) — October 2018 - September 2022 (Expected)! "University of Extremadura; Badajoz (Spain) – MEng in Industrial Engineering Research — 2015-2016; 9.4/10 (with honors)! "University of Extremadura; Badajoz (Spain) – BEng in Electronics and Control Engineering — 2011-2015; 8.1/10 (with honors)! 1 David Palomeque Mangut •Advisor: José Luis Ausín. •Advisors: Prof. Raquel Pérez-Aloe and Prof. Miguel Ángel Domínguez. •Thesis title: High-Voltage Compliant Neurostimulator With On-Chip Power Management in Standard CMOS Technology.! •Advisors: Dr. Manuel Delgado Restituto and Prof. Ángel Rodríguez Vázquez. Seville, Spain [email protected] •Advisor: Prof. Alexandre Schmid. •Designing mixed-signal circuits for In-Memory Computing solutions. •Lecturer in electronics and engineering subjects in the Faculty of Physics and the Higher Technical School of Engineering of the University of Seville. •Developed Android applications and back-end Python scripts for processing data obtained with the company’s electrical bioimpedance-based technology.