An Amplified Offset Compensation Scheme and its Application in a Track and Hold Circuit.

1549-7747 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2017.2695162, IEEE Transactions on Circuits and Systems II: Express Briefs 1  Abstract - This paper proposes a fully differential track and hold circuit using a new DC offset compensation scheme. It stores an amplified version of the offset during the hold phase, which is used in attenuated fashion during the track phase to compensate offset. This scheme is less sensitive to charge injection and other errors than conventional offset compensation schemes. Experimental results of a test chip in 0.18 µm CMOS technology verify the proposed scheme. Index Terms –Sample and hold (S/H), Differential difference amplifier (DDA), Mixed-signal circuits, Offset compensation. I. INTRODUCTION C offsets drastically limit the performance and accuracy of analog and mixed-signal blocks, such as sample-and-hold (S/H) circuits. A common S/H circuit that cancels the input offset voltage of the op-amp [1] is shown in Fig. 1a and it operates as follows: 1) During the sample phase ΦS, S1 and S2 are closed and S3 is open, so, the op-amp is connected with unity gain feedback and the capacitor stores the value VCin=Vin-Vos. 2) During the hold phase ΦH, S1 and S2 are open and S3 is closed, so, Cin is connected to the output of the op-amp and the output voltage takes a value VCin+Vos=Vin. An advantage of this scheme is that the inputs of the op-amp always remain at a constant voltage (close to mid supply) and do not change with the applied input signal. Disadvantages of this scheme are that the accuracy of offset compensation is affected by charge injection Qinj from S2 when it opens. This introduces and error ΔVo=Qinj/Cin in the voltage VCin that leads to a modified value VCin’=VCin+ΔVo=Vin-Vos+ΔVo. Given that the offset voltage is very small, the charge injection error ΔVo can be comparable to Vos unless large capacitors Cin are used. Increasing Cin (which is in the signal path) is detrimental to speed because it adds non-dominant poles. Also, the output resets to zero during the sample phase and this imposes a speed limitation. The fully differential (FD) configuration of the circuit shown in Fig. 1b alleviates the charge injection problem, however, the mismatch of charge injection of S2 and S2’ and of the input capacitors still limits the accuracy in the offset cancellation. This scheme is representative of most offset cancellations schemes that store the relatively small value Vos at face value during one phase and compensates it during a second phase [2]-[4]. S. Pourashraf and J. Ramirez-Angulo are with the VLSI Laboratory, Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM, 88003, USA (e-mail: [email protected]; [email protected]). A. R. Cabrera-Galicia is with the Electronics Department, National Institute for Astrophysics, Optics, and Electronics, Puebla 72840, Mexico (e-mail: [email protected]). (a) (b) Fig. 1. Simple switchedcapacitor sample and hold. (a): Single ended. (b): Fully differential. A simple, non-offset compensated fully differential track and hold (T/H) circuit [1], [5] that does not reset the output of the op-amp to zero is shown in Fig. 2a. It is based on a two-stage Miller op-amp with two differential input stages (differential difference amplifier) [6]-[7] whose outputs are connected in parallel at nodes A and B to common active loads. The transistor level implementation of Fig. 2a is shown in Fig. 2c. Nodes A and B drive a FD output stage. A. J. Lopez-Martin is with Department of Electrical and Electronic Engineering, Public University of Navarra, 31006 Pamplona, Spain (e-mail: [email protected]). R. Carvajal is with the Departamento de Ingeniería Electrónica, Escuela Superior de Ingenieros, Universidad de Sevilla, E-41092, Spain (e-mail: [email protected]). An Amplified Offset Compensation Scheme and its Application in a Track and Hold Circuit Shirin Pourashraf, Member, IEEE, Jaime Ramirez-Angulo, Fellow, IEEE, Alfonso R. Cabrera-Galicia, Member, IEEE, Antonio J. Lopez-Martin, and Ramon González-Carvajal, Senior Member, IEEE D 1549-7747 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2017.2695162, IEEE Transactions on Circuits and Systems II: Express Briefs 2 (a) (b) (c) Fig. 2. Clocked fully differential conventional T/H. (a): Internal structure. (b): Voltage follower configuration. (c): Transistor level schematic. It operates as follows: During the track phase, switch S2, S2’ are closed and S1, S1’ are open. This connects the op-amp as a FD voltage follower (Fig. 2b), and the output voltage follows the input voltage including the offset error Vo=Vin+Vos1+Vos2. At the end of the track cycle, when S2, S2’ opens, the output voltage is held during the hold phase in the compensation capacitors Cc and the outputs of the first stage (A1) are connected to DC voltages Vbias in order to prevent their saturation. A sample and hold can be implemented by cascading two track and hold circuits with complementary control phases. This scheme allows higher operating speed since the output of the op-amp does not go to zero during the track phase ΦT. An additional advantage is that no capacitors are inserted in series with the signal path. In section II of this paper we present a modified offset compensated version of this circuit. It includes additional auxiliary circuitry that stores an amplified version of the total offset. This makes the scheme less sensitive to charge injection, and to other errors. Simulation and experimental results are discussed in section III. Summary and conclusions are given in section IV. II. PROPOSED OFFSET COMPENSATED MILLER T/H The track and hold (T/H) circuit of Fig. 3 is a modified version of the circuit of Fig. 2 that is able to compensate offset by storing its amplified version. This is done in order to make offset compensation less sensitive to charge injection and to other errors. A differential input stage (Aoc1) and an auxiliary differential output stage (Aoc2) have been added in order to store an amplified version of the total offset voltage. The outputs of three input stages (terminals A and B) are connected in parallel. Fig. 3c shows the transistor level schematic of the proposed T/H. The auxiliary input stage (Aoc1) is formed by transistors Mn3, and Mn3’ while the auxiliary output stage (Aoc2) is formed by Mocp, Mocn, Mocp’, and Mocn’. The proposed circuit works as follows: 1) During the hold phase ΦH, switches S3, S3’, S5, and S5’, are closed (Fig. 4a). This connects the inputs of the main amplifier to ground while the auxiliary amplifier implements an amplifier with gain Goc=1+R2/R1. Its output voltage is given by Voc=(1+R2/R1)(Vos1+Vos2+Vos3). 2) During the track phase the main amplifier is connected as a FD buffer and the amplified offset Voc is held by the compensation capacitors Ccoc (Fig. 3b). In this case Voc performs as a DC voltage source that generates a voltage VX-VX’=Vos1+Vos2+Vos3 at the input of the auxiliary amplifier. This compensates the offset of all input stages and leads to an offset free main amplifier output Vo=Vin. 1549-7747 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2017.2695162, IEEE Transactions on Circuits and Systems II: Express Briefs 3 (a) (b) (b) (c) (d) Fig. 3. Clocked fully differential offset compensation T/H. (a): Internal structure. (b): Voltage follower configuration. (c): Transistor level schematic. (d): Implementation of CMF in FD T/H. (a) (b) Fig. 4. Proposed T/H circuit including offset voltages. (a): During hold phase ΦH. (b): During track phase ΦT. 1549-7747 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2017.2695162, IEEE Transactions on Circuits and Systems II: Express Briefs 4 Remarks: a) The proposed scheme is less sensitive to charge injection errors than conventional schemes since it stores an amplified version of the total offset Voc in Cc. In practice, Goc is subject to gain errors due to the finite gain of the DC loop and to resistive loading. Given that the offset compensation voltage VX-VX’=Voc/Goc is an attenuated version of Voc the gain errors are cancelled out and do not affect the accuracy of the proposed scheme. b) Output offset compensation schemes in multistage comparators also store an amplified version of the input offset in capacitors in the signal path [8]. However, they are feedforward structures that have no global feedback. c) Conventional auto zero techniques also use an auxiliary amplifier to store an offset compensation voltage Voscomp in a capacitor given by Voscomp=(Am/Aa)Vosm+Vosa where Am and Aa are the gains of the main and auxiliary amplifiers respectively and Vosm and Vosa are their associated offsets [8]. It can be seen that Vosm is amplified by a factor Am/Aa (typically about 10) while Vosa is not amplified. Due to this, the cancellation of Vosa remains sensitive to charge injection errors. Also, in auto-zeroing techniques the switches connected to the offset storage capacitors have a charge injection error that depends on the stored amplified offset voltage (Voscomp). The switches do not have the same charge injection since their gate-source voltages are not equal. This is due to the fact that the switches transfer complementary voltages (Voscomp/2 , -Voscomp/2) to the offset storage capacitors. This also makes conventional auto-zero techniques sensitive to charge injection even without mismatch in the switches. The approach proposed here is less sensitive to charge injection because all switches driving Ccoc, and Cc (S1, S1’, S2, and S2’) have equal and constant gate-source voltages that do not depend on the amplified offset voltage Voc stored in the Miller capacitor Coc. d) Note that the proposed scheme, as opposed to a ping-pong architecture, i.e. [9], stores an amplified version of the total offset during one phase. Ping-pong architectures use two independent auto zeroing stages operating with alternative phases. e) The DC offset compensation loop (auxiliary stage) in the proposed scheme increases power consumption and area. Since the output of the auxiliary stage is not connected to a capacitive load, the compensation capacitor Ccoc can be small. (Fig. 3c) and Aoc2 can operate with low quiescent current and down scaled transistor sizes i.e. by a factor of 5 but at the same time with the same bandwidth as the main feedback loop. This allows to decrease the power and area requirements of the DC offset compensation circuitry and the quiescent power dissipation by %20. f) In order to improve the accuracy of the offset compensation without the risk of saturating the output of the auxiliary amplifier, a moderate gain Goc=20 was selected. In this case, with typical offsets Vos~5-10mV the output Voc still represents an essentially amplified version of the total offset Vos=Vos1+Vos2+Vos3. g) The proposed circuit uses two common mode feedback networks (CMF). Their common mode control voltages Vcnto and Vcntoc are connected alternatively to VcntCM as shown in Fig. 3. h) Resistors R1, and R2 in Fig. 3 contribute to input noise. In order to reduce this contribution, a capacitor (in parallel with R2) can be used to limit the resistor’s noise bandwidth. III. SIMULATION AND EXPERIMENTAL RESULTS A test chip prototype including a non-overlapping clock generator, and both the conventional and offset compensated Miller T/H circuits of Figs. 3 and 4 respectively were fabricated in 0.18 µm CMOS technology with NMOS and PMOS threshold voltages of approximately 0.45 V. Fig.5. Photograph of test chip including offset compensator and conventional T/H designs. Fig. 6. Floating battery acting like an externally controllable DC offset source for test purposes. 1549-7747 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2017.2695162, IEEE Transactions on Circuits and Systems II: Express Briefs 5 (a) (b) Fig. 7. Experimental Input and output differential waveforms of fabricated circuit (100 mVpp at 100 kHz input signal, 1 MHz input clock, and 40 mV total offset). Horizontal scale 2 µs/div., vertical scale 20 mV/div. (a) Proposed T/H. (b) Conventional T/H. The unit transistor dimensions in micrometer are (W/L)p=(100/0.7) and (W/L)n=(20/0.7). Sizes of PMOS and NMOS transistors of NAND and Inverter gates used in digital non-overlapping clock generator are respectively (W/L)p(NAND,INV)=(0.88/0.22), and (W/L)n(NAND,INV)=(0.44/0.22). PMOS and NMOS transistors in the complementary switches had dimensions (W/L)psw=(W/L)nsw=(0.22/0.22). Capacitances and resistors have values Cc=10 pF, Ccoc=2 pF, Rz=3 kΩ, Rzoc=1 kΩ, R1=8 kΩ, R2=150 kΩ. Fig. 5 shows the micrograph of the fabricated chip. The dimensions of the conventional and offset compensated circuits were 372 µm × 190 µm (0.07 mm2) and 400 µm × 270 µm (0.11 mm2) respectively. Three independently controllable floating batteries generating offsets Vos1, Vos2 and Vos3 were included in the circuit for testing purposes. They were implemented as shown in Fig. 6 using two matched DC current sources IBos and a resistor Ros=5 kΩ in parallel with a small bypass capacitor Cbyp=1 pF. The circuit was simulated and tested with dual supplies ±0.9 V; a bias current Ibias=200 µA and load capacitance CL=23 pF. Simulations of the circuit of Fig. 3 (with ΦH set to VSS and ΦT to VDD) led to a DC open loop gain Aol=53 dB and gain-bandwidth GB=40 MHz. The circuit was able to remove accurately large offsets even when the peak-peak input signal was as small as 50 mV and the total offset around 40 mV (Vos2=Vos3=Vos3=13.5 mV). Figs. 7a and 7b show the experimental input and output waveforms of the proposed offset compensated and conventional T/H. The circuits were tested with 100 mVpp 100 kHz input signal with a 1 MHz clock and a load capacitance CL=23 pF. The total applied offset (controlled externally) was approximately 40 mV. Harmonic distortion measurements with the presence of total applied offset Vos=40 mV shows that SFDR is 7 dB higher in the proposed scheme (68 dB) than in the scheme without offset compensation (61 dB). IV. CONCLUSION A method for offset compensation in Miller (Integrating) sample and holds was presented. It stores an amplified version of the total offset in Miller capacitors and this amplification reduces its sensitivity to charge injection. Experimental results of a test chip in 0.18 µm CMOS technology validated experimentally that the circuit can compensate large DC offset voltages. REFERENCES [1] T. C. Carusone, D. A. Johns, and K. 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