HADES-1: A rapid prototyping environment based on advanced FPGA’s

HADES-I: A Rapid Prototyping Environment based on Advanced FPGA's M.A. Aguirre, J.N. Tombs, A. Torralba and L.G. Franquelo Departamento de lngenierla Electr6nica. Escuela Superior de lngenieros de Sevilla Avda. Camino de los Descubrimientos sin {aguirreJon,torralba,leopoldo }@gte.esi.us.es Abstract Rapid protolyping of large digital systems is becoming supported witb tbe use of new advanced FPGA's. These FPGA's ean give mOre Information than functional simulation and emulation tasks, due to their inner inspection features~ Tbis paper presents HADES-l, a new environment for rapid prototyping and hardware debugging. HADES-l is based on one FPGA of the VIRTEX family, exploiting the advanced features of the SeleetMap port and a fast link witb tbe bost PC. 1. Introduction The improvements in the area of microelectronics lead to shorter design cyeles and rapidly rising complexity of electronics designs [I]. Therefore, developers are forced to refine the system development process to avoid a productivity gap. Rapid prototyping is a technique to support the system development. The tenn rapid prototyping is defined as a type of prototypiog in which emphasis is placed 00 developing prototypes early in the development process to pennit early feedback and analysis. Thc tradltional development process can be represented in the V-model (fig I). The V-model enhanced by different levels of rapid prototyping is called VP-medel[2]. The idea of rapid prototyping is to skip time intensive steps of the development process, and reduce the time to get a first functional prototype of the entire system or a part of the system. This prototype allows the validation of functionality and early pcrfonnance tests. Tile comparison between different design alternatives can be simplified and therefore the conceptoal validation rises. Compared to system simulation, rapid prototyping offers a test in the real environmeot. Hence, real-time behaviour, interferences and interfaees with the real environment must also be taken into account. Three different levels can be distinguished: • Concept oriented rapid prolotyping represents Ihe fast conversion of an executable specification into a functional prototype. This prototype serves 32 10 clarify system goals and must support a widespread range of hardware interfaces, The concept is orienled at high level. The support environment is not specifie and can be reused for other prototypes. • Architecture-oriented rapid prototyping, where the final architecture of the system is fixed. Some components of the entire system are already developed or standard components are used, whilst other parts are stitt ueder line development. • implementation-oriented rapid prolotyping is highly specialized and precise, the prototypes don't permit a widespread applicability. Usually it is fonned from several final release components surrounded by new components. This approach allows performance analysis. Requirements Elicitati Syst Spacilica Module Design System se Module Test Fig 1. VP Diagram for Rapid Protolyping This paper describes the solutions for a cost effective environment that supports prototyping in the first level and second level, named HADES-I (HArdware DEbugging System). HADES-J is a framework 10 exploit the most specialised characteristics of edvanced FPGA's. It eonsists of a prototypmg board which is presented as a digital microelectronic insystem emulator [34]. There are three main lines that have hecn extensively developed in HADES-I: • For large digital system analysis, an advanced FPGA is used with an extensive use of its high flexibility, capacity and performance. • For some primary perfonnance analysis a system clock eontroller is introdueed. now on referred to as the C-FPGA). This C-FPGA works as an interfaee between the host PC, the General purpose Signals for System Interface Low Speed Control Signals Host Controller Figure 2. Overview of HADES-l System • For human analysis purpose a fast and seeure link with a host PC takes control of the internal features of the FPGA. This paper is organised as follows. In Section 2 the system hardware is described. section 3 and 4 show the interface with the internal parts of the FPGA and the system clock controller and, section 5 the link with the host PC is shown and seetion 6 the software is described. 2. Overview ofHADES-l HADES-I consists of a system for emulating large digital circuits using an advanced FPGA. HADES-I has been developed using a VIRTEX device from XILINX, using any member of this family with a PQ240 footprint. A photo of HADES-I is shown in figure 5. HADES has all the functional pins available for being use in the system, without any specialisation. In this way HADES can be adapted for the requirements of any system. Figure 2 shows a scheme of HADES-I and its most interesting features. The core for control and analysis features is a second FPGA, one XC40lOXL also from XILINX, (from 33 VIRTEX programming and debugging system, the programmable oscillator and some static Input/output lines. The C-FPGA solves the link between the host PC and board. This part will be described in detail in seetion 5. Internally, the C-FPGA is organised as a memory map deviee with 32 memory addresses. This C-FPGA runs with the built-in clock to make it absolutely independent of the on-board oscillator. C- FPGA has a fixed program that is downloaded during board start-up time. However C-FPGA can be booted from another program due to the availability of a flash memory. As clock system is an essential part of a prototype we have introduced a programmable oscillator dcviec from Dallas, DS-1075. This progranunable oscillator can be in-run-thoe programmed form the host PC in runtime, without any effect on the Virtex FPGA. 3. Interface with VIRTEX The fastest and simplest way to interface with VIRTEX FPGA (from now on the S-FPGA) is using the call SeJectMap method. SclectMap is a parallel port that can be read and written in an asynchronous process, this is the fastest configuration method. From the host PC every byte of the configuration file i. downloaded through this port and every sequence of the control signals is generated from an internal state machine. This state machine is also designed to be used for reading S-FPGA, allowing the configuration and the internal state of the S-FPGA to be transferred and analysed in the host PC. Some internal checks are introduced in the downloading process to avoid potential damages inside the S-FPGA due to an almost impossible (note "almost") potential mismatch in the programming method. This requires the stan-up process to be well controlled. In the case of successful progranmling the nost receives a flag on the start-up from the S-FPGA. 4. System Clock Controller One of the most interesting features for a Rapid Prototyping system is a full controlled Sysrem Clock. We have selected the well-known programmable frequency clock generator from Dallas DS-I075. This oscillator can generate frequencies from a base frequency characteristic of every DS-l075 model. This oscillator can be programmed to frequencies given by f,,,,,iN, with N=I, ... ,SI2, and f bB ., 60, 66, 80 and 100MHz. Other commercial prototyping boards also use this oscillator, but for its programming method it needs a power-off plus power-on sequence for the programmed process. In HADES-l this process has been introdueed automatically and controlled by the host PC through the C-FPGA. The System Clock can be stopped if needed, and from the PC the oscillator ean be programmed, inspected and modified. C-FPGA I I ... ...! L----.System Ctock Figure 3.Programmablc Oscillator Control Scheme Due to its programming method, that shares the same wire for programming and for the system clock, the clock is connected to the C-FPGA to generate the programming sequence {Dallas I-Wire propeny)[9], The Power-off plus power-on programming sequence is only performed on DS-1075, as the C-FPGA controls a set of analog switches that allow the clock power, and clock stopping as well. 5. Link with the host PC The system programming and analysis process can only be done using a fast and robust link. HADES-l uses a well-known and common protocol called EPP[S]. EPP means Enhanced Parallel Port and is described in the IEEE-1284 Standard. EPP is a bidirectional and hardware controlled link that ean achieve speeds between 500Kbytes!s to 2Mbytes!s that is more than enough for our purpose. A Vinex 800 S-FPGA needs 576 Kbytes for its configuration. Due to the control process the configuration would be perfonned in less than 2 seconds. The C-FPGA has a state machine that produces a dialog between the PC and the board. It generates the neeessary handshake signals and decouples addresses and data in the designed memory map. The state machine is depicted in figure 4, and it shows how it generates a single clock cycle read, write and address pulse and the wait handshake signal. Figure 4. EPP Interrace State Machine 6. HADES-l Software. The host PC implements the human-machine interface. The design is developed using the standard desigu flow using Xilinx tools. When the bitstrearu file is produced, HADES-Software can read this file and download it into the S-FPGA, during the configuration process. Also, the HADES-Software allows an easy control of the system elock frequency, and the configuration and readback processes from S- FPGA and panial reconfignration of the device. The software is a Windows based tool and uses a lowlevel control of the parallel pan. Figure 6 shows the dialog window for the Oscillator and figure 7 shows the S-FPGA programming dialog window, Other useful features that have been included in lbe software, such as inspection chans. These allow the observation of the current content of lbe internal f1ip- flops of the S-FPGA after a capture command has been done, The inspection pmcess goes as follows: I. During the standard design flow two files are generated: bitstream ffile.bit) and eross reference (file.ll), 2. The bitstream generation have to keep the programming port active, 3. An speci.l internal reading allows a downloading of the intern.l state from the FPGA. A new file (file. CLB) is created. 4, From tlle file.!l the exact place of the information inside the file.CLB and can be reconstructed. Theftlc,1I only gives the information for those nodes that has not been eollapsed by the synthesis process. If a particular node is desired to be explicit, adequate cOlrunands can be introduced for preserve hierarchy. Figure 8 shows the window chart for the signal selection of an example design. Also shows the result of an inspection process uploaded from the board. Figure S. HADES-l Board 7. Conclusions and Future Work In this paper we have presented a new board for large digital circuit emulation and rapid system prototyping. It can run a. an in-system circuit 35 emulator with many hardware debugging eapabilities. It also has full control of the system eloek. Currently, we've under development some new features fOT HADES-I: 1. Development of a dedicated port for the construction of a multi-board system, for parallel processing proto typing system. 2. Easy modification of the C-FPGA eon figuration. 3. HADES-2 will have one VIRTEX-E and one SPARTAN for the S-FPGA and the C-FPGA, respectively, 4. Run-Time partial reconfiguration using JBITS classes The up to date information about this project is weekly maintained in the web site: http://woody.us.esl-aguirrelhades.html Figure 6. Programmable Oscillatnr Dialog Window 7. Bibliography [1] Dolla., A. Kanopoulos, N, «Reducing Time to Market Through Rapind Prototyping". IEEEComputer, Feb, 1995. [2]A.Burst, B.Spitzer, M.Wolff, K.D. MUller-Glasser. "On Code Generation of Rapid Prototyping Unsing CDFI". OOPSLA'98, Vancouver, CA [3] Hutchings B., Nelson B. and Wirth lin M.L "Designing and Debugging Custom Computing Applications". IEEE Design & Test of Computers. Jan-March 2000. pp 20-28, [4] Koch A. "A Comprehensive Prototyping-Platform for Hardware-Software Codesign". II" IEEE Internation Wnrkshop on Rapid System Prototyping. Paris Jun-2000. pp7S-82. [5] Xilinx. Co, "The Programmable Logic Darn Book". 2001. [6] Xess Co. XSV Board Vl.O Manual. March 2000 [7] Insight. Virlex-E Deyelopment Kit. Aug-2000 [8] Peacock C. "Interlacing the enhanced parallel pori". http://www.senet.com.aw-coeacock. D .... 1997. [9] DS-I075 Datasheet. Figure 7. S-FPGA Pr<>gramming Dialog Window Figure 8 HADES-l Analisy. window 36