EC-RASP: A new electrical energy static counter based on random signal processing conference topic: IC's for instrumentation and control

EC-RASP: A new Electrical Energy Static Counter based on Random Signal Processing S. Toral, J. M. Quero and L. G. Franquelo Dpto. de Ingenier´ıaElectr´ onica EscuelaSuperior de Ingenieros, Avda. ReinaMercedes s/n, Sevilla–41012(SPAIN) Tel.: +34(9)5 45568 57 FAX: +34(9)5 45568 49 e–mail: [email protected] Conference Topic: IC’s for instrumentation and control Abstract— Thispaperconcernsthedesignanddevelopmentof electrical energy static counter, based on random pulse stream processing. Measurementproceeding, calibrationand hardware implementation are checked in a prototype. As a result, a simple low cost measurement system has been obtained. The resulting measures have been compared with the ones obtainedusing a poly phase commercialanalyzer. A maximum 2% error has been achieved. This measurement proceedingis patentpending. I. STATE OF ART Historically the monitoring of electrical energy consumption has been done by various types of induction watt meters. The conventional induction watt meter, with rotating disc and shaft, contains a mechanical register (driven by a gear on the shaft) which continuously displays the total accumulated kilowatt hours consumed. Switch or clutch activable mechanical demand and time of use registers are also used on these meters to display demand and time of use quantities. Electronic registers are in common use todaywith induction type watt meter, to accumulate pulse data proportional to power consumption. This pulse data is usually provided to the register from an optical pick up or sensor device which senses meter disc rotation. These registers have the advantage that they can perform calculations on accumulated pulse data and electronically display much more information than ispossiblewith conventional mechanical type registers. Nowadays, better performances are required and achieved using static counters. In this sense, electric companieshave foundit desirable tomeasure, in addition to total kilowatt-hours, power factor, KVA, or reactive volt amperes. The measurement of reactive volt amperes typically has been accomplished by using a second meter in conjunction with the conventional kilowatt-hour meter. From thereactivevoltamperesandtherealvoltamperes, quantities such as power factor and KVA can be calculated. This second meter for measurement of reactive volt amperes is a wattmeterconnected withphaseshiftingtransformersin thevoltagecircuits. It is also interesting to provide the capability to digitally configure the meter to measure electric energy flow in any of the different electrical services. Finally, it is desirable the possibilityof connecting to either single phaseor poly phasepower line systems. All these characteristics should be accomplished by low cost and precise simple devices. Presently, electronic counters and watt meters use either analog circuits, or an analog to digital conversion, followed by a pure digital processing, basedonmicroprocessorsystems,microcontroller systemsor digital signal processor (DSP). Inthefollowing,severalpatentsaredescribed. European patentNo. 94110967.0[1] describes a static kWh meter that makes use of an analog multiplier. From the pulse-width modulated voltage, a pulse-width/pulse-height modulated signal, proportional to the power, is generated, using analog connectors. A frequency signal is thus obtained, which is passed through a divider circuit to the counter of the kWh meter for determination of the energy that has been consumed. Analog connectorshaveadetrimentalproperty, becausetheyproduce extra voltage and current pulses in the signal to be measured. So, it is necessary to compensate this effect, including an additional electronic to solve the problem. Besides, typical disadvantages ofanalogelectronic devices are present: noisesensitiveness, thermical sensitiveness, manufacturer tolerances ::: European patent No. 94203283.0 [1] uses a digital signal processor from the analog todigital conversion of voltage and current. High number of performances are achieved at the expenses of a high cost device. In this paper a new static energy counter is presented. That is, a counter in which both current COMP |U| COMP INC/DEC I U |I| (1) (2) (3) (4) (6) (7) (8) (9) (10) (11) (12) (13) (15) (14) CAD CAD sign(I) 10 10 10 10 U II ld f m f e f l m U d I e U e (5) sign(U) SENSOR NUMBER GENERATOR RANDOM COUNTER Figure 1: Detailed block diagram and voltage change properties of solid state electronic devices, generatingpulsesoffrequency proportional to kWh. At first, current and voltage are sensed and digital converted. Stochastic pulse streams are produced by comparing these digital numbers with random numbers. The multiplier is achievedbyasimpleANDgate. Itsoutputisarandom pulse stream that represents instantaneous active power. Time integration is achieved by a digital counter. It should be noticed that stochastic signal processing is entirely digital. In contrast with the last mentioned method our digital circuitsareextremelysimpleandeasilyimplemented in low cost programmable devices or ASICs, preserving all the performances described above. In the following sections, it will be explained in detail the design and development of the measurement system. First of all, it will be described the mono phase architecture of an active energy counter, that has been implemented. Prototype characteristics, calibration proceeding and illustrative measurements will be shown next. Finally, possible generalizations and several conclusions will be withdrawn. II. MONO PHASE ARCHITECTURE Figure 2 is a simplified block diagram of the electronic meter: Rectified current and voltage signals are digital converted. Stochastic pulse streams are produced by comparing thesedigital numbers with random numbers. The multiplier is achieved by a simple AND gate. Instantaneous power, coded in the random pulse stream at the output of the AND gate, is time integrated by a counter thatincreasesodecreasesitsvalueaccording tothe multiplying signal signs. Figure 1 is a detailed logic block diagram. Blocks (1) and (7), connected to the wires of the U I 1 1 ADQUISITION ADQUISITION SIGNAL SIGNAL COUNTER up/down sign(U) sign(I) CONVERSION RANDOM PULSE RANDOM PULSE CONVERSION Figure 2: Block diagram electricity network generates measures U l and I l , proportional to voltage (U) and current (I). Blocks (2) and (9) rectify both magnitudes and (3) and (10) calculate the sign. (4) and (11) make analog to digital conversion. (5) generates pairs of random numbertogetrandompulsestreams U e e I e . AND gate (13) generates the random pulses stream P e , which codes instantaneous power. This power is integrated by a counter (14), which increases or decreases according to voltage and current signs. III. REALIZATION Infigure3aphotographoftheprototypeisshown: The prototypeisa monophase staticactive energy counter. This test board has been developed as a PC expansion board, in order to debug hardware easily. The test board includes a current interface with tariff devices, according toDIN 43864. Every 3600 W  s , it is generated a current pulse greater than 30 ms. Measurements of both current and voltage are taken from two transducers, according to figure 4. Actually, voltage transducer is not necessary. It could be used a simple resistor voltage divider. R 1 − + +12V -12V R 1 Vo = RVi 0 si Vi > 0 5 si Vi < 0 − + +12V -12V (x=i,v) Rx RR R − + +12V -12V Vi Vo Zener Roffset 5 V sign = Zener 4 V I transducer To A/D input To FPGA input Figure 5: Rectification circuit Figure 3: Prototype Rectification circuit is illustrated in figure 5. Once signal acquisition has been completed and digital converted, data is fed into an Actel FPGA, 1020B, 509 logic blocks of 547 [3] [4] (93 %) (figure 6). The FPGA has been designed with Verilog [5] and synthesized with Cadence. Clock and supplies are taken from PC. Frequency clock is 8 MHz and sampling speed is 250 kHz. So, for each sample, 32products ofrandom streamsare computed. Internally, arandomnumbergeneratoranda32bit counter, according to figure 1, is implemented insidetheFPGA.Thiscountercanbeeitherincreased or decreased, and is readable from the PC. Every time the PC reads the less significant byte of the counter, itresets automatically. This functionality has been included for debugging purposes. IV. CALIBRATION It is necessary to define a calibration proceeding of the measurement system according to the scale limits. Maximum voltage value is 380 V, and maximumcurrent value 7A. Thatmeansthatthevalue (LA 25-NP) I in - + I out Ri Vss (-12 V) Vcc (+12 V) M Current Voltage (LV 25-P) I out Vss (-12 V) Vcc (+12 V) M Rv V in + ΗΤ − ΗΤ 25 k Ω Figure 4: Schematic diagram of transducer connections . . . data addresses clk reset Supplies +5, -5, +12, -12 FPGA MAXIM MAXIM 1020BNF MAX151 MAX151 Figure 6: Test board of a counter unit will be: 1 pul se = V  I 8  106 W  s = 3 : 325  10 , 4 W  s Maximum counting time is: T ime = 232 8  106 = 536 : 87 s = 8 : 947 min In two FPGA’s pins, we extract voltage and current random pulse streams, and, with a very simple circuit, we recover analog value. This circuits consistsof alow passfilter [6]. Calibration is done by two potentiometers that modify voltage and current gain. A DC powersupply has beenused to modifyvoltage between 0 and 100 V. For 100 V and 3.75 A, analog value of current and voltage has been recovered at the end of the chain, that is, at the output of FPGA. Potentiometers has been calibrated so that we get the equivalent value of 100 V and 3.75 A atthe output ofthe FPGA. Once calibration isfinished, inter mediumvaluesare takentocheck calibration quality. The result is illustrated in figures 7 and 8. Y axis represents in both cases the mean value at the output of the low pass filter, as mentioned above. 0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 450.0 500.0 Voltage Mean value (mV) Figure 7: Voltage calibration 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 0.0 100.0 200.0 300.0 400.0 500.0 Current (A) Mean value (mV) Figure 8: Current calibration It can be observed that we do not cover the whole voltage and current scale, because our DC power supplyisonlyupto100V.Besides,thereisanoffset incurrentandvoltagecalibrationthatcorresponds with one bit of the analog to digital converter. Continuous power measurementerror, for 2s time intervals, is detailed in figure 9. It has been representedrealpowerandexperimentalpoweragainst voltage. 0.0 100.0 200.0 300.0 400.0 0.0 100.0 200.0 300.0 400.0 actual power measured power Figure 9: Continuous power measurement error V. MEASUREMENTS Measurementshave been done using a polyphase analyzer Equa, based on a DSP technique, as a reference device [8]. Internally, Equa has a 0.2 % error in measurement of voltage and current. All other magnitudes are computed from these ones. Reference device uses the following equation to compute magnitudes:  RMS voltage: V L iN = v u u t P P k = 1  2 L iN k P  RMS current: I L i = v u u t P P k = 1 i 2 L i k P  Active power: W L i = P P k = 1  L iN k  i L i k P  Reactive power: Q L i = P P k = 1  L iN k  i L i ( k , ) P  Power factor: PF L i = W L i p W 2 L i + Q 2 L i whereP=128,i=1,2,3y  =P/4. Itcanbenoticedreactivepoweriscomputedusingold current values instead of shifting instantaneous current value. Experimental results are separated from load:  Resistive power factor: PF EC-RPS Equa Error 1 553.6 557 0.6 % 1 569.4 573.8 0.76 % 1 1088 1104 1.45 %  Capacitive power factor: PF EC-RPS Equa Error 0.888 439.4 443 0.81 % 0.885 447.5 451 0.77 % 0.693 537 546 1.64 %  Inductive power factor: PF EC-RPS Equa Error 0.994 536 538.7 0.50 % 0.994 556.8 560.6 0.67 % 0.979 1032 1045 1.24 % 0.979 513.5 519 1.05 % 0.979 524.8 530.6 1.09 % 0.923 900 916.3 1.7 % 0.910 86.81 86.13 0.78 % 0.834 81.88 82.3 0.51 % Measures under 2% error are achieved. According to [7], this device would be a class 2 static counter. In futures improvements, lower error values are expected. We can mention, although we have not included such results, the stability of measurements. The standard deviation of results is very low. VI. GENERALIZATIONS From the mono phase description, its poly phase versioncanbeeasilydeduced. According tofigure 2, its generalization is drawn in figure 10: A multiplexor is utilized to combine the power signal streams for each phase. Each phase is sequentially selected, increasing o decreasing the counter according to signs. The final result is a random codification of n-th part of instantaneous poly phase power at the multiplexor output, integrated in time by the counter. Reactive power measurement is done by integration of reactive power. In the mono phase architecture, current is the same of the mono phase circuit, but voltage shifts 90 degrees respect voltage of mono phase circuit (figure 12). U 1 90 o ADQUISITION ADQUISITION STOCHASTIC CONVERSION STOCHASTIC CONVERSION up/down CONTADOR I 1 U 1 ’ SHIFTED SIGNAL SIGNAL Figure 12: Reactive energy computation: mono phase architecture Reactivepolyphaseenergywillbethesumofreactive mono phase reactive energy. Again, the same multiplexor strategy is applied (figure 11). VII. CONCLUSIONS This paper describes the complete proceeding of design, development and calibration of an electrical energy counter based on random signal processing. It has been developed a FPGA prototype with satisfactory results. Above, it has been explained all the generalizations over this simple prototype,sowecanachieve similarutilitiesgiven by moderns measurement equipments, based on DSP. But, as a great difference with these equipments,wehaveimproved alowcostmeasurement system. One of these equipments have been used as a reference device. A maximum 2 % error has been obtained under any load condition. As a future improve, we can think in an ASIC implementation. It would be positive a mixed technology ASIC, including analog to digital converters. This way, it would be only necessary a previous stage of signal acquisition before ASIC, reducing manufacturing cost. This measurement proceeding is patent pending [9]. REFERENCES [1] Lahti,Teuvo. Europeanpatentapplication,No. 94110967.0 . ENERMET OY. [2] W. R. Germer, M. Negahban-Hagh, M. J. Ouellette, B. White. European patent application, No. 94203283.0 . SILICON SYSTEMS, INC. [3] The AC T TM Family Macro Library Guide Actel Corporation. [4] Field Programmable Gate Array. Application Handbook . Texas Instruments. [5] Verilog-XL. Reference Manual, vol 1,2,3 . Cadence Design Systems,Inc. [6] J.G. Ortega, C.L. Janer, J.M. Quero and L.G. Franquelo. “Analog to Digital and Digital to Analog Conversion Based on Stochastic Logic” . Proceedings IECON’95. [7] UNE-EN 61036:1994 . AENOR. [8] Electric Power Quality Analyzer . TeamWare. [9] J.M. Quero, S. Toral, L.G. Franquelo. Electrical energy static counter based on random signal processing. No. 9700600 . Seville University. SIGNAL ADQUISITION CONVERSION STOCHASTIC SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION . . . . . . mux U I 1 1 U I 2 2 U n n COUNTER up/down I Figure 10: poly phase system generalization SIGNAL ADQUISITION CONVERSION STOCHASTIC SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION SIGNAL ADQUISITION U 1 90 o 90 o 90 o . . . . . . mux I 1 I 2 I n COUNTER up/down 2 U 2 ’ U n ’ n UU U 1 ’ SHIFTED SHIFTED SHIFTED Figure 11: Reactive energy computation: poly phase architecture