Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.

º q Doctoral Thesis Industrial Electronics and Telecommunications Engineering Electronic Engineering Department Higher Technical School of Engineering University of Seville 2018 Author: Elena Cabrera Bernal Supervisors: Antonio Jesús Torralba Silgado Clara Isabel Luján Martínez Performance enhancement in the design of amplifier and amplifier-less circuits in modern CMOS technologies i Doctoral Thesis Industrial Electronics and Telecommunications Engineering Performance enhancement in the design of amplifier and amplifier-less circuits in modern CMOS technologies Author: Elena Cabrera Bernal Supervisors: Antonio Jesús Torralba Silgado Clara Isabel Luján Martínez Electronic Engineering Department Higher Technical School of Engineering University of Seville Seville, 2018 ii iii Tesis doctoral: Performance enhancement in the design of amplifier and amplifierless circuits in modern CMOS technologies Autor: Elena Cabrera Bernal Tutores: Antonio Jesús Torralba Silgado Clara Isabel Luján Martínez El tribunal nombrado para juzgar el Proyecto arriba indicado, compuesto por los siguientes miembros: Presidente: Vocales: Secretario: Acuerdan otorgarle la calificación de: Sevilla, 2018 El Secretario del Tribunal iv v A mi familia. vi vii Acknowledgements They are some many, the people to whom I have to show my gratitude, that I am afraid some lines may not be enough. Shall I start with my supervisors, Antonio Torralba and Clara Luján, as they gave me the opportunity of starting, developing and completing this exciting research, guiding me, with their expertise and wisdom, all along the path that has led me to the conclusion of this work. Must also thank the economic support from the Government of Spain that granted me under the program FPI-MICINN. I am also deeply grateful to Salvatore Pennisi, my advisor during my internship at the University of Catania and Esther Rodríguez, my advisor at Imperial College London. Not only they taught me about electronics, but also made me feel welcomed and at home. I want to mention also Jaime Ramirez as every talk I have had with him has been really inspiring. Thanks to all my research group at the University of Seville, especially Fernando Muñoz and Ramón G. Carvajal whose technical advice has been essential. Not to forget Enrique López, Jose Ramón García and Fernando Marquez, always willing to help, and all my colleagues in the office, whose company has made everything funnier and easier to stand. Every day, I am surprised how lucky I have been to share this period with not only a colleague but also a friend, Jose María Hinojo. The shared coffees, bacon and technical discussions (in the Spanish meaning of the word) may never be forgotten. This would have been much harder without you. Y por encima de todo, gracias a mi familia. Es por ellos que hoy soy lo que soy. Gracias a mi padre, a mi madre, a mi hermana, por ser un ejemplo a seguir, por su apoyo, paciencia y cariño incondicional. Gracias también a Seba que ha vivido a mi lado esta etapa, con todos sus malos y buenos momentos. Sois lo mejor que tengo. Os quiero. Elena Cabrera Bernal Sevilla, 2018 5 2. LOW-VOLTAGE OPERATIONAL TRANSCONDUCTANCE AMPLIFIERS ne of the most important blocks in analog microelectronics, is undoubtedly, the operational amplifier (OpAmp). It is used in a wide range of applications such as voltage regulation, filtering or analog to digital conversion among others, what makes it one of the most critical cell in any analog or mixed-signal system. OpAmps are usually composed by a differential transconductance stage, one or more high-gain stages, a compensation network and an output buffer, that allows to drive low-resistance loads. OpAmps that are not intended to drive low resistance loads are usually called Operational Transconductance Amplifier (OTA) [4]. In this chapter, the first line of this thesis is explored: the classical OTA cell is revisited in order to achieve competitive performances at extremely low voltage solution with the aim of making it suitable for modern technologies. For that purpose, three multistage low voltage bulk-driven OTAs are presented. O 6 Performance enhancement in the design of amplifier and amplifier-less Low Voltage Amplifier Design Techniques. On the one hand, low power is one of the most important areas in nowadays electronics. The huge consumer demand of portable devices with great autonomy makes low power a key feature for product competitiveness. Therefore, the interest in low voltage has significantly increased due to the limitation in power consumption. On the other hand, in modern submicrometric technologies the maximum allowed voltage supply has decreased more abruptly than the threshold voltage, Vth, dramatically reducing the available voltage swing in classical OTA topologies. Nevertheless, achieving high enough gains has become more challenging as transistor’s output resistance is reduced and, with the decrease of biasing voltages, the effective transconductance has also decreased [2]. Moreover, classical techniques such as cascoding are no longer appropriate for low voltage design. Consequently, low voltage design techniques are lately receiving plenty of interest. An overview of the most important ones is presented below. 2.1.1. Threshold lowering. As the main problem to achieve an appropriate signal swing in modern technologies is due to the high Vth values altogether with the reduced supply voltage, the more straightforward idea to implement a low voltage design is by reducing it. In some technologies, there are special transistors that perform low Vth o even zero Vth, but this usually implies higher costs and/or the use of special technologies. Still, there is another option: in standard devices the Vth values can be reduced using the bulk [5]–[10]. The threshold voltage is given by    =     +  󰇡  | 2   −   | −  | 2   | 󰇢 (2–1) where, Vth0 is the zero-bias threshold voltage, γ is the bulk effect factor and φF is the Fermi potential. This technique can only be used in p-type MOS transistors in standard CMOS technologies. 2.1.2. Subthreshold. Biasing transistors in the subthreshold region is an alternative way of increasing the voltage swing in a low voltage design [11]–[13]. Under these biasing conditions the gate-source voltage, Vgs, is slightly lower that Vth and the drain source voltage, Vds, only needs to be around one hundred millivolts to be in saturation [14], thus the voltage headroom is increased compared to strong inversion operation. Transistors in the subthreshold region are usually biased with small currents, Low-Voltage Operational Transconductance Amplifiers 7 what is advantageous in a low power design context. However, low biasing currents entails less slew rate and bandwidth. That is why this design technique is very common when low power consumption is required and speed is not a concern, for instance in biomedical applications [15]. 2.1.3. Non-Tailed Pair. The classical single-ended-OTA differential input stage is depicted in Figure 1 (a). It is well-known that in this structure, transistor MX implements a current source that sets the bias current through the input pair transistors, M1 and M2. However, MX consumes one Vds_sat1 of the available voltage headroom. Hence, getting rid of it will increment the voltage swing, making the structure suitable for low voltage design. In Figure 1 (b) the non-tailed version of the classical input stage is depicted. Removing the tail current, however, makes this stage pseudo-differential and with a severe deterioration of common-mode rejection ratio, needing additional techniques to achieve reasonable rejection [16]. A fully-differential version, with better common-mode rejection ratio can be achieved by the non-tailed input stage shown in Figure 1 (c) [10]. Nevertheless, both input stages of Figure 1 (b) and Figure 1 (c) need additional methods to control de biasing current through the input pair should be added as the lack of the tail current makes them extremely dependent on temperature and process variations [7]–[10], [17], [18]. (a) (b) (c) Figure 1: (a) Differential input stage of a classical OTA (b) Non-tailed version of the classical input stage (c) Non-tailed fully differential input stage. 2.1.4. Floating Gate Transistors. Floating Gate (FG) transistors were first proposed in [19] for the design of a low voltage differential input pair. The operation of FG transistors consist on a 1 Vds_sat is the Vds saturation voltage. M1M2 M3M4 MX vi+ vi- VDD VSS Vbias VSS vo2 M1M2 M3M4 vi+ vi- VDD VSS VSS vo2 R R vb M1M2 M3M4 vi+ vi- VDD VSS VSS vo2 vo1 vo1 vo1 VbVb 8 Performance enhancement in the design of amplifier and amplifier-less weighted capacitive coupling at the gate of a conventional MOS transistor as shown in Figure 2. Figure 2: Floating Gate transistor. Capacitor values are usually chosen to ensure that C2>>C1 and, given that   =       +   +       +   (2–2) the transistor can be properly biased through C2 and Vbias while v1 drives the signal, that is attenuated at the gate of the transistor, ensuring a wide input range [19], [20]. The main disadvantage of this technique is the reduction of the input stage transconductance and, thus, the total gain and bandwidth. Moreover, C2 implementation may increase the consumed area. In deeply scaled technologies, the gate leakage current increases, jeopardizing the FG transistor behaviour. 2.1.5. Quasi-Floating Gate Transistors. Similarly to FG transistors, in Quasi-Floating Gate (QFG) transistors [21], the input signal in capacitively coupled to a conventional MOS transistor, but instead of biasing the gate by a large capacitor, it is weakly connected to Vbias through a large resistor, Rlarge, as shown in Figure 3. Figure 3: Quasi-Floating Gate transistor. The gate voltage, vG can be calculated as,   =   1 1 +      +        1 +      (2–3) Thus, for s=0 the gate is biased to the Vbias voltage, while the input signal v1 will v1 C1 C2 Vbias MOS FGMOS vG v1 C1 Rlarge Vbias MOS QFGMOS vG Low-Voltage Operational Transconductance Amplifiers 9 be high pass filtered. However, as Rlarge should be large enough, the cut off frequency of the filter should be placed at frequencies lower than the minimum operating frequency of the circuit. QFG transistors does not suffer from the transconductance reduction that affects FG transistors and, in practice, Rlarge can be implemented using transistors in cut off region (pseudoresistors) reducing the FG area consumption. However, experimental results show that they suffer slow large signal dynamics when the circuit is turned on. Those dynamics are not usually well modelled in computer aided design (CAD) software, so special attention must be paid when performing simulations [22]. In modern technologies passive resistors with relatively large values are feasible to integrate, so that, if the operating frequency is high enough, there is no need to use pseudoresistors. 2.1.6. Complementary Input Pair. With the aim of increasing the input voltage swing in headroom-limited designs, two complementary pairs can be used as OTA input stage [23]–[26] as shown in Figure 4 [23]. Figure 4: Complementary input pair. The main idea is to have at least one pair operating over the complete input voltage range. Hence, when the input is too high for the p-type pair, the n-type is going to be active, and vice versa. Despite complementary pairs indeed achieve rail-to-rail behaviour, the transconductance, as well as the slew rate, suffer important variations across the input signal swing, as the circuit passes through three different “states”: only ptype pair active, both pairs active, only n-type pair active. 2.1.7. Level Shifting. Similarly as in the complementary input pair, using two input pairs of the same, p or n type plus level shifters, can ensure rail-to-rail operation [27]. The idea is, again, turning on one of the pairs when the other turns off. vi+ vi- VDD VSS VSS VDD VDD VSS 10 Performance enhancement in the design of amplifier and amplifier-less Figure 5: Double input pair with level shifters. Level shifting presents the same disadvantages of transconductance and slew rate input dependence. It needs additional techniques to stabilize those parameters and additional circuitry to implement the level shifters. 2.1.8. Bulk Driven. Bulk driven circuits use the bulk transconductance, gmb, instead of the gate transconductance, gm. The main advantage of driving the input though the bulk is that it has no threshold voltage associated and, as a result, the Vth limitation is avoided, making it specially suitable for low voltage designs. Figure 6 (a) shows the regular gate driven transistor where the input is applied though the gate terminal and the bulk terminal is set to a constant bias voltage. In Figure 6 (b) a bulk driven transistor is depicted, where the input is applied through the bulk and the gate terminal is connected to a bias voltage that properly bias the transistor. (a) (b) Figure 6: (a) Gate driven and (b) bulk driven PMOS transistors. As this technique requires the bulk terminal to be accessible, in standard n-well technologies, only p-channel transistors can be bulk driven. The main disadvantage is the fact that gmb is significantly smaller than gm and, in amplifier design, this leads to poor DC gain and gain-bandwidth performances with larger noise and offset. Specifically, if strong inversion is assumed, then the drain current is given by = (−||). If the threshold voltage is substituted by =+ |2−|−|2|, then [28], vi+ vi- VSS VSS VS VS viVbias vi Vbias Low-Voltage Operational Transconductance Amplifiers 11   ≡       = |  | 2  2 |   | +    2    = |  | 2  2 |   | +     =    (2–4) Depending on the technology 0.1 < η < 0.4. The rest of the parameters have their usual meanings, being γ the body effect parameter,  the Fermi potential and =′  . State of Art of Sub-1V Operational Transconductance Amplifiers. In this section, the State of Art of Sub-1V OTAs is presented. First, previous works found on literature are briefly discussed and summarized, to finish with a comparison of their performances. In order to discuss the different approaches found on literature, a chronological order is going to be followed here. In 2001 Lehmann et al. [5], propose a gate-driven folded cascade OTA implemented by a current driven bulk technique. In this proposal, the threshold voltage of the input pair is lowered by driving the bulk with a current instead of a voltage avoiding the possibility of forward biasing the bulk-source diode by maintaining the bulk current controlled under a certain value. Results demonstrate that the solution is able to work under 1 V supply in a 3.3 V technology with proper small signal performances but with poor SR. In [29], Stockstad et al. propose a weak inversion OTA whose input pair is bulkdriven, but the input is applied through depletion-mode transistors used as buffers to minimize bulk currents. They achieve 70 dB gain and rail-to-rail behaviour at the input and the output under a 0.9 V supply in a 2.5 µm technology, with a reduced power consumption. However, the unity gain bandwidth is only 5.6 kHz. Yao et al. propose, in [30], a single-stage gate-driven fully differential OTA, based on a current mirror amplifier with gain enhancement. Although it has very good small signal behaviour with a low power consumption, its slew rate is poor. In [6] Chatterjee et al. propose two 0.5 V fully-differential OTA, both biased in moderate inversion. The first approach is bulk-driven while the second one is driven by the gate and implements threshold lowering through the bulk of n-type transistors, thus requiring triple-well devices. The proposed OTAs achieve good performances, but extremely limited input common-mode range. In [31] Ferreira et al. propose an improved version of the traditional two-stage Miller OTA, operating at weak inversion and combining bulk-driven input and level-shifters to provide rail-to-rail operation. It effectively achieves low voltage (0.6 V in a technology of 2.5 V) and low power, but speed and slew rate are not particularly good. 12 Performance enhancement in the design of amplifier and amplifier-less In [32], Zuo et al. propose a two-stage bulk-driven folded-cascode OTA with transconductance enhancement able to operate under 1 V in a technology whose nominal supply voltage is 3.3 V. Although it achieves good small signal performances, the large signal behaviour is rather poor Ferreira et al. presents, in [33], a two-stage bulk-driven folded-cascode OTA in weak inversion, able to operate under 0.25 V and very low-power consumption. It achieves very good performances, considering the extremely low supply and power consumption, by enhancing the transconductance and, also, the output resistance of transistors at the expense of area consumption. In [16], a three-stage bulk-driven OTA with non-tailed input pair operating in subthreshold is presented by Abdelfattah et al.. The OTA is able to operate even under 0.35 V in a technology with a nominal supply voltage of 1.2 V. They show good measured performances but under a quite small loading capacitance. Tang et al. propose in [34] a rail-to-rail bulk-driven two-stage OTA that operates under 0.9 V in a technology with a nominal supply of 1.8 V. It also implements a transconductance stabilization technique. Although it achieves good speed and slew rate, it consumes too much current. Finally, in [7] Grasso et al. propose a gate-driven two-stage non-tailed OTA with threshold lowering that operates under 0.9 V in a 3.3 V technology, achieving a good common-mode range but limited slew rate. Table 1 summarizes the main performance of the works that have been discussed here. Year, Ref. Tech [μm] Supply [V] DC Current [μA] CL [pF] DC Gain [dB] UGBW [MHz] PM [°] Average SR [V/µs] CMRR [dB] FoMS [MHz·pF /mW] FoML [V·pF/ (µs·mW)] 2001 [5] 0.5 1 40 20 69 2 57 0.5 - 1000 250 2002 [29] 2.5 0.9 0.5 12 70 0.0056 62 - 26 149 - 2003 [30] 0.25 0.8 10 18 50 1.2 60 0.2 - 2700 450 2005 [6] 0.18 0.5 220 20 52 2.5 - 2.89 78 455 525 0.18 0.5 150 20 62 10 - 2.0 74 2666 533 2007 [31] 0.35 0.6 0.916 15 69 0.011 65 0.014 74 300 382 2013 [32] 0.35 1 197 15 88 11.67 66 1.95 40 889 148 2014 [33] 0.13 0.25 0.072 15 60 0.002 52 0.0007 - 1667 583 2015 [16] 0.065 0.5 366 3 46 38 57 43 35 623 705 0.065 0.35 49 3 43 3.6 56 5.6 46 630 980 2015 [34] 0.18 0.9 290 17 76 7.11 72 2.98 55 463 194 2017 [7] 0.35 0.9 27 10 65 1 60 0.25 45 411 102 Table 1: Performance comparison of Sub-1V OTAs. Low-Voltage Operational Transconductance Amplifiers 13 The two traditional Figures of Merit (FoM) [35]–[37] shown in equation (2-5) have been evaluated and included in Table 1.   =  ·       =  ·    (2–5) FoMS and FoML allow a comparison of small signal and large signal performance, respectively. In both cases higher values mean better performances: in FOMS (where subscript S stands for “small signal”) higher unity-gain bandwidth, UGBW, and load capacitance, CL, at low power consumption is preferred, whereas in FOML (where subscript L stands for “large signal”) higher slew rate, SR, higher, CL and low power consumption is preferred. Figure 7 graphically shows the FoMs of each publication discussed above. It can be observed that the amplifiers with better FoML [16] present poor FoMS and viceversa [6], [30]. Figure 7: FOMS and FOML Vs Year of Publication of Sub-1V OTAs. 14 Performance enhancement in the design of amplifier and amplifier-less Contributions. Taking advantage of more than one of the described low-voltage techniques is a common strategy [6], [7], [16], [24], [29], [31], [33], [38], [39]. For the OTAs proposed in this thesis, with the aim of achieving good small and large signal performances, a bulk-driven version of the non-tailed differential input pair of Figure 1 (c) is used as the first stage of all the three contributions, what allows extremely reduced biasing voltage and, as the quiescent current through the input pair is fixed by the gates while the input is driven through the bulk, no additional bias current control is required. This input stage is interesting, as it can implement either single-ended or fully-differential solutions as it is. As a proof of concept, three single-ended OTA are proposed. In order to provide adequate DC gain, the first two proposed OTAs adopt three-stage architectures [13], [16] while the last one is a four-stage [40]. Class-AB outputs are chosen to enhance the large signal performances, and, additionally, for the last two contributions, the classical Class-AB output is improved taking once again advantage of the bulk terminal. The three proposed OTAs were fabricated in a standard 180 nm CMOS technology in order to validate their performances. 2.3.1. Non-Tailed Bulk-Driven Differential Input Stage. The Non-Tailed Bulk-Driven Differential pair, used as the input stage for the three proposed OTAs, is the bulk-driven version of the input stage proposed on [8] and it is depicted in Figure 8. It is composed by transistors M1 and M2, whose quiescent currents are accurately set by transistor MR, whose body is tied to the virtual ground (i.e., (VDD+VSS)/2). Hence, MR-M1 and MR-M2 form two accurate current mirrors, provided that also the bulk of M1-M2 is connected to the analog ground. The active load of the first stage is implemented by transistors M3-M4 and two resistors, R. Due to the fact that no DC current flows through resistors, the drains and gates of M3-M4 are at the same potential. This stage is specially suitable for low voltage design, as the minimum supply voltage (VDD-VSS) can be as low as VDS1,2 + VGS3,4. Moreover, resistors R accurately set the output DC common-mode voltage, what would not happen in the bulk-driven version of the classical nontailed pair of Figure 1 (b). The transistors and biasing values used for the three implementations are summarized in Table 2. Low-Voltage Operational Transconductance Amplifiers 21 Due to the advantages of the proposed bulk-driven non-tailed input stage in terms of CMRR, DC common mode output and large signal behavior when compared to the classical non-tailed stage, it has been chosen as the input stage for the three OTAs proposed in this thesis. This input stage is particularly advantageous for the implementation of fully-differential solutions, anyway, single-ended OTAs has been implemented in this thesis as a proof of concept for the validation and test of its performances. Fully differential implementation is straightforward and part of the future work. 2.3.2. Low-Voltage Bulk-Driven Three-Stage Class-AB OTA. Using the proposed input stage of Figure 8, together with Class-AB stages the complete OTA of Figure 14 is proposed with the aim of achieving both good large and small signal performances under low voltage supply. It is made up of three gain stages: the already explained differential input stage (M1-M4), a second common-source stage (M5-M6) and a third common-source stage (M7-M10). The implemented transistors dimensions and device values for this design are summarized in Table 3. Figure 14: Three-stage Class-AB OTA. vin+ vin- MR IB M1M2 M3M4M5 M6 M7 M8 M9 M10 CC2 CC1 R R vout CL VDD VSS VSS 22 Performance enhancement in the design of amplifier and amplifier-less Device Value Device Value MR, M1, M2, M10 12µm/540nm IB 4 µA M3, M4, M9 2µm/540nm CC1 550 fF M5, M7 5µm/540nm CC2 30 fF M6, M8 30µm/540nm R 250 kΩ CL 20 pF VDD-VSS 0.7 V Table 3: Transistors dimensions and device values of the Three-Stage Class-AB OTA. Transistor MR, whose bulk is tied to the virtual ground, as explained in the above section, sets the quiescent current of the differential pair (M1-M2) and load (M3-M4) of the first stage. At the same time, MR also sets the quiescent current of transistor M6 that acts as the load of the second stage. Due to the fact that no DC current flows through resistors R, the drains of M3-M4 are at the same potential of their gates and, consequently, the DC current of M5 is also accurately set by (pseudo) current-mirror ratios of M4 and M5 = 󰇡   󰇢  󰇡   󰇢  (2–19) The matching between the DC currents of M5 and M6, causes the drain of M5 to be theoretically at the same potential of the drain of M4, ultimately defining the current of M7, again through a mirror ratio = 󰇡   󰇢  󰇡   󰇢  (2–20) Note that current ID8 is set through current mirror M8-M10 and pseudo current mirror M9-M4. Therefore, to theoretically nullify systematic offset, ID8 must be equal to ID7 leading to 󰇡   󰇢  󰇡   󰇢  󰇡   󰇢  󰇡   󰇢  = 󰇡   󰇢  󰇡   󰇢  (2–21) A final comment regards the Class-AB behaviour of the third stage. Both transistors M7 and M8 can deliver a maximum signal current that is not limited by any DC value. Indeed, M7 is in common source configuration, whereas the current in M8 increases when Vin+ increases because vGS9 also increases. Low-Voltage Operational Transconductance Amplifiers 23 2.3.2.1. Frequency compensation. Frequency compensation of the differential (open loop) gain is obtained through Miller capacitors CC1 and CC2 and a current buffer [42] implemented by M3-M4, with a similar technique to that developed in [37] for a nested-Miller- compensated OTA. The simplified small signal model of the OTA of Figure 14 is depicted in Figure 15, where the parasitic capacitances have been neglected for simplicity and Roi represents the resistance of the output node of the ith stage. Values of transconductances and resistances for the proposed OTA are provided in Table 4: . Figure 15: Small signal model of the Three-stage Class-AB OTA. Transconductance Value [µA/V] Transconductance Value [µA/V] Output resistance Value [kΩ] gmb1,2 12 gm7 150 Ro1=rds1//rds3 1535 gm1,2 65 gm8 150 Ro2=rds5//rds6 214 gm3,4 65 gm9 60 Ro3=rds7//rds8 224 gm5 162 gm10 60 Rox=rds1//(1/gm10) 16 gmb6 30 Table 4: Transconductances and output resistance values of the Three-Stage Class-AB OTA. Solving the simplified small signal model circuit leads to the following open loop gain transfer function: gmb1,2vin/2 gm3,4vx R R Ro1 -gmb1,2vin/2 Ro1 CC2 vin vx gm3,4vx Ro2 gm5vo1 Rox gm9vo1 vo1' vo1 vo2 CC1 gm7vo2 Ro3 gm8vx2 vout CL vx2 24 Performance enhancement in the design of amplifier and amplifier-less  (  ) ≈   󰇡 1 +    󰇢 󰇡 1 +    󰇢 (    +  + 1 ) (2–22) Assuming gmiRoi, gmiR >>1, simple equations can be provided for the DC gain, A0, zero, z1, and dominant pole, p1, as well as for the coefficients of the polynomial of the complex conjugate poles, a, b.   =                    2 (  +   ) = − =2(+)  =(+2)   =   (   +       )             (2–23) The damping coefficient of the pair of complex poles is given by  =  2 √  =   +       2                     ( 2    +    ) (2–24) Given gmb1,2, CL and CC1, one can derive from (2-24) a suitable value of CC2 in order to avoid peaking in the frequency response and to obtain a phase margin in the range of 60 to 70 degrees. Besides, gm5/gm3>CC2/CC1 can be chosen in order to obtain a negative zero from (2-23) useful to increase the phase margin. From (2-23) the gain-bandwidth product, ωGBW, is given by   =    ,     (2–25) Substituting the values given in Table 4 on the above equations, the calculated transfer function can be plotted. In Figure 16 the calculated Bode is depicted altogether with the postlayout simulated Bode diagram. It can be seen that at low frequencies the equations provide a good approximation. In the vicinity of the unity gain frequency, the effect of parasitics makes the simulated and the calculated Bode differ. However, the proposed simplified model provides manageable equations and reasonably Low-Voltage Operational Transconductance Amplifiers 25 good modelling. Further details regarding these discrepancies are provided on Appendix A. Figure 16: Calculated and simulated frequency response of the Three-Stage Class- AB OTA. 2.3.2.2. Slew Rate. The slew rate (SR) of an OTA is the maximum output voltage rate. It occurs when the maximum current flowing into a capacitor is limited [4]. Hence, in multistage amplifiers the SR is going to be determined by the slowest stage, i.e., SR=min[Ix/Cx], where Ix is the maximum charging of discharging current of the load capacitor of the x-th stage, Cx. For the proposed OTA implementation, the slowest stage is the last one as the loading capacitor CL is the largest. The negative SR is determined by common source transistor M7, whose maximum instantaneous current is in principle larger than the maximum current that the load transistor, M8, can provide. This makes the positive slew rate smaller that the negative one. This fact is partially alleviated making the output stage Class-AB, as explained before, using the current mirror formed by transistors M8 and M10, however, still with this Class-AB operation the maximum current that M8 can provide to the load capacitor, CL is still smaller than the one that M7 provides, so that the unbalanced positive and negative SR persists. Simulations show positive SR of 2.16 V/µs and negative SR of 4.42 V/µs for nominal corner. 26 Performance enhancement in the design of amplifier and amplifier-less 2.3.2.3. Power Supply Rejection Ratio. The Power Supply Rejection Ratio (PSRR) defines the capability of a circuit to reject the variations of the power supply. It is defined as [4]  = ∆   ∆    (  ) (2–26) A common strategy to determinate the PSRR is using the voltaje-follower configuration, where the output is fedback to the negative input of the OTA and the positive input is set to the analog ground. PSRR+ and PSRR- can be then calculated as PSRR+ = Vdd / Vout and PSRR- = Vss / Vout [4]. Figure 17 shows the low-frequency small signal model used for calculating the positive PSRR at DC, where rdsi = 1/gdsi is the drain-source resistance of transistor i. Figure 17: Small signal model for the calculation of PSRR+ at low frequencies for the Three-Stage Class-AB bulk-driven OTA. Solving the circuit, the numerator and denominator of PSRR+ are given by    =    ,                  =2[(++R +R)(+− −   (   +   )   ) +    (  +    ) (    +    ) (          +         ) ] (2–27) For the calculation of the PSRR-, the low-frequency small signal model of Figure 18 was solved, giving a negative PSRR numerator and denominator that can be approximated by    =    ,                  =2[(++R +R)(+ −     (   +   ) −   (   +   )   ) +    (  +    ) (    +    ) (          +         ) ] (2–28) gm3,4vx R R rds3 vdd vx vo1'vo1 gm3,4vx rds3 -gmb1,2vdd rds1 gmb1,2(vo3-vdd) rds1 vo2 gm5vo1 rds5 -gmb6vdd rds6 vx2 gm9vo1 rds9 1/gm10 vo3 gm7vo2 rds7 rds8 gm8(vx2-vdd) Low-Voltage Operational Transconductance Amplifiers 27 Figure 18: Small signal model for the calculation of PSRR- at low frequencies for the Three-Stage Class-AB bulk-driven OTA. Substituting the transconductance and resistance values of Table 4 on the provided equations, a positive and negative PSRR of 60 dB and 71 dB are obtained, while in simulations 62 dB and 72 dB, respectively, are obtained, validating the equations. 2.3.2.4. Implementation and validation. As it has been mentioned before, the proposed OTA has been designed and implemented in a standard 180 nm CMOS technology with threshold voltages around Vthp = 0.35 V and Vthn = 0.45 V. The design operates under a 0.7 V single supply. Transistors’ aspect ratios and transconductances, as well as the rest of the design parameters and values were summarized in the tables of Table 3 and Table 4. Resistors are physically implemented with 1792 /□ high-resistive poly. Each resistor occupies 13.47 µm  1.67 µm. Figure 19 shows a microphotograph of the chip the designed layout, which occupies a total area of 0.019 mm2. Figure 19: Microphotograph of the chip and layout of the Three-stage Class-AB OTA. gm3,4(vx-vss) R R rds3 vx vo1'vo1 rds3 gm3,4(vx-vss) rds1 rds1 gmb1,2vo3 vo2 rds5 gm5(vo1-vss) rds6 vx2 rds9 gm9(vo1-vss)1/gm10 vo3 rds7 gm7(vo2-vss) rds8 gm8vx2 vss 28 Performance enhancement in the design of amplifier and amplifier-less The proposed OTAs were designed for a certain technology option (Option 1) but due to foundry imposition they were finally fabricated in a different option (Option 2). That issue has negatively impacted on the measured performances. Specifically, it has been observed that Option 2 has smaller transconductances, bigger output resistances and higher bulk and gate-related parasitics. To note that the simulation results provided throughout all this chapter correspond to the technology option Option 1 for which the OTAs were designed. Appendix B provides more details regarding the technology options. In order to check the robustness of the standby current control in the last stage of the proposed structure, a MonteCarlo simulation is performed (process and mismatch, 1000 iterations). The associated histogram is plotted in Figure 20. Figure 20: Histogram of the standby current of the third stage of the Three-stage Class-AB OTA. From this analysis, a mean quiescent current of 8.9 µA is obtained (aspect ratios designed for 10 µA). The standard deviation is only 0.7 µA. Input Common Mode Range. As stated before, the maximum ICMR is actually limited by the maximum allowable input current, that was set to 1000 times the drain current of the input pair (4 nA) so that it can be neglected, resulting in a simulated ICMR of 550 mVpp (from 150 mV to 700 mV). The input current has been measured at 20°C, obtaining the results shown in Figure 21. Low-Voltage Operational Transconductance Amplifiers 29 Figure 21: Measured input current versus bulk-source voltage @ 20°C of the Threestage Class-AB OTA. It can be observed from the results that the actual measured input current for |VBS|=550 mV is lower than the estimation of the simulator; actually, 1.24 nA. This was expectable not only because the design was fabricated in another technology option but also because the current of a forward-biased pn junction is usually overestimated in simulators [28]. Regarding the dependence with temperature of the input current, it is going to be presumably strong, as, again, it corresponds with the temperature dependence of the current through a pn junction that approximately doubles each 10°C [4]. Thus, according to the measurements it can be inferred that if the ICMR is limited to 550 mV, then the input current will remain below 100 nA up to 80°C. A final comment regarding the input current stands for the possibility of latch up to occur if |VBS| > 0.6 V. With the ICMR limitation, the maximum |VBS| is limited to |VBS|max = 550 mV so the bulk-source diode should not enter conduction, hence latch up should not occur. Despite this, usual layout precautions (double guard rings) have been also taken. Indeed, during experimental verification latch up has not happened, even if the ICMR was forced to a higher value (~0.7 V). Frequency response. The nominal postlayout simulated frequency response Bode plot is represented in Figure 22. Additionally, Figure 23 shows the results of MonteCarlo analysis (process and mismatch, 1000 iterations) for the DC gain, unity gain bandwidth (UGBW) and phase margin (PM). 30 Performance enhancement in the design of amplifier and amplifier-less Figure 22: Nominal simulated frequency response of the Three-Stage Class-AB OTA. (a) (b) (c) Figure 23: MonteCarlo results for (a) DC gain, UGBW (b) and (c) phase margin of the Three-Stage Class-AB OTA. These results show the robustness of the solution. A mean DC gain of 61 dB, with standard deviation (σ) of 0.7 dB is obtained. The mean UGBW is equal to 3.5 MHz, with a deviation of 0.2 MHz, while the phase margin mean value results to be 59°, with a standard deviation of 2.2°. That means, considering the 3-σ rule4, that even in the worst case the phase margin is above 45° (actually, 52°) so the system should remain stable. These three parameters were also experimentally tested: Figure 24 shows a measurement of the UGBW and phase margin, carried out using a vector network analyzer (Rohde&Schwarz ZVRL). A UGBW of 3 MHz and a phase margin of 60° were measured. 4 3-σ rule states that 99.7% of the outcomes lie within three standard deviations of the mean. Low-Voltage Operational Transconductance Amplifiers 37 foundry imposition, they were finally fabricated in a different technology option (details provided in Appendix B) with smaller transistor gm, higher transistor ro and, higher parasitics. Due to the robustness of the design and compensation, this has barely affected the performances of the Three-Stages OTAs Table 16 shows a comparison of the performances of the proposed OTAs altogether with the Sub-1V amplifiers found in the State-Of-Art that were commented in section 2.2. In order to carry out a quantitative comparison, the two traditional Figures of Merit (FoMS and FoML) are evaluated and, for convenience, shown again in equation (2-55).   =  ·       =  ·    (2–30) Figure 33 and Figure 34 show the comparison in a graphical way. It is apparent that the proposed amplifiers outperform almost all other previously reported bulk-driven OTAs. In particular, as far as parameter FoML is concerned, the proposed OTAs display the maximum values by far. Regarding the FoMS parameter, Contribution 3 performs the best result, followed by [30] and [6] and then Contributions 1 and 2. Figure 33: FOMS and FOML Vs Year of Publication of Sub-1V OTAs. In Figure 34 FOMS and FOML are depicted together for further comparison. 38 Performance enhancement in the design of amplifier and amplifier-less As the proposed OTAs are the only ones placed in the upper-right quadrant it is apparent that their overall performance outstand the other solutions proposed in literature. However, they perform the worst CMRR among all the other solutions found in the comparison, thus, an effort to overcome this issue should be accomplished in future research. Figure 34: FOMS Vs FOML of Sub-1V OTAs. The achieved performances have been possible thanks to the combination of all the discussed techniques. Summarizing, the bulk-driven input, applied in a non-tailed differential pair, allows a very low-voltage supply while maintaining a wide input common-mode range. Gain is provided by multiple stages, and quiescent currents properly set structurally. Large signal performances are achieved through Class-AB stages, and, in the last two contributions, making use of the bulk to further enhance the Class-AB behavior. Nonetheless, the bulk-driven non-tailed structure means poor CMRR and PSRR and the noise worsening related to bulk-driven inputs. Low-Voltage Operational Transconductance Amplifiers 39 Year, Ref. Tech. [μm] Supply [V] DC Current [μ A] CL [pF] DC Gain [dB] UGBW [MHz] PM [°] Average SR [V/µs] CMRR [dB] PSRR [dB] Noise [nV/√Hz] FoM S [MHz·pF /mW] FoM L [V·pF/ (µs·mW)] 2001 [5] 0.5 1 40 20 69 2 57 0.5 - - - 1000 250 2002 [29] 2.5 0.9 0.5 12 70 0.0056 62 - 26 - - 149 - 2003 [30] 0.25 0.8 10 18 50 1.2 60 0.2 - - - 2700 450 2005 [6] 0.18 0.5 220 20 52 2.5 - 2.89 78 76 80 @ 1MHz 455 525 0.18 0.5 150 20 62 10 - 2.0 74 81 70 @ 1 MHz 2666 533 2007 [31] 0.35 0.6 0.916 15 69 0.011 65 0.014 74 53 290 @1kHz 300 382 2013 [32] 0.35 1 197 15 88 11.67 66 1.95 40 40/46 60@ 1MHz 889 148 2014 [33] 0.13 0.25 0.072 15 40 0.002 52 0.0007 - - 3300 @- 1667 583 2015 [16] 0.065 0.5 366 3 46 38 57 43 35 37 - 623 705 0.065 0.35 49 3 43 3.6 56 5.6 46 35 - 630 980 2015 [34] 0.18 0.9 290 17 76 7.11 72 2.98 55 48 800 @ 10 kHz 463 194 2017 [7] 0.35 0.9 27 10 65 1 60 0.25 45 55 65 @ 100KHz 411 102 Cont r. 1 0.18 0.7 36.3 20 57.5 3 60 2.8 19 45/57 100 @ 1MHz 2361 2204 Contr . 2 0.18 0.7 76.2 33 57.7 2.6 50 4.6 14 43/47 100 @ 1MHz 1674 3155 Contr . 3 0.18 0.7 50.16 33 91 2.9 11 2.6 13 35/44 100 @ 1MHz 3155 2443 Table 7: Performance comparison of Sub-1V OTAs. 40 Performance enhancement in the design of amplifier and amplifier-less 41 3. AMPLIFIER-LESS SWITCHED CAPACITOR CIRCUITS witched Capacitor (SC) Circuits are one of the most commonly used type of circuits. Their versatility and suitability for being integrated have made them widely used since the early days of integrated electronics [46]. They are based on a charge transfer carried out by a charge conveyor (CC), switches and capacitors. In traditional SC design, the CC is implemented by an OpAmp, but, as stated before, achieving proper performances in OpAmp design has become more challenging with the technological downscaling. Thus, recently, researchers try to substitute the OpAmp by other CC that do not suffer the OpAmp limitations: the so called amplifier-less techniques. In this chapter the second line of this thesis is explored: a new differential structure for switched capacitor circuits, specially suitable for reducing low frequency noise and distortion and, thus, enhancing the dynamic range (DR) is presented. S 42 Performance enhancement in the design of amplifier and amplifier-less Amplifier-less techniques. 3.1.1. Charge-Coupled devices. One amplifier-less alternative for SC circuits is the use of charge-coupled devices (CCD) in standard CMOS technologies [47]. They were proposed by Boyle and Smith in 1970 [48] and are mainly used in imaging applications. CCD are metal-oxide-semiconductor (MOS) structures, similar to MOS transistors, in which adjacent gates are close enough to allow channel overlapping. In Figure 35 the transversal view of a CCD structure is shown. Figure 35: Transversal view of a CCD structure. In consists of three different sections: input, transfer and output.  Input section. It consist on a diffusion, and the input gate. The diffusion provides minority carriers and its potential can be controlled. The input gate potential can be turned on or off in order to allow the carriers pass from the diffusion to the input gate potential well.  Transfer section. It consists on some control gates whose potential is controlled to allow the charge to pass through the structure.  Output section. Consists on a reverse-biased junction capacitance. Its voltage changes depending on the amount on charge that receives. A switch resets the diode voltage after each charge transference. Figure 36 depicts an example of how a charge transfer is carried out. n+n+ Input Gate ctrl1 ctrl2 ctrl3 Output Gate Output Diode Input Source Input Section Transfer Section Ouput Section Amplifier-less Switched Capacitor Circuits 43 Figure 36: Charge transfer example. CCD are used in SC circuits as they are based on charge transfer and its efficiency can be really high [47]. The main advantage of CCD structures is that they are not affected by thermal noise, charge injection or coupling from the substrate or clock but they need special process to be implemented and, usually, a high supply voltage is required for the clock signals. 3.1.2. Dynamic Amplifiers. Another OpAmp-less technique for SC circuits substitutes the OpAmp by a group of switches that act as a dynamic amplifier [39], [49]. In charge transfer circuits, where the operation is based on a virtual ground condition, the implementation of dynamic amplifiers is straight-forward. Figure 37: Classic OpAmp-based SC integrator. In Figure 37 the classical OpAmp-based SC integrator is depicted. It is well know that the high gain and virtual ground condition of node vx is only needed during the charge transfer phase to fully complete the charge transfer from C1 to C2. Thus, the OpAmp can be substituted by a dynamic amplifier as shown in Figure 38. “0”“0”“0” “1”“0”“0” “1”“1”“0” “0”“1”“0” “0”“1”“1” “0”“0”“1” - + C2 C1 vivo vx 1 2 =Switch Controlled By ΦX X 44 Performance enhancement in the design of amplifier and amplifier-less Figure 38: SC integrator with dynamic amplifier implementation. This structure recreates the virtual ground condition on node vx by the feedback provided by C2 as follows: during the sampling phase, Φ1, the capacitor C1 receives the charge from the input, then, at the beginning of the charge transfer phase, Φ2, the switch controlled by Φ2P closes. This precharges the output node, vo to the positive bias voltage, and, consequently, sets node vx to a voltage higher than the M1 threshold voltage, Vth. After this preset phase, the switch opens and the switch controlled by Φ2P2 closes, beginning the amplification phase: node vo starts to discharge from the positive bias and, due to the capacitive coupling, the voltage at node vx also starts to diminish. When vx is under Vth, transistor M1 is turned off and the virtual ground condition is achieved. Even though dynamic amplifiers considerably reduce the power consumption that a OpAmp may require, there is still an analog feedback and, in fact, the output will never settle completely [50]. 3.1.3. Parametric Amplifier. In a parametric amplifier, the amplification is achieved though the variation of one circuit parameter or element [51]. For instance, in a capacitor, the voltage drop between its terminals is given by Vout=Q/C where Q is the stored charge and C its capacitance. If it is charged to a certain value Vin and then the capacitance C is lowered, the voltage drop, Vout, increases achieving the amplification as shown in Figure 39. Figure 39: Parametric amplification. A varactor can be used instead of a traditional capacitor in order to electrically control the capacitance value and apply the amplification to sampled systems such as SC [51]. Φ1 Φ2 Φ2P2 Φ2P C2 C1 vi vo vx 1 2 2P2 VDD 2P Dynamic Amplifier + - viQ=CV Q=CV vo=vi vo vi C Amplifier-less Switched Capacitor Circuits 45 3.1.4. Inverter-Based Switched Capacitors Circuits. In SC circuits the OpAmp can also be replaced by a logic inverter [52]. Figure 40 shows the implementation of an inverter-based single-ended integrator. Figure 40: Inverter-Based SC integrator. Its main advantage is that it can work under very low supply voltages. However, as the inverter only has one input terminal it is not able to provide an inherent virtual ground, instead, the node vx is kept close to the offset voltage of the inverter. As this offset is unknown and sensitive to any process, size, supply variation, offset cancellation techniques must be implemented. Figure 41 shows an integrator with offset cancellation [52]. Figure 41: Inverter-Based SC integrator with offset cancellation. 3.1.5. Comparator-Based Switched Capacitor Circuits. In Comparator-Based SC (CBSC) circuits [53] the OpAmp is replaced by a comparator and a current source, as depicted in Figure 42 (a). As the comparator operates in open loop configuration, the requirements of gain and power consumption are substantially relaxed, but speed and accuracy are strongly related to the comparator and current source implementation. The contribution of this chapter is based on the CBSC technique so it is explained in detail in next section. C2 C1 vivx 1 2 vo C1 vi1 12 Cc C2 vx vo 1 2 46 Performance enhancement in the design of amplifier and amplifier-less Comparator-Based Switched Capacitors A CBSC integrator is depicted again for reference in Figure 42 (a), as mentioned before, this technique substitutes the amplifier by a comparator and a current source. The main idea of this technique is that, for properly transfer the charge from C1 to C2, the CC needs to stablish a virtual ground condition on node vx. (a) (b) Figure 42: (a) CBSC integrator (a) structure (b) clock phases and operation. Hence, the comparator controls the activation of the current source, Ib1, responsible for the charge of the output node, vo. At the beginning of the charge transfer phase, Φ2, during a brief time, called preset phase, signal ΦP2, Figure 42 (b), is activated so that node vo is short-circuited to the negative bias voltage, VSS, ensuring that node vx always starts below VCM. At the end of ΦP2 the comparator activates the current source Ib1, which starts the charge of vo. As a consequence, as vx and vo are capacitively coupled in an integrator, vx increases until it equals VCM. At this moment the virtual ground condition is achieved so the charge transfer is completed and the comparator turns Ib1 off. Let us now consider a non-ideal integrator, where the comparator has some delay and the current source is not perfectly linear. Under these realistic conditions an error in the output appears: the overshoot error, which is explained in next section. 3.2.1. Overshoot Error. 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Grasso, “0.7-V bulk-driven three-stage class- AB OTA,” in 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 2015, pp. 1–4 4. E. Cabrera-Bernal, S. Pennisi, A. D. Grasso, A. Torralba, and R. G. Carvajal, “0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 63, no. 11, pp. 1807–1815, Nov. 2016. Fig. 1. Proposed bulk-driven three-stage class-AB amplifier. The differential stage is made up of the bulk-driven differential pair, M1-M2, biased by diode-connected transistor, MR, whose body is tied to the analog ground, i.e., (VDD+VSS)/2. In this way, MR-M1 and MR-M2 form two current mirrors that accurately set the DC current, provided that also the body of M1-M2 is connected to the analog ground. The active load of the first stage is realized with transistors M3-M4. The use of resistors R enables true differential mode operation from pair M1-M2 that is otherwise intrinsically pseudo differential. Indeed, the small-signal voltage at the drain of M4 (output of the first stage) depends on both Vin+ and Vin-. The first stage DC gain can be approximated by gmb·R. Resistors R set also the common-mode voltage at the drain of M3-M4 to be equal to their gate voltage. The DC current in the second stage is set through current generator M6, and thanks to the mirroring action between M4 and M5 (they have the same VGS), M5 can be dimensioned so as to minimize systematic offset (by setting equal nominal DC current in M5 and M6). The last stage is biased by current generator M8, whose current is set by the pseudo current mirror formed by M4 and M9. Note that this current is signal dependent and that increases when Vin+ increases. In other words, both M7 and M8 can deliver a large-signal current greater than the standby value, and therefore the third stage works in class AB. Frequency compensation is obtained through Miller capacitors CC1 and CC2 and a current buffer implemented by M3-M4, with a technique similar to that developed in [9] for a nested Miller compensated OTA. Dominant pole is hence achieved through CC1, and the unity-gain bandwidth (GBW) is equal to gmb1,2/CC1. Transistors aspect ratios, as well as the main circuit devices values are summarized in Table I. TABLE I. TRANSISTORS DIMENSIONS AND DEVICES VALUES. Device Value Device Value M1, M2 12μm/540nm IB 4μA M3, M4 2μm/540nm CC1 500fF M5, M6 5μm/540nm CC2 50fF M7, M8 30μm/540nm R 250kΩ M9 2μm/540nm CL 20pF M10 12μm/540nm VDD 0.7v MR 12μm/540nm IV. RESULTS In this section, the main simulation results of the proposed amplifier are shown. At the end of the section, a brief comparison of performances among this amplifier and other low voltage amplifiers is also carried out. Fig. 2 illustrates the frequency response of the proposed amplifier. The open loop gain is 61dB and the unity-gain bandwidth is 3.7 MHz. The phase margin resulted to be around 62º. The common mode rejection ratio, CMRR, and the power supply rejection ratio, PSRR, have also been simulated. Their DC values are 46.8dB for the CMRR and 61.2dB and 72.4dB for the positive and negative PSRR, respectively. The amplifier was connected in inverting unity gain configuration as shown in Fig. 3 (Ra=Rb=100 kΩ). The response to an input step of 600 mV is illustrated in Fig. 4. The positive (negative) slew rate was 2.2V/μs (4.9V/μs) besides, 1% settling time was 594 ns (positive step) and 379 ns (negative step), respectively. It is seen that an almost rail-to- rail output swing is achieved. The input common mode range (ICMR) is also in principle rail to rail but is, actually, set by the maximum allowed input current that flows into the bulk. Thus, it should be limited to 400mV in order to maintain the input current below 3nA. Fig. 2. Frequency respose of the proposed amplifier. Main performance parameters of the proposed OTA are summarized in Table II. A comparison with other sub-1V amplifiers is also presented in Table III where a figure of merit (FOM) is included in order to make the comparison easier. The FOM is defined in (2), where I is the standby current consumption and CL is the load capacitance [12]. Highperformance amplifiers are characterized by a larger FOM. (2) It is apparent from TABLE III. that the proposed solution exhibits the best FOM among the considered sub-1V amplifiers. The FOM value versus the year of publication for the amplifiers appearing in TABLE III. is also plotted in Fig. 5. Fig. 3. Amplifier in inverting closed loop configuration. Fig. 4. Step response of the proposed OTA in unty gain configuration. TABLE II. RESULTS SUMMARY. Parameter Value Supply voltage [V] 0.7 Power dissipation [uW] 22.4 ICMR [mV] 400 Max Input current [nA] 2.96 Open Loop Gain [dB] 61.07 Open Loop Unity Gain BW [MHz] 3.7 Phase Margin [º] 62 SR+/SR- [V/us] 2.2/4.9 1% Settling time (+/-) [ns] 594/379 CMRR@DC [dB] 46.8 PSRR+@DC [dB] 61.2 PSRR-@DC [dB] 72.4 Input Ref. Noise @1MHz [nV/√Hz] 273 THD @100kHz (250mV input) [%] 0.058 THD @250kHz (250mV input) [%] 0.460 V. CONCLUSIONS In this paper, a bulk-driven three-stage class-AB CMOS OTA, suitable for very low voltage supplies has been presented. Operation under 0.7 V was simulated using the models of a 180-nm standard CMOS technology and results compared with the state-of-the-art sub-1V amplifiers. The proposed solution exhibits the best FOM. Future work will be aimed to balance the positive and negative slew rate in order to reduce the settling time and drive even larger load capacitors. TABLE III. PERFORMANCE COMPARISON OF SUB-1V AMPLIFIERS. Works Technology [μm] CL [pF] UGBW [MHz] PM [º] SR+/- [V/us] Supply [V] Power [μW] FOM 1998 [3] 2 22 1.3 57 0.7/1.6 1 287 10 2001[4] 0.5 - 2 57 0.5 1 40 50 2002[5] 2.5 - 0.56 62 - 0.9 0.45 13.4 2005[6] Bulk Driven (BD) 0.18 20 2.5 - 2.89 0.5 110 22.7 2005[6] Gate Driven (GD) 0.18 20 10 - 2 0.5 75 133.4 2009[7] 0.35 2.5 0.54 52 - 0.9 9.9 12.3 2013[8] 0.35 15 11.67 66 2.53/1.37 1 197 88.9 2000[10] 1.2 15 1.9 61 0.8/1 1 410 13.7 2003[11] 0.25 18 1.2 60 0.2 0.8 8 218 This work 0.18 20 3.7 62 2.2/4.9 0.7 22.4 231.8 Fig. 5. FOM vs Year of Publication for the amplifiers appearing in the comparison of TABLE III. ACKNOWLEDGMENT This work was partially supported by the Spanish Ministry of Economy and Competitiveness under the project TEC2011- 28724-C03-01 and the Andalousian ―Consejería de Economía, Innovación y Ciencia‖ under the project TIC-6323. REFERENCES [1] Ramirez-Angulo, J., Choi, S.C. & Gonzalez-Altamirano, G. 1995, "Low-voltage circuits building blocks using multiple-input floating-gate transistors", IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 42, no. 11, pp. 971-974. [2] Rajput, S.S. & Jamuar, S.S. 2001, "Low voltage, low power, high performance current mirror for portable analogue and mixed mode applications", IEE Proceedings: Circuits, Devices and Systems, vol. 148, no. 5, pp. 273-278. [3] Blalock, B. J. , Allen, P. E., & Rincon-Mora, G. A., 1988, ―Designing 1- V Op Amps using standard digital CMOS technology‖ IEEE Trans. Circuits Syst. II Analog Digit. Signal Process., vol.45, no. 7, pp. 769- 780. [4] Lehmann, T. & Cassia, M., 2001, ―1-V power supply CMOS cascode amplifier‖ IEEE J. Solid-State Circuits, vol 36, no.7, pp. 1082-1086. [5] Stockstad, T. & Yoshizawa, H., 2002, ―A 0.9-V 0.5 μm rail-to-rail CMOS operational amplifier‖, IEEE J. Solid-State Circuits, vol. 37, no. 3, pp.286-292. [6] Chatter, S., Tsividis, Y. & Kinget, P., 2005, ―0.5-V analog circuit techniques and their application in OTA and filter design‖, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2373-2387 [7] Pan, S. W., Chuang, C. C.,Yang, C. H. & Lai, Y. S., 2009, ―A novel OTA with dual bulk-driven input stage‖, Proc. IEEE Int. Symp. Circuits Syst., pp. 21-24. [8] Zuo L. & Islam S.K. 2013, ―Low-Voltage Bulk-Driven Operational Amplifier With Improved [9] Grasso, A. D., Palumbo, G., Pennisi, S., 2007―Advances in Reversed Nested Miller Compensation‖ IEEE Transactions on Circuits and Systems—I, vol. 54, no. 7. [10] Duque-Carrillo, J. F., Ausin, J. L., Torelli, G. Valverde, J. M. & Dominguez, M. A. 2000, ―1-V rail-to-rail operational amplifiers in standard CMOS technology”, IEEE J. Solid-State Circuits, vol.35, no. 1, pp. 33-44. [11] Libin, Y., Steayert, M. & Sansen, W., 2003, ―A 0.8 V, 8 μm, CMOS OTA with 50-dB gain and 1.2-MHz GBW in 18-pF load‖, Proc. Eur. Solid-State Circuits Conf., pp.297-300 [12] Peng, X & Sansen, W., 2004 ―AC boosting compensation scheme for low-power multistage amplifiers‖. IEEE Journal of Solid-state Circuits; 39:2074–2077. 0.7-V Bulk-Driven Three-Stage Class-AB OTA E. Cabrera-Bernal Electronic Engineering Department University of Seville Seville, Spain [email protected] S. Pennisi, A. D. Grasso DIEEI University of Catania Catania, Italy [spennisi, agrasso]@dieei.unict.it Abstract—A high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution exploits a three-gain-stage topology and, as a distinctive behavior, provides an inherent class-AB performance with simple and robust standby current control. A 0.7-V supply OTA is designed using a 180-nm standard CMOS technology. Post layout simulations show a 61-dB open loop gain and a unity gain bandwidth of 3.6 MHz, under a capacitive load of 20 pF. Significant performance improvement when compared to prior art is achieved, so that the best figure of merit is found. Keywords—Bulk-driven; Low-Voltage; OTA; class-AB; CMOS I. INTRODUCTION The continuous downscaling of transistor size in CMOS technologies implies, unavoidably, the decrease of the supply voltage in order to ensure circuit reliability and lifespan. Moreover, electronic industry is continuously demanding for portable devices with increasingly operation time in order to satisfy modern lifestyle, where portable devices have become ubiquitous. However, while supply voltages decrease, threshold voltages (VT) do not decrease in the same proportion. This is a main concern in analog design, where transistors operating in saturation are usually preferred to achieve higher transconductances, lower noise and overall better performance. Consequently, in order to preserve circuit performances in low voltage conditions, new topologies and design techniques must be developed to deal with low power supply and large VT, while maintaining acceptable signal swing. Techniques such as floating gate transistors [1], level shifting [2] or employing special low VT devices are some examples of low voltage design approaches. Bulk-driven techniques have also been extensively exploited ([3]-[8]). In this approach, the bulk terminal of the MOS transistor is driven by the signal, while the transistor is properly biased from its gate terminal. Applying the signal through the bulk allows modifying the VT, thus modifying the current through the device and obtaining a bulk transconductance, gmb. The main drawback of this method is the low achievable transconductance that, especially in the design of amplifiers, implies low gain, low bandwidth and high noise. In this paper, a bulk-driven class-AB operational transconductance amplifier (OTA) in 0.18-Pm CMOS, which works under 0.7-V supply, is presented. The OTA provides more than 60-dB DC gain thanks to a three-stage architecture that is used to compensate for the transconductance reduction. The added stage, however, does not sacrifice the gainbandwidth product, which resulted larger than 3 MHz under a load capacitance of 20 pF, a value comparable with three-stage gate-driven OTAs under the same load and current consumption [9]. After a brief review of bulk driven technique in Section II, the proposed OTA topology is presented in Sec. III. The main post layout simulation results along with a comparison with other sub 1-V solutions are carried out in Sec. IV. Conclusions are drawn in Sec. V. II. BULK DRIVEN TECHNIQUE In traditional gate-driven transistors, the conductivity of the channel and, thus, the drain current, ID, is controlled by the gate-source voltage VGS, but, as already stated, the drain current can also be controlled by the bulk-source voltage VBS. This is normally an unwanted parasitic effect, but in a bulk driven transistor the idea is to use that gmb instead of the source transconductance gm. The bulk terminal has no threshold voltage associated and, as a result, the VT drawback is eliminated. This makes the technique especially suitable for low voltage design. One of the main disadvantages of bulk driven technique is the fact that gmb is smaller than gm, as quantified in (1)  =  =  (1) where η is usually between 0.2 and 0.4. When designing amplifiers, this leads to poor DC gain performance, larger noise and offset. In the proposed structure a third stage is added in order to counteract the drawback of low DC gain. Another issue that must be considered is the fact that the bulk-driven technique requires each bulk to be accessible, hence, in standard CMOS technologies, only p-channel transistors can be driven from the bulk. III. PROPOSED BULK-DRIVEN CLASS-AB AMPLIFIER The schematic of the proposed solution is shown in Fig.1. It is made up of three gain stages, namely the differential stage M1-M4, the second common-source stage M5-M6 and the third common-source stage M7-M8. The differential stage is made up of the bulk-driven differential pair, M1-M2, biased by diode-connected transistor, MR, whose body is tied to the virtual ground, i.e., (VDD+VSS)/2 978-1-4799-8893-8/15/$31.00 ©2015 IEEE (it should be noted that the proposed structure can work under double or single supply). In this way, MR-M1 and MR-M2 form two current mirrors that accurately set the DC current, provided that also the body of M1-M2 is connected to the analog ground. The active load of the first stage is realized with transistors M3-M4. The use of resistors R enables true differential mode operation from pair M1-M2 that is otherwise intrinsically pseudo differential. Indeed, the small-signal voltage at the drain of M4 (output of the first stage) depends on both Vin+ and Vin-. The first stage DC gain can be approximated by gmb·R. Fig. 1. Schematic diagram of the proposed OTA. TABLE I. TRANSISTORS DIMENSIONS AND DEVICES VALUES. Device Value Parameter Value M R , M1, M2 , M10 12μm/540nm IB 4 μA M3, M4, M9 2μm/540nm CC1 550 fF M5, M7 5μm/540nm CC2 30 fF M6, M8 30μm/540nm R 250 kΩ CL 20 pF VDD -VSS 0.7 V Resistors R set also the common-mode voltage at the drain of M3-M4 to be equal to their gate voltage. The DC current in the second stage is set through current generator M6, and thanks to the mirroring action between M4 and M5 (they have the same VGS), M5 can be dimensioned so as to minimize systematic offset (by setting equal nominal DC current in M5 and M6). The last stage is biased by current generator M8, whose current is set by the pseudo current mirror formed by M4 and M9. Note that this current is signal dependent and that increases when Vin+ increases. In other words, both M7 and M8 can deliver a large-signal current greater than the standby value, and therefore the third stage works in class AB. Frequency compensation is obtained through Miller capacitors CC1 and CC2 and a current buffer implemented by M3-M4, with a technique similar to that developed in [10] for a nested Miller compensated OTA. Dominant pole is hence achieved through CC1, and the unity-gain bandwidth (GBW) is equal to gmb1,2/CC1. Transistors aspect ratios, as well as the main circuit devices values are summarized in Tab. I. IV. POST LAYOUT SIMULATION RESULTS The OTA shown in fig. 1 was designed in a 180-nm standard CMOS technology. The layout of the amplifier is shown in fig. 2. The occupied area is 120 ×165Pm2. Figure 3 illustrates the frequency response of the proposed amplifier. The open loop gain is 61 dB and the unity-gain bandwidth is 3.6 MHz. The phase margin resulted to be around 60º. The common mode rejection ratio, CMRR, and the power supply rejection ratio, PSRR, have also been simulated. Their DC values are 46.7 dB for the CMRR and 60.2 dB/72.6 dB for the positive/negative PSRR, respectively. The amplifier was connected in inverting unity gain configuration as shown in Fig. 4 (Ra=Rb=100 kΩ). The response to an input step of 600 mV is illustrated in Fig. 5. The positive (negative) slew rate was 2 V/μs (4.4 V/μs) besides, 1% settling time was 733 ns (positive step) and 380 ns (negative step), respectively. It is seen that an almost rail-to-rail output swing is achieved. The input common mode range (ICMR) is also in principle rail to rail but is actually set by the maximum allowed input current that flows into the bulk. Thus, it should be limited to 400 mV in order to maintain the input current below 4 nA. Fig. 2. Layout of the proposed amplifier, area is 120 ×165Pm2. Main performance parameters of the proposed OTA are summarized in Tab. II. The effect of temperature and process variations on the amplifier’s performance has been investigated via corner simulations at 27°C, -40°C, 125°C. Results are summarized in Tab. III. The proposed amplifier remains stable across the extreme temperature and process corners. A comparison with other sub-1V amplifiers is also presented in Tab. IV where a figure of merit (FOM) is included in order to make the comparison easier. The FOM is defined as [9]  = 100 · ·  (2) where IDD is the standby current consumption and CL is the load capacitance. High-performance amplifiers are characterized by a larger FOM. The FOM value versus the year of publication for the amplifiers appearing in TABLE IV. is also plotted in Fig. 6. It is apparent from TABLE IV. that the proposed solution exhibits the best FOM. Besides, it provides one of the highest GBW values with reduced DC current consumption. Fig. 3. Frequency response of the proposed amplifier (magnitude and phase). Fig. 4. Amplifier in inverting closed loop configuration. Fig. 5. Step response of the proposed OTA in inverting unity gain configuration. TABLE II. SIMULATION RESULTS SUMMARY (CL=20 PF). Parameter Value Supply voltage (VDD-VSS) [V] 0.7 Power dissipation [P P W] 22.4 ICMR [mV] 400 Max Input current [nA] 3.5 Open Loop Gain [dB] 61 GBW [MHz] 3.6 Phase Margin [deg] 60 Gain Margin 5.08 SR+/SR- [V/Ps] 2/4.4 1% Settling time (+/-) [ns] 733/380 CMRR@DC [dB] 46.7 PSRR+@DC [dB] 60.2 PSRR-@DC [dB] 72.6 Input Ref. Noise @ 1MHz [nV/ Ĝ Hz] 273 THD @100kHz, 250mV input [%] 0.061 THD @250kHz, 250mV input [%] 0.509 TABLE III. MAIN PERFORMANCE PARAMETERS OVER PROCESS AND TEMPERATURE VARIATIONS. T= 27°C Corner TT FF SS SF FS DC Gain [dB] 60.9 61.3 60.2 61.1 60.6 GBW [MHz] 3.57 3.70 3.41 3.54 3.57 PM [°] 59.74 61.2 58.90 60.57 59.28 GM [dB] 5.08 5.06 5.32 5.16 5.15 SR+/SR- [V/PPs] 1.9/4.5 2.4/6.2 1.5/3.3 1.9/5.7 1.8/3.5 1% Ts+/Ts- [ns] 733/380 655/366 843/408 729/378 761/391 T= 125°C Corner TT FF SS SF FS DC Gain [dB] 58.4 58.4 58.1 58.2 58.4 GBW [MHz] 3.15 3.24 3.04 3.10 3.18 PM [°] 56.81 58.45 55.90 57.87 56.20 GM [dB] 5.10 5.20 5.16 5.28 5.03 SR+/SR- [V/PPs] 1.4/4.3 1.5/5.7 1.2/3.3 1.4/5.3 1.3/3.5 1% Ts+/Ts- [ns] 803/418 643/403 896/442 698/414 837/426 T= -40°C Corner TT FF SS SF FS DC Gain [dB] 62.0 62.6 60.7 62.3 61.1 GBW [MHz] 4.01 4.17 3.77 3.99 3.96 PM [°] 60.59 61.90 59.72 61.11 60.22 GM [dB] 5.27 5.13 5.74 5.28 5.53 SR+/SR- [V/PPs] 1.9/4.4 2.6/6.5 1.4/3.1 1.9/5.9 1.7/3.2 1% Ts+/Ts- [ns] 706/340 603/329 871/357 705/339 755/346 TABLE IV. PERFORMANCE COMPARISON OF SUB-1V AMPLIFIERS. Works b Technology [μm] Supply [V] DC Current [μA] C L [pF] DC Gain [dB] GBW [MHz] PM [º] SR+/- [V/P P s] FOM [MHz • pF/ P A] 1998 [3] GD 2 1 287 22 48.8 1.3 57 0.7/1.6 10 2001 [4] BD 0.5 1 40 20 62-69 2 57 0.5 100 2002 [5] BD 2.5 0.9 0.5 12 79 0.56 62 - 13.4 2005 [6] BD 0.18 0.5 220 20 52 2.5 - 2.89 22.7 GD 0.18 0.5 150 20 62 10 - 2 133.4 2009 [7] BD 0.35 0.9 11 2.5 62 0.54 52 - 12.3 2013 [8] BD 0.35 1 197 15 88.3 11.67 66 2.53/1.37 88.9 2000 [11] GD 1.2 1 410 15 87 1.9 61 0.8/1 6.9 2014 [12] BD 0.13 0.25 0.072 15 40 0.002 52 0.71 42 2013 [13] a BD 0.05 0.5 200 20 74 4.8 49° 3.4 0.48 This work a BD 0.18 0.7 32 20 61 3.6 60 2/4.4 225 a Simulations. b BD: Bulk Driven. GD: Gate Driven. Fig. 6. FOM vs Year of publication for the amplifiers appearing in TABLE IV. IV. CONCLUSIONS In this paper, a bulk-driven three-stage class-AB CMOS OTA, suitable for very low voltage supplies has been presented. Operation under 0.7 V was demonstrated through simulations using the models of a 180-nm standard CMOS technology. Compared to the state-of-the-art sub-1V amplifiers, the proposed solution exhibits a significant improvement in small-signal and large-signal performance thanks to an efficient class AB configuration, as a result, it presents the best FOM. Future work will be aimed to balance the positive and negative slew rate in order to reduce the settling time and drive even larger load capacitors. Besides, fully-differential solutions to increase signal swing and CMRR should be developed. REFERENCES [1] J. Ramirez-Angulo, S.C. Choi, and G. Gonzalez-Altamirano, "Lowvoltage circuits building blocks using multiple-input floating-gate transistors", IEEE Trans. Circ. Syst.-I: Fund. Theor. App., vol. 42, no. 11, pp. 971-974, 1995. [2] S. S. Rajput, and S. S. Jamuar, "Low voltage, low power, high performance current mirror for portable analogue and mixed mode applications", IEE Proceedings: Circ. Dev. Syst., vol. 148, no. 5, pp. 273-278, 2001 [3] B. J. Blalock, P. E. Allen, and G. A. Rincon-Mora, “Designing 1-V Op Amps using standard digital CMOS technology” IEEE Trans. Circ. Syst. II Analog Dig. Sig. Proc., vol.45, no. 7, pp. 769-780, 1998 [4] T. Lehmann, and M. Cassia, “1-V power supply CMOS cascode amplifier” IEEE J. Solid-State Circ., vol 36, no.7, pp. 1082-1086, 2001. [5] T. Stockstad, and H. Yoshizawa, “A 0.9-V 0.5 μm rail-to-rail CMOS operational amplifier”, IEEE J. Solid-State Circ., vol. 37, no. 3, pp.286- 292, 2002. [6] S. Chatterjee, Y. Tsividis, and P. Kinget, “0.5-V analog circuit techniques and their application in OTA and filter design”, IEEE J. Solid-State Circ., vol. 40, no. 12, pp. 2373-2387, 2005. [7] S. W. Pan, C. C. Chuang, C. H. Yang, and Y. S. Lai, “A novel OTA with dual bulk-driven input stage”, Proc. IEEE Int. Symp. Circ. Syst., pp. 21-24, 2009. [8] L. Zuo and S. K. Islam, “Low-Voltage Bulk-Driven Operational Amplifier With Improved Transconductance”, IEEE Trans. Circ. Syst.- I: Regul. Pap., vol. 60, no. 8, pp. 2084-2091, 2013. [9] P. Monsurrò, S. Pennisi, G. Scotti and Trifiletti, "0.9-V CMOS cascode amplifier with body-driven gain boosting," Int. J. Circ. Theor. Appl., vol. 37, pp. 193–202, 2009. [10] A.D. Grasso, G. Palumbo and S. Pennisi, “Advances in Reversed Nested Miller Compensation” IEEE Trans. Circ. Syst.I: Regul. Pap., vol. 54, no. 7, pp. 1459-1470, 2007. [11] J. F. Duque-Carrillo, J. L. Ausin, G. Torelli, J. M. Valverde and M. A. Dominguez, “1-V rail-to-rail operational amplifiers in standard CMOS technology”, IEEE J. Solid-State Circ., vol.35, no. 1, pp. 33-44, 2000. [12] L. H. C. Ferreira and S. R. Sonkusale, “A 60-dB Gain OTA Operating at 0.25-V Power Supply in 130-nm Digital CMOS Process,” IEEE Trans. Circ. Syst.I: Regul. Pap., vol. 61, no. 6, pp. 1609–1617, 2014. [13] T. Kulej, “0.5-V bulk-driven CMOS operational amplifier,” IET Circ. Dev. Syst., vol.7, no. 6, pp. 352-360, 2013. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 11, NOVEMBER 2016 1807 0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier Elena Cabrera-Bernal, Student Member, IEEE, Salvatore Pennisi, Senior Member, IEEE, Alfio Dario Grasso, Senior Member, IEEE, Antonio Torralba, Senior Member, IEEE,and Ramón Gonzalez Carvajal, Senior Member, IEEE Abstract—A simple high-performance architecture for bulkdriven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. The OTA is fabricated in a 180-nm standard CMOS technology, occupies an area of 19.8·10−3mm2 and is powered from 0.7 V with a standby current consumption of around 36 μA. DC gain and unity gain frequency are 57 dB and 3 MHz, respectively, under a capacitive load of 20 pF. Overall good large-signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art. Index Terms—Bulk-driven, class-AB, CMOS analog integrated circuits, low-voltage, operational transconductance amplifier. I. INTRODUCTION ONE of the main trends of modern consumer electronics industry is towards the extension of portable devices autonomy through the adoption of low power design techniques [1]–[5]. This has reinforced the interest in the development of low-voltage design approaches and techniques for the limitation of power consumption. Considering the CMOS technology, the most straightforward methodologies to enable operation below 1-V supplies are subthreshold biasing and bulk driving (or body driving) and even a combination of both [6]–[20]. Subthreshold transistors can be biased with currents in the range of a few nanoamperes, but this also implies low unitygain frequency and low achievable slew rate values. Therefore, subthreshold operation is particularly suitable in wireless sensor networks, biomedical applications and in all those applications where speed is not a concern, e.g., for bandwidth specifications in the range of a few kilohertz [21]. Manuscript received June 6, 2016; revised July 27, 2016; accepted July 28, 2016. Date of publication August 30, 2016; date of current version October 25, 2016. This work was partially supported by the Spanish Ministry of Economy and Competitiveness under the project TEC2013-47286-C3-1-R and the Andalousian “Consejería de Economía, Innovación y Ciencia” under the project P12-TIC-1862. This paper was recommended by Associate Editor A. Demosthenous. E. Cabrera-Bernal, A. Torralba, and R. G. Carvajal are with the Ingenieria Electronica, University of Seville, EscuelaTécnica Superior de Ingenieria, 41012 Seville, Spain (e-mail: [email protected]; [email protected]; [email protected]). S. Pennisi and A. D. Grasso are with the Dipartamento de Ingegneria Elettrica Elettronica e Informatica, University of Catania, Catania I-95125, Italy (e-mail: [email protected]; alfio.grass[email protected].it). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSI.2016.2597440 Fig. 1. Schematic diagram of the proposed OTA. As said, bulk-driven has also been exploited extensively for low voltage applications. While in traditional gate-driven transistors, the conductivity of the channel and, hence, the drain current, ID, is controlled by the gate-source voltage VGS,in bulk driven transistors the drain current is controlled by the bulk-source voltage VBS. The main idea is to use the bulk transconductance, gmb, instead of the gate transconductance, gm, since the bulk terminal has no threshold voltage associated and, as a result, the VTlimitation is eliminated. Note that the bulk-driven technique requires the MOS bulk terminal to be accessible, hence, in standard n-well CMOS technologies, only p-channel transistors can be utilized. One of the main disadvantages of the bulk driven technique is the fact that gmb =γgm/2√2ϕF+VBS =ηgm, with 0.1<η<0.4.This means that gmb is smaller than gmand, specifically for amplifiers design, this leads to poor DC gain and gain-bandwidth performance with larger noise and offset. In this paper, a high performance bulk-driven three-stage class-AB amplifier topology able to work under sub-1 V supply is presented. To provide adequate DC gain, the solution adopts a three-gain stage architecture, as also recently proposed in [22]–[24] for a subthreshold OTA. The proposed topology will be thoroughly explained and analyzed with the derivation of useful design equations in Sections II and III. Implementation and experimental results are presented in Sections IV as well as a comparison with other similar amplifiers. Some conclusions are drawn in Section V. II. CIRCUIT DESCRIPTION The schematic of the proposed OTA is shown in Fig. 1. As already mentioned, it is made up of three gain stages, 1549-8328 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. 1808 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 11, NOVEMBER 2016 namely the differential stage M1−M4, the second commonsource stage M5−M6and the third common-source stage M7−M10. Transistor MR, whose body is tied to the virtual ground, i.e., (VDD +VSS)/2, sets through mirror ratios the quiescent current of the differential pair M1−M2and of its load M3−M4, as well as of transistor M6acting as a load of the second stage. Indeed, MR−M1and MR−M2form two current mirrors that accurately set the DC current in the pair, provided that also the body of M1−M2is connected to the analog ground. The active load of the first stage is realized with transistors M3−M4and two resistors, R. Due to the fact that no DC current flows through resistors, the drains of M3−M4are at the same potential of their gates and, consequently, the DC current of M5 is also accurately set by (pseudo) current-mirror ratios ID5=ID4W L5 W L4 .(1) The excellent matching between the DC currents of M5and M6, causes the drain of M5to be theoretically at the same potential of the drain of M4, ultimately defining the current of M7, again through a mirror ratio ID7=ID4W L7 W L4 .(2) Note that current ID8is set through current mirror M8− M10 and pseudo-current mirror M9−M4. Therefore, to theoretically nullify systematic offset, ID8must be equal to ID7 leading to W L8W L9 W L10 W L4=W L7 W L4 .(3) In our design (W/L)9=(W/L)4was assumed for simplicity, but (W/L)9<(W/L)4could be used to slightly reduce current consumption. The minimum supply voltage (VDD − VSS)can be as low as VDS1,2+VGS3,4. A final comment regards the class AB behavior of the third stage. Both transistors M7and M8can deliver a maximum signal current that is not limited by any DC value. Indeed, M7 is in common source configuration, whereas the current in M8 increases when Vin+ increases because vGS9also increases. III. ANALYSIS AND DESIGN In this section the main behavior of the proposed amplifier will be analyzed and design equations derived. A. Differential Gain The use of resistors Rin the active load of the input stage enables fully differential operation of an otherwise pseudodifferential pair M1−M2. To understand this fact, let us apply a single-ended small-signal voltage, vd, at one input (e.g., the body of M1), while grounding the second input. Referring to Fig. 3, voltage vdis converted into a current, gmb1vd, one half Fig. 2. Equivalent circuit used for demonstrating the differential behavior of the adopted solution. of which will flow through the resistor series and the other half through transistor M3, because M3and M4have the same vgs, have the same transconductance and must consequently carry the same current. Fig. 2 shows then that a differential output voltage, vo1−vo2, is generated. The expression of the individual output voltages is approximated by1: vo1=vgs −gmb1Rvd 2=gmb11 gm3−Rvd 2(4a) vo2=vgs +gmb1Rvd 2=gmb11 gm3 +Rvd 2(4b) where in the second equality we used the following result: gmb1(vd/2) = gm3vgs. Given that gmb1=gmb2=gmb1,2and gm3=gm4=gm3,4. Assuming that gm3,4R1, then (4a), (4b) yield vo1=−vo2∼ =gmb1,2R(vd/2), demonstrating differential operation, since the application of vdfrom only one input terminal produces a differential output, as opposed to a pseudodifferential topology. For the symmetry of the circuit, the same result holds also if we apply the input signal from the body of M2. As a conclusion, the (single ended) gain of this first stage, vo2/vdcan be approximated by gmb1,2R/2. This outcome can be easily understood by referring to the fact that under small-signal differential input thegateofM3−M4is at virtual ground and therefore the load seen by the couple M1−M2is R(or, more accurately, R//rds1//rds3, as explained in footnote 1). From the above considerations, it follows that the proposed solution is well suited to implement a fully differential OTA. In this paper, for the sake of simplicity, we will limit the design to a single-ended topology to focus our attention on the operating principles and to determine basic design equations. B. Common Mode Rejection Ratio Resistors R have the additional role of setting the commonmode voltage at the drain of M3−M4to be equal to their gate voltage (because no current flows in the resistors under common-mode input). Referring to Fig. 3, under common mode 1We are neglecting for simplicity the output resistance of M1(M2)and M3 (M4). If this is not the case, a more accurate expression of the output voltage should include the parallel of R,rds1,andrds3, instead of Ralone. CABRERA-BERNAL et al.: 0.7-V THREE-STAGE CLASS-AB CMOS OPERATIONAL TRANSCONDUCTANCE AMPLIFIER 1809 Fig. 3. Differential input stage CMRR analysis. input no current flows onto resistors R and gmb2vcm must equal gm3vgs. Therefore, the common mode gain is Acm =vo2 vcm =−gmb1,2 gm3,4 .(5) This outcome can be easily understood by considering that if no current flows through the resistors then M3and M4operate as they are connected in diode and offer an equivalent resistance equal to 1/gm3,4. The (single ended) common mode rejection ratio, defined as |Ad/Acm|, is hence CMRR = Ad Acm  =1 2 gmb1,2R gmb1,2 gm3,4 =1 2gm3,4R. (6) From (6) we see that R1/gm3,4must be chosen to obtain adequate CMRR values. C. Frequency Compensation Frequency compensation of the differential (open loop) gain is obtained through Miller capacitors CC1and CC2and a current buffer [25] implemented by M3−M4, with a technique similar to that developed in [26] for a nested-Miller- compensated OTA. Dominant pole is hence achieved through CC1. Assuming both gmiroi,gmiR1,wheregmi is the gate transconductance of transistor iand roj is the resistance of the output node of the amplifier jth stage, the OTA loop gain transfer function can be approximated as A(s)≈A0 1+ s z1 1+ s p1(as2+bs +1) (7) where the DC gain, A0, the dominant pole, p1, and the zero, z1, are given by2 A0=gmb1,2gm5gm7(R//ro1)ro2ro3 2(8a) p1=2 gm5gm7(R//ro1)ro2ro3CC1 (8b) z1=gm5gm3 2CC1gm5−CC2gm3 .(8c) 2In this accurate computation of the DC gain, the MOS transistors output resistances are included. And for the remaining non-dominant complex conjugate poles, the coefficients of the polynomial in (7) are a=CC2CL(2gm5+gm3) gm3gm5gm7 (9a) b=CC1CL+CC2CLgm5ro2 CC1gm5gm7ro2 .(9b) The damping coefficient of this pair of complex poles is given by ξ=b 2√a=CC1+CC2gm5ro2 2CC1ro2CLgm3 gm5gm7CC2(2gm5+gm3). (10) Given gmb1,2,CL,andCC1, one can derive from (10) a suitable value of CC2in order to avoid peaking in the frequency response and to obtain a phase margin in the range of 60 to 70◦. Besides, gm5/gm3>C C2/(2CC1)can be chosen in order to obtain a negative zero from (8c) useful to increase the phase margin. From (8a) and (8b) the gain-bandwidth product, ωGBW ,is ωGBW =gmb1,2 CC1 .(11) D. Noise Noise in multistage amplifiers is usually dominated by the first stage provided that this first stage has a voltage gain considerably larger than the unity. Considering only white noise for simplicity, the equivalent input-referred noise voltage power spectral density (PSD) of the proposed amplifier can be approximated as (see the Appendix for the calculation of the inputreferred equivalent noise contribution of resistors, SVR,in) SV,in ≈2SV1,2gm1,2 gmb1,22 +2SV3,4gm3,4 gmb1,22 +SVR,in =22 34kT 1 gmb1,2gm1,2 gmb1,2 +gm3,4 gmb1,2 +4kTR1 gmb1,2ro121+1+2ro1 R2 ≈16 3kT 1 gmb1,2 gm1,2+gm3,4 gmb1,2 (12) where SVi is the gate-referred noise voltage PSD of the i-th transistor and kand Tare the Boltzmann’s constant and the absolute temperature. In the above expression noise from MRwas neglected since it is seen as a common-mode signal and rejected. Besides, also the noise from Rresults to be negligible provided that (gm1,2+ gm3,4)ro1(3/4)(R/ro1)[1+(1+(2ro1/R))2]. This condition is usually met. Finally, it is also seen from (12) that to make noise of M3,4 negligible, gm3,4gm1,2must be selected, yielding SV,in ≈16 3kT 1 gmb1,2 1 η=16 3kT 1 gm1,21 η2 .(13) However, gm3,4gm1,2cannot be easily set since large gm3,4 values are needed from (6) to achieve sufficient CMRR without requiring excessive Rvalues.