Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 1/158 Trabajo Fin de Máster “Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométricos” Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies Author: Miguel Gaitero Pérez Advisor: Juan Antonio Le ñero Bardallo Date: June 26, 2019 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 2/158 This page intentionally left blank Master Thesis 1 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 3/158 INDEX ❖Acknowledgments ❖List of figures and tables ❖List of abbreviations ❖List of equations ❖Key words 1. Introduction 1.1. Motivation 1.2. Summary 1.3. Goal 1.4. Scope 1.5. Methodology 1.6. Planning 2. State-of-the-art 2.1. Process evolution 2.2. Classification based on the source element 2.3. Market trends and cutting-edge 2.4. Physical limitations 2.5. Alternatives 3. Body 3.1. Photolithography 3.1.a. Physics 3.1.b. Optics: lens components, aberrations 3.1.c. Alignment and overlay: process and tool systematic errors 3.1.d. Throughput: cycle time breakdown 3.1.e. Current trends to improve accuracy 3.1.e.I. The Resolution Enhancement Techniques ( RET s) 3.1.e.II. Immersion tools 3.1.e.III. Extreme UltraViolet ( EUV ) lithography Master Thesis 2 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 4/158 3.2. 3D -integration 3.2.a. Market and applications 3.2.b. Through Silicon Vias (TSVs) 3.2.b.I. Classification 3.2.b.II. Process description 3.2.b.III. Process characterization: yield and reliability concerns 3.2.c. Bonding 3.2.c.I. Classification and direct bonding description 3.2.c.II. Process requirements/materials 3.2.c.III. Bonding quality characterization 3.2.d. 3D -patterning by modulated lithography 3.2.d.I. Tilted patterns by inclined/rotated lithography 3.2.d.II. Patterns by modulated exposure 3.2.d.III. Periodic 3D -patterns by holographic lithography 3.2.d.IV. Built-in lens mask lithography 4. Challenges 5. Conclusions ❖ Bibliography Master Thesis 3 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 5/158  ❖ Acknowledgments I would like to thank first of all to my family for the continuous support during the whole master degree and specially throughout the thesis realization, always motivating me to keep on working on this interesting project with passion. Thanks Miguel Ángel, María del Rosario and Alicia for your smile always trying to get the best of me. Second, let me thank the support of my friends. Especially two former student colleagues, Javi and Juan, who has been shown always interest in the project and keep on motivating me with their brilliant advice and successful careers. Moving onto the institutional support, I would like to thank the University of Seville for the challenging master degree and, specially, to my tutor throughout the thesis, Mr. Juan Antonio Leñero, who has been always attentive providing the required help and feedback in an impressive lead time. Last but not least, I want to thank my current employer, ASML , for having been an inspiration for me with the topic election at this master thesis and the knowledge sharing. The high tech work that they do contributes enormously to the technological progress and it is a great opportunity to take part of it. Master Thesis 4 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 6/158  ❖List of figures and tables Throughout the document some figures and tables are cross-referenced. The reader may find below an index with all the used figures and tables for convenience. ●Figure 1: Yearly sales for the semiconductor industry. ●Figure 2: History of transistor generations and logic styles. ●Figure 3: Patterning size evolution throughout the years. ●Figure 4: Master thesis Gantt chart. ●Figure 5: Different approaches for printing tools. ●Figure 6: Stepper sketch. ●Figure 7: Photolithography tool classification depending on the source element. ●Figure 8: Ultraviolet light spectrum. ●Figure 9: Resolution and wavelength trends in lithography. ●Figure 10: Microprocessors scaling timeline. ●Figure 11: Dissipated power for different interconnect delays. ●Figure 12: New technologies and materials roadmap. ●Figure 13: 2D vs. 3D-Integrated Circuits cross section. ●Figure 14: 3D-ICs advantages. ●Figure 15: Reticle with pellicle and its rest of components. ●Figure 16: Major polymer platforms for the different photolithography generations. ●Figure 17: Projection image. (a) Ideal situation. (b) Diffraction-broadened projection imaging. ●Figure 18: Light intensity distribution from a point source projected through a circular imaging lens. ●Figure 19: Projection lens basic sketch. ●Figure 20: Optical configurations for different photolithography generations. ●Figure 21: Rays and wavefront at a spherical lens. ●Figure 22: Spherical aberration. ●Figure 23: Critical Dimension (linewidth) versus Exposure Energy for different focus. ●Figure 24: Coma aberration and result. ●Figure 25: Astigmatism aberration. ●Figure 26: Field curvature aberration and result. ●Figure 27: Distortion aberration. ●Figure 28: Polar representation of Zernike polynomials. ●Figure 29: First five orders of Zernike coefficients and their related aberrations. ●Figure 30: Example of overlays errors in a transistor. ●Figure 31: Phase grating alignment mark. ●Figure 32: Hierarchy of overlay errors. ●Figure 33: Effect of a contaminant particle in the image formation. ●Figure 34: Throughput model for steppers and scanners for different field sizes and resist sensitivities . ●Figure 35: Wafer cycle of life between the track and the photolithography tool (scanner). ●Figure 36: Alternating phase shift masks. (a) Superposition of aerial images amplitude for conventional lithography. (b) Superposition of aerial images amplitude for PSM. (c) Comparison of conventional and PSM image and resolution. ●Figure 37: Optical rays for different NAs. (a) Dry. (b) Wet environment. Master Thesis 5 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 7/158 ●Figure 38: Example of an advanced catadioptric projection lens. ●Figure 39: Reflectivity and spectra density for different source elements. ●Figure 40: EUV laser light source. ●Figure 41: EUV lithography light path. ●Figure 42: Major 3D-integration technology platforms. (a) Chip-on-Chip (CoC). (b) Chip-on-Wafer (CoW). (c) Wafer-on-Wafer (WoW) vertical integration. ●Figure 43: Microelectronics packaging evolution. ●Figure 44: Features and schematic of the main 3D-integration processes/technologies. ●Figure 45: Market segments for advanced packaging (e.g. 3D-integration). ●Figure 46: Evolution of 3D-CMOS image sensors using TSVs. ●Figure 47: Bosch accelerometer package using TSV integration. ●Figure 48: Schematic of logic devices Arria 10 and Stratis 10 by Altera. ●Figure 49: Hybrid Memory Cube (HMC) by Micron. ●Figure 50: A 3D-IC with different components such as TSVs. ●Figure 51: Regular TSV top and side view. ●Figure 52: Annular TSV top and side view. ●Figure 53: Tapered TSV top and side view. ●Figure 54: Coaxial TSV top and side view. ●Figure 55: TSV-first approach process flow. ●Figure 56: TSV-middle approach process flow. ●Figure 57: TSV-last approach process flow. ●Figure 58: Backside TSV-last process flow. ●Figure 59: Frontside TSV-last process flow. ●Figure 60: DRIE process steps. ●Figure 61: DRIE features etched in Si. (a) Top view of TSV with sidewall scallops. (b) Cross section of scallops in Si trench. (c) “Scallop-free” TSV etch. ●Figure 62: TSV insulation process steps. ●Figure 63: Typical TSV formation process steps. Metallization comes after the isolation. ●Figure 64: CMP process. ●Figure 65: Comparison of protrusions between annealed and unannealed TSV-Cu after ten thermal cycles. ●Figure 66: Temporary bonding/bonding, wafer thinning and TSV reveal process flow for conventional 3D-integration. ●Figure 67: Electrical circuit model of TSV. ●Figure 68: Induced stress at TSV due to CTE mismatch. ●Figure 69: SEM images showing Cu protrusion for different annealing conditions. (a) 25ºC. (b) 250 ºC. (c) 300 ºC. (d) 350 ºC. (e) 400 ºC. (f) 450 ºC ●Figure 70: Major 3D-bonding approaches: direct, indirect and hybrid bonding. ●Figure 71: Direct bonding between Au electrodes into SiO 2 . (a): Top view. (b): Cross section. ●Figure 72: Process flow of the 3D-Direct Bonding using Au electrodes to connect with SiO 2 . ●Figure 73: Direct Bonding Interface (DBI) for a sensor. ●Figure 74: Sensor manufacturing by using direct bonding, TSVs and DBI. ●Figure 75: Impact of bonding surfaces-roughness. (a): Rigid bonding surfaces preventing bonding. (b): Rigid bonding surfaces using an intermediate material to allow bonding. ●Figure 76: Combination of SLID bonding process and TSVs. ●Figure 77: TEM cross section of Cu-Cu bonding at 40 degrees Celsius. ●Figure 78: Critical adhesion energy measured by a four-points bending technique for wafers with Master Thesis 6 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 8/158 oxide, Cu-oxide and Cu-low-k interconnects, bonded to an oxidized Si wafer using BCB. ●Figure 79: Measured chain resistance by using daisy-chain device in an Au (electrodes)-SiO 2 junction. ●Figure 80: Cu-Sn IMC bonding cross section. Before (top) and after thermomechanical stressed (bottom), where voids can be seen to enlarge. ●Figure 81: Shear strengths for direct bonding Au/SiO 2 without and with plasma treatments. ●Figure 82: Tilted patterning by inclined lithography. ●Figure 83: Tilted pillars by inclined lithography. Scale bar corresponds to 100 μm. ●Figure 84: Asymmetric pillars with aspect ratio=10 by combining X-ray vertical and tilted exposure. ●Figure 85: Tilted and rotated patterning by inclined lithography. ●Figure 86: Tapered structures by tilted and rotated UV exposure. Scale bar corresponds to 50 μm. ●Figure 87: Structures fabricated by tilted UV on nonreflective (silicon, left hand side), and reflective (aluminum-coated silicon, right hand side) substrates. Scale bar corresponds to 100 μm. ●Figure 88: Suspended 10 μm thick grid structures made by gray scale lithography. ●Figure 89: Interference lithography with two laser beams. ●Figure 90: Chiral 3D-structures (spirals) produced by holographic lithography. Scale bar corresponds to 1 μm. ●Figure 91: Basic concept of the built-in lens mask having complex optical transmittance g*. ●Figure 92: 3-dimensional imaging by superposing complex amplitudes of the seed patterns in various focal planes. ●Figure 93: 3-dimensional imaging of a pattern “S” by computational lithography. ●Figure 94: Challenges for EUV lithography. ●Figure 95: Example of EUV materials and resolution concerns for a circuit manufacturer. ●Figure 96: Lithography tool supplier roadmap. ●Figure 97: TSV formation manufacturing defects. (a) Etching defects. (b) Cu out-diffusion. (c) Cu fill voids. (d) Good TSV formation. ●Figure 98: 3D-integration simulation and optimization prior to the manufacturing. ●Table 1: Patterning resolution and photolithography source wavelength. ●Table 2: The Moore’s law limits. ●Table 3: Basic relationships on photolithography technology generations. ●Table 4: Classification of alignment methods for photolithography. ●Table 5: Resolution Enhancement Techniques (RETs). ●Table 6: TSVs fabrication processes classification. Master Thesis 7 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 9/158  ❖ List of abbreviations As other technical sectors, circuit manufacturing is full of abbreviations. A list of them (also the ones used at equations), properly sorted alphabetically with their signification, is included to allow the reader to always come back to check the meaning. ●%: per cent ●2D: Two Dimensional ●3D-IC: Three Dimensional Integrated Circuit ●A eff : cross sectional area of the TSV ●Al: Aluminium ●AMD: Advanced Micro Devices (company) ●APA: American Psychological Association ●Ar: Argon ●ArF: Argon FLuoride ●ASIC: Application-Specific Integrated Circuit ●ASML: Advanced Semiconductors Materials Lithography (company) ●Be: Beryllium ●BEOL: Back-End-Of-Line ●BGA: Ball Grid Array ●BSI: Backside Imager ●C: capacitance ●c: light speed in vacuum ●C 4 F 8 : Octafluorocycloebutane ●CAD: Computer-Aided Design ●CaF 2 : Calcium Fluoride ●CD: Critical Dimension ●CFET: Complementary Field-Effect Transistor ●cm: centimeter ●cm 2 : square centimeter ●CMOS: Complementary Metal-Oxide-Semiconductor ●CMP: Chemical Mechanical Planarization ●CoC: Chip on Chip ●CoCoS: Chip on Chip on Substrate ●CoW: Chip on Wafer ●CoW: Chip on Wafer ●CoWoS: Chip on Wafer on Substrate ●CSP: Chip Scale Packaging ●CTE: Coefficient of Thermal Expansion ●Cu: copper ●Cu 3 Sn: no formal chemical name, represents the compound in the copper-tin phase diagram (Intermetallic Compound) Master Thesis 8 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 16/158 for EUV lithography, which has improved the resolution of the pioneer systems, in opposition to the conventional Deep UltraViolet ( DUV ) lithography, which typically uses wavelengths between 193 and 365 nm . ●Fab/factory: utility where the circuits are manufactured. ●Front-End-Of-Line (FEOL): term used at the manufacturing industry to describe the first processes during circuit manufacturing. It includes the process steps preceding the first metal layer. ●Holographic/interference lithography: alternative lithography technique consisting on using various coherent laser to create a interferences so that an inclined pattern is printed into the surface of the wafer. Used for 3D -lithography novel techniques. ●Hybrid bonding: 3D -circuits manufacturing process consisting on attaching two materials with the help of an added material in one of the bonding surfaces, forming the electrical connection. ●Immersion (wet) lithography/tool : using liquid -concretely watersurrounding the lens instead of air, in order to improve the resolution of the photolithography process. ●Inclined mask/lithography: alternative lithography technique consisting on tilting the reticle and the wafer so that inclined/ 3D -patterns can be printed into the wafer. Used for 3D -lithography novel techniques. ●Indirect Bonding: 3D -circuits manufacturing process consisting on attaching two materials by means of an intermediate material which makes the connection. ●Integrated Circuit ( IC ) :electronic circuit formed on a small piece of semiconducting material (typically silicon) which performs different functionalities. ●Keep Out Zone ( KOZ ): area surrounding TSV to create a safe distance between TSV s and active devices in order to eliminate proximity effects. ●Key Performance Indicator ( KPI ) : figure which specifies the quality/performance of a process. It is specific of the process, being the most common for photolithography the overlay. ●(Excimer) laser : ultraviolet light generator used in the production of microelectronics among others. It is the light source for the photolithography tool. ●(Optical/projection) lens : single, optically transparent device which enhances the transmission and refraction of light. In photolithography, it allows the light generated by the laser to pass through, so that the pattern can be imaged onto the wafer. ●(Alignment) marks/keys/targets/fiducials : distinguishable patterns used as reference point for the photolithography tool to establish the coordinate system at the wafer level. ●Modulated/ 3D -lithography: alternative lithography techniques not consisting on using optical means, but other processes able print 3D -patterns. ●Moore’s law : observation and prediction made in 1965 by Gordon Moore, co-founder of Intel, postulating that the number of transistors per square inch on integrated circuits had doubled (and will double) every two years. ●Multilayer Mirror/Bragg Mirror : type of mirrors used at EUV lithography since they are able to reflect the light, thus achieving larger incident angles that conventional mirrors. Master Thesis 15 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 17/158 ●Numerical Aperture ( NA ) : dimensionless number that measures the ability to gather light and to print a pattern at a fixed distance. It is a lens feature which is to be enlarged, in order to allow more light to pass through. ●Overlay/alignment : figure which indicates how well the stack-up between layers is done (in terms of relative position). The alignment is the process performed at the photolithography tool in order to achieve better overlay. ●Pattern : pre-defined model or shape which is used in photolithography to build the circuits by imaging it onto the wafer. ●Pattern generator : photolithography tool which uses as input data a database to directly create a physical image on the wafer. ●Pattern replicator : photolithography tool which creates a master pattern image in the form of a reticle and them replicates the pattern in a massively parallel fashion onto the wafer by means of a projection lens. It is the most common type of photolithography tool. ●Phase Shift Mask ( PSM ) : a technique based on the principle of light interference with the goal of creating destructive interferences between the light from the adjacent openings, so that the resolution of the photolithography tool is improved. ●Photolithography/optical lithography/conventional/ UV lithography : process of imaging a pattern onto a wafer by means of light. It is a key process in the electronic manufacturing, since its quality defines the performance of the circuit. ●(Wafer) processing : all the methods performed at the track. It includes coating and baking among others, which are needed to condition the wafer in order to perform the photolithography process. ●Rayleigh equation : mathematical relationship between the resolution of the photolithography process with respect to the Numerical Aperture of the lens and the wavelength of the inciding light. It also specifies the Depth of Focus used by the image lens. ●Refraction index n : d imensionless number which describes how fast the light propagates through the material. It is characteristic of each medium, thus defining the optical features in that environment. ●Reliability: concept to describe how well a product will behave in the long run. It is a key feature on a product, since has to be tested during product verification to guarantee the customer that the functionality will be kept throughout the time. ● (Photo)resist :organic material which consists of a polymer base resin. It is coated at the track to the wafer surface, allowing a certain wavelength to pass through to print the pattern into the wafer. ●Resolution/accuracy : figure which defines the ability to distinguish different components within a group of objects. Whereas the Critical Dimension or pattern size is more related to the circuit (the result of the photolithography process), the resolution/accuracy refers more to the photolithography tool itself. ●Resolution Enhancement Techniques ( RET s) : methodologies which improves the imaging performance (better resolution) by wavefront, mask or resist process engineering, thus reducing the Rayleigh constant k 1 . Master Thesis 16 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 18/158 ●Reticle/photomask : both terms are identical, defining an opaque element with a “written” pattern on it. Physically it is a thin sheet with some holes which allows the light to pass through, thus replicating the patterns into the wafer. ●Scallop: small ridges formed during TSV etching, being a well-known pattern as a result of that process. ●Scanner/step-and-scan tool/(photo) lithography tool/exposure tool : it is the system (machine) which performs the photolithography process. The three concepts will be used as synonyms throughout the thesis, consisting in the most advanced system types, where both the reticle and wafer are moving at the same time to improve accuracy and throughput. ●Silicon ( Si ): semiconductor material which is mainly used at the electronic industry due to its properties. It is provided to the factories in small rounded-pieces called wafers. ● System in Package ( SiP ): concept used to describe numeral IC s integrated in one single chip carrier package. ● Throughput : indicator of the amount of parts (in photolithography, wafers) that can be processed in a certain amount of time (typically one hour). ●Through Silicon Via ( TSV ) : vertical electrical interconnection in the 3D-Integrated Circuits, which passes through the different layers of the die. ●Tier/layer: each of the strata for 3D -Integrated Circuit. Typically interconnected by TSV s. ●Track : system or machine which performs the processing of the wafer, i.e. the chemical treatments before and after the photolithography process to condition the wafer. ●TSV -first: process flow for 3D -Integrated Circuits, consisting on creating the via before the FEOL . ●TSV -last: process flow for 3D -Integrated Circuits, consisting on creating the via during or after the BEOL . Two variants exist depending on where the interconnection is done: backside or frontside. ●TSV -middle: process flow for 3D -Integrated Circuits, consisting on creating the via after the FEOL but before the BEOL . ●Voids: concept which describes the absence of material at 3D -bonding, being a reliability concern since the electrical connection and the junction robustness are degraded. ●Wafer : a thin slice of semiconductor used as substrate for electronics manufacturing. It is conventionally made on a circular shape with a diameter of 200 or 300 mm . ●Wafer-on-Wafer ( WoW )/Wafer to Wafer ( W2W ): sort of 3D -bonding technique consisting on stacking a wafer into another wafer. ●Wavelength : physics feature which represents the distance between two consecutive points on a wave shape, where the same state is achieved. In photolithography, it is used to characterize the light source, thus defining the resolution of the tool by means of the Rayleigh equation. ●Yield: figure to show how well a process performs. Typically represents the ratio between the good (based on one or multiple criteria) manufactured parts out of the total manufactured parts. Master Thesis 17 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 19/158 ●Zernike coefficients : mathematical invention which consists on numeral polynomials describing an optical tool. They are used to easily observe the aberrations in optical systems. Master Thesis 18 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 20/158 This page intentionally left blank Master Thesis 19 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 21/158   1. Introduction Electronic market has experienced an incredible growth during the past century, thus being nowadays one of the leading economies at the industry. The semiconductor companies, which customize the conductivity of the raw piece of silicon to fabricate the microchips, have generated sales in 2018 equivalent to 477.94 billion U.S. dollars [1] , proving the increasing importance of the market as shown in figure 1 . Figure 1: Yearly sales for the semiconductor industry [1] . The origin of that revolution, the seed that caused this “big-bang” of electronics, was a grain of germanium on which the point contact transistor was fabricated for the first time in 1947 by J. Bardeen, W. Brattain, and W. Shockley [2] . That was the trigger for an unending race on continuous improvement to look for the “perfect transistor” which has the best physical and mechanical features to makes the chips of today. The evolution throughout history is depicted in figure 2 , where different paths have been explored by the researchers community. Master Thesis 20 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 22/158  Figure 2: History of transistor generations and logic styles [3] . The boom of the robust MOSFET as preferred option, empowered the semiconductor market throughout the years, where the chips manufacturing was considerably advanced due to automation, reducing the cost and time to market and offering more reliable products, while increasing employee safety through highly sophisticated electronic security systems that can recognize and warn of critical equipment failures [4] . Electronics appeared then as an easy solution for storing media, making communication faster and better with each other (the Internet), improving medical procedures with noninvasive techniques or helping the science to advance by making computational tasks ultra fast. Master Thesis 21 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 23/158 Using electronics today is so much a part of our daily lives we hardly think of the way the world would be without electronics [5] . Everything from cooking to music uses electronics or electronic components in some way. Our family car has many electronic components, as does our cooking stove, laptop and cell phone. Cell phones are everywhere to take and send pictures, play music, text messages or just checking whe weather forecast. The Internet is used by almost everyone, from companies to send emails or store the information, to the personal usage such as online shopping or checking the bank statement. Music is a prime user of electronics, both in recording and in playback mode: music players, head- or earphones and speakers would not be existing without the electronic revolution. Television as main pastime fully incorporates the latest advances in electronics, being now able to get connected to the Internet and to other devices. Cameras of today are affordable, being included in the cell phone or as individual device, with the pictures easily to be easily edited through the marvel of electronics. Electronics devices are being used in the health field, not only to assist in diagnosis and determination of medical problems, but also to assist in the research that is providing treatment and cures for illnesses and even genetic anomalies, thus being pacemakers or similar equipment implanted in the body as almost a routine activity. It is clear that today’s lives are impossible to conceive without the electronics. How is that progress possible and for how long can withstand? Well, the electronic evolution through the years is known as the Moore’s law, who stated that the amount of transistors on a chip doubles every two years. But the implication is not only about that figure, but also about the feature size, cost or power, as the figure 3 suggests, resulting in smaller, cheaper and more power microchips, respectively. Master Thesis 22 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 24/158  Figure 3: Patterning size evolution throughout the years [6] . This is where the photolithography came to the play, being the main process of the chip manufacturing. Its process quality, cost and cycle time are the main figures for the factories to take into account at the chip production. The evolution of the transistor size has gone hand-by-hand with the photolithography progress: the smaller the feature size printed by the photolithography tool, the faster and smaller the microchip. Advances in lithography have been possible thanks to good understanding of the optics and physics behind the process, as well as material properties, making possible to keep Moore’s law valid until nowadays. However, the size shrinking can not long forever: even with the most advanced lithographic techniques, it is expected that physical limitations will impide the transistor size to be decreased. Some alternatives have appeared with the goal of replacing the conventional photolithographic process to drive the future of the semiconductor industry. Concretely, the approach of stacking-up different layers to create a 3D -integrated device, has recently gained a lot of weight at some electronic applications, since it allows to integrate different functionalities at a chip without increasing the power dissipation which is one of the main factors braking the scaling progress. 3D -integration seems as a valid candidate for certain applications, but it is not yet used for mass production due to some technological challenges. Master Thesis 23 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 25/158 The present is clear: using the photolithography breakthroughs is allowing to continue with the trends to improve our daily lives with smaller microchips. The future is uncertain though: will the 3D -integration the solution for the chip of tomorrow? It is difficult to predict the market evolution, but at least knowing the state-of-the-art of both technologies will help to have a better understanding of the current issues and how the industry is tackling them to improve our lives with better chips. Master Thesis 24 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 32/158 The total realization of the master thesis comprehends 12.0 ECTS which are equivalent to 300 hours. The total spent time at the whole master thesis by the student was approximately 97 days, with an average of 3 hours/day, thus making a total of approximately 291 hours (only by the student), which is within the budget. In terms of cost, since there was no finished products to provide and the access to all the literature has been granted through the university collaborations and internal sources, it was limited to the amount of working time. Master Thesis 31 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 33/158  2. State-of-the-art Since the beginning of the circuits manufacturing, the key process to determine the performance of the chip was to perform the patterning, i.e. to replicate a predefined pattern into the circuit so that the different regions are created. This process, called photolithography, continues with the natural trend of doubling the transistor size every two years predicted by Gordon Moore, thanks to the manufacturer innovations to continue decreasing the pattern size. Despite the fact that this process seems to crash soon against physical limitations of the conventional physics, based on analysis of various reports, press announcements, news stories, and technical articles written in the past 20 years, it has been forecasted that the optical lithography can long until 2024 [7] . Master Thesis 32 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 34/158   2.1. Process evolution Up to the early 1970s, the most common process to perform the patterning was to use proximity printing or even printing by contact, in which blue and near UltraViolet ( UV) light was passed through a photomask onto a photoresist-coated semiconductor substrate [8] . However, this fashion was replaced in the 1970s by the projection printing tools manufactured by Perkin-Elmer, the so-called Micralign projection aligners. The main difference for those tools was the performance enhancement, since they scan and image only a portion of the wafer, whereas the previous tools cover the whole wafer at the patterning, as shown in figure 5 . Using this methodology, also the optical resolution was improved, since the printed details could be more specified having less field to expose. Figure 5: Different approaches for printing tools [9] . But the main breakthrough in terms of accuracy and performance happened in the early 1980s, where the steppers were introduced [10] . The revolution of those new systems was that only one single chip was patterned at a time, performing many times the “stepping-and-repeating” process to cover the whole wafer, which movement is easy to be understood by checking the stepper sketch in figure 6 . This has a huge impact on the photomask (also called reticle throughout this thesis) and the lens, since the size of the first one could be enlarged whereas the lens would reduce the size (and thus the accuracy improves) by not augmenting the complexity of the reticle. Another implication of this new process is the improving overlay, in other words, the accuracy of a printed layer versus the previous one (how well they are stacked up), since the small printed areas are controlled independently from each other, allowing correction for wafer- and lens-induced distortion. Master Thesis 33 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 35/158  Figure 6: Stepper sketch [11] . So far it has been described the reticle movement (scanning) and the wafer movement (stepping), but what about mixing both methodologies? Well, that was the main idea introduced in the mid-1990s with the first tool Microscan by the manufacturer Silicon Valley Group, where both the reticle stage and the wafer stage moved at the same time, thus improving the accuracy and utmost the throughput of the tools. This is also called step-and-scan tool or simply scanner, which is nowadays the most common accepted strategy since it combines all the benefits of the previous invented processes. Master Thesis 34 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 36/158   2.2. Classification based on the source element In terms of the element which creates the pattern, one differentiates between pattern generators and pattern replicators, which can be also subdivided depending on the source that they use, in accordance to figure 7 . Figure 7: Photolithography tool classification depending on the source element [12] . -The pattern generators use as input data a database to directly create a physical image on the wafer. They utilize either charged particles or photons to create the image. The photomask fabrication is done with electron or photon beam tools, while the mask pattern defects are repaired with ion and photon beam tools. Their main disadvantage is the throughput (the speed to perform the process), only reaching one single 200 mm -wafer per hour, obviously not being that enough to cope with the actual chips demand. -The pattern replicators , on the other hand, create a master pattern image in the form of a reticle and then replicate the pattern in a massively parallel fashion onto the wafer by means of a projection lens. A variety of image transfer techniques can be used, such as photons and charged particles, having a throughput -depending on the accuracy and extra software packageson the range of 220-260 wafers/hour for a 300 mm -wafer size (one can imagine the amount of difference in terms of money of producing one versus 240 wafers/hour). The most common pattern transfer agent is a well-conditioned beam of monochromatic photons, whose wavelength is in the range of ultraviolet spectrum. The wavelength, in fact, has been decreased in the photolithography history to achieve greater resolution or, in other words, better accuracy Master Thesis 35 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 37/158  by reducing the pattern size. This has to do with the Rayleigh equation , which will be further explained in the main body of the thesis. Throughout the photolithography history, one can differentiate different element sources, each one with a corresponding wavelength. ❖The most basic approach uses mercury as source (also called as g -line of mercury), with a 436 nm -light source. ❖The second generation reduces the wavelength until 365 nm , being called the i -line of mercury. ❖The main change in terms of the source was to introduce the excimer lasers to replace the High Pressure lamps of mercury, having then very high intensity and a narrower bandwidth, thus reaching the 248 nm wavelength using Krypton Fluoride ( KrF ) as source element. This light wavelength -and the following generations with even smaller λ - is already at the ultraviolet region, which spectrum is shown in figure 8 . ❖The fourth generation uses an Argon Fluoride ( ArF ) excimer laser, with a wavelength of 193 nm . ❖Some trends researched to go down to a source of 157 nm with Calcium Fluoride ( CaF 2 ) as lens material. However, it needs as required environment the vacuum, and the CaF 2 large intrinsic birefringence complicates the design and manufacturing of high-quality optical lenses [13] . ❖The previous three sources are in the region of the Deep UltraViolet ( DUV ), whereas the new breakthroughs use vacuum and Extreme UltraViolet ( EUV ) light, reducing the wavelength to an impressive 13 nm ( 13.5 nm indeed). Figure 8: Ultraviolet light spectrum [14] . Master Thesis 36 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 38/158  The resolution of each generation has been improved by techniques which will be discussed in the body of this thesis, but one can already observe the correspondence between decreasing the wavelength with the improvement in resolution (the minimum feature size is reduced). The table 1 establishes the correspondence between the light source wavelength and the minimum feature size achieved with that lithography tool. Table 1: Patterning resolution and photolithography source wavelength [14] . Master Thesis 37 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 39/158   2.3. Market trends and cutting-edge The outstanding evolution of the photolithography, with impressive breakthroughs as the immersion lithography and now the EUV lithography, is continuing to reduce the pattern size. At the figure 9 the trend can be easily identified, reducing from a pattern of 1.5 microns ( μm ) in the early eighties, until the current 7 nm : Figure 9: Resolution and wavelength trends in lithography [15] . The trend is clear: the Moore’s law remains applicable. Every time the microprocessor scaling trend was about to be cut off, anyhow new inventions -such as the EUV lithographycame up to continue reducing the patterning size, as sketched in figure 10 . But what about the future? Well, the Numerical Aperture ( NA ) of the lens, which defines how good is the resolution at the printed pattern, has become a clear limitation: if the NA cannot be further improved (increased) for EUV , it is expected to reach a theoretical limitation at 3 nm . New devices, such as the Complementary Field-Effect Transistors ( CFETs ) or the Vertical Field-Effect Transistors ( VFETs ), or the integration of three-dimensional ( 3D )-logic at EUV lithography with higher NA , can make the Moore’s law still valid with the von Neumann architecture. Master Thesis 38 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 40/158   Figure 10: Microprocessors scaling timeline [16] . What is currently in the market? The leading foundries are in mass production using both dry and wet tools (for the most demanding applications). Dry tools are the conventional ones, thus using air surrounding the lens, whereas the wet tools uses water to improve the resolution of the system even further. But the revolution does not stop there: the transition into the EUV lithography is a reality: Samsung is using now the EUV light as source to manufacture nodes with 7 nm sizes, and it is rumoured [17] that their cell phones for 2021 will include a 3 nm -technology node. The main manufacturer for microprocessors at the cell phone industry, the Taiwan Semiconductor Manufacturing Company ( TSMC ), is more than certain [17] of reducing their pattern size from their current 7 nm to 5 nm -nodes for the new iPhone to be released in 2020. At the computer microprocessors, Intel is taking a more safe approach since Global Foundries is not going to use EUV in the near future. Intel current nodes of 14 nm are expected [18] to shift into EUV lithography by mid-2021, when they expect to introduce at the market a 7 nm -node. Other foundries are not using the EUV yet (the cost of the tools is hundreds of million euros), since not all the market needs the ultra high accuracy of that technology. Even if a circuit requires that precision in the critical layers, conventional production lines accomplish multiple photolithography tools for different patterning sizes. Master Thesis 39 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 41/158   2.4. Physical limitations Even with all the advances in lithography, the current manufacturing process as we know it nowadays must finish some day. The semiconductors physics applied to devices of few nanometers is no longer valid, but quantum physics has to be considered as well. The physical limitations are almost there: ❖High electrics fields: they can create avalanche processes increasing the current passing through the transistor, and thus getting to a chip malfunctioning. ❖Interconnection delays: the parasitic RC -network effect is huge for small dimensions, thus having problems with the signal integrity to operate at high frequencies. ❖Heat/power dissipation: the faster the microchip, the more power is dissipated. The figure 11 illustrates that trend, showing that for smaller interconnect delays, the power is increased. Even using very powerful fans the generated heat it is a well-known issue, such as the incident with the batteries for the cell phone Samsung Galaxy Note 7. The only real solution is to completely rethink chip packaging and cooling, for instance having microfluidic channels that increase the effective surface area for heat transfer [19] . The power dissipation is one of the main bottlenecks for keeping on scaling the transistor size, thus the market looking already for packages alternatives such as the 3D -integration. In fact, even when that approach is considered as a potential alternative to mitigate the issue, the heat dissipation at each individual layer remains as one of the major headaches of the industry. Figure 11: Dissipated power for different interconnect delays [20] . Master Thesis 40 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 48/158 Despite the fact that both trends seem to work in different directions, i.e. lithography on reducing the patterning size and 3D in reducing the dissipated power, the 3D -Integrated Circuits need of photolithography process for manufacturing, but not the latest techniques with the best accuracy. However, what would happen if the solution for the future is to combine both techniques to reduce cycle time and cost for 3D -circuits manufacturing? The last part of the thesis body will research about different novel techniques which are trying to merge both techniques. Master Thesis 47 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 49/158   3.1. Photolithography Photolithography is the process of defining useful shapes on the surface of a wafer, thus creating the different regions where the physics will act -by means of electrons/holes balanceby building different functionalities and, in the end, composing the whole semiconductor device. The main component for the process is the reticle, which has the patterns to be printed into the substrate, also called wafer. The reticle (also called photomask) is depicted in figure 15 , being an opaque element with a “written” pattern on it. It consists of a thin sheet with some holes which allows the light to pass through, thus replicating the patterns into the wafer. As the reticle will be used to generate million of Integrated Circuits ( IC s), one can imagine that if some contamination is found on it, the result will be that the patterned circuits will be wrong, therefore utmost cleanliness of the photolithography tool and, in particular, of the reticle, is mandatory for the circuit manufacturing. To ensure that, a transparent polymer film known as pellicle, protects the printed pattern. Figure 15: Reticle with pellicle and its rest of components [34] . Not only perfection in terms of cleanliness for the reticle handling is needed but also, due to the fact that they are light sensitive, the lighting used at the clean rooms needs to be yellow (not absorbed by the reticle) in order to avoid chemical reactions with the film which may alter the pattern. If handling and preservation are critical for the reticle life, o ne can also infer that the reticles manufacturing has to be at utmost perfection (in terms of accuracy) and taking into account the “well-known” issues which have been learned by trial-error and complex studies, therefore Design Rules ( DR s) are common in its manufacturing. Reticle cost is therefore very expensive (not talking about its manufacturing lead times), thus being considered by the foundries as “holy” reticles. Master Thesis 48 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 50/158  Awafer , a thin slice of semiconductor e.g. crystalline silicon, whose conductivity properties are explained with the energy levels, which represents the silicon -and other semiconductorsas quantized levels of energy forming energy bands. One can differentiate between the conduction and the valence band, which represents the first and the last energy band to be filled by electrons, respectively [35] . Between them it appears the bandgap, where the electrons are forbidden to stay due to their energy. The difference in terms of energy between the conduction and the valence band represents the bandgap energy. An electron can step between levels if its energy is greater than the bandgap energy of the material. The energy is calculated with the Planck’s equation , where hrepresents Planck's constant and fthe incident light frequency, which is also related to c (the light speed in vacuum) and lambda (the light wavelength). On this way, a balance between generated electrons-holes can be chemically -artificially- implemented, where the properties of the silicon makes it ideal to build the electronics that is nowadays used. The wafer is coated (covered) by a photosensitive material known as photoresist , which is an organic material which consists of a polymer base resin with additional components to provide photosensitivity and other properties. Its sensitivity range has to match the wavelength of the light source, thus absorbing only that wavelength allowing the pattern to trespass the coating, so that the pattern is replicated onto the wafer. The main photoresist figures of merit are the resolution, the process latitudes and the reactive ion etch resistance. The previous features are also photolithography tool-dependent, therefore every change in the process parameters will affect the exposure, as well as using a different coating for the wafers [36] . Additional intrinsic parameters for the photoresist are the sensitivity, the compatibility with industrial standard developers, the adhesion to the substrate, the environmental stability and the shelf life. Obviously each generation of the photolithography process has implied a matching counterpart in the used photoresist, which is summarized at the figure 16 . Master Thesis 49 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 51/158  Figure 16: Major polymer platforms for the different photolithography generations [36] . Master Thesis 50 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 52/158     3.1.a. Physics The main physical property behind the photolithography is the use of the wave nature of the light. Its wavelength ( λ ) is related to the projection system (defined by the Numerical Aperture NA , the Resolution Rand the Depth of Focus DoF ) by means of two constants: k 1(Rayleigh Resolution) and k 2(Rayleigh Depth of Focus). The basic relationships are known as Rayleigh equations , thus defining the Resolution and the DoF as follows: ❖The Numerical Aperture is defined as: where n is the index of refraction of the medium surrounding the lens (in case of vacuum will be 1 and for air it is usually simplified to 1). It is a dimensionless number that measures the ability to gather light and to resolve fine specimen detail while working at a fixed object (or specimen) distance [37] . ❖The Resolution defines the ability to distinguish different components within a group of objects. ❖The Depth of Focus ( DoF ) determines the tolerance of the distance between the lens and the wafer which can be modified in order to still achieve a correct patterning process. Using those basic equations , the figures of table 3 are obtained for the different photolithography technologies: Master Thesis 51 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 53/158    Table 3: Basic relationships on photolithography technology generations. Source: own, based on [12] . Light source Light wavelength [ nm ] NA k 1 Resolution [ nm ] DoF [ nm ] i-line ( Hg ) 365 0.62 0.48 280 950 KrF 248 0.82 0.36 110 370 ArF 193 0.92 0.41 65 230 KrF 2 157 0.85 0.41 57 220 When the maximum angle of the light rays is relatively small or, in other words, when the NA is small, sin (Θ) can be considered to be simply Θ . For larger angles and values of the Numerical Aperture, the error in using this simple approximation grows unacceptably large [38] , thus becoming the Rayleigh equations for large angles : To finish up the physics analysis, let us remark that so far we have considered that all the light is passing through the space defined by the Numerical Aperture of the lens, without having any attenuation. However, in an actual projection imaging process, the simple copy of the reticle pattern is not achieved, but some diffractions and imperfections appear in the projection system, since the projected image is altered as shown at the figure 17 on the right hand side. Master Thesis 52 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 54/158   Figure 17: Projection image. (a) Ideal situation. (b) Diffraction-broadened projection imaging [12] . The spreading of the image profile has been deeply investigated for the last two centuries, thus concluding that it is a consequence of the wave nature of the light and thus effectively limits the resolution capability of the optical imaging systems. Its characteristic was well studied by G.B. Airy, who first plotted in 1835 [39] the dependence on the intensity with respect to the distance x between the object and the image, with a defined pattern illustrated at the figure 18 . Figure 18: Light intensity distribution from a point source projected through a circular imaging lens [12] . Master Thesis 53 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 55/158   3.1.b. Optics: lens components, aberrations The key component for the “magic” to happen is the projection lens : its goal is to replicate a pattern into the wafer. Usually it reduces the size of the image -by a factor of 4:1 nowadays [40] - and costs the most in the lithography tool (a couple of millions euro), therefore only the main optics manufacturer (such as Nikon, Canon or Zeiss) are in the lead for its manufacturing. Mainly contributor of the patterning resolution, the design of the lens is based on projection principles. The pattern printed on the reticle will be passed through the lens, being the light rays distributed in a conical shape to converge in the image plane, i.e. where the image is located, in case of the photolithography the wafer surface. The conventional lens has a circular shape, and can be very easily plotted with a basic schematic such the figure 19 . Figure 19: Projection lens basic sketch [12] . Some elements are highlighted: ●Diameter D : will impact the accuracy on the patterning. It has to be designed in accordance to the reticle size too. ●Focal distance f : it is the distance between the lens itself and the image plane, which in photolithography is the surface of the wafer. ●Angle Θ : it defines the NA of the lens, which will have a direct impact on the accuracy. The empirical meaning is that the NA is a feature to understand how many light rays (light orders) may pass through the lens, thus allowing the light to be printed onto the wafer. Therefore, the greater the NA , the better the resolution, since more orders of lights can traverse through the lens to recompose the image at the image plane. Master Thesis 54 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 56/158 While the previous analysis the reader may have got acquainted with the basic concepts of optics, the conventional lens used in optical lithography are much more complex that a simple mirror though. In particular, the lens has to control the Critical Dimension ( CD ), alignment (overlay), reticle errors and many other details. But in addition to that, the lens can be breakdown into multiple mirrors: it is not just a thin piece of glass anymore. It is beyond the scope of this thesis to deep into the optics breakdown, since the focus is more oriented to the potential issues that the lens can introduce ( e.g. optical aberrations), rather than the whole light ray-study traversing all the mirrors to reshape the original pattern. The optical aberration can then be defined for photolithography as a flaw or distortion in the patterned image (at the wafer level) versus the original image at the reticle, being generated by the optical lens. Nevertheless, it will be pointed out that the mainstream at the industry is using refractive imaging lens working at a monochromatic wavelength. To build it up, up to 30 separate lens elements are used [41] with the goal of reducing the aberrations to less than 1 %of the wavelength, having evolved the complexity through the main technology nodes. The figure 20 shows the complexity evolution throughout the years. Master Thesis 55 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 57/158  Figure 20: Optical configurations for different photolithography generations [41] . It has been already mentioned before the main issues on the lens: the aberrations. How do they affect the patterning process? To answer this question, one has to talk first about the wavefront, which is shown at the figure 21 , being defined as the surface over which an optical disturbance has a constant phase. In addition to that, the rays are defined as lines normal to the wavefronts at every point of intersection [42] . Master Thesis 56 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 64/158   The low orders of the Zernike coefficients clearly show the astigmatism, coma and spherical aberrations and, what is more, they show a complete set so that they can represent arbitrarily complex continuous surfaces giving enough terms [58] . The figure 29 represents the aberrations obtained for different Zernike orders. Figure 29: First five orders of Zernike coefficients and their related aberrations [59] . Master Thesis 63 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 65/158   3.1.c. Alignment and overlay: process and tool systematic errors The analysis of the lens and its characterization provided the reader the understanding of the potential issues of non-properly exposing the wafer due to the aberrations. However, even if the light is properly aligned and the rays are converging in a point in the Z- axis, how can we make sure that the exposing process is centered in Xand Ycoordinates? Well, it comes now to the alignment and overlay. Thinking about a transistor, that semiconductor element will only work if the contacts have sufficient overlap with the appropriate parts of the transistors and do not contact the parts of the transistor from which they are supposed to be electrically isolated. On the contrary, if there are overlay errors such as the ones at the figure 30 , it may well happen that the transistor malfunctions. Figure 30: Example of overlays errors in a transistor [60] . The alignment is defined as the proper position of the photolithographic pattern relative to prior reference patterns, which are “commercial” marks conventionally known as fiducials, wafer or alignment marks . The fiducials are typically printed at the zero layer of the wafer (indeed it is the first printed layer) and at every added layer, prior or more usual at the photolithography tool, being an adequate shape in order to be detected via pattern recognition processes or laser beams. Once the fiducial mark is detected, the mask and wafer positions are properly re-positioned so that the projected image from the reticle and projection lens falls as close as possible onto the desired location on the wafer. Master Thesis 64 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 66/158  Having defined the alignment as a process, the result of that “fine tuning” versus the fiducial is the overlay ,i.e. how well the stack-up is done in terms of relative position between the different layers. The most accurate definition of overlay is: a vector quantity defined at every point on the wafer [61] . It is the difference, , between the vector position, , of a substrate geometry and O P2 the vector position of the corresponding point, , in an overlaying pattern, which may consist P1 of photoresist: The reader may notice that the definition of overlay is a relative one, since it relates the tolerances between layers and not versus a zero-reference. A similar definition, known as registration, defines the overlay but this time versus a reference grid. In fact, it is just a matter of references: even if the wafer has its own mark who represents its absolute zero, the wafer coordinates are also referenced to the wafer chuck (and stage) coordinates, which are at the photolithography tool. To achieve the best overlay, just detecting the fiducial mark will not be accurate enough, since some misalignment still can occur between the stage and the wafer, therefore the alignment process takes several steps: 1) The wafer stage is firstly zeroed using encoders to detect its position. By means of the zeroing process, the interferometers take over the control on the wafer stage since it starts from a “well-known” position (the zero position), thus being more accurate than just measuring by means of encoders. 2) The next step is the pre-alignment, where a small wafer feature (typically a wafer notch) is detected to pre-align the wafer on the stage, thus providing a suitable range for the fine alignment. 3) By this moment, the photolithography tool already knows the position of the wafer stage, and more or less the relative position of the wafer within the wafer stage. Now it is time to very accurately locate the wafer within the wafer chuck, which is the place where the wafer is vacuum-clamped at the photolithography tool. To do so, some marks (which varies between the different tool manufacturers) are in the chuck, so that the photolithography tool knows, now by means of laser optics, where the chuck is located. 4) The last process would be to pattern (or read) the fiducial or alignment marks on the wafer, so that their positions are related to the wafer chuck marks, which have been previously referenced to the position of the wafer stage. Master Thesis 65 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 67/158  The basic measurement of gratings (or marks) could be done by one light source and using two reference marks, thus correcting rotation and translation. However, due to the nanometer-required accuracy, more marks are needed to correct the potential expansion (wafer contractions) in the two axes ( Xand Y ) if the alignment marks are not all collinear on a single axis. There is also a measurement in the Z -direction, since the non-flatness would imply also errors in the other coordinates. The methodology to detect the marks and perform the alignment process can be classified into three different criteria, as the table 4 specifies: Table 4: Classification of alignment methods for photolithography. Source: own, based on [60] . Alignment classification Types Optical method Bright-field Dark-field Diffraction Referencing of wafer to reticle On-axis or Through-The-Lens (TTL) Off-axis Number of alignment sites Global Enhanced global Die-by-die The photolithography tool manufacturers have been using the different approaches mentioned on the table 4 , sometimes utilizing different combinations or even evolving from one technique to another. It is beyond this thesis to deepen in each and every single technique, but the reader is strongly encouraged to research further [61] . As reference, the technology used by the tool manufacturer Advanced Semiconductor Materials Lithography ( ASML ) will be described. Concretely, their steppers use a phase grating alignment system to directly align reticle and wafer images through the main stepper lens [62] , a process sketched in figure 31 : Master Thesis 66 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 68/158   Figure 31: Phase grating alignment mark [60] . The maximum alignment signal results when the two phases differ by 180 degrees, having auxiliary optics (minimum two laser sources) to compensate for optical path differences. By not detecting the edge, the resolution requirements of the alignment optics are considerably relaxed, also achieving an excellent signal-to-noise ratio. Instead of using the mainstream technique of having wafer marks in each layer, ASML just etches the alignment marks in the zero layer, thus using this reference for building up the whole wafer layers by aligning the subsequent reticles to this zero layer. That approach has to use a wavelength suitable to trespass the coating without any damaging and uses extra time, but it has good advantages such as maintaining marks integrity throughout all the layers and avoiding lens offsets (the offset will be placed in all the layers but its total overlay will be null). Enough talked about the ideal world of the alignment process to achieve the best overlay. The real world means that there are a lot of mechanical limitations that will make the overlay to not achieve the targeted result. There are two categories of overlay errors: intrafield, which involve the variation of overlay errors within exposure fields, and interfield, which are the ones that vary from exposure field to exposure field across wafers. For its analysis, a hierarchical model is used, where three main categories are defined as summarized at the figure 32 : Figure 32: Hierarchy of overlay errors. Source: own, based on [60] . Master Thesis 67 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 69/158 a) Process-dependent effects : this category refers to the problems introduced by the track, i.e. the tool responsible for processing the wafer before (and after) the exposure at the photolithography tool. Numeral processes can go wrong before the exposure, such as film depositions, resist coatings, etches or polishes. To overcome those issues, the lithography tool has to be optimized depending on the previous process parameters, for instance by adjusting the dose and the energy of the exposure. Typical failures that are observed in this category are: ❖Addition and removal of highly stressed films causing wafer distortion. The stress (compressive or tensile) of the deposited film layers might change the wafer dimensions once the wafer is chucked (clamped) into the wafer chuck. Usually it is a linear dimensional change, which can be read and automatically compensated by the magnification control of the exposure tool. But, if the highly-stressed film were partially removed from the wafer, the distortion might not be linear and would be almost impossible to be corrected [63, 64] . ❖Sputter deposition of metals causing asymmetries in overlay targets, since metal ions are partially shadowed by the alignment mark topography. That might lead to apparent shifts in the position of the alignment marks, therefore the exposure control will be degraded. ❖Asymmetrical resist coating can cause apparent displacement on the wafer alignment marks, since they consist typically of raised or depressed features in the underlying pattern layers. The consequence for the overlay will depend upon the alignment detection system used [65] . The Chemical-Mechanical Polishing ( CMP ) process can help to reduce that asymmetry, but also might lead to other issues as described in the following paragraph. ❖Chemical-mechanical polishing ( CMP ) process can reduce the alignment target contrast by rounding the alignment marks more on one side than on the other, therefore they become invisible when the planarization process is completed. Thus, accompanied with the polishing, often produces asymmetries particularly when the pattern width is large. ❖Not only related to the process done on the track, but also appearing at the photolithography tool itself, contamination is one of the main root causes of exposure defects. Therefore an extreme clean environment is mandatory at the fab in order to avoid contamination in the wafer, the reticle and the photolithography tool environment. The figure 33 allows the reader to understand the consequences in the image formation of having a contaminant particle before the lens. Master Thesis 68 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 70/158  Figure 33: Effect of a contaminant particle in the image formation [66] . b) Matching errors : they are the consequence of using different steppers for the same Integrated Circuit ( IC ). In common manufacturing processes, many steppers can appear, sometimes even from different brands, since in the same circuit different accuracies might be required (not always the tool with best accuracy is the most used, since throughput and cost also have an influential weight for the decision). Therefore, even if the accuracy of one stepper seems to be within specifications, its relatively small error, converging with another inaccuracy from a different stepper, might make the circuit to fail. This type of failures are related with the elements of the stepper itself, such as the lens or the reticle: ❖Mask errors: even if they are manufactured by an electron beam or a laser beam writer, still residual errors exist. Furthermore some mechanical errors are added at the chucking (clamping) of the reticle into the exposure tool (which might fit better at the fundamental overlay errors), thus leading to apparent distortion in the printed pattern. It is generally accepted a reticle error below or equal to 40 %of the overall error caused by the photolithography tool. ❖Lens distortion and magnification: they have been discussed at the optics subchapter with the aberrations before. But on top of that, let us remember that the distortion is usual at any optical projection system, and that telecentricity at the lens may also lead to magnification errors. Typically all exposure tools have control systems to maintain the magnification (reduction ratio of the pattern) corrected by every wafer, therefore the magnification error tends to be random and not characteristic of any tool in a matched set. Master Thesis 69 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 71/158 c) Fundamental overlay errors : they are related to the photolithography tool mechanical limitations, and also due to the substrate non-flatness within the tool. One can highlight: ❖Wafer chucking errors: when the wafer is clamped at the wafer, it is flattened and clamped by means of vacuum to the chuck. This might lead to the well-known “hot-spot” issue, which makes the wafer has more elevated parts at its surface, which will cause resolution failures and Critical Dimension errors. In addition to that, the effective locations of wafer features with respect to the optical column are slightly changed due to local tilt of the wafer, as it rests on the contamination. The opposite effect is the “cold-spot”, which is obviously appearing a lowered/depressed part at the wafer. To avoid those issues, extremely careful control of the air pressure for clamping, temperature, stage motions and contamination is required at the scanner. ❖Stage errors: the reticle and wafer stages are basically manipulators with limited accuracy, since they have to step with determined precision, being affected by dynamic forces such as friction, stiction, hysteresis and/or vibrational modes. They are tracked by encoders (coarse tracking) and laser interferometer gauges with measurement resolution of less than 1 nm (for the fine positioning control), but even so it can obtain false measurements due to turbulences or temperature non-uniformity of the air in the region of the stage. Therefore, extreme care is needed for the design and manufacturing of the airflow and thermal control around the stages (improper heating of silicon wafers leads to non-flatness and to a slippery silicon surface). The high speeds increasing the throughput will create and augmentation on the vibrations, thus leading to secondary errors [67, 68] . As appendix of this subsection , one has to mention that the overlay of the tool is always measured with an equipment, which can be internal or external to the photolithography tool. Even if the photolithography process looks good (by the internal feedback of the photolithography tool), the metrology tool introduces also an error at the measurement, therefore sometimes may exist a false negative or a false positive. The metrology errors can come from different sources: for instance the metrology offset and shift itself, which is usually below 2 nm . Particularly critic is the methodology of measuring, which is usually done with a large (10 mm ) box pattern, but that size has to be optimized and customized to the pattern size on the wafer. The metrology tool also has a lens, which can suffer from aberrations, therefore a study of that optics is needed too. Master Thesis 70 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 72/158    3.1.d. Throughput: cycle time breakdown Obviously the industry is always focusing on the cutting edge in terms of accuracy, thus finding news like the latest information by the taiwanese manufacturer TSMC which announced the 5 nm -technology node mass production from the second half of 2019 (the reader may refer to the section state-of-the-art for manufacturers comparison). But accuracy has literally a price: not always it is needed to have the most precise system since the price of the tool can be ridiculously high. But, what if a manufacturer makes the best chips of the market but they are only able to produce one IC per hour, in comparison to another foundry which produces hundred of less accurate chips at a reduced price? It comes obvious that the concept of throughput/productivity is enormously important for the photolithography. Indeed, the wafer throughput is the most prominent factor in advanced cost of ownership models, even more important than the price of the tools. Photolithography is generally the most used process in the wafer fab, typically accounting for 30 % –35 %of the total process cost. Therefore, most fabs are designed so that the photolithography area will be fully loaded at all times. This, in turn, drives very high importance to the productivity of photolithography tools. To analyze the throughput, some definitions are needed. The easiest one is the so called “ sprint rate ”, which defines the maximum run rate, i.e. how fast the tool can expose in optimal conditions. The previous figure defines one measurement of throughput ,i.e. an indicator of the amount of parts (in our case wafers) that can be processed in a certain amount of time (one hour). The wafer process time can be also breakdown into the following components: Master Thesis 71 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 73/158  Let us describe the meaning of each term: ❖t woh is the overhead time per wafer : its first contributor is the time to load and unload the wafer, which is system-dependent and has typical figures of few seconds or less. The other factor is the alignment time, which depends on the alignment strategy: no alignment, two or three marks, or the most common nowadays having between 8 and 10 positions on the wafer (takes generally a few seconds). One very interesting approach to reduce the overhead time per wafer is the one used by ASML , which employs two interchangeable wafer chucks running in parallel: during exposure of one wafer, the other wafer is being measured, and then they are swapped [69] , thus reducing the cycle time. ❖t foh is the overhead time per exposure field , which represents the movements between consecutive exposures. It includes stepping time, settling time, scan acceleration time, die-by-die alignment time (if used by the tool manufacturer) and shutter delay times. The overall figure is typically between 100 and 200 ms . ❖t exp is the actual exposure time during which the actinic radiation is exposing the resist. For a typical 193 nm chemically amplified resist, with an exposure sensitivity in the 20–30 mJ/cm 2range, and an exposure power density of 2000 mW/cm 2at the wafer, the resist-limited scan rate is 30–80 cm/s , which spans the mechanical scanning rate specification [12] . The relative throughput can be plotted as a function of the field size and the resist sensitivity, as represented at the figure 34 : Figure 34: Throughput model for steppers and scanners for different field sizes and resist sensitivities [12] . Master Thesis 72 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 80/158 The result is that the resolution is improved by a factor of 1.44, and also the DoF is increased by that factor n . In fact, some analysis [38] has proven that the Depth of Focus can be increased even more than by the factor 1.44. How the implementation of the water medium is implemented at the tool depends on the manufacturer. Different approaches have been considered: the first one was to completely immerse the wafer, wafer stage and the bottom of the lens. Due to the rapid stepping and scanning motions, the mechanical difficulties make abandoned this approach. The second one consisted on limiting the water to a smaller region at the wafer stage (like a small pool), thus having no need for the stage itself to travel through a large bath of water [80] . This approach is also not used nowadays by the manufacturers. The most accepted one consists on creating a film of water between the bottom of the lens and the wafer, in an area called Immersion Hood ( IH ). That film is constantly refreshed by the flow of water from a fill port to a removal port [81, 82] , being its cleanliness and temperature control key for a proper patterning. The implementation of the wet tools have some extra challenges for practical implementation though: ❖Optical design of projection lens : larger NA greatly increases the required size of the individual lens elements, impacting both cost and manufacturing difficulties [83] . The alternative choice is to use a catadioptric lens design, employing a small number of reflective elements (which provides the imaging power) in addition to refractive elements (responsible for correcting the aberrations). For instance, once can use three mirrors as sketched the figure 38 : two would be simple folding mirrors and the third one (curved) is responsible for providing a substantial portion of the imaging power of the lens, whereas refractive lens elements correct the aberrations and provide some of the imaging power of the lens. Master Thesis 79 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 81/158  Figure 38: Example of an advanced catadioptric projection lens [12] . By using this approach it is possible to increase the NA up to 1.30 or even more, while maintaining the overall lens size. The complexity also remains similar to the largest possible all-refractive designs [84] . ❖Mechanical system design : in order to maintain high productivity and accuracy, it is essential that the wafer stage motion will not be degraded by the immersion environment. To avoid so, the thin film of water (around 1 mm thick) has to be maintained in position by surface tension properties of the nozzle materials. To do so, a typical approach is to use an air curtain to keep the water in the proper position [85] . ❖Additional wafer defects : the existence of air bubbles or floating particles at the wafer sheet may block or scatter the imaging light from the lens, therefore it is important to filter and properly handle the extremely high-pure water at the fab. Large bubbles (diameter greater than 1 micron) must be avoided since they will block the light, whereas smaller bubbles (smaller than 100 nm ) can be tolerated unless they are close to the wafer surface, since there they can create a distortion of the patterned image on the wafer [86] . Also the interaction between the water and the resist can create potential defects such as different pattern density across the wafer, therefore the solution is to add topcoat or using extra processes such as pre- and/or post-soaking, having as drawback extra cycle time -therefore costat the processing on the track. Master Thesis 80 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 82/158 ❖Control of the wafer-resist surface effects : it is important to locate properly the nozzle around the periphery of the exposure field at the bottom of the lens. The optimum angle between the water and the resist has been determined to be 70 degrees or higher [87] , to allow containment of the water film under the lens. In terms of the resist surface, creating an extra hydrophobic coating would help to avoid that the resist would draw water from the Immersion Hood, as well as improving the mechanical performance of the resist. Consequently, a hydrophilic surface is to be avoided (to not pull out droplets from the water film). ❖Thermal control of the water : the ultra-high accuracy required for the optical and mechanical components of modern tools required extra attention to the thermal expansion of materials and the alteration on optical properties due to temperature drifts. Adding the water as new element introduces two new difficulties: the first one is that the water heats easier than air, therefore the change in the refractive index (10 -4 per K ) will lead to degrade imaging, consequently the water temperature has to be within a 10 mK range [88] . The second concern has to do with the evaporation of the water: it is essential that the flow is recovered and none of it evaporates, since otherwise it can result in residual water films or droplets imaged onto the wafer. Master Thesis 81 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 83/158   3.1.e.III. Extreme UltraViolet ( EUV ) lithography The Extreme UltraViolet (EUV) lithography uses a different light source, having nowadays an extremely short wavelength of 13.5 nm . The first experiment with such short wavelength was done with Molibdenum ( Mo ) and Beryllium ( Be ) as element sources, using a wavelength of 11.3 nm . The reflection optic used was composed of multiple multilayer mirrors, each one absorbing around 70 %of the light. However, in 1999-2000, the international semiconductor community abandoned that approach due to health and safety issues with the very toxic Be particles [89] and went for the 13.5 nm approach. Further experimentation [90] drove to use tin ( Sn ) as source element due to the high reflectivity : a comparison of that feature for different element is plotted at the figure 39 . It is also important to notice that EUV radiation is strongly absorbed in virtually all materials, even gases [40] , therefore a vacuum environment is to be used. Figure 39: Reflectivity and spectra density for different source elements [90] . For EUV lithography, the generation of the light is no longer by an excimer laser (or Hg source at the old-fashioned high pressure lamps), but generated by a high-temperature and high-density plasma. There are basically two methods [91] to generate it: the Laser-Produced Plasma ( LPP ), which condenses a strong laser beam onto a certain material, and the Discharge-Produced Plasma ( DPP ), that uses a pulsed high-current discharge between electrodes in an atmosphere of certain materials. The EUV laser light source becomes much more complex, as the figure 40 depicted, needing in addition more space and cost to be generated. Master Thesis 82 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 84/158  Figure 40: EUV laser light source [91] . But the major difference introduced by this new light generation for the lithography tool is the use of reflection optics. It is implemented by means of multilayer mirrors -also called Bragg mirrors since their properties are described by Bragg’s lawinstead of the transmission optics (lenses) used for the conventional DUV lithography. The multilayer mirrors are able to reflect the light, achieving larger incident angles for nearly monochromatic light than with conventional mirrors [92] . The alternating layers have dissimilar EUV optical constant, thus providing a resonant reflectivity when the period of the layers is approximately half times the wavelength [40] . The EUV beam follows a well-studied path, first exiting from the plasma to be collected by a condensing mirror, then passing through a point called the intermediate focus ( IF ), and lately illuminating a reflection-type mask after it is reshaped by the illumination optics [93] . The EUV beam reflected by the mask is exposed then by the projection optics (notice that there is no longer a direct path between the reticle and the wafer through a lens), forming a pattern on the wafer surface. The figure 41 represents the whole EUV light path. Master Thesis 83 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 85/158  Figure 41: EUV lithography light path [94] . If resolution is improved with EUV light, the metrology has also to accompany this progress. Therefore, to measure the wafer positions, new inventions have appeared, such as the Sommargren interferometer, which has achieved by using visible light an unprecedented accuracy [95] . It measures the wavefront, compared to a highly accurate spherical wave generated by an optical fiber, or by an accurate small pinhole. The resolution achieved is 0.25 nm RMS and it is expected to be reduced by an extra 50 % [40] . Other differences of the EUV lithography versus conventional lithography arise from the masks: they are reflective and not transmissive. They consist of a patterned absorber of EUV radiation placed on top of a multilayer reflector deposited on a robust and solid substrate, such as a silicon wafer. The mask reflectance spectrum needs to match with the one from the multilayer-coated mirrors at the optic system [40] . The resists are also affected by this absorption-difference, therefore they are structured so that printing occurs in a thin imaging layer at their surface. Master Thesis 84 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 86/158   3.2. 3D -integration Driving in another direction than the concept of reducing the photolithography patterning size, the 3D -integration appears as a major candidate to meet the performance and cost demands of the new generation-devices. The 3D -integration, in addition to allow to mix disparate technologies in a stacked chip, offers more choices in terms of process flows [96] : Chip-on-Chip ( CoC ), Chip-on-Wafer ( CoW ) and Wafer-on-Wafer ( WoW ). Making the same distinctions, but using different names -replacing ‘chip’ by ‘die’ and inciding more in the bonding connection from a circuit to another circuit, not highlighting the fact that a circuit is mounted on another circuit-, three similar names can be found in the literature [97] : Die-to-Die ( D2D ), Die-to-Wafer ( D2W ) or Wafer-to-Wafer ( W2W ). Despite the terminology discussion, it is clear the cost advantage that can be achieved in 3D -Integrated Circuits fabrication, therefore the use of the WoW ( W2W ) is expected to be inevitable [98] . The three different process flows are shown at the figure 42 . Figure 42: Major 3D-integration technology platforms [96] . (a) Chip-on-Chip (CoC). (b) Chip-on-Wafer (CoW). (c) Wafer-on-Wafer (WoW) vertical integration. Before trying to understand the new technology, let us ask ourselves for the origins of the 3D -integration: why did it appear? Well, whereas significant advancements were done on the miniaturization of the patterning size, the reduction in feature sizes on the Printed Circuit Board ( PCB ) side has evolved at a much lower rate, thus creating a gap between the features, pitch sizes achievable on the silicon and PCB substrates [94] . In order to bridge this gap, several packaging technologies have been developed over the years, as the figure 43 reflects: for instance the through-hole in the 1970s or the surface mount in the 1980s. On the 1990s, new technologies appear such as the Ball Grid Array ( BGA ), System-in-Package ( SiP ) and Chip Scale Packaging ( CSP ), whereas around 2000 the trends were fan-in or Wafer Level CSP ( WLCSP ), flip chip BGA and package on package. Due to continuous increase in requirements of more performing packages, the need for advanced packaging technologies has raised in importance, therefore appearing recently the 2.5D -interposers (using an intermediary interposer, typically silicon or glass, which is included in the package) and, there we are, the 3D -integration (stacking-up without that interposer). Master Thesis 85 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 87/158   Figure 43: Microelectronics packaging evolution [99] . The current society demands for the advance packaging ( e.g. 3D -integration) include among others [94] : ● Reduced cost. ● Small form factor (thinner packages, smaller footprint). ● Lightweight packages. ● Increased Input/Output ( I/O ) density (enabled by smaller pitch sizes). ● Increased integration capabilities. ● Increased electrical performance. ● Reduced thermal performance. ● Increased reliability. There is no technology that can fit all the current packaging needs , but each market segment will have its own requirements depending on the application. In other words, depending on the functionality and the end-user, some of the previous needs will have more importance than the others. The first section on the 3D -coverage at this thesis will be focused on the different market segments which are used the 3D -integration, also showing the cutting-edge by the main producer in each application. Master Thesis 86 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 88/158  After that, the reader will be driven to the processes to form the 3D -integration, To achieve the vertical stacking of the layers (also known as tiers), basically two main processes are required, being their features compiled at the figure 44 :bonding directly the layers over the others and creating vias to connect all the layers . Indeed, the whole process for stacking up can be subdivided in four unique sub-processes: Through-Silicon Via ( TSV ) formation, alignment, bonding and thinning [96] . Through silicon via ( TSV ) technology is the most mature approach [100, 101] but it is not always suitable for high-density integration for via sizes of 5 μm or less. Nevertheless, it performs the electrical (among others) connection between the layers, thus occupying the second subsection in this part about 3D -integration . Bonding is closely related to alignment and thinning, even including those sub-processes for some assembly processes ( e.g. microbump bonding between chips), therefore the third subchapter will be dedicated to analyze its main process variants, as well as the requirements, materials and limitations. Figure 44: Features and schematic of the main 3D-integration processes/technologies [102] . To finish up with the 3D -integration section , an insight on the advanced lithography for 3D -circuits (also known as modulated-lithography) is given. Trying to link with the main core of the thesis, that subsection will review the trends and current technologies at the market, exploring the possibilities of integrating both technologies state-of-the-art for the future user demands. Master Thesis 87 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 89/158   3.2.a. Market and applications Even if the reader may think that the whole electronic market is full of 2D -devices, with regards to the market and products the advanced packaging can be found across various segments [94] : from end-user (smartphones, cameras, personal computers, tablets, gaming, set-up box, TV s, etc.) to industrial applications (network, high performance computers, servers), transportation (automotive, trains, hybrid and electrical vehicles), medical, military, aerospace, telecommunication and renewable energy. The figure 45 provides an overview of the different market segments used for advanced packaging. Figure 45 : Market segments for advanced packaging (e.g. 3D-integration) [103] . The 3D -Integrated Circuits have been tested across several of those applications, from CMOS image sensors to Micro-Electro-Mechanical Systems ( MEMS) , Radio Frequency ( RF)/ Power/Analog/Mixedsignal processors, memories, photonics and even LED s. Some of those applications are furthered explained below: ❖CMOS image sensors : the first application of 3D -Integrated Circuits for image sensors was done by electrodeposition (lining) of copper as TSV s on a 150 mm -wafers. That process was relatively simple, using larger via sizes and small aspect ratios of via diameter to via depth, and a via last type integration [94] (the TSV is formed from the backside of the wafer after the front-side process is finished). From there, the industry has transitioned to backside imagers ( BSI ) and then to hybrid 3D -stacked BSI with the introduction by Sony of via-middle type integration ( TSV formation is inserted after FEOL but before BEOL Cu interconnect) using a full filled TSV . The evolution throughout history is represented at the figure 46 , achieving Sony with the latest inventions a more efficient utilization of the silicon space by occupying 90 %of it with the pixel area. The die Master Thesis 88 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 96/158   3.2.b.I. Classification During the last years, different types of TSV s fabrication processes have been proposed. The first distinction can be done in terms of the lay-out or shape of the via, whereas the second distinguishes where in the process the TSV is done, not only determining the manufacturing process but also the process requirements. For the first classification, each TSV type has associated a material choice, thus fixing the properties and also the application of those vias, each of them having benefits but also technological challenges. One can distinguish different shapes: ❖Regular (square or cylindrical) TSV : the most common shape is cylindrical, using metals such as Cu , plated Cu , tungsten or doped Polysilicon ( poly-Si ), thus resulting in a wide range of resistivities [31] . The design is depicted at the figure 51 , being simpler than other types, having a dielectric surrounding the metal. As main challenges, the regular TSV s have the substrate noise and the thermo-mechanical stress. An advantage of the square shape with regards to the cylindrical one is that the first one allows more uniform insulation layer, thus having a higher breakdown voltage [117] . Figure 51: Regular TSV top and side view [31] . ❖Annular TSV : it consists of a polymer-filled core surrounded by a metallic annulus (usually copper), which is separated from the substrate by means of a dielectric layer (conventionally SiO 2 ). The figure 52 illustrates the differences versus the previous type: the polymer is now replacing the metal at the via core, whereas the inclusion of the last one is sandwiched between the polymer and dielectric. The invention of this type of TSV was to overcome manufacturing challenges of cylindrical TSV s[118] , thus using a simple manufacturing process at a lower cost. Another advantage is the conductivity: to achieve the same conductivity than a regular TSV , the required cross sectional area is smaller, thus resulting in improved thermomechanical stability [119] . Master Thesis 95 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 97/158   Figure 52: Annular TSV top and side view [31] . ❖Tapered TSV : it is made of a metal and a dielectric, like the regular TSV s. However, their side view (see figure 53 for reference) has a different cross section. Introduced by MIT Lincoln Laboratory, this type of TSV s are built in SOI technology [120] . As advantages, they do not require insulation, have lower capacitance and a simpler fabrication process [121] than the resular TSV s. On the other hand, this type of vias are more resistive when compared to a non-tapered one with the same maximal cross sectional area. The control of tapering is also more difficult to be controlled: excessive tapering can lead to V- shaped vias, the via slope process has to be optimized [122] and a specific interconnect pitch control is required at the bottom side of the tapered TSV s. Figure 53: Tapered TSV top and side view [31] . ❖Coaxial TSV : first proposed by Sparks [123] , this type of vias have the same structure than a regular TSV but with an added surrounding metal layer, as illustrated in figure 54 . On that way, they have the main core (inner metal, used for signal transmission) surrounded by an annulus of outer metal (connected to the circuit ground to provide shielding) and the last layer of dielectric. Although few processes have been proposed to fabricate coaxial TSV s[124, 125, 126] , no mature technology currently exists to fabricate them, having in addition disadvantages such as electrical coupling and critical substrate noise in neighboring active devices [127] due to the extensive dielectric liner. Master Thesis 96 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 98/158   Figure 54: Coaxial TSV top and side view [31] . The previous list allowed the reader to understand the different types of TSV s in terms of their layout and composition. However, it is even more important the classification of table 6 depending on when, in the overall manufacturing process, the TSV s are manufactured, since that is determining the manufacturing line layout, the process constraints and even the physical place where the TSV s is done: there are alternatives of performing all the 3D- integration and then send out the circuit to an external foundry which creates only the TSV s. Table 6: TSVs fabrication processes classification [31] . To understand the “timing” of the TSV s within the foundry, let us understand the context of the vias fabrication. The IC fabrication from a helicopter view can be divided into two major stages: the front-end-of-line ( FEOL ) processes and the back-end-of-line ( BEOL ) steps. The first one, the FEOL , include the processing steps preceding the first metal layer, whereas the rest of the methods lie in the BEOL . The TSV s classification is done bearing in mind if the vias manufacturing is done prior to the FEOL ( TSV -first), in between FEOL and BEOL ( TSV -middle) or after BEOL ( TSV -last). For the third option, there is a distinction between backside TSV -last and front-side TSV -last, whereas the backside one is the more common approach. Throughout the last years, the three (or four considering the distinction between the TSV -last options) approaches have been used, but the viewpoint of the 3D -community for most commercial applications is to use the TSV -middle [114] . Master Thesis 97 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 99/158  ❖TSV -first : this is the simplest process, consisting on fabricating the TSV s in the bulk substrate before any devices or interconnect layers are formed [128] . The necessary steps are sketched in figure 55 . This approach does not require any backside lithography and it is compatible with all the FEOL -processes, including high temperature thermal oxidation, therefore can be used to deposit TSV insulation (under the condition that the TSV conducting material is poly-Si ). Being a highly reliable (electrically and mechanically) process, those types of vias can be formed with densities larger than 100000 per cm 2and aspect ratios of 25:1 [129] . However, since the limitation of only using the poly-Si as the TSV conductor, and the inherent limitations such as the via resistance, the TSV -first approach is no longer viewed as a viable option for 3D - IC manufacturing [114] . Figure 55: TSV-first approach process flow [114] . ❖TSV -middle : at this approach whose steps are depicted in the figure 56 , the vias are made at the IC fabrication facility (or at the own foundry for large IC foundries) after the FEOL active device layers have been created, and prior to the BEOL interconnect wiring layers. With regards to the materials used, at this approach the vias are conventionally fabricated with Cu or Wdeposited by Chemical Vapor Deposition ( CVP ) or Electric Discharge ( ED )[129] . To build them up, the TSV s are initially formed as blind vias, being revealed later in the process from the back during wafer thinning to allow the backside interconnection and routing. Typically solder bumps or microbumps are added for interconnecting to another tier or substrate. One advantage of the TSV -middle is the lowest consumption of real estate, since they can be made small while with high accuracy, being the BEOL metal layers routed over the TSV s[114] . Another advantage, making this approach the most used nowadays, is the compatibility with the rest of processes (wafer thinning, TSV reveal , etc.), since a lot of progress has been recently done in temporary carrier wafer bonding. Master Thesis 98 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 100/158   Figure 56: TSV-middle approach process flow [114] . ❖TSV -last : this approach allows the whole FEOL to be finished, and then build the vias at anytime during and after BEOL [130, 131] , being the steps illustrated in figure 57 . As mentioned before, the TSV -last approach has two different possibilities, depending on the side where the vias are formed: either at the back or at the front side. Figure 57: TSV-last approach process flow [114] . ➢Backside TSV -last : on this approach the vias are formed from the backside of the substrate after the wafer has been thinned, landing the vias on the front-side metal. The figure 58 illustrates the overall process flows: a handle-wafer is attached to the front side, and the TSV s are connected to the lower metal layers ( M 1or M 2 ) of the die to avoid etching through the higher metal layers. This approach has been adopted for producing CMOS image sensors (used at mobile devices), since they use relative low aspect ratio periphery TSV s[132, 133] , often with sloped sidewalls and a conformal metallization layer (unfilled TSV s). However, the backside TSV -last approach has numeral drawbacks: first of all, this process requires a low temperature TSV insulation technique to minimize thermal effects on already fabricated devices and interconnect [31] . Secondly, it requires back-to-front lithography alignment capability. Not only that extra process is needed, but also a specialized etch step -sometimes called a “bottom-clear etch”- is required to reopen the metal at the base of the via, while not removing the deposited insulator from the TSV sidewalls [114] . Furthermore, still some other manufacturing challenges have to be mastered, such as wafer-thinning and handling, and properly opening the insulation at the vias base to make reliable electrical connections. Last, but not least disadvantage of this Master Thesis 99 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 101/158  approach, is that the metal surface can be affected by exposure of the numeral etching plasmas, thus being difficult to restore using standard sputter etch techniques since it is as the bottom of a deep via. Having all the highlighted issues in mind, this process flow is unlikely to see widespread use for higher density, higher aspect ratio TSV applications [114] . Figure 58: Backside TSV-last process flow [114] . ➢Frontside TSV -last : in this approach, the blind vias are formed from the front of the wafer, and then the rest of the process flow is similar to the TSV -middle methodology, including the backside TSV reveal and metallization. The complete process flow is depicted in figure 59 for reference. This approach is mostly used for defense and aerospace applications as well as for advanced medical imaging, since those sectors need a high-performance TSV caring less about the cost and product volumes. As concern -apart from the pricethis approach needs the wafers to be designed and fabricated with “ TSV exclusion” areas, free of metal and active circuitry. On those areas, the TSV s can be etched through the Interlayer Dielectric ( ILD ) stack and the Si layer, without obstructing the metal or damaging the active circuitry [31] . Master Thesis 100 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 102/158  Figure 59: Frontside TSV-last process flow [114] . Master Thesis 101 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 103/158   3.2.b.II. Process description The different steps required to form a TSV depends upon the approach taken by the factory, i.e. there would be some differences in the flowchart (and/or at the process parameters/materials) if aTSV -first would be chosen instead of a TSV -last. Due to the fact that the most common approach nowadays is the TSV -middle, and 3D took the advantage over the 2.5D -interposers, that combination would be used for the process steps description at this section . It is beyond the scope of this thesis to really deep into every single process, but it is more oriented to give the reader an overall understanding of the necessary steps to achieve the vias formation. Each process step will be characterized, mentioning also the requirements and the main challenges to get the TSV in mass production. 1) TSV etching/patterning: the process is performed by Deep Reactive Ion Etching ( DRIE ), which was introduced by Bosch in the mid- 1990s and is widely used in MEMS fabrication [134] . The technique alternates steps of etching and passivation to enable etching of deep features in Si with vertical sidewalls, thus providing high selectivity to the photoresist or the SiO 2mask layers. To achieve that, an Inductively Coupled Plasma ( ICP ) source is used, firstly using SF 6as element source to etch in the Si , and later using C 4 F 8for the sidewall passivation. The process is cyclical, where the four steps sketched in figure 60 are repeated: in each etching step, a small amount of Si is removed, and then the passivation layer is applied over all of the surfaces. After that, the passivation is removed from the bottom of the feature, allowing the Si etch to continue downward, but still remaining on the sidewall and protecting it from further etching. Figure 60: DRIE process steps [135] . Master Thesis 102 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 104/158   The process repetition generates a easy-to-recognize pattern which results in a vertical feature sidewall, made up of a series of small ridges, also known as “scallops”. Since it is required to etch small vias with high throughput and minimal sidewall roughness, the trends today go into the direction of reducing the scallops to enable sufficient coverage of TSV insulation and seed metal in high aspect ratio vias [31] . The advancements in plasma source has allowed to shorten the process cycles, appearing at the market alternatives which are “scallop-free”. The figure 61 plots both structures: with and without scallops. Figure 61: DRIE features etched in Si [31] . (a) Top view of TSV with sidewall scallops. (b) Cross section of scallops in Si trench. (c) “Scallop-free” TSV etch. 2) TSV insulation: this step is accomplished by deposition of a highly conformal SiO 2 layer. Three processes are needed for insulation, as depicted at figure 62 : firstly an etching is performed on the top surface, followed by the SiO 2layer deposition which later will be etched away at the TSV itself. For the deposition, the most conventional process is Subatmospheric Chemical Vapor Deposition ( SACVD ) using O 3 /TEOS or, when lower temperatures are required, the used of Plasma-Enhanced Chemical Vapor Deposition ( PECVD ) is typically used. Figure 62: TSV insulation process steps. Source: own, based on [136] . Master Thesis 103 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 105/158  Since the layer is deposited after the FEOL (to bear in mind that this description is for TSV -middle approach and also in this case would be applicable for TSV -last, but not for TSV -first), the deposition temperature has to be limited to a range of 400 ºC maximum. Achieving conformal insulator coverage can be a challenge without using high-temperatures, specially for high aspect ratio vias, vertical profiles and sidewall roughness. Other requirement for the TSV insulator films is to have suitable electrical insulation properties, such as dielectric constant, leakage current or breakdown voltage. 3) TSV metallization : after the via has been isolated, the metal layer is deposited (see figure 63 for reference). The most common approaches nowadays are based on a “bottom-up” growth process Electrochemically Deposited ( ECD ) of copper [135 ,137] , although CVD of tungsten is still used for small-diameter holes or annular vias [31] . For the Cu metallization schemes, it is necessary to deposit a thin Cu seed layer prior to the metallization, typically by Ionized Metal Plasma ( IMP ) sputtering, achieving continuous coverage along the via walls to enable uniform and void-free fill deposition. Furthermore for this process approach, after the Cu metallization, it is needed to add a barrier metal between the copper and the SiO 2layers, typically being TiN or TaN deposited by IMP sputtering or Metallo-Organic ( MO )CVD processes [138] . An alternative appeared recently at the market consisting of using MOCVD Cu , since it can produce nearly 100 % conformal deposition in high aspect ratio features and can be used to fill small TSV s [139, 140] . However, it is not very practical for using at large vias due to limited deposition rates, having the process a high cost and being the throughput too low for a much wider adoption by the semiconductor industry. Figure 63: Typical TSV formation process steps. Metallization comes after the isolation [141] . Master Thesis 104 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 112/158   Another concern is the issue highlighted in figure 69 : the Cu protrusion effect, which arises at the TSV anneal process, consisting in having hillocks formed during the heating process, thus resulting in a permanent surface topography [153] , creating a potential for thermomechanical failures in subsequent layers. To address this issue, the solution is to limitate the via size, optimize the ECD chemistries and perform a stabilization anneal prior to building up additional layers of metal and dielectric over the TSV s [31] . Figure 69: SEM images showing Cu protrusion for different annealing conditions [154] . (a) 25ºC. (b) 250 ºC. (c) 300 ºC. (d) 350 ºC. (e) 400 ºC. (f) 450 ºC. To mention as well as major reliability issue the plating voids, since they can trap chemicals which can lead to contamination or corrosion. To eliminate their effect it is necessary to use optimal ECD techniques and process monitoring, ideally using non-destructive void-detection methods. The last two reliability concerns are the insulator integrity and the interconnect degradation. The first one can makes the current to leak as a consequence of insufficient sidewall coverage, thus potentially damaging the quality in further steps such as TSV reveal or die bonding. For the interconnect degradation, the concern is about the electromigration, which have to be addressed through proper materials selection and process controls. Master Thesis 111 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 113/158 Even if good progress has been done in the last year at understanding the TSV formation process, still the yield and reliability issues make the cost too high to continue scaling the 3D -circuits. Therefore, a better know-how of the process will allow the integrated circuits using three dimensional approaches to become more competitive. Master Thesis 112 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 114/158  3.2.c. Bonding The bonding process is the key to enable technology for 3D -integration: it glues multiple functional IC chips vertically, thus providing mechanical, thermal, electrical and optical connections between the chips and the wafers permanently. The process consists of attaching two substrate materials, either directly or indirectly. The first section will explain the different types of bonding that exists nowadays for the 3D -integration, also explaining the necessary steps with some real applications. Secondly, the process requirements will be described. The limitations in terms of process applies to the chosen material, and vice versa, therefore an excellent know-how of the material features is needed to clearly understand compatibility between them and with different process techniques. Following the analogy with the TSV section , the last point consists of an overview of the process quality : the main reliability concerns will be described, showing with real examples which are the current problems in the industry, and how the fabs come up with different solutions to get a continuous improvement in the process. Master Thesis 113 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 115/158   3.2.c.I. Classification and direct bonding process descriptio n Depending on the type of contact between the materials, one classifies the process in three different bonding types, differentiated at figure 70: ❖Direct bonding : when the attachment is done between two similar or dissimilar materials without using anything in between them. Examples of used materials are the junction Si-Si hydrophobic (with identical or different properties, e.g. crystal orientation and impurity) [155] ,Si–SiO 2bonding [156] , Plasma-Enhanced Chemical Vapor Deposition ( PECVD )SiO 2 –SiO 2bonding [120] ,Cu–Cu bonding (or metal bonding in general) [157, 158] and benzocyclobutene ( BCB ) to BCB bonding (or adhesive bonding in general) [159] . ❖Indirect bonding : it uses an intermediate material to link the two surfaces. Examples of indirect bonding includes Si-Si hydrophilic bonding (notice it is no longer hydrophobic) where a thin oxide layer is formed at the bonding interface [160] ,BCB and a variety of polymers or polyimides to bond two other materials (such as Si chips or wafers [159] ), metal layer (such a thin Ti film) to bond two Si wafers [161] and intermetallic compounds ( IMC s) to bond two chips or wafers [162, 163] . ❖Hybrid bonding : there is an added material in one of the bonding surface. It is mainly used to form electrical connections between two materials, with non-metal bonding to provide additional thermal/mechanical support [164] . The metal patterns are often formed within an insulator matrix on each side of the bonding surface, such as copper pads within an oxide matrix ( Cu –oxide) [165] or a BCB matrix ( Cu–BCB )[166] , microbumps within an underfill [167] . Other polymers may be used as the insulator matrix material. Figure 70: Major 3D-bonding approaches: direct, indirect and hybrid bonding [102] . The more extended use of direct bonding, explained by the cost saving without using any extra material, makes that approach the one selected to be discussed in this thesis. From all the available literature, two interesting applications were chosen in order for the reader to visually understand that bonding itself occupies only a part of the whole 3D -integration. The first one is represented in figure 71 , consisting on direct bonding of Silicon-On-Insulator ( SOI ) layers using Au electrodes to connect with SiO 2 [102] . Master Thesis 114 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 116/158   Figure 71: Direct bonding between Au electrodes into SiO 2 . (a): Top view. (b): Cross section [102] . The process consists of various steps, as the figure 72 illustrates: a) Some FET s are formed on a Fully Depleted Silicon-On-Insulator ( FDSOI ) wafer and an Al wiring layer is created. b) After a SiO 2intermediate layer is patterned, an Au thin layer is electroplated in the top surface. c) Damascene process by Chemical-Mechanical Polishing ( CMP ) is applied to form embedded Au electrodes, removing the Au thin layer where not needed. d) Chips are diced into a 20 mm square size, and the surface is activated by Ar and O 2 plasma. e) The direct bonding is performed at 200 degrees Celsius. Figure 72: Process flow of the 3D-Direct Bonding using Au electrodes to connect with SiO 2 [168] . Master Thesis 115 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 117/158  The result is to have the Au electrodes embedded into the SiO 2surfaces after CMP , as can be shown in both the top view and the cross section of the bonding interface (figure 71) . The second example ( figure 73 ) is the so-called Direct Bond Interface ( DBI ), which uses oxide bonding to solder planarized wafers with embedded metal contacts [169] . This technique uses standard fab processes at low temperatures (for both the initial bonding and the subsequent annealing) and can be utilised for W2W or C2W bonding. Figure 73: Direct Bonding Interface (DBI) for a sensor [169] . The whole circuit is not only made of this DBI process, but also uses typical direct bondinge and TSV s. The overall packaging manufacturing process is shown at figure 74 , and could be described as follows: 1) W2W bonding. 2) Exposure of the TSV s and patterning in the top of the Al side. 3) Oxide bonding the previous subassembly with a so-called handle wafer. 4) Exposure of the TSV s at the sensor side and patterning the DBI structures. 5) Dicing of the chip. 6) DBI between the chip and the sensor wafer. 7) Grinding and etching for top connection exposure. Master Thesis 116 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 118/158  Figure 74: Sensor manufacturing by using direct bonding, TSVs and DBI [169] . Master Thesis 117 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 119/158    3.2.c.II. Process requirements-materials One does not have to forget that the bonding is only one of the processes of the 3D -integration, therefore the frond-end-of-line ( FEOL ) and back-end-of-line ( BEOL ) processes have to be taken into account with regard to the bonding conditions to be used. For that reason, numeral requirements are included for the bonding, so that the overall process quality is not being degraded: ❖Temperature lower than 400 degrees Celsius to be compatible with BEOL , thus using bonding materials which are relatively thin and of low stress. ❖High thermal and mechanical stability of the bonding interface over the ranges of BEOL and packaging processing conditions. The heat distribution has to be carefully controlled in order to avoid defects at bonding or while thermo-compressing the wafer [97] . ❖No outgassing -or having outgassing channels- to avoid voids formation during the bonding process. ❖Seamless bonding interface having high bond strength to prevent delamination. ❖Angstrom-scale (10 -10 m ) flatness to achieve strong chemical bonds. This feature is especially important for rigid bonding surfaces such as Si-Si or SiO 2 -SiO 2bonding [156, 160] , being not that relevant for soft bonding surfaces such as Cu-Cu or BCB-BCB [159, 170] . Nevertheless, for rigid bonding surfaces there are some solutions at the market: using surface deformation (by affixing the wafer to a wafer holder) [97] , interface diffusion or an intermediate material. The figure 75 compares the impact at rigid bonding without and with an intermediate material. Figure 75: Impact of bonding surfaces-roughness [96] . (a): Rigid bonding surfaces preventing bonding. (b): Rigid bonding surfaces using an intermediate material to allow bonding. Master Thesis 118 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 120/158 ❖Diffusion of massive atoms across the bonding interface during bonding or post-bond annealing. ❖A surface extremely clean, i.e. totally free of particles and defects. This is extremely important for rigid bonding surfaces, whereas soft bonding surfaces ( e.g. Cu-Cu or BCB-BCB bonding) can tolerate some level of contamination [156] . For all the previous requirements , some materials combination performs better than others. However, on top of the previous conditions, depending on the applications some extra requirements can be added. For instance, some circuits would imply more focus on the thermal or electrical connections, whereas others would require more mechanical or optical connections between the functional chips or wafers or even a temporary mechanical support for wafer thinning. Nevertheless, the preferred combination of materials nowadays can be summarized as follows: ❖Cu - Cu and BCB - BCB bonding, as well as PECVD oxide bonding are said [171] to satisfy all the requirements. ❖The Cu-Cu bonding at temperatures higher than 350 degrees Celsius leads to high bonding strength, since the copper diffusion across the bonding interface with Cu grain regrowth [96] . In addition to that, using further thermal processes may enhance the bonding strength with more copper interdiffusion at the bonding interface [171] . ❖BCB-BCB reflows at 180 degrees Celsius and forms cross-link networks rapidly at 250 ºC without outgassing, leading to very strong bonds, which can be further enhanced by thermal processes up to 400 ºC [172] . ❖PECVD oxide, despite the fact that requires better surface flatness and cleanliness compared to the previous methods, but with Si-OH bonds at thermal annealing at 275 ºC creates strong Si-O-Si bonds, but releasing a small amount of H 2 Owhich can easily diffuse in oxide [173] . ❖Cu-Sn can work well for CoC and CoW bonding if conducted in air atmosphere [174] , thus being called as Solid-Liquid Interdiffusion ( SLID ) or Intermetallic Compound ( IMC ) bonding. The substrates to be bonded are deposited in layers at a temperature range between 240 and 270 degrees Celsius, being the deposited tin completely transformed into the Cu 3 Sn intermetallic compound. It is important to use the appropriate film thicknesses, so that the tin is consumed and the solidification takes place within few minutes. The SLID technology has the advantage of forming simultaneously the mechanical and the electrical interconnects ( i.e. no post-processing is required) but the materials might melt during the bonding process [96] . An example of SLID bonding and TSV s is provided at figure 76 . Master Thesis 119 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 121/158  Figure 76: Combination of SLID bonding process and TSVs [175] . ❖Another good combination is the Au-In using eutectic bonding at low temperatures. However, it is very difficult to control the lateral size of the bonding pad and the vertical height of the bonding bump, therefore requiring large bond pads. One important reliability concern is that after bonding the solder joints are usually brittle [174] . Master Thesis 120 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 128/158    3.2.d.I. Tilted patterns by inclined/rotated lithography This first approach is an intermediate step between the conventional lithography and the 3D -lithography that one can imagine. In conventional lithography, the mask and the resist form an angle of 90 degrees versus the illumination source (the excimer laser). The light on this way is shadowed by the reticle, who is in charge of making the binary-contrast lithography patterns. However, if the reticle and the resist at the wafer are both being tilted (see figure 82 for reference) with respect to the beam by tilting the stage, inclined structures can be produced [187] . Figure 82: Tilted patterning by inclined lithography [188] . By these means, oblique cylinders, embedded channels, bridges, V -grooves, and truncated cones with aspect ratios greater than 4 times have been fabricated using 100 μm thick SU-8 layers and a conventional UV mask aligner [187] , as the figure 83 illustrates. Figure 83: Tilted pillars by inclined lithography [187] . Scale bar corresponds to 100 μm. Master Thesis 127 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 129/158   Even more complicated 3D -structures can be generated using multiple inclined UV exposures along different axes [189, 190] . Another more advanced option would be to combine tilted exposure with conventional photolithography to create asymmetric pillars with vertical and inclined sidewalls [191] , being represented at figure 84 . Figure 84: Asymmetric pillars with aspect ratio=10 by combining X-ray vertical and tilted exposure [191] . So far only the tilting has been described. However, there is another enhanced option showed figure 85 , which is to tilt and simultaneously rotate the photomask and the wafer. Figure 85: Tilted and rotated patterning by inclined lithography [188] . On that way, also tapered structured with non-vertical sidewalls can be generated [192] , such as the ones in figure 86 . Those structures are very useful when a master for subsequent replications are needed, since they provide a draft angle and facilitate a posterior process called demoulding. A combination of multiple X- ray exposures, tilting, and rotation with PMMA reticles can be achieved to pattern tilted and crossed features [193, 194, 195] . Master Thesis 128 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 130/158   Figure 86: Tapered structures by tilted and rotated UV exposure [187] . Scale bar corresponds to 50 μm. The process parameters for exposure have to be changed, because otherwise the incident light would be reflected by the photoresist on the wafer, since the energy of the reflected UV light is too low to initiate cross-linking of the resist. Therefore, the dose used to expose (or the exposure time) has to be increased, or reflective substrates have to be used, so that cross-linking is initiated [188] . The figure 87 compares the structures obtained after single tilted exposure with a normal silicon wafer (left hand side) and with reflective aluminium-coated silicon wafer (right hand side), where the irradiation conditions remain the same but not the printed pattern. Figure 87: Structures fabricated by tilted UV on nonreflective (silicon, left hand side), and reflective (aluminum-coated silicon, right hand side) substrates [187] . Scale bar corresponds to 100 μm. Master Thesis 129 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 131/158   3.2.d.II. Patterns by modulated exposure Instead of tilting and rotating the reticle and the wafer, numeral 3D -approaches are under investigation to generate multilevel structures from single resist layers. On that way, it would avoid cycle time since no (or few) multiple exposures would be required. To do so, special masks and projection optics are needed, needing the photolithography tool to be able to modulate the exposure dose on the resist. On that way, multiple depths of exposure photoresist would be achieved and, consequently, different heights of the photoresist structure would remain after wafer development. One can make an analogy to having incident lights with different energies, therefore some of the light would only trespass the first reticle film layer, whereas some other light would continue its path, therefore multiple layers patterning may be achieved with one single exposure. Different options exist: ❖The “gray scale” lithography : it uses special reticles which modulate the light intensity in accordance to their gray levels. Two different types of masks exist: the first one, the halftone chrome masks, are binary chrome masks with gray levels simulated by different densities of opaque pixels on a transparent background. The second option is the High-Energy Beam-Sensitive ( HEBS ) glass masks, which are fabricated by exposing this glass to controlled doses of a high-energy electron beam, causing the reduction of silver ions in the glass [188] . The areas of the mask with high concentrations of reduced silver ions correspond to high levels of gray shading. This method has been used to produce 10 μm thick grid structures on the top of 15-100 μm pillars [196] , which can be seen at the figure 88 . Figure 88: Suspended 10 μm thick grid structures made by gray scale lithography [196] . Master Thesis 130 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 132/158 ❖Proximity lithography : it consists on inducing diffraction patterns from a conventional chrome-on-glass mask by leaving a controlled air gap between the resist film and the mask [197] . This type of lithography was also used at the beginning of optical lithography (see figure 5 for reference), but in this case the use is enhanced for the 3D -patterns. The diffraction process creates a modulated intensity pattern across the surface of the waver, something similar to the PSM . The intensity pattern would depend upon the mask features (size, geometry and spacing) and the gap between the mask and the resist layer. ❖Other ways of generating ranges of exposure levels include microlens arrays [198] or conformable phase-shift edge masks [199, 200] . This last option, the phase-shift edge masks, uses the PSM technique with the help of a topographical relief at the mask. The geometry of the intensity pattern would depend not only upon the design (depth and layout of the relief structures and refraction index) of the mask, but also on the exposure light features (wavelength, coherence and polarization). Master Thesis 131 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 133/158    3.2.d.III. Periodic 3D -patterns by holographic lithography The holographic lithography , also known as interference lithography ( IL ), is based on the interferences produced by multiple coherent laser beams, which form a periodic and sinusoidal intensity pattern in space [201] , as the figure 89 illustrates The main difference of this type of lithography is that not only one excimer lasers is used, but the beams of many of them are used to produce the interference between the light rays. Figure 89: Interference lithography with two laser beams [201] . The lasers expose a photosensitive material, thus creating periodic structures of various symmetries after development of the wafer. The pattern is periodic, whose period (to bear in mind that it is a spatial periodicity and not in terms of time) is determined by the light wavelength ( λ) and the angle of intersection of the beams ( Φ ): According to the previous equation , the spatial resolution that can be achieved with the interference lithography far exceeds that of conventional projection lithography using the same irradiation wavelength (typically λ /4) [188] . The depth of focus is not only determined by the angle of intersection, but also by the beam diameter and the intensity profile, being typically so large that it is considered to be infinite. By adjusting the number, amplitude, phase, wave vector and polarization of the interfering beams, different symmetry patterns can be generated. Take for instance the surface gratings produced by three beams while overlaying two sequential exposures with an angle of 90 degrees [202, 203] . Another examples [204, 205, 206] are the 3D -periodic structures fabricated by using additional beams in a single exposure -or overlaying multiple exposuresas the ones at figure 90 . Different shapes like a spiral microstructure are possible, by using six equally spaced circumpolar linear polarized side beams and a circular polarized central beam, whose pitch and separation of the spirals was varied by changing the angle between the side beam and the central beam [207] . Master Thesis 132 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 134/158  Figure 90: Chiral 3D-structures (spirals) produced by holographic lithography [207] . Scale bar corresponds to 1 μm. Interference Lithography offers numerous advantages over the previously discussed 3D -lithographic strategies: it is both maskless and lense-less, thus minimizing cost and eliminating the optical aberrations associated with complex lens systems. As drawback, holographic lithography is limited to the fabrication of periodic structures and combinations thereof [208] . Master Thesis 133 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 135/158   3.2.d.IV. Built-in lens mask lithography This novel technique integrates the reticle directly at the lens, therefore no more lens is needed. The figure 91 sketches the concept: the pattern is already built-into the lens mark, having a complex optical transmittance g* , where the incident coherent light is focused on the focal plane for arbitrary shaped pattern [209] . Figure 91: Basic concept of the built-in lens mask having complex optical transmittance g* [209] . At the previous figure 91 it is shown a single layer but, in reality, the built-in lens mask consists of multiple layers which will be able to provide the 3D -integration at wafer level, with a multi-level structure superpositioning pre-designed patterns in different focal planes. To eliminate the interference between layers, phases are shifted in each layer, and the complex amplitudes are superposed to design the built-in lens mask for seed patterns in voluntary focal depths [209] , thus resulting the overall complex transmittance the sum of the complex transmittance per layer. A breakdown of the focal planes is depicted at figure 92 . Master Thesis 134 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 136/158  Figure 92: 3-dimensional imaging by superposing complex amplitudes of the seed patterns in various focal planes [209] . The deep focal length imaging was confirmed for this technique [210] . It has been reported [209] its effectiveness by both computational lithography and experimental works using 5 seed layers, an illumination light of 365 nm wavelength ( i -line of Mercury), a 1.0 μm seed pattern and 60 μm as focal depth. With the help of the phase shifted superposition, the 3-dimensional projection images were successfully obtained including parallel tubes in spaces, T- shaped connection of tubes and tilted tubes, which may result in essential components for 3D -Integrated Circuits. The figure 93 depicts the result for the pattern " S " by that technique. Master Thesis 135 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 137/158  Figure 93: 3-dimensional imaging of a pattern “S” by computational lithography [209] . Master Thesis 136 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 144/158 This page intentionally left blank Master Thesis 143 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 145/158  5. Conclusions The Moore’s law is not only the analysis of the electronics evolution, but also the driving force to guide new breakthroughs to continue scaling the transistor size. Some years ago, no one would have bet to have the current technology: smartphones able to fold, biometric identification, smart wearables, 3D -printing, domotics or Artificial Intelligence, among others. But the reality is that technology continues to surprise us with new ways of re-inventing the way to interact with the environment, making easier for the user to gather information to improve his/her quality of life -that is how they sell it. Even what we think that nowadays is normal, in a couple of years will be obsolete, and our pioneer technology will be considered primitive. The reader has been driven through the evolution of the photolithography, understanding the process behind to better comprehend how it has evolved thanks to improvements with respect to physics and optics. What some years ago, the DUV , was considered the innovation, has been improved by the immersion lithography, and after that by the EUV . But one does not have to forget that all new technologies need a lot of validation to get costwise effective. There are even technologies who were thought to be the future but suddenly disappeared: would you remember the Blackberry phones which was trendy for some years in the 2000s? They bet for one solution which resulted to not appeal to the market (versus the LCD -smartphones), thus becoming bankrupt after some years. The bottom line is here: we are all impressed about the news of releasing a phone with a microprocessor built in 5 nm technology-node, how good and fast must be, but the cost and the time to market is very important too, not talking about the marketing. So the conclusion is: even if we are delighted by the capabilities of this new technologies -e.g. EUV -, what is currently providing money to the market is the DUV , both wet and dry tools. In five years, it is expected that the trends will be leading to EUV , where the majority of the foundries will adopt those systems but, for the moment, the driven force -the one which sustains the microelectronics market and the preference for the consumers in terms of used devicesis the safe approach, the DUV . And in parallel there is that 3D -integration, also fascinating us with the potential of improving efficiency while enhancing the systems. What is -literally- the price for that? It is true that some market applications, such as the NAND memories, are increasingly adopting the 3D -approach to get it into the market. For that concrete example, the whole industry is moving to the 3D -integration, even the photolithography tool manufacturers are investing in that -or at least trying to keep up with the metrology systems for those applications. Furthermore, the image sensors segment have showed a clear increase in the 3D adoption by allowing to add some processing functions keeping the same pixel size. But for the rest, what is the real implementation of the 3D -circuits? For the moment, almost null, and the reason being is rather simple: money. 3D -integration is not yet costwise efficient, the yield and reliability issues which has been highlighted during this thesis makes the foundries not able to get it into HVM making a Master Thesis 144 6/26/2019 TFG_Lithography_&_3D_Integration_final_version_Miguel_Gaitero - Google Docs https://docs.google.com/document/d/1b0gG5g2YyYKNLAsArbpV-xxvgGvkz845NQrurjyQskI/edit#bookmark=id.w7xr47g454gc 146/158 profit from that. What will happen in a couple of years, it is still unknown but, roughly speaking, the 3D -integration is not a serious alternative for the moment to the conventional lithography. Thinking about the 3D -photolithography as doable alternative to integrate both advancements, seems to me something to far away. It is clear that there are some results, do not get my wrong, but one thing is to manufacture a prototype and another call is to make money in a mass production-manner. It sounds as all those new materials -such as the carbon nanotubes- or technologies -quantum cellswith spectacular results, which are all said to be the future, but only the intrepid investors are going to put some money on that, not still affordable -or accessible- to the general public. Bearing in mind all the above arguments, in my opinion nowadays it is clear that the mainstream is continuing using DUV , increasingly the market share for wet tools since they have been demonstrated to improve the patterning size in a costly-effective way. EUV is promising, true, but so far only manufactured by one supplier, which is investing a lot of money on that. Nevertheless, also influenced by my subjective experience of currently being working for that supplier, I am convinced that the EUV is the way to go for the industry during some years. The major foundries are convinced on that, as well as ASML collaborators, and the HVM for EUV is now there: it is just a matter of years to get it more mature to dominate the market versus the DUV . With respect to the 3D -integration, I admit there are some market lines moving quickly to that direction, and I am sure that they well know why: the performance improvement must have been demonstrated expecting to make money from that. But do not forget this is only some products where the 3D -integration may fit better: it is more an alternative for new products -with enhanced featuresthan a sustitutive. With that I mean: do not imagine a microprocessor for the new iPhone built with 3D -Integrated Circuits, do imagine a microprocessor built with the most powerful -and costly-efficient demonstrated- EUV photolithography tool. But of course, there are some facts and opinions in the previous quote. Do remember what happened to Blackberry for being focus in one application, or how Microsoft was laughing at Apple when they proposed their disruptive concept of phones. The future looks fascinating: new materials, new technologies and new devices, and everything comes in a world which demands more and more technology to the daily lives. What will the human being be able to achieve? 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