Reducing the nonlinearity and harmonic distortion in FD-SOI CMOS current-starved inverters and VCROs

Int. J. Electron. Commun. (AEÜ) 142 (2021) 153992 Available online 6 October 2021 1434-8411/© 2021 The Authors. Published by Elsevier GmbH. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Regular paper Reducing the nonlinearity and harmonic distortion in FD-SOI CMOS current-starved inverters and VCROs Promise I. Okorie, Javad Ahmadi-Farsani, Jos´ e M. de la Rosa * , 1 Institute of Microelectronics of Seville, IMSE-CNM (CSIC/University of Seville), C/ Am´ erico Vespucio 28, 41092 Sevilla, Spain ARTICLE INFO Keywords: Body Effect Fully-Deplected Silicon-on-Insultator (FD-SOI) Bulk-input voltage-controlled ring oscillators Harmonic Distortion ABSTRACT This paper demonstrates experimentally how to reduce the nonlinearity of some analog and mixed-signal circuits by using the enhanced body effect provided by Fully-Depleted Silicon on Insulator (FD-SOI) CMOS technology. A current-starved CMOS inverter and a Voltage-Controlled Ring Oscillator (VCRO) are considered as case studies. The inverter is configured as a simple amplifier stage in which the harmonic distortion can be reduced and even removed by the combined action of the control voltages applied at the gate and bulk terminals of the currentsource transistors. This current-starved inverter is used as the basic building block of a VCRO, where a more linear voltage-to-frequency characteristic can be achieved if the bulk terminal is used as the control voltage of the oscillator. The circuits under study have been designed and fabricated in a 28-nm FD-SOI technology and experimental results are shown to validate the presented approach. 1. Introduction As CMOS technology is evolving towards the nanoscale, there are a number of design challenges that arise to design Analog and Mixed- Signal (AMS) circuits. One of the most limiting factors is the reduction of supply voltages below 1 V, which makes it difficult to design such circuits while keeping the required Dynamic Range (DR) with low power consumption and high linearity. Among the technology alternatives, those based on Fully Depleted (FD) devices are becoming mainstream processes, namely: Fin-FET and FD Silicon-On-Insulator (FD-SOI). The former is widely used nowadays as mainstream for Digital Signal Processing (DSP) [1,2], while the latter is featuring very promising results to design AMS/RF circuits and systems where ultra-low power consumption is a must [3–7]. The use of the so-called digital-based analog solutions and time-based signal processing postulate as a good alternative for the implementation of AMS and Radio-Frequency (RF) front-ends and analog/digital interfaces in many diverse applications such as biomedical devices and Internet-of-Things (IoT) end-terminals [8–11]. However, one of the main limitations of time/frequency-based analog techniques is the nonlinear error associated to the voltage-to-frequency (V-to-F) transformation required to move from amplitude-based to time-based signal processing [11]. Prior art on FD-SOI shows that this technology is potentially better than (bulk) CMOS to design high-linearity AMS circuits with reduced supply voltages [12,13]. However, to the best of authors’ knowledge, previous works were only based on theoretical analyses and simulation results [14]. This paper goes from theory to practice and shows the first experimental evidences which demonstrate that the use of the bulk terminal, rather than gate terminal – used as either input or control node – can benefit from the enhanced body effect provided by FD-SOI to improve the linearity of AMS circuits. Two circuits – integrated in a 28- nm technology – are considered as case studies: a current-starved CMOS inverter and a VCRO. These circuits are building blocks of a number of AMS circuits and systems, including filters, Analog-to-Digital Converters, Phase-Locked Loops (PLLs), just to cite some examples. Measurement results are shown to validate prior theoretical predictions and open the doors to exploit FD-SOI technology to design analog and mixed-signal circuits and systems with enhanced linearity and DR in those applications requiring low energy consumption with reduced supply voltage. The paper is organized as follows. After this introduction, Section 2 describes the current-starved inverter circuit used as example, and analyses its performance in terms of linearity and harmonic distortion. The use of such inverter as the basic cell of VCROs is shown in Section 3. Finally, experimental results are shown in Section 4 and conclusions are * Corresponding author. E-mail address: [email protected] (J.M. de la Rosa). 1 http://www.imse-cnm.csic.es/~jrosa. Contents lists available at ScienceDirect International Journal of Electronics and Communications journal homepage: www.elsevier.com/locate/aeue https://doi.org/10.1016/j.aeue.2021.153992 Received 24 August 2021; Accepted 30 September 2021 AEUE - International Journal of Electronics and Communications 142 (2021) 153992 2 drawn in Section 5. 2. Bulk-controlled Current-Starved Inverter Fig. 1 shows the schematic of the current-starved inverter under study [14]. The bias current which flows through the inverter – made up of transistors Mp2 and Mn2 – is provided by transistors Mp1 and Mn1, which are configured as current sources. These current-source transistors are controlled by voltage Vc – connected at the gate of Mn1 through a source-follower circuit – and by the bulk voltage, Vbn – connected at the body terminal of both Mp1 and Mn1. An enable signal, denoted as enb in Fig. 1, is used to turn the inverter off or on – a functionality used by some types of VCROs such as Gated switched-Ring Oscillators (GROs) in order to make the oscillator either to oscillate or to stop running [9]. For the analysis that follows, it will be considered that the node enb is connected to ground. 2.1. Enhanced Body Effect in FD-SOI Technology The proposed current-starved inverter has been designed in a FD-SOI process in order to take advantage of its enhanced body effect as compared to a bulk CMOS process [3]. The bulk terminal of MOS transistors in FD-SOI technology can be biased by a wider voltage range, which increases the body effect, and therefore, the tuning range of the threshold voltage, Vth, with the voltage applied at the bulk terminal, by a linear relationship given by [3]: Vthn =Vthn0 −rn⋅Vbn,|Vthp| = |Vthp0| + rp⋅Vbp (1) where Vbn and Vbp are the voltages applied at the bulk terminals of an nMOS and a pMOS transistor; Vthn0 and Vthp0 are the zero-bias threshold voltages of nMOS and pMOS, respectively; and rn and rp stand for the corresponding body factors. In the technology under study, a 28-nm FDSOI process, the values of Vthn0 and Vthp0, are respectively Vthn0= 326mV and Vthp0=335mV for minimum-size transistors, while rn≃70mV/V and rp≃80mV/V [14]. 2.2. Harmonic Distortion in Current-Starved Inverter Amplifiers For the analysis that follows, let us consider that all transistors are working in strong inversion and in saturation region, so that the drainsource current of an nMOS transistor can be expressed as 2 : IDS =βn 2(VGS −Vth)2⋅(1+λ⋅VDS)(2) where VGS and VDS stand for the gate-source and drain-source voltages; βn=W L μ nCox; μ n is the mobility of electrons; Cox is the gate-oxide capacitance per unit area; λ is the channel-length modulation parameter; and W and L, are respectively the transistor channel width and length of the nMOS transistor. The small-signal transconductance, gm≃βn(VGS −Vth), and its derived performance metrics, such as intrinsic voltage gain, Av≡gm/gds, transconductance efficiency, gmID ≃gm/IDS, and transit frequency, fT≡gm/Cg, can also benefit from the body biasing [3]. In the case of a current-starved inverter as that shown in Fig. 1, the current flowing through the main inverter, denoted as IQ, can be expressed as: IQ=IDS|n1 =IDS|n2 =IDS|p1 =IDS|p2 (3) where IDS|n1,2 and IDS|p1,2 stand for the drain-source currents of Mn1,2 and Mp1,2, respectively given by: IDS|n1 =βn 2(VG−Vthn)2⋅[1+λ⋅VX](4) IDS|n2 =βn 2(Vin −VX−Vthn0)2⋅[1+λ⋅(Vout −VX)] (5) IDS|p1 =βp 2(Vdd − |Vthp|)2⋅[1+λ⋅(Vdd −VY)] (6) IDS|p2 =βp 2(VY−Vin − |Vthp0|)2⋅[1+λ⋅(VY−Vout)] (7) where Vdd is the supply voltage; βn and βp stand for the β of Mn1,2 and Mp1,2 respectively; VG,X,Y are the voltages at internal nodes G,X,Y (see Fig. 1), and it has been assumed that λ is the same for both nMOS and pMOS transistors. Let us consider the expressions of Vthn,p given in (1). Replacing these expressions in (4) and (6), and solving the set of equations in (4)–(7), the output voltage of the inverter, Vout, can be derived as a function of the input, Vin, and the control voltages, Vc and Vbn, i.e. Vout =f[Vin,Vc,Vbn](8) Applying a Taylor series expansion of (8), it can be shown that the input–output characteristic of the inverter in its amplification region can be approximated by a polynomial function as: Vout ≃ α 0[Vc,Vbn]+ α 1[Vc,Vbn]⋅Vin + α 2[Vc,Vbn]⋅V2 in + α 3[Vc,Vbn ]⋅V3 in +…(9) where α 0 is the DC (operating-point) output voltage; α 1 stands for the linear gain of the inverter; and coefficients α i (with i>1) are the i-th order nonlinear gain coefficients. Note that all these polynomial coefficients, α i, depend on the control voltages Vc and Vbn – denoted in (9) as α i[Vc,Vbn]. For the sake of simplicity, let us assume that βn=βp. Considering that a sinewave signal is applied at the input, the second- and third-order Harmonic Distortion (HD) coefficients can be approximated by the following expressions: HD2≡ α 1 2 α 2 ⋅Vin ≃[1 4(VinDC −Vthn0)−3λ(Vdd −Vthn)2 4(Vc−Vdd)(Vc+Vdd −2Vthn)]⋅Vin (10) HD3≡ α 1 4 α 3 ⋅V2 in ≃λ(Vdd −Vthn)2 4(Vdd −Vc)(VinDC −Vthn0)(Vc+Vdd −2Vthn)⋅V2 in (11) where Vin is the amplitude of the input sinewave and VinDC stands for the Fig. 1. Schematic of the bulk-controlled current-starved inverter. 2 A simplified first-order model is used in this work to get some insight about the harmonic distortion in FD-SOI inverters. More accurate models (including second-order effects) can be considered, although they will lead to more complex mathematical expressions, without adding significant information to the purposes of this research work. P.I. Okorie et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153992 3 DC (operating-point) input voltage. The Total Harmonic Distortion (THD) can be approximated by the sum of the contributions of the first two harmonic coefficients (HD2 and HD3) as: THD ≡ ∑ ∞ n=1 HD2 i √≃ HD2 2+HD2 3 √(12) Fig. 2 depicts the theoretical estimation of THD vs. Vbn, where it can be seen how the harmonic distortion can be modulated by the combined action of Vc and Vbn as will be demonstrated by experimental measurements. 3. Bulk-controlled VCRO Fig. 3 shows the conceptual schematic of the bulk-controlled VCRO used as circuit example in this work. It consists of a ring oscillator made up of current-starved inverters (I1,2…n) as that shown in Fig. 1. The output of each inverter – denoted as phi (i=1,2…n)– can be taken to generate a multi-phase output. Note that the circuit can be configured either as a GRO or as a VCRO, depending on the value of the enable signal –denoted as enb in Fig. 1. Thus, if enb switches between OFF (logic “0”) and ON (logic “1”) states, this will cause the VCO to oscillate or get frozen. The operation of the VCRO is governed by voltages Vc and Vbn. These voltages control the operation of each VCO (inverter) cell – depicted in Fig. 1. The oscillation frequency, fosc, can be expressed as: fosc =1 2⋅mph⋅ τ d(Vc,Vbn)(13) where mph is the number of inverters, i.e. the number of phases of the VCRO (see Fig. 3), and τ d stands for the propagation delay of each inverter-based VCRO cell. This delay depends on the charging/discharging time of the load capacitance at each inverter output, which is in turn a function of the current flowing through the inverter – controlled by Vc and Vbn. Thus, the overall propagation delay can be expressed as: τ d= τ LH + τ HL (14) where τ LH and τ HL stand respectively for the charging (”Low–High”) and discharging (”High-Low”) transient times. Let us consider that the VCRO cell is implemented using FD-SOI, and hence, Vthn depends on Vbn according to (1). In this case, it can be shown that [14]: fosc ≃fq+kVCO2⋅Vbn +k22⋅V2 bn (15) where fq= α osc⋅(Vc−Vthn0)2,kVCO2=2⋅ α osc⋅(Vc−Vthn0),k22 = α osc⋅ r2 n and α osc =βn/(2⋅mph⋅CL⋅Vdd). Note from (15) that only a second-order nonlinearity is obtained in the case of FD-SOI bulk-input controlled VCRO cells. However, in the case of conventional bulk processes, higher-order nonlinear terms (3rd- order, 4th-order, etc.) are obtained [14]. Let us consider now the most conventional situation in which the control voltage of the VCRO cell is Vc, and there is not any body effect, i.e. Vbn =0. In this case, it can be shown that the oscillation frequency is given by: fosc ≃ α osc⋅V2 thn0 −2 α osc⋅Vthn0⋅Vc+ α osc⋅V2 c(16) Comparing (15) and (16), it is clear that in both cases, quadratic dependencies on the control voltages are obtained. However, the secondorder nonlinear term (k22) in FD-SOI case – Eq. (15) is attenuated by the body factor, which in a 28-nm technology process is rn≃70mV/V, i. e. almost two orders of magnitude lower than the nonlinearity obtained in the case of conventional gate-controlled VCROs – Eq. (16). An estimation of the nonlinear error can be computed as [15]: ∊osc =fosc −fosc−ideal fosc−ideal (17) Fig. 2. THD vs. V bn for Vc=0.5V (dashed line) and Vc=0.8V (solid line). Fig. 3. Conceptual schematic of the bulk-controlled VCRO under study. Fig. 4. Nonlinear error of the V-to-F characteristic in VCROs: FD-SOI versus bulk CMOS. P.I. Okorie et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153992 4 where fosc−ideal stands for the ideal (perfectly linear) V-to-F characteristic. As an illustration, Fig. 4 shows the theoretical nonlinear error of a VCRO by considering an FD-SOI technology and a bulk CMOS process. It can be shown how the use of enhanced body effect allows to reduce ∊osc by more than two orders of magnitude. This theoretical prediction is confirmed by experimental results as shown below. 4. Experimental results In order to validate the presented approach, the circuits under study have been designed and fabricated in a 28-nm FD-SOI technology from STMicroelectronics. Fig. 5 shows a microphotograph of the chip and a picture of the Printed Circuit Board (PCB) used for testing purposes. The latter includes additional circuitry such as voltage regulators, decoupling capacitors and connectors for the instruments required to measure the chip. Due to the opacity of passivation materials and top metals, the layout of the chip is superimposed on the chip microphotograph in order to distinguish the different subcircuits inside the chip. A 40-pin Quad- Flat No-leads (QFN) package is used for the device under test, which Fig. 5. Chip microphotograph (including the chip layout superimposed inset) and test PCB. Fig. 6. Conceptual diagram of the test set-up. Fig. 7. Input and output waveforms of the current-starved inverter (VCO-cell). P.I. Okorie et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153992 5 is integrated in the same die with another chip not related to this work. The silicon area is 590 μ m x 975 μ m including bonding pads and a nominal supply voltage of 1 V and regular-Vth transistors [3] have been used to design the circuits in this work. Fig. 6 shows the measurement set-up. A programmable DC signal supply generator (HP 6624A) is used to sweep the values of Vc and Vbn, while an EL302T equipment provides the supply voltage of 1 V. In the case of the current-starved inverter (VCO-cell), a sinewave signal is generated using a Tektronix AFG3102 signal generator. The output voltage of both circuits, i.e. the inverter and the VCO, are captured by a (Keysight DSO6104A) oscilloscope to get the waveforms and an (HP3585A) spectrum analyzer to obtain the output spectra. All instruments are controlled through General Purpose Interface Bus (GPIB) and USB by a PC, where the measured data is processed in MATLAB®. 4.1. Harmonic Distortion in Current-Starved Inverters Let us consider that a sinewave signal with amplitude 25mVpp and 1- kHz frequency is applied at the input node of the current-starved inverter in Fig. 1. The input DC voltage is VinDC =746mV, such that the inverter is operating in the amplification region, i.e. it behaves as an inverting amplifier. The output voltage amplifies the input signal as illustrated in the measured waveforms shown in Fig. 7, where a voltage Fig. 8. Effect of varying V c and Vbn on the harmonic distortion of the VCO-cell, considering an input signal amplitude of (a)-(b) Vin =25mVpp and (c)-(d) Vin = 30mVpp. Fig. 9. THD vs. V bn for different values of Vc and Vin =25mVpp. P.I. Okorie et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153992 6 Fig. 10. THD vs. V bn for Vc=550 mV and different values of Vin. Fig. 11. VCO output waveforms for different cases of V c and Vbn. (a) Vc=900 mV, Vbn =500 mV; (b) Vc=700 mV, Vbn =500 mV; (c) Vc=500 mV, Vbn =750 mV; (d) Vc=500 mV, Vbn =250 mV; (e) Vc=500mV, Vbn =1V; (f) Vc=1 V, Vbn =500 mV. P.I. Okorie et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153992 7 gain of about 10 can be observed. As stated in previous sections, the combined action of Vc and Vbn can improve the linearity of the circuit. This is illustrated in Fig. 8, where several output spectra of the circuit in Fig. 1 are shown for different values of the input signal amplitude, Vin =25Vpp (Fig. 8)) and Vin = 30Vpp (Fig. 8(c)-(d))). Note that in both cases, the harmonic distortion can be reduced, and even removed, by properly choosing the values of Vc and Vbn. Fig. 9 represents the measured THD versus Vbn for Vin =25mVpp and different values of Vc. It can be shown how the enhanced body effect inherent to FD-SOI MOS transistors allows to improve the linearity of the circuit, thanks to the wider tuning range of Vbn and the enhanced body effect, as stated in Section 2. The influence of this enhanced body effect on the linearity is modulated by the value of Vc as predicted by theory, since the operating point of the current-starved inverter is more sensitive to the variation of Vc as compared to the changes in Vbn. Obviously, as the input signal amplitude increases, the THD will increase as well, as depicted in Fig. 10, where THD is shown as a function of Vbn for Vc= 550mV and different values of Vin. Overall, an improvement of 25–30 dB in the THD can be achieved by properly choosing the values of control voltages Vc and Vbn. 4.2. Nonlinear Error in VCROs Compared with bulk CMOS technologies, the enhanced body effect allows to further reduce the harmonic distortion and improve the linearity of some circuits based on inverters. This is the case of the VCRO shown in Fig. 3. The oscillation frequency of this circuit can be varied by two different control signals, either the gate voltage, Vc, or the bulk voltage, Vbn. This is illustrated in the waveforms shown in Fig. 11, where the measured output signal waveform is shown for different cases of Vc and Vbn. Fig. 12 shows the measured Voltage-to-Frequency (V-to-F) characteristic of the circuit, considering two control voltages, either gate- Fig. 12. Measured V-to-F characteristic of the VCRO considering (a) a bulk-input (V bn) and (b) a gate-input (Vc). Fig. 13. Measured nonlinear error of the VCRO considering a bulk-input (V bn) and a gate-input (Vc). P.I. Okorie et al. AEUE - International Journal of Electronics and Communications 142 (2021) 153992 8 controlled, i.e. Vc as control voltage, or bulk-controlled, i.e. Vbn. As expected, the bulk-controlled case features a more linear V-to-F characteristic than the gate-controlled case. This is better illustrated in Fig. 13, where it is shown how the use of bulk-input voltage drastically reduces the nonlinear error, at the price of reducing the frequency tuning range with respect to the gate-input control case. However, both control voltages, i.e. Vc and Vbn can be combined to increase the programmability of the VCRO in terms of frequency range – by using Vc – and nonlinear frequency error – by using Vbn, thanks to the combined action of both voltages. This feature – predicted by theory in [14] – is confirmed by the experimental results shown in this paper. 5. Conclusions The enhanced body effect provided by FD-SOI CMOS technology can be used to improve the performance of analog and mixed-signal circuits as compared to the use of bulk-based CMOS. This has been demonstrated in this paper by several experimental results taken from a currentstarved inverter and a bulk-controlled VCRO. It has been shown how measurements of the THD of an inverter amplifier and the nonlinearity of the V-to-F characteristic of a VCRO can be notably reduced or even removed by the combined action of gate- and bulk-based control voltages. These experiments validate prior theoretical predictions and provide an alternative approach to design high-performance analog circuits in deep nanomenter processes with reduced supply voltages. Declaration of Competing Interest The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper. Acknowledgments The authors would like to thank the editor and the anonymous reviewers for their constructive and valuable comments and suggestions to improve the quality of this paper. This work was supported in part by the Spanish Ministry of Science and Innovation (with support from the European Regional Development Fund) under contract PID2019- 103876RB-I00 and by Junta de Andalucía under contracts US- 1260118 and P20-00599. References [1] Loh K. Fertilizing AIoT from Roots to Leaves. IEEE ISSCC Digest of Technical Papers 2020:15–21. [2] Liu M. Unleashing the Future of Innovation. IEEE ISSCC Digest of Technical Papers 2021:9–16. [3] Cathelin A. Fully Depleted Silicon on Insulator Devices CMOS. IEEE Solid-State Circuits Mag. 2017;9:18–26. [4] Gao L, Wagner E, Rebeiz G. Design of E- and W-Band Low-Noise Amplifiers in 22- nm CMOS FD-SOI. IEEE Trans. Microw. Theory Tech. 2019;68(1):132–43. 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