Methodology to improve the model of series inductance in CMOS integrated inductors

sciendo Journal of ELECTRICAL ENGINEERING, VOL 69 (2018), NO3, 250–254 Methodology to improve the model of series inductance in CMOS integrated inductors Eric F. Gutierrez-Frias∗, Luis A. Garc´ıa-Lugo∗, Edwin C. Becerra-Alvarez∗, Juan J. Raygoza-Panduro∗, Jos´e M. de la Rosa∗∗, Edgardo B. Ortega-Rosales∗∗∗ This paper presents a systematic optimization methodology to achieve an accurate estimation of series inductance of inductors implemented in standard CMOS technologies. Proposed method is based on an optimization procedure which aims to obtain adjustment factors associated to main physical inductor characteristics, allowing to estimate more accurate series inductance values that can be used in design stage. Experimental measurements of diverse square inductor geometries are shown and compared with previous approaches in order to demonstrate and validate presented approach. K e y w o r d s: optimization, inductance, adjustment factors, integrated inductors 1 Introduction Huge growth of mobile communications in last years demands more and more high-performance, low-cost and power-efficient on-chip Radio Frequency (RF) circuits and systems. Continuous incorporation of new standards and services [1], together with the trend toward interconnection of billions of wireless devices in so-called Internet of Things (IoT), make the optimized design of RF transceivers one of pillars supporting this new technology wave [2]. Among others, integrated inductors are key circuit elements enabling implementation of efficient IoT devices [3], since they are essential parts used to build basic RF subcircuits, such as Low-Noise Amplifiers (LNAs), Power Amplifiers (PA), mixers and Voltage-Controlled Oscillators (VCOs) [4]. Inductors are employed for tasks such bias feeding and impedance matching of transistors. Reactively matched transistors enable significantly higher gain-DC power rations and better noise performance [5]. A problem in using on-chip inductors in design of integrated circuits is poor quality of inductors models in many available technologies. Using available inductor models in technology library may lead to a situation where parameters of manufactured systems do not match expected specifications [6]. An accurate and systematic design of integrated inductors requires taking into account most important physical effects associated to their implementation in CMOS technologies [7]. To this end, a physical model and an equivalent circuit, usually considered by RF circuit designers, is illustrated in Fig. 1(a) and pi-model Fig. 1(b) [8], which is a good approximation for the physical behavior of integrated inductors. Physical model, Fig. 1(a), shows separation distance between spires s, spire width w, internal diameter din and outer diameter dout . Equivalent circuit, Fig. 1(b), consists of main circuit-element parameters as series inductance Ls, series resistance Rs, overlap capacitance between segment and underpass Cs, and oxide capacitance between the silicon substrate Cox . The substrate losses including parasitic capacitance Csi and its resistance Rsi , are also considered in this model [9]. One of the most important characteristics in pi-model is Ls, which has been exhaustively analyzed by a number of authors in order to get compact and precise closedform design expressions that relate the physical implementation with geometric dimensions of inductor structure [10,11,12,13]. Such design equations give an estimation of Ls, which can be used for design purposes. However, model value of Lscan be further improved by properly adjusting their main physical parameters through an optimization methodology. 2 Background of Series Inductance Modeling As stated above, a number of closed-form expressions to estimate the series inductance have been reported. Two of the simplest formulations were presented by Mohan et al in [10], where Lsis modeled by two series inductances: modified Wheeler’s formula, and current-sheet approximation, denoted as LMW and LMC , respectively. * University Center for Exact Sciences and Engineering, Universidad de Guadalajara, Av. Marcelino Garc´ ia Barrag´an and Calz. Ol´ impica 1421, Guadalajara, Jalisco, M´exico, ** Instituto de Microelectr´onica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla, C/Am´erico Vespucio, 41092 Sevilla, Spain, *** Universidad Tecnol´ogica de la Zona Metropolitana de Guadalajara, camino a San Isidro Mazatepec Km 4.7, Tlajomulco de Zu˜niga, Jalisco, M´exico eric.gutierr[email protected], [email protected], edwin.b[email protected], juan.raygoz[email protected], [email protected]c.es, [email protected] DOI: 10.2478/jee-2018–0034, Print (till 2015) ISSN 1335-3632, On-line ISSN 1339-309X c 2018FEI STU Journal of ELECTRICAL ENGINEERING 69 (2018), NO3 251 s din w (a) dout (b) LsRs Cox vivo CoxCs Csi Rsi Csi Rsi Fig. 1. Integrated inductor model: (a) – conceptual physical structure, (b) – equivalent circuit These two series inductances can be approximated by the following expressions LMW =K1 µ0n2davg 1 + K2ρ(1) LMC =µ0n2davgc1 2ln c2 ρ+c3ρ+c4ρ2(2) ρand davg are respectively given by ρ=dout −din dout +din davg =dout +din 2 where µ0stands for the magnetic permeability in vacuum; din and dout are respectively the inner and outer diameter shown in Fig. 1(a) as mentioned previously, n is the number of turns, with K1= 2.34, K2= 2.75, c1= 1.27, c2= 2.07, c3= 0.18, c4= 0.13 being some adjustment coefficients for square inductors [10]. Another approach to derive closed-form design expressions for Lswas proposed by Jenei et al [11] and Asgaran et al [12], which were in turn mainly inspired in Greenhouse’s work [14]. Contrary to former approaches, Jenei’s model expressions are based on an approximation of total length of the inductor, ltot , rather than checking self-inductance and mutual inductance of every spire – as suggested by Greenhouse. This way, model proposed by Jenei et al can be formulated as LJ=L0J +M+J −M−J(3) where L0J =µ0 2πltot ln ltot n(w+s)−0.2 M-J =0.47µ0ltotn 2π M+J =µ0 2πltot(n−1) ln p1 + x2+x −r1 + 1 x2+1 x,x=ltot 4nd+ d+= (w+s)(3n−2Ni−1)(Ni+ 1) 3(2n−Ni−1) with Nibeing integer part of n,wis metal width and sis spacing between segments, as previously was mentioned. On the other hand, expressions obtained by Asgaran et al [12] are similar to that in (3), except that, instead of taking total length of the inductor, it considers the average diameter in the model, which is given by [12]. LA=L0A +M+A −M−A(4) where L0A =2µ0n πdavg 1 2+ ln 2davg w+ 0.178w M−A=2µ0 π0.47n2davg M+A =2µ0 π{Ni(2n−Ni−1)dsln 2ds w+s−1− 2ds[ln P+ (n−Ni) ln Ni!] + (w+s)× ×√2−ln(1 + √2) 3Ni(Ni+ 1)(3n−2Ni−1)} P= 1!,2!,...,(n−1)!, ds=davg +w 2. 3 Experimental implementation Different square-shaped inductors were designed and fabricated in TSMC (Taiwan Semiconductor Manufacturing Company) 0.35µm CMOS technology process (the presented methodology can be extended to any standard CMOS process). These inductors were used to obtain the adjustment factors ∆s, ∆w, ∆nand ∆dout , which ones are about physical dimensions of inductors that have variations due manufacturing process, for instance ∆sis about distance between segments, ∆wis about segments width, etc. They were built with the top-metal layers, 252 E. F. Gutierrez-Frias et al : METHODOLOGY TO IMPROVE THE MODEL OF SERIES INDUCTANCE IN CMOS . . . Table 1. Integrated inductors sizing Inductor s w dout n (µm) (µm) (µm) (-) 1 3.0 15.0 145 3.25 2 5.0 5.0 160 2.5 3 5.0 5.0 190 6.5 4 3.0 10.0 200 3.0 Table 2. Inductance values in nH Inductor LMW LMC LJLAMeasured 1 1.02 1.03 0.93 1.05 1.5 2 1.84 1.88 1.83 1.95 2.1 3 7.11 7.06 6.13 7.11 11.5 4 2.70 2.69 2.89 2.70 3.0 Table 3. Estimated,initial error in % Inductor MW MC J A 1 31.49 31.25 37.68 29.74 2 12.03 10.16 12.73 6.96 3 38.11 38.58 46.64 38.14 4 9.78 10.1 3.41 9.71 Table 4. Error after the optimization in % Inductor MW MC J A 1 0.00 0.00 0.00 0.00 2 0.00 2.15 0.00 1.03 3 6.06 0.00 0.00 0.00 4 4.38 2.79 5.96 0.00 MW, MC – Mohan, J – Jenei, A – Asgaran (a) (b) Fig. 2. Integrated inductors: (a) – microphotograph of the fabricated inductors in a multi-project chip, (b) – illustrating the inductors characterization in a network analyzer Fig. 2(a) shows the microphotograph of the multi-project chip – which includes other subcircuits not related to this work – highlighting fabricated inductors, corresponding inductors sizes are shown in Tab. 1. Experimental characterization was carried out by using a network analyzer HP8719D, a synthesized signal generator HP8664A and a MXA signal analyzer N9020A. As an illustration, Fig. 2(b) shows the Smith chart s12 parameter measured from network analyzer, while Tab. Tab. 2 shows the inductance values obtained for models given in (1) to (4) as well as their corresponding experimental measured values of fabricated inductors. The difference between model and experimental measurements are computed as a percent error, defined as (Lse −Lsm)/Lse , where Lse and Lsm are respectively the experimental and the model inductance values, as can be seen in Tab.2(a). 4 Error Reduction Procedure Starting from the error values in Tab. 1 the proposed optimization algorithm depicted in Fig. 3 is applied to determine the corresponding adjustment factors in an iterative way. In order to determine the best values of them, the optimization algorithm proceeds iteratively, starting from ∆s, ∆w, ∆nand ∆dout , with an initial aleatory value. Afterwards, the error corresponding to the difference between the model estimation and the real experimental inductance value for each inductor is determined, a new aleatory value for adjustment factors is proposed, considering that every individual error must be reduced for all inductances at each iteration of the optimization procedure. Process is repeated until a minimum error is achieved corresponding to a given tolerance . In order to optimize Journal of ELECTRICAL ENGINEERING 69 (2018), NO3 253 Fig. 3. Inductance error reduction algorithm LAerror (%) 100 50 20 10 5 1 2 Iteration 2510 20 13 4 2 Fig. 4. Illustrating the error reduction process for LA– Asgaran. and to speed up the procedure, the so-called gradientbased method [15] is used in order to find out a local minimum with a low computational cost. Outcome of this optimization adjustment factors is shown in Tab. 5, where applying these factors to the models, the percent error associated to estimated series inductance is reduced in the most of the cases to 0%, being highest error the 6.06% as shown in Tab. 3. As an illustration of the optimization procedure, Fig. 4 shows the error reduction obtained by applying the algorithm to the LA– Asgaran, series inductance. For this case, we have that in just five iterations the biggest percent error for the inductor No. 3 goes down from 38.14% to 0.0%. Optimization algorithm for the inductor No. 1, for all inductor models, gives a reduction error that goes from 32.5% as average to 0.0%. Table 5. Optimized adjustment factors Model ∆s∆w∆n∆dout Mohan W 1.2092 7.2173 0.0770 0.7609 Mohan C 0.3744 1.6050 0.2941 0.7445 Jenei 0.1097 0.4182 1.0815 0.7762 Asgaran -1.2247 1.1708 0.5534 0.9646 Conclusions An optimization-based methodology has been presented in order to find out a more accurate estimation of the series inductance in integrated inductors by means of adjustment factors that compensate fabrication variations of inductors, it is intended to be an useful tool during early design stages providing adjustment factors that are easily added to the well known inductance models, predicting more accurate inductance values. Experimental results are shown for a number of square integrated inductors with diverse sizes and geometry parameters, and used to obtain the mentioned adjustment factors, that allow an important error reduction as can see for Jenei model with a maximum of 46.64% to zero, thus validating the presented approach which can be extended to optimize the design of inductors in whatever RF CMOS circuit. Acknowledgments This work was partially supported by the National Council of Science and Technology of M´exico (CONACYT) and by the Spanish Ministry of Economy and Competitiveness (with support from the European Regional Development Fund) under contract TEC2013-45638-C3- 3-R, and by “Consejer´ ia de Econom´ ia, Innovaci´on, Ciencia y Empleo de la Junta de Andaluc´ ia”, under contract P12-TIC-1481. References [1] S. Onoe, ”Evolution of 5G Mobile Technology Toward 2020 and Beyond IEEE International Solid-State Circuits Conference ISSCC, 2016, pp. 23-28 (DOI: 10.1109/ISSCC.2016.7417891). [2] S. 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[14] and Greenhouse, ”Design of planar rectangular microelectronic inductors IEEE Transactions on parts hybrids, and packaging, vol. 10, no.2, pp. 101-109, 1974 (DOI: 10.1109/TPHP. 1974.1134841). [15] J. Snyman, ”Practical mathematical optimization: an introduction to basic optimization theory and classical and new gradient-based algorithms Springer Science & Business Media vol. 97, 2005. Received 21 March 2018 Eric F. Gutierrez Frias received the BSc degree in Communications and Electronic Engineering and MSc degree in Electronic and Computer Engineering from University of Guadalajara, M´exico in 2012 and 2015 respectively. Currently he is working toward the PhD degree in electronic and computer sciences at the University of Guadalajara. His current research interests include power amplifier and optimization of analog circuits. Luis A. Garc ´ ia Lugo received the BSc degree in Communications and Electronic Engineering from University of Guadalajara, M´exico and MSc degree in Electrical Engineering in Semiconductors from the Center for Research and Advanced Studies of the National Polytechnic Institute, M´exico in 1997 and 2001 respectively. He worked as quality, device and product engineer for Motorola, On Semiconductor, Siemens VDO and Hitachi GST, where he was involved in fabrication and testing of discrete semiconductor devices as power rectifiers, MOS and bipolar transistors as well as sliders for hard disk drives. He is a final year student of PhD studies in Electronic and Computing Sciences at the University of Guadalajara. The fields of his interest are low-noise amplifiers and sigma-delta modulators. Edwin C. Becerra Alvarez received the BSc degree on Communications and Electronic Engineering from the University of Guadalajara, Mexico in 2004, the MSc degree on Electric Engineering from CINVESTAV, Mexico in 2006 and the PhD degree on Microelectronics from the University of Seville, Spain in 2010. Since 2010 he is working in the University of Guadalajara and his current research interests are on CMOS RF circuits. Juan J. Raygoza Panduro received the BSc degree in Communications and Electronics from the University of Guadalajara, the MSc degree from the Center of Research and Advanced Studies of the IPN, Zacatenco, M´exico. He received his PhD degree in Computer Science and Telecommunications from Autonomous University of Madrid, Spain. He worked for IBM and participated in the technological transfer of manufacturing hard disk heads, from San Jose, USA to Guadalajara, M´exico. He specializes in the design of digital architecture based on FPGAs, Microprocessors, embedded system and bioelectronics. He is Professor at CUCEI; University of Guadalajara, his lines of research are: Electronic Systems Applied to Biomedicine, Neuroengineering, Microprocessor Design, Digital Control and Embedded system. Jos´e M. de la Rosa received the MSc degree in Physics in 1993 and the PhD degree in Microelectronics in 2000, both from the University of Seville, Spain. Since 1993 he has been working at the Institute of Microelectronics of Seville (IMSE), which is its turn part of the Spanish Microelectronics Center (CNM) of the Spanish Council of Scientific Research (CSIC). He is presently the vicedirector of IMSE and he is also a Full Professor at the Dept. of Electronics and Electromagnetism of the University of Seville. His main research interests are in the field of analog and mixed-signal integrated circuits, especially high-performance data converters, including analysis, behavioral modeling, design and design automation of such circuits. Edgardo B. Ortega Rosales received the BSc and MSc degrees in Electronics Engineering from the University of Guadalajara, M´exico, in 1997 and 2004, respectively. He received the PhD degree in 2016 from the Centre of Research and Advanced Studies (CINVESTAV), M´exico. He was a special student in 1998 at Gettysburg College while working as an assistant professor in Gettysburg, Pa, USA. He worked at the University of Guadalajara as a professor from 1999 to 2011. Currently, he is working at the Technological University of the Metropolitan Area of Guadalajara. He is interested in analog and RF circuit design areas for integrated communication systems.