A Generalized Predictive Controlled T-type power inverter with a deterministic dc-link capacitor voltage balancing approach

A Generalized Predictive Controlled T-type Power Inverter with a deterministic dc-link capacitor voltage balancing approach A PROJECT REPORT Submitted by CHARANRAJ MOHAN In the partial fulfillment for the award of the degree of MASTER in ELECTRONICS, SIGNAL PROCESSING & COMMUNICATION ESCUELA TECNICA SUPERIOR DE INGENIERIA UNIVERSIDAD DE SEVILLA SEVILLE 41092 JULY 2015 ACKNOWLEDGEMENT First and foremost, I sincerely thank our beloved director Prof. Jaime Dominguez Abascal, deputy director of studies, Prof. Francisco Rodriquez Rubio, Secretary, Prof. Francisco Javier Gutierrez Ortiz and head of the electronics engineering department, Prof. Antonio Jesus Torralba Silgado of Escuela Superior de Ingenieria, University of Seville at this high time for providing the necessary facilities to complete my project successfully. I would like to express my sincere thanks to the HERITAGE consortiumteam and its coordinators for providing me an opportunity to do Masters under the HERITAGE-Erasmus Mundus project. I am grateful to Prof. Leopoldo Garcia Franquelo, Department of Electronics Engineering for his anchoring support and guidance in doing this project. I express my sincere thanks to Associate Prof. Sergio Vazquez, Associate Prof. Jose Ignacio Leon Galvan and Mr. Abraham Marquez from the department of Electronics Engineering for their constant guidance, high patience, constructive criticism and encouragement throughout the project work. I also thank all the teaching, nonteaching staffs, friends, colleagues and family who had directly and indirectly helped in bringing out the project in a success. CHAPTER NO. TITLE PAGE NO. ABSTRACT i LIST OF TABLES ii LIST OF FIGURES iv LIST OF ABBREVATIONS viii 1. INTRODUCTION 1 2. MULTILEVEL INVERTERS 3 2.1. INVERTER TOPOLOGIES 4 2.1.1. NEUTRAL POINT CLAMPED MULTILEVEL INVERTER 4 2.1.2. CASCADED H-BRIDGE INVERTER 5 2.1.3. FLYING CAPACITOR MULTILEVEL INVERTERS 6 2.2. MODULATION SCHEMES 8 2.3. CONTROL STRATEGIES 9 3. NEUTRAL POINT PILOTED (NPP) POWER INVERTER 11 4. SYSTEM DESCRIPTION, MODELING & CONTROL DESIGN 13 4.1. GPC STRATEGY FOR OUTPUT VOLTAGE CONTROL 13 4.2. T-TYPE INVERTER SYSTEM WITH INDIVIDUAL VOLTAGE SOURCES 19 4.3. T-TYPE INVERTER SYSTEM USING INDIVIDUAL DC LINK CAPACITORS 22 4.3.1. REDUNDANCY DC LINK CAPACITOR VOLTAGE BALANCING APPROACH 22 4.3.2. DETERMINISTIC DC LINK CAPACITOR VOLTAGE BALANCING APPROACH 24 4.4. COMPARISON OF THE DC LINK CAPACITOR VOLTAGE BALANCING APPROACHES 36 5. DESIGN OF A NPP POWER INVERTER 38 6. ADVANTAGES & APPLICATIONS 47 7. CONCLUSION & FUTURE WORK 48 8. REFERENCES 49 i ABSTRACT The thesis consists of implementing a Generalized Predictive Control (GPC) strategy for controlling the output voltage of the T-type converter with output LC filter, whose control signals are modulated by a fast three-dimensional Space Vector Modulation (SVM). The GPC strategy used for the T-type converter involves developing a system of dynamic equations from the output LC filter and load, which is transformed to a Controlled Auto-Regressive and Moving-Average (CARIMA) model in order to obtain a sequence of control signals, so that a cost function is optimized and the reference is tracked. The core of the thesis addresses the main problem of dc-link capacitor balancing. This is done by modeling the converter and deploying a mathematical analysis of the capacitor voltage difference dynamics, by singular perturbation approach. This analysis results in an explicit sinusoidal disturbance. Now, classical control theory is applied by using a Luenberger Observer (LO) in order to estimate the disturbance and encounter it, thereby keeping the dc-link capacitor voltage balanced in the due flow of the modulation and output voltage control. By this method, the output voltage across the filter capacitor is controlled, the dc-link capacitor voltage is balanced and the lowfrequency voltage ripples present in the dc-link of the T-type converter are reduced to an acceptable level. ii LIST OF TABLES TABLE DESCRIPTION PAGE NO. Table 2.1 Switching states of a Three level single phase NPC 4 Table 2.2 Switching states of a single phase three level HBridge converter 5 Table 2.3 Switching states of a Five level single phase HBridge Converter 6 Table 2.4 Switching states of a three level single phase FCC 7 Table 3.1 Switching states of a single phase T-type converter 11 Table 4.1 System Variables and Parameters 16 Table 4.2 Model & Simulation Parameters for GPC 16 Table 4.3 GPC recursive polynomial calculation across horizons 17 Table 4.4 Redundancy control strategy to balance the dc link capacitor voltages 22 Table 4.5 Model parameters used in the equivalent ideal switch 25 Table 4.6 Resolving the input currents flowing towards the switches into quadratic function 27 Table 4.7 Space vector sequence & switching times for 3DSVM 32 Table 4.8 Space vector sequence & switching times for 3DFFSVM 35 Table 5.1 Switching modes of AT-NPC 3-level IGBT module (a three level NPP converter leg) 39 Table 5.2 Pin configuration of Input connectorsCN1 & CN101 for each driver board 39 Table 5.3 Pin configuration of Output connectorsCN2, CN3, CN4, CN5, CN6 & CN7 for each IGBT driver board 40 Table 5.4 List of Faulty components during FFD 41 Table 5.5 Ratings of output side power supply of optocoupler 43 iii Table 5.6 Observed values in the faulty optocouplers 43 Table 5.7 Summary of faults in driver & its correction 44 iv LIST OF FIGURES FIGURE DESCRIPTION PAGE NO. Figure 2.1 Different multilevel converter topologies 3 Figure 2.2 A single phase NPC 4 Figure 2.3 Conventional H-bridge (3 level, single phase) converter 5 Figure 2.4 Five-level single phase H-bridge converter 6 Figure 2.5 Three-level single phase flying capacitor converter 7 Figure 2.6 Various modulation schemes for multilevel converters 8 Figure 3.1 Leg schematic of a three-level T-type power inverter: (a) bidirectional switch with conventional IGBT, (b) bidirectional switch with RB-IGBT 11 Figure 3.2 Leg schematic of a single phase three level T-type module 11 Figure 4.1 Scheme of T-type converter connected to load via LC filter 15 Figure 4.2 Block diagram of the T-type inverter system with separate dc voltage source 20 Figure 4.3 Parallelogram comprising two equal triangles 20 Figure 4.4 Two dimensional Space Vector Modulation algorithm 21 Figure 4.5 Output voltage-reference and controlled waveforms for the T-type inverter system with individual dc voltage sources 21 Figure 4.6 Block diagram of the T-type inverter system with redundancy dc link capacitor voltage balancing approach 22 Figure 4.7 Switching state vectors of a three level converter 23 Figure 4.8 DC link capacitor voltages vc1 & vc2 balanced by redundancy approach with initial imbalance condition 23 v Figure 4.9 Output voltage-reference and controlled waveforms for Redundancy approach 24 Figure 4.10 DC link capacitor voltages vc1 & vc2 for redundancy approach 24 Figure 4.11 Block diagram of deterministic capacitor voltage balancing approach using 3D SVM 25 Figure 4.12 Block diagram of deterministic capacitor voltage balancing approach using 3D FFSVM 25 Figure 4.13 Equivalent circuit of a 3L T-type converter with ideal switches 26 Figure 4.14 Deterministic dc link capacitor voltage balancing approach 30 Figure 4.15 3D-SVM algorithm for selection of each tetrahedron for corresponding state vectors 32 Figure 4.16 DC link capacitor voltages vc1 and vc2 balanced by deterministic approach using 3D SVM with initial imbalance condition 33 Figure 4.17 DC link capacitor voltages vc1 and vc2 balanced by deterministic approach using 3D SVM with initial imbalance condition by fine tuning 33 Figure 4.18 Output voltage-reference and controlled waveforms for deterministic approach using 3D SVM 33 Figure 4.19 DC link capacitor voltages vc1 & vc2 for deterministic capacitor voltage balancing approach using 3D SVM 33 Figure 4.20 3D-feedforward SVM algorithm for selection of each subprism for corresponding state vectors 34 Figure 4.21 DC link capacitor voltages vc1 & vc2 balanced by deterministic approach using 3D FFSVM with initial 35 2 consequently solves the dc link capacitor voltage balancing problem. In our project a simple redundancy approach is used when the control strategy is defined in the αβ stationary frame; where as a deterministic approach is used when the control strategy is defined in the αβγ frame. In the control strategy defined in αβγ frame (or three component control), the γ-component is used to balance the dc-link capacitor voltages and to remove the lower order harmonics, occurred during capacitor switching to an acceptable level. The thesis work primarily addresses the two possible cases in the T-type inverter system, i.e. the case of using separate DC voltage sources and the case of introducing the dc link capacitors. The former case does not need a dc link capacitor voltage balancing strategy and a simple two dimensional SVM scheme is used. The latter one needs a separate control strategy for balancing the dc link capacitors. This case is again discussed into two strategies of balancing the dc link capacitor voltages i.e. the redundancy approach and the deterministic approach. In redundancy approach a simple static relation is considered to solve the dc link capacitor voltage balancing issue, whereas in deterministic approach a Luenberger Observer control scheme is used. In redundancy approach a two dimensional SVM is used, whereas in deterministic approach both three dimensional SVM and three dimensional FFSVM are the possible modulation schemes. It is to be noted that in all the cases a Generalized Predictive Control (GPC) approach is used for tracking output voltage. The GPC calculates the control signals to track the desired output filter capacitor voltages. A comparison of the T-type inverter system’s performance is made for the different approaches, in order to understand, investigate and realize the importance of the deterministic approach of capacitor voltage balancing method. The thesis report mainly comprises eight chapters including the introductory chapter. The 2nd chapter gives a basic idea of multilevel inverters, its topologies, various modulation and control schemes. The next chapter throws light on the NPP power inverter, thereby stating its importance. The 4th chapter, named ‘System description, modeling and control design’ is the core work of the thesis, which initially describes the GPC strategy. It also discusses the Ttype inverter system in case wise including its modulation-cum-control methodologies. This further includes modeling the inverter system for both GPC design and for deriving the dc link capacitor and inductor dynamics, which are the key concepts in deterministic approach. At the end of this chapter a comparison of the redundancy and the deterministic approaches are discussed. The 5th chapter describes the prototype design of the NPP converter and its evaluation. The advantages and applications are discussed in chapter 6. Chapter 7 is inferred with few conclusions and future work. Chapter 8 comprises the references cited. 3 CHAPTER 2 MULTILEVEL INVERTERS Industrial applications utilize both high and medium power levels and this is fairly possible only with multilevel converters. So, one can extract many voltage levels from multilevel converters based on his/her application need or interest. The foremost reasons to go for multilevel inverters are to avoid step up transformer during each stage of power conversion and to reduce output harmonics. Such multilevel converters are widely used in integration of renewable energy resources, ships, aviation, traction, Uninterruptible Power Supplies (UPS), High Voltage Direct Current (HVDC) systems, Flexible AC Transmission System (FACTS), variable-frequency drives, electric vehicle drives and air conditioning applications. By definition, ‘Multilevel inverters are power converters composed by an array of semiconductors and capacitor voltage sources, that when properly controlled, can generate waveform output voltages with adjustable frequency and amplitude’. Since the inception of multilevel converters [19] during 1975, research and development in multilevel converters have revolutionized much. Firstly, it all began with a simple three level power converter, which later led to development of different topologies and control methods [20]. These revolutions have mainly resulted in possible up-gradations of different topologies, modulation schemes, control methodologies, harmonics reduction possibilities and balancing of dc link capacitor voltages. The basic idea of multilevel converter is to get different output voltage levels by switching the semiconductor switches in an orderly fashion, resulting in a staircase output voltage, which is later inverted by a filter circuit to produce an AC output to be utilized by the load. Turning off a semiconductor switch is called commutation and this commutation is done in an orderly fashion, such that a different voltage levels are achieved at the output. Switching sequences of these semiconductor switches are generated by modulators, which are discussed in detail in section 2.2. Fig. 2.1. Different multilevel converter topologies The multilevel power converters have the following advantages:  Reduced dv/dt stresses and electromagnetic compatibility (EMC) problems, which improves the staircase waveform quality.  Smaller Common Mode (CM) voltage 4  Low distortion of input current  Operates at both fundamental and high switching frequencies  Higher voltage operation (above classic semiconductor limits)  Lower voltage distortion (more sinusoidal waveforms)  Multilevel converters are well suitable for reactive power compensation. Although multilevel converters are mature technologies, there is always a rising demand in new topologies, modulation schemes and control strategies to counteract one or more drawbacks of conventional one and to go on with a newly proposed converting technology. 2.1. INVERTER TOPOLOGIES Although many topologies and its industrial applications are found in literature [21] [22], the three major multilevel converter types are Neutral Point Clamped (NPC) converter, Cascaded H-Bridge (CHB) converter and Flying Capacitor Converter (FCC). Figure 2.1 shows the classification of multilevel converters [23]. 2.1.1. NEUTRAL POINT CLAMPED MULTILEVEL INVERTER The Neutral Point Clamped (NPC) converter was initially proposed by Nabae, Takahashi, and Akagi in 1981 [24], which laid a foundation to the era of voltage source multilevel high power converters. Figure 2.2 shows a single phase NPC for which the switching states are given in Table 2.1. The lower leg switches are the complementary of those of the upper leg switches. The clamping diodes allow the connection of the phase output to the midpoint of the dc link i.e. neutral (N) and this paves a way for three voltage levels. It is to be noted that if ‘L’ is the number of levels in phase to neutral voltage (VaN), then the number of steps in phase to phase voltage (Vab) is ‘2L-1’. The blocking voltage of the power devices is equal to Vdc/(L-1). NPCs are used for medium and high voltage applications. Integrated Gate Commutated Thyristors (IGCT) or Insulated Gate Bipolar Transistor (IGBT) is commercially used as switching devices. If the converter is for high voltage and high current applications, IGCT is a good choice of option. It is to be noted that IGBT has lower commutation losses and easy drivers, but it has high conduction losses.. Commercial NPCs include ACS 1000, SINAMICS SM120, Altivar 1000, etc. whose maximum power ranges from 10 to 40 MW. Advantages of multilevel diode-clamped inverters:  As all of the phases share a common dc bus, the capacitance requirement of the converter gets reduced. Due to this, NPC favors back-to-back regenerative applications.  The capacitors can be pre-charged in a group.  For fundamental switching frequency, the efficiency is high. Fig. 2.2. A single phase NPC Table.2.1 Switching states of a three level single phase NPC Voltage VaN Switching states S1 S2 S1’ S2’ Vdc/2 1 1 0 0 0 0 1 1 0 - Vdc/2 0 0 1 1 5 Disadvantages of multilevel diode-clamped inverters:  Real power flow is difficult for a single inverter because the intermediate dc levels will tend to overcharge or discharge without precise monitoring and control.  The inner most devices are switched on for most of the time. To overcome this and maintain a nominal uniformity, the Active Neutral Point Clamped (ANPC) were introduced.  The total number of clamping diodes required is quadratically related to the number of levels, which can be more complex for units with a high number of levels. 2.1.2. CASCADED H-BRIDGE INVERTER The cascaded H-Bridge converters are first introduced during late 1960s [25], [26], which paved a way to think of using a separate DC source in multilevel converters. As the name ‘CHB’ defines the use of multiple units of H-bridge power cells, which are connected in series such that the output voltage is the sum of each inverter outputs. Each Separate DC Source (SDCS) is connected to a single-phase full-bridge or H-bridge inverter. A conventional H-bridge cell is shown in the figure 2.3, whose switching states are given in table 2.2. The lower leg switches in each CHB cell are the complementary of the upper leg switches. The H-bridge cells are connected in series to form multilevel cascaded converters. The connection can be symmetrical (using same dc source values) or asymmetrical (using different dc sources). Figure 2.4 shows the leg-scheme of a symmetrical five-level CHB converter, whose switching states are given in the table 2.3. It is to be noted that, for a ‘m’ level symmetrical cascaded H-bridge converter the number of dc sources needed is (m-1)/2 & the maximum number of level of line-to-line output voltage is (2m-1). CHB converters are best suitable for large PV-plants, when used with an isolated DC-DC conversion stage [27]. They are ideal for renewable energy integration and traction systems. Commercial CHB converters are available in ABB, Arrow speed & Siemens (Perfect harmony). Fig. 2.3. Conventional H-bridge (3 Level, single phase) converter Table.2.2 Switching states of a single phase three level H-Bridge converter Voltage, VaN Switching states S1 S2 Vdc/2 1 0 0 0 0 0 1 1 - Vdc/2 0 0 Advantages of cascaded H-bridge inverters:  The modular structure or the multiple units of identical H-bridge power cell reduces the manufacturing cost.  The number of possible output voltage levels is more than twice the number of dc sources.  Less voltage THD and dv/dt when compared to two level converters operating at the same 6 voltage rating and switching frequency.  H-bridge cells are cascaded to produce high AC voltages, which eliminates the problem of equal voltage sharing for series-connected devices. Fig. 2.4. Five-level single phase H-bridge converter Table.2.3 Switching states of a Five level single phase H-Bridge Converter Voltage, VaN Switching states Individual cell output voltage S1 S2 S3 S4 Va1 Va2 2Vdc 1 0 1 0 Vdc Vdc Vdc 1 0 1 1 Vdc 0 0 0 1 1 1 0 0 Vdc 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 0 1 Vdc -Vdc 0 1 1 0 -Vdc Vdc -Vdc 0 1 0 0 -Vdc 0 1 1 0 0 0 1 0 -Vdc 1 1 -2Vdc 0 1 0 1 -Vdc -Vdc Disadvantage of cascaded H-bridge inverters:  A large number of separate dc sources are required for CHB, which are usually obtained from a multi-phase diode rectifier by employing an expensive phase shifting transformer. 2.1.3. FLYING CAPACITOR MULTILEVEL INVERTER The flying capacitors were first introduced by Meynard and Foch in 1992 [28]. As the name suggests, a capacitor is connected between the upper and the lower leg or between the two cells. In other words, the free-wheeling diodes in NPC are replaced by a capacitor. Figure 2.5 shows a three level single phase FC, which has two cells. Additional cells can be added to increase the number of output levels, but the nominal power of the converter remains the same. It is to be noted that for ‘m’ voltage level, flying capacitor needs 2(m-1) semiconductor switches, (m-1) DC bus capacitors and (m-1)(m-2)/2 number of balancing capacitors per phase. Table 2.4 shows the switching states of a three-level single phase FC. The phase redundancy switching state-zero voltage is used to control the floating capacitor voltage. A well-known commercial flying capacitor converter is Alstom VDM 6000. ABB’s ACS 2000 is an example of hybrid FCC, which is a combination of a 3L-ANPC and a FCC. 7 Advantages of flying capacitor inverters:  Unlike other inverters, switching combination redundancies even in inner voltage levels makes balancing the voltage levels of the capacitors easier and flexible with more switching combinations.  Real and reactive power flow can be controlled making a possible voltage source converter candidate for high voltage dc transmission [29], [30].  Large number of capacitors enables the inverter to ride through capabilities during power rage. Fig. 2.5. Three-level single phase flying capacitor converter Table.2.4 Switching states of a three level single phase FCC Voltage, VaN Switching states S1 S2 Vdc/2 1 1 0 1 0 0 0 1 -Vdc/2 0 0 Disadvantages of flying capacitor inverters:  Control is complicated to regulate the voltage levels for all of the capacitors. Also, precharging all of the capacitors to the same voltage level and startup are complex.  Inverter control will be very complicated and the switching frequency and switching losses will be high for real power transmission.  The large numbers of capacitors are both more expensive and bulky than clamping diodes in multilevel diode-clamped converters. Packaging is also more difficult in inverters with a high number of levels. Apart from the above topologies, there are Modular Multilevel Converter (MMC) [31], Cascaded Matrix Converter (CMC) [32], [33] and Neutral Point Piloted (NPP) converter [34]. There also exists symmetrical topologies like n-level Cascaded Cell Multilevel Converter (CCMC) [35], [36], which do not have a common dc link; instead they are made of stages, connected in series, which comprises two basic cells in parallel connection. These basic cells share a common DC source or capacitor. Asymmetric topologies also prevail, like Hybrid Multilevel Converter (HMC) [37] where different stages are connected in series, that has different values of DC voltages and Cascade Asymmetric Multilevel Converter (CAMC) [38], which is a combination of ANPC and FC. In the project work, the NPP or T-type inverter is used & the emphasis lies on it, which is discussed in chapter 3 in detail. 8 2.2. MODULATION SCHEMES The major modulation schemes are Pulse Width Modulation (PWM), Space Vector Modulation (SVM) & harmonic control. Focus on new and hybrid modulation schemes rely on encountering other issues like using less number of switches, optimizing output voltage control, solving the dc link capacitor voltage balancing problem, reducing or eliminating the harmonic contents, increasing robustness & fault tolerance capability, etc. Figure 2.6 shows the major modulation types in multilevel converters [39]. Fig. 2.6. Various modulation schemes for multilevel converters Pulse Width Modulation (PWM): The basic idea in PWM is to compare a reference signal with a carrier signal in order to obtain a constant frequency PWM signal, which is used as firing pulses for the semiconductor switches. Numerous developments in optimizing the PWM technique have been done since its inception [10]. In Bipolar PWM (Two level voltage case), a simple triangular carrier signal is compared with a sine reference and those overlapping with the upper and lower carrier signals are given as switching pulses to the lower and upper switches respectively. In Unipolar PWM (used for single phase, three level voltage converter) a triangular carrier signal is compared with two reference sine waves of 180⁰ shifted from each other. The switching pulses obtained from the positive sine wave overlapping are applied to one leg and the switching pulses obtained from the negative sine wave overlapping are applied to the other leg. In Phase shifted PWM (used for FCC or CHB converter) n-1 triangular carrier signals are used with optimal displacement 180⁰/m (where ‘n’ is the number of voltage levels and ‘m’ is the number of cells) are overlapped using a reference sine wave and the switching pulses are given to the converters. The number of carrier signals depends on the number of cells used. For example: In a three level FCC two carrier signals are used whereas in a four level FCC three carrier signals are used. In Level shift PWM the carrier signals are arranged in a vertical shift. For a m-level inverter, (m-1) carrier signals are needed. The below control logics are used in the level shifted PWM used for a three level converter:  If the reference is above the carriers the upper switches are turn on.  If the reference is between both carriers the output is connected to the neutral point.  If the reference is under both carriers the lower switches are turned on. In phase disposition, the carrier signals are aligned in a similar fashion, whereas in opposition disposition, the lower carrier signals are 180⁰ phase shifted from the upper signals, whereas 9 in alternate opposition disposition, the carrier signals are 180⁰ phase shifted from each other. Space Vector Modulation (SVM): The basic idea of SVM is to switch the semiconductor switches, by locating a reference signal on the Space Vector (SV) of appropriate level and finding the nearest switching vectors and their corresponding switching times. In a 2D SVM [11], the three phase reference is transformed to g-h coordinate system and the closest three vector are found and switched, whereas in a 3D SVM [12], a normalized phase voltage references are located in a three-dimensional space and the closed four vectors are switched. The feedforward 3D SVM [13] takes into account the actual dc-link capacitor voltage imbalance and uses a modulation scheme similar to 3D with slight changes. The 1DM for single phase multilevel converters uses the 1-D control region to identify the possible switching states and their duty cycles [40]. The multidimensional modulation technique is a generalized modulation scheme for cascaded multilevel converters, which determines the switching states on a multidimensional control region [41]. Here, the DC voltage control strategy is used on a 2D control region. One can consider the real values of dc-link capacitor voltages and extend the feedforward mD-PWM scheme for cascaded converters. (where m is the number of cells). In SVPWM technique, the reference voltage vector is resolved by timeaveraging with the nearest active switching vectors. In Multilevel multiphase SVPWM [42], the concept of permutation matrix is introduced, which determines the switching time of the switches. Hybrid multilevel modulation: Modified carrier-based PWM are used in Active NPCs, where n-1 triangular carriers are used which are phase-shifted by 90⁰(where n is the number of voltage level). Such modulation schemes are advantageous to balance the dc link capacitor voltages inherently in medium voltage power inverters. In 5L-ANPC a fundamental switching is used for ANPC cell and a phase-shifted PWM is used for the flying-capacitor cell [43]. Space vector control for multilevel converters: The basic idea of space vector control is when using multilevel inverters with high number of levels (which results in high space vector density) there is no need of modulation. Space vector control approximates the reference vector by the closest space vector generated by the inverter. The approximation is compensated by outer loop controllers and the inverter works with low switching frequency. Harmonic control: In Selective Harmonic Elimination (SHE) [44] the ‘n’ lower-order odd, nontriplen (non-multiple of 3) harmonics are eliminated by solving a set of m= n+1 equations for fundamental amplitude and ‘m’ angles. The Selective Harmonic Mitigation (SHM) [45] is based on SHMPWM, that generates switching three-level PWM patterns to meet grid codes with high quality from harmonic perspective, thereby avoiding the elimination of some specific harmonics. Later an optimized SHM [46] is identified by, which are applied to high power converters with low switching frequency. In both the cases the objective functions are optimized by algorithms like Genetic Algorithm (GA), simulated annealing, etc. The modulation schemes used in the project are 2D SVM, 3D SVM and 3D FFSVM, which are explained in detail in the chapter 4. 2.3. CONTROL STRATEGIES The control strategies comprise concepts like direct power control [47], [48], [49], Model Predictive Control (MPC) [50], [51], hysteresis/non-hysteresis control of current [52], using conventional controllers like PI [53], fuzzy PID [54], neural network & fuzzy logic methods 10 [55] etc. and other advanced control techniques. Most new works rely and emphasize on strategies like harmonics reduction, dc link capacitor voltage balancing, less computation effort, new efficient control methods, that can solve one or more other issues and increased system performance. For this, one has to undergo a modeling approach to the converter system which is discussed in detail in chapter 4. All these modeling strategies need a prior knowledge of fundamental Clarke [56] & Park [57] transformation. Both the transformations are basically used to simplify the analysis of three phase circuits. The Clarke’s transformation is used in the project, which facilitates the inclusion of the third control component i.e. the gamma (γ) or zero (0) component. This γ component is used to solve the dc link capacitor issue in the deterministic approach, which is discussed in detail in chapter 4. 11 CHAPTER 3 NEUTRAL POINT PILOTED (NPP) POWER INVERTER The Neutral Point Piloted converter [58], [59] or the T-type converter is an extension of the conventional two-level Voltage Source Converter (VSC) with an active bidirectional switch to the dc-link midpoint, which blocks only half of the dc link voltage. Figure 3.1 (a) shows the leg schematic of a three-level T-type power converter, whose bidirectional switches are conventional IGBTs. Hence, it can be implemented with devices having a lower voltage rating. Due to this feature, the converter shows very low switching losses, acceptable conduction losses and lower number of semiconductor devices, when compared to conventional topologies like NPC and FCC. Although the T-type converters were introduced during 1985 [60], owing to demand in rise of compact and efficient low power converters, various developments are made in these T-type converters to be more reliable and fault tolerant [61], [62]. Later these conventional AC switches were replaced by Reverse blocking IGBT (RBIGBT) [63] which has low switching losses and better reverse blocking capability. When seen from fabrication perspective, the module with RB-IGBT has only one pn-junction and this reduces the reverse recovery. Figure 3.1(b) shows the leg schematic of a three-level T-type power converter, whose bidirectional switches are RB-IGBT. Fig. 3.1. Leg schematic of a three-level T-type power inverter : (a) bidirectional switch with conventional IGBT, (b) bidirectional switch with RB-IGBT Table 3.1. Switching states of a single phase T-type converter Voltage, VaN Switching states T1 T2 T3 T4 Vdc/2 1 0 0 0 0 0 0 1 1 -Vdc/2 0 1 0 0 Fig. 3.2. Leg schematic of a single phase three level T-type converter 18 The predicted output calculated for values from j=1 to j=6 and is given by, =0++0E∆−1 with                     = 0490.01892.04039.06697.09589.02427.1 00490.01892.04039.06697.09589.0 000490.01892.04039.06697.0 0000490.01892.04039.0 00000490.01892.0 000000490.0 G;                     − − − − − − = 6743.131496.294752.16 9580.100958.241378.14 0446.83740.183294.11 2212.55385.123173.8 7756.21738.73982.5 9672.08369.28697.2 F;                     = ′ 6856.0 5494.0 4034.0 2618.0 1392.0 0485.0 G where 0′ is the matrix of coefficients of the right-most backward shift operator of Gj, where j takes the value 1 to Nh or N2 (prediction horizon). K = first row of TT GIGG 1 )( − + λ = first row of TT                                                               +                                        − 0490.01892.04039.06697.09589.02427.1 00490.01892.04039.06697.09589.0 000490.01892.04039.06697.0 0000490.01892.04039.0 00000490.01892.0 000000490.0 100000 010000 001000 000100 000010 000001 95.0 0490.01892.04039.06697.09589.02427.1 00490.01892.04039.06697.09589.0 000490.01892.04039.06697.0 0000490.01892.04039.0 00000490.01892.0 000000490.0 0490.01892.04039.06697.09589.02427.1 00490.01892.04039.06697.09589.0 000490.01892.04039.06697.0 0000490.01892.04039.0 00000490.01892.0 000000490.0 1 = first row of                     −−−−− −−−−− −−−− −−−− −− 0256.00172.00099.00048.00017.00003.0 0817.00274.00467.00230.00084.00017.0 1349.00001.00688.00609.00230.00048.0 1654.00485.00334.00688.00467.00099.0 1646.01061.00485.00001.00274.00172.0 1317.01646.01654.01349.00817.00256.0 K= ( ) 1317.01646.01654.01349.00817.00256.0 Expression for control law is given by, )()( fwKtu − = ∆ = ( )                                         −+−−+−∆ −+−−+−∆ −+−−+−∆ −+−−+−∆ −+−−+−∆ −+−−+−∆ −                     + + + + + + )2(6743.13)1(1496.29)(4752.16)1(6856.0 )2(9580.10)1(0958.24)(1378.14)1(5494.0 )2(0446.8)1(3740.18)(3294.11)1(4034.0 )2(2212.5)1(5385.12)(3173.8)1(2618.0 )2(7756.2)1(1738.7)(3982.5)1(1392.0 )2(9672.0)1(8369.2)(855.2)1(0485.0 )6( )5( )4( )3( )2( )1( 1317.01646.01654.01349.00817.00256.0 tytytytu tytytytu tytytytu tytytytu tytytytu tytytytu tw tw tw tw tw tw 19 = ( )                     −−−+−−∆−+ −−−+−−∆−+ −−−+−−∆−+ −−−+−−∆−+ −−−+−−∆−+ −−−+−−∆−+ )2(6743.13)1(1496.29)(4752.16)1(6856.0)6( )2(9580.10)1(0958.24)(1378.14)1(5494.0)5( )2(0446.8)1(3740.18)(3294.11)1(4034.0)4( )2(2212.5)1(5385.12)(3173.8)1(2618.0)3( )2(7756.2)1(1738.7)(3982.5)1(1392.0)2( )2(9672.0)1(8369.2)(855.2)1(0485.0)1( 1317.01646.01654.01349.00817.00256.0 tytytytutw tytytytutw tytytytutw tytytytutw tytytytutw tytytytutw =                     −−−+−−∆−+ +−−−+−−∆−+ +−−−+−−∆−+ +−−−+−−∆−+ +−−−+−−∆−+ +−−−+−−∆−+ )2(80090531.1)1(83900232.3)(16978384.2)1(09029352.0)6(1317.0 )2(8036868.1)1(96616868.3)(32708188.2)1(09043124.0)5(1646.0 )2(33057684.1)1(0390596.3)(87388276.1)1(06672236.0)4(1654.0 )2(70433988.0)1(69144365.1)(12200377.1)1(03531682.0)3(1349.0 )2(22676652.0)1(58609946.0)(44103294.0)1(01137264.0)2(0817.0 )2(02476032.0)1(07262464.0)(073088.0)1(0012416.0)1(0256.0 tytytytutw tytytytutw tytytytutw tytytytutw tytytytutw tytytytutw )(tu ∆ =         +++++++++++ +−−−+−−∆− )6(1317.0)5(1646.0)4(1654.0)3(1349.0)2(0817.0)1(0256.0 )2(89103567.5)1(19439835.13)(00687319.8)1(29537818.0 twtwtwtwtwtw tytytytu Note: A similar calculation is carried out for prediction horizons 5, 7, 8 & 9 with a range of weighting factors λ and the comparison is made to extract the one with best pair of weighting factors and prediction horizon. The output of GPC yields to the control component δαβ, which is used as reference for modulation. 4.2. T-TYPE INVERTER SYSTEM WITH INDIVIDUAL VOLTAGE SOURCES In this case separate dc voltage sources of each 200 V is used at the dc link instead of capacitors, so that there is no necessity of using a separate control strategy for balancing the dc link capacitor voltages. Figure 4.2 shows the block diagram of the T-type inverter system, when individual dc voltage sources are used. The control signal δabc, obtained from the GPCstrategy, discussed in the section 4.1 is first transformed to δαβ, which is then transformed to δgh using the transformations (17) & (18) and normalized to H IJ , where n(=3) is the number of levels of the inverter & vdc (=vdc1+vdc2=400 V) is the DC source voltage. It is to be noted that as δγ is not needed here in the case of T-type inverter system with individual voltage sources. Hence, it is neglected. KLMN OPQ=R A S T T T U 1 − −  0√A −√A   √ √ √ W X X X Y (17) KOP Z[=\1 √A 0 √A] (18) (17) is the power variant form of Clarke’s transformation, where the gain isR A. In ordinary Clarke’s transformation the gain is 2/3. In order to make the transformation matrix unitary i.e. 20 the inverse matrix coincides with its transpose and to preserve the active and reactive power one has to consider power invariant form of Clarke’s transformation. Fig. 4.2. Block diagram of the T-type inverter system with separate dc voltage sources Once the control signal (or reference for modulator), δgh is obtained, it is sent to the modulator to get the firing pulses for the semiconductor switches. The modulation strategy used here is two-dimensional SVM [11]. This involves finding the nearest three coordinates in the two-dimensional space vector coordinate system and switching the corresponding vectors, with their respective duty cycles. It is done by rounding the values and doing a simple comparison in the two dimensional coordinate system. After finding the diagonal vectors of the parallelogram, another simple comparison is done to find if the reference, δgh is in the upper triangle or in the lower triangle, as shown in the figure 4.3. Once all the three coordinates in the g-h coordinate system are obtained, the duty cycles are computed and the switching pulses are generated for the IGBT switches. Figure 4.4 shows the 2D SVM algorithm. Fig. 4.3. Parallelogram comprising two equal triangles 21 Fig. 4.4. Two dimensional Space Vector Modulation algorithm It is to be noted that the two dimensional SVM is very fast and computationally efficient, which can be extended to n-level three phase converters. Figure 4.5 shows the reference and the actual output voltage of GPC control during simulation, which reveals the efficiency in tracking the reference and the performance of GPC to tackle the mismatch of model parameter. Fig. 4.5 Output voltage-reference and controlled waveforms for the T-type inverter system with individual dc voltage sources 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 -200 -100 0 100 200 Time (ms) v ca & v ca * (V) vca vca * 22 4.3. T-TYPE INVERTER SYSTEM USING INDIVIDUAL DC LINK CAPACITORS In this case the dc sources are replaced by separate dc link capacitors and this needs a separate control strategy for balancing the dc link capacitor voltages. The efficiency of the control strategy relies on system performance parameters like computational effort, harmonic reduction and good tracking of the output voltage. There are two dc link capacitor voltage balancing approaches i.e. the redundancy approach and the deterministic approach, whose performances are simulated and compared. 4.3.1. REDUNDANCY DC LINK CAPACITOR VOLTAGE BALANCING APPROACH In this approach, an extra redundancy block is used, that facilitates a simple static comparison [70], [71], [72] of the dc link capacitor voltages and current as shown in the figure 4.6. According to this comparison result, the redundancy of the inner level switching vectors in a three level converter is used and appropriate switching is done as shown in the table 4.4. Figure 4.7 shows the possible switching states of a three level converter. The inverter has three states per phase and as there are three phases, 33=27 different switching states exists. It is to be noted that the redundancy exists in the inner level vectorsV1, V2, V3, V4, V5 & V6 in a three level space vector. For exampleconsider the vector V7 (+, 0, -), which denotes that, phase a is connected to the positive terminal, phase b is connected to the dc link mid-point and phase c is connected to the negative terminal. In zero vector (V0) the magnitude of voltage is 0V. In the internal vectors (V1 to V6) the magnitude of voltage is IJ A V. The middle vectors (V7 to V12) have magnitude of IJ √AV, whereas the external vectors (V13 to V18) have the magnitude of IJ √AV. Fig. 4.6. Block diagram of the T-type inverter system with redundancy dc link capacitor voltage balancing approach Table 4.4 Redundancy control strategy to balance the dc link capacitor voltages Voltage imbalance DC link current Internal redundancy (vc1-vc2) < 0 idc < 0 Positive redundancy (0) idc > 0 Negative redundancy (1) (vc1-vc2) > 0 idc < 0 Negative redundancy (1) idc < 0 Positive redundancy (0) 23 Fig. 4.7. Switching state vectors of a three level converter It is to be noted that a two-dimensional SVM is used, as discussed in the section 4.2. The GPC strategy used is the same as the one discussed in section 4.1. On performing a series of simulation experiments, it is found that the GPC performs well when prediction horizon, Nh=6 and weighting factor, λ=0.242. This performance of the system is assessed by the Root Mean Square (RMSerror) and Total Harmonic Distortion (THD) values, which are discussed in section 4.4. The RMSerror is given by, ^_`aaba%=defJ,ghJJ,ghJ ∗ J,ghJ ∗|def ×100 % where /N,LMN is the actual output voltage /N,LMN ∗ is the reference output voltage & /N,LMN ∗|^_` is the RMS voltage reference =120 V, 50 Hz Fig. 4.8 DC link capacitor voltages vc1 & vc2 balanced by redundancy approach with initial imbalance condition 0 0.1 0.2 0.3 0.4 100 150 200 250 300 Time (ms) v c1 & v c2 (V) vc1 vc2 24 Fig. 4.9 Output voltage-reference and controlled waveforms for Redundancy approach Fig. 4.10 DC link capacitor voltages vc1 & vc2 for redundancy approach Figure 4.8 shows that an initial imbalance condition of dc link capacitor voltages is enforced and after some time instant the redundancy approach is activated. The capability of the approach to handle the imbalance situation and balance it later within the given stipulated time is observed. Figure 4.9 shows the GPC tracking the output reference voltage. Figure 4.10 depicts the balanced dc link capacitor voltages. Although this approach is simple with less computational efforts, it has its own drawbacks like high RMSerror values and THD values of the output voltage & existence of lower order harmonics in the dc link capacitor voltage difference which are overcome by the deterministic dc link capacitor voltage balancing approach. The comparisons of these strategies are discussed in detail in section 4.4. 4.3.2. DETERMINISTIC DC LINK CAPACITOR VOLTAGE BALANCING APPROACH Two serious problems in NPC and NPP converters are the capacitor voltage balancing issue and the sinusoidal disturbances in the dc link capacitors during switching. Such disturbances have pulled researcher’s interest, which are encountered by basic control system design. Although many dc link capacitor voltage balancing approaches were found in literature [73], [74], still focus prevails on eradicating other issues along with balancing dc link capacitors. The control component, δγ serves a freedom degree for solving the capacitor voltage imbalance and the reduction of the low-frequency oscillations. The deterministic approach of dc-link capacitor voltage balancing approach is based on using a state observer, called Luenberger observer [75], which estimates the sinusoidal oscillation at each sampling instant and minimizes certain level of lower order harmonics of dc link capacitor voltage difference, thereby regulating the dc link capacitor voltages [18]. The application of such control strategy couldn’t be possible unless we model the converter and derive the phase current dynamics and the dc link capacitor voltage difference dynamics, which are effectively used in the deterministic approach [76]. Such parameter aids the controller and observer to keep the output voltage to go allied with the deterministic control approach. The block diagram consists mainly of an output voltage control block (GPC), dc link capacitor voltage balancing block and the modulation block, which is depicted in the figures 4.11 & 4.12. The difference between these two figures is, in 3D FFSVM the real values of the dc link capacitor voltages are considered, which is discussed in detail in the modulation part of this section. 0 0.02 0.04 0.06 0.08 -200 -100 0 100 200 Time (ms) v ca & v ca * (V) v ca v ca * 0 0.1 0.2 0.3 0.4 185 190 195 200 205 210 215 Time (ms) v c1 & v c2 (V) v c1 v c2 25 Fig. 4.11. Block diagram of deterministic dc link capacitor voltage balancing approach using 3D SVM Fig. 4.12. Block diagram of deterministic dc link capacitor voltage balancing approach using 3D FFSVM In order to model the converter, the three level equivalent circuit model of T-type power inverter is considered with the ideal switches [77], as shown in the figure 4.13. Table 4.5 Model parameters used in the equivalent ideal switch Variable Description vdc Source voltage idc dc-link current C1, C2 dc-link capacitance L Filter inductance Cf Filter capacitance idc1, idc2, idc3 Currents at top, middle and bottom connection points of capacitors vabc Injected voltage referred to ‘B’ iabc Inductor currents δabc Switching position RL Load resistance LL Load inductance 26 Fig. 4.13. Equivalent circuit of a 3L T-type converter with ideal switches Table 4.5 shows the model parameters of the equivalent ideal switch. By applying KCL, idc1 + ic1 = idc → idc1 = idc – ic1 (19) idc2 + ic2 = ic1 → idc2 = ic1 – ic2 (20) idc3 + idc = ic2 → idc3 = ic2 – idc (21) idc1+idc2+idc3 = 0 (22) where C1 = C2 = C dt dv C=i 1c 1C dt dv C=i 2c 2C Subtracting equation (19) from (21), dc 2i+ii=i+i 1dc3dc2c1c - (23) (20) → dc2 i- =ii 2c1c A relationship between the currents idc1k, idc2k, idc3k in terms of the three possible switch positions δk and for every k ϵ {a, b, c} is established, where idc1k, idc2k, idc3k are the input current flowing towards the switches from the dc link capacitors connected to a DC voltage source as shown in the figure 4.13. Thus, for a given k ϵ {a, b, c} three points are known, and a quadratic function relating idc1k, idc2k, idc3k and δk can be designed to fit all three points as shown in table 4.6. Note: The above equivalent circuit is similar for a three level converter, in general. 27 Table 4.6 Resolving the input currents flowing towards the switches into quadratic function 2 iδ )1+δ(=i kk kk1dc for k ϵ {a, b, c} kk2dc i)δ1(=i 2 k - for k ϵ {a, b, c} 2 iδ )δ(=i kk kk3dc 1for k ϵ {a, b, c} j N    ! L  1  k g l g                 ! M  1  khlh                 ! N  1  kJlJ  (24) j N    1  ! L   j L                1  ! M   j M   1  ! N   j N !LjL!MjM!NjN (25) Since j L  j M  j N  0 j N A   ! L  1  k g l g                 ! M  1  khlh                 ! N  1  kJlJ  (26 ) Substituting (24), (25) & (26) in (20) & (23) , m+  J+  J)  !LjL!MjM!NjN2jN (27) m)  J+  J)  !LjL!MjM!NjN (28) where x2 = vc1-vc2 & x1 = vc1+vc2 Applying power invariant form of Clarke’s transformation (17) to (27) & (28), (27)→ no!LMN pjLMN2jN no1K!OPQ2pKjOPQ2jN no!OP pjOP2jN As jLjMjN0→ jQ0, the gamma component is removed. As the value no becomes zero, since /N/N is always constant, the above equation can be written as, qrstuv wquv x (29) (28)→no#!L!M!N'jLMN no#!L!M!N'KjOPQ noRA#!L1kh )ykJ)2 √A !M!N √!L!M!N'jOPQ z{ox| √}3tu xtv xxtutv<quvx √~ttv wquvt (30) where  34 This is done by comparing the position of elements in Von and Vs vectors. For example, for phase a if Oa=0 and Osa=δ1, as these values occupy the 1st and 2nd position in Von vector, the same positioned values of Vs vectors gives the corresponding switching state. So, in the above example the 1st and 2nd position in the Vs vectors are 0 and 1. So, Opa=0 & OSpa=1 are the switching state for phase a in the particular example discussed. Figure 4.20 shows the 3D-feedforward SVM algorithm for selection of sub-prism. It is to be noted that, in 3D feed forward SVM, the second order harmonic distortion and the Total Harmonic Distortion (THD) are quickly and drastically reduced to lower values even when using a lesser voltage imbalance. It is also to be significantly noted that, in 3D feed forward SVM, the dynamic response achieves the same good operation compared to the steady state response. This paves a way to reduce the capacitance of the dc link capacitance, as possible oscillations and imbalance of the dc voltage values will not affect the output voltages and currents of the converter. Fig. 4.20. 3D-feedforward SVM algorithm for selection of each subprism for corresponding state vectors Table 4.8 State sequence & switching times for 3D-FFSVM 35 Simulation results of deterministic dc link capacitor voltage balancing approach using 3D FFSVM also depicts improved GPC performance. Figure 4.21 shows the dc link capacitor voltages when an initial imbalance condition is enforced. Here =0.5, l=525, ´=25 & N=0.1. As there are few transients initially, a perfect tuning procedure can be done to obtain a less settling time. Figure 4.22 depicts the output voltage tracked with the reference and figure 4.23 shows the dc link capacitor voltages. Fig. 4.21 DC link capacitor voltages vc1 & vc2 balanced by deterministic approach using 3D FFSVM with initial imbalance condition Fig. 4.22 Output voltage-reference and controlled waveforms for deterministic approach using 3D FFSVM Fig. 4.23 DC link capacitor voltages vc1 & vc2 for deterministic capacitor voltage balancing approach using 3D FFSVM 0 0.5 1 1.5 160 180 200 220 240 Times (ms) v c1 & v c2 (V) vc1 vc2 0.01 0.02 0.03 0.04 0.05 0.06 -200 -100 0 100 200 vca vca * 0 0.1 0.2 0.3 0.4 0.5 0.6 185 190 195 200 205 210 215 v c1 & v c2 (V) Time (ms) v c1 v c2 Ca ses Space vector sequence Switching times Sa Sb Sc 1 2 3 4 1 2 3 4 1 2 3 4 D1 D2 D3 D4 A Oa OSa OSa OSa Ob Ob Ob OSb Oc Oc OCa OCa 1-μa μa-μc μc-μb μb B Oa Oa OSa OSa Ob Ob Ob OSb Oc OCa OCa OCa 1-μc μc-μa μa-μb μb C Oa Oa a OSa Ob Ob OSb OSb Oc OCa OCa OCa 1-μc μc-μb μb-μa μa D Oa Oa a OSa Ob OSb OSb OSb Oc Oc OCa OCa 1-μb μb-μc μc-μa μa E Oa Oa OSa OSa Ob OSb OSb OSb Oc Oc Oc OCa 1-μb μb-μa μa-μc μc F Oa OSa OSa OSa Ob Ob OSb OSb Oc Oc Oc OCa 1-μa μa-μb μb-μc μc 36 4.4. COMPARISON OF THE DC LINK CAPACITOR VOLTAGE BALANCING APPROACHES The simulation results for comparing various dc link capacitor voltage balancing strategies comprises both the single-sided amplitude frequency spectrum of the dc link capacitor voltage differences and the RMSerror-cum-THD values for deterministic and the redundancy approaches which are depicted below. The harmonics in the dc link capacitor voltage difference are observed for all the three approaches i.e. redundancy, deterministic-using 3D SVM and deterministic using 3D FFSVM. A set of simulations are performed for different values of weighting factor, λ and prediction horizon, Nh and the results of both RMSerror and THD are compared for the redundancy and the deterministic approaches. RMSerror is given by, ^_`aaba%  defJ,ghJJ,ghJ ∗ J,ghJ ∗|def ×100 % where /N,LMN is the actual output voltage /N,LMN ∗ is the reference output voltage & /N,LMN ∗|^_` is the RMS voltage reference =120 V, 50 Hz Fig. 4.24 Single sided amplitude frequency spectrum of n /N − /N for redundancy capacitor voltage balancing approach Fig. 4.25 Single sided amplitude frequency spectrum of n /N − /N for deterministic capacitor voltage balancing approach using 3D SVM Fig. 4.26 Single sided amplitude frequency spectrum of n /N − /N for deterministic capacitor voltage balancing approach using 3D FFSVM 0 100 200 300 400 500 600 700 800 900 1000 0 2 4 6 8 10 12 14 Frequency (Hz) |x 2 (f)| (V) 0 100 200 300 400 500 600 700 800 900 1000 0 2 4 6 8 10 12 14 Frequency (Hz) |x 2 (f)| (V) 0 100 200 300 400 500 600 700 800 900 1000 0 2 4 6 8 10 12 14 Frequency (Hz) |x 2 (f)| (V) 37 Fig. 4.27 A zoom preview of single sided amplitude frequency spectrum of n /N − /N for deterministic capacitor voltage balancing approach using 3D SVM Fig. 4.28 A zoom preview of single sided amplitude frequency spectrum of n /N − /N for deterministic capacitor voltage balancing approach using 3D FFSVM Fig.4.29 RMSerror values between the reference and the measured output voltages for different values of prediction horizons and weighting factors using redundancy and deterministic (3D SVM) approaches Fig.4.30 THD values of measured output voltages for different values of prediction horizons and weighting factors using redundancy and deterministic (3D SVM) approaches Simulation results reveal that, in deterministic approach, there is fair reduction of low frequency ripples in the single-sided amplitude frequency spectrum of the dc link capacitor voltage difference, which are shown in the figure 4.24, 4.25 & 4.26. These low frequency ripples are caused by the switching of the dc link capacitors. In order to have a better comparative view, the figures 4.27 & 4.28 are depicted, which shows a zoom preview of the single-sided amplitude frequency spectrum of the dc link capacitor voltage difference of deterministic approach using 3D SVM and 3D FFSVM. The simulation results also reveal that the deterministic approach of capacitor voltage balancing has low RMSerror and THD values, than the redundancy approach, which are depicted in the figure 4.29 & 4.30. It is to be noted that in figures 4.29 and 4.30 the 3D SVM is used in the deterministic approach. 0 100 200 300 400 500 600 700 800 900 1000 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Frequency (Hz) |x 2 (f)| (V) 0 100 200 300 400 500 600 700 800 900 1000 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Frequency (Hz) |x 2 (f)| (V) 56789 0 1 2 0 2 4 6 Prediction horizon(N h ) Weighting factor( λ λλ λ ) Error(% ) Redundancy approach Deterministic approach 56789 0 1 2 0 1 2 3 Prediction horizon(N h ) Weighting factor( λ λλ λ ) THD(%) Redundancy approach Deterministic approach 38 CHAPTER 5 DESIGN OF A NPP POWER INVERTER The foremost step in designing the prototype of NPP power inverter is evaluating the IGBT module. The main components used in this process are the Digital Signal Processor (DSP) device (TMS320F28335), IGBT driver board & its I/O connectors, IGBT module, a resistive load (say 300 Ω), a Cathode Ray Oscilloscope (CRO), a computer/laptop with installed Code Composer Studio (CCS) , regulated DC power source for converter input, a 15 V DC power source for IGBT driver board and few connecting wires. Figure 5.1 shows the block diagram of the main components including Integrated Circuits (ICs) & connectors and their connections for the NPP module evaluation. The switching pulses across the gate-emitter terminal and the output voltage across the load resistor are observed by CRO during evaluation. Although the IGBT driver is used to drive two modules in parallel, only one module (single mode operation) is used for evaluation purpose. The main aim of the evaluation of the AT-NPC 3-level 4in1 IGBT module [79] is to ensure, that the PWM pulses (T1, T2, T3 and T4), which are generated by the DSP properly fires the semiconductor switches in the IGBT module, via the IGBT driver board and the output voltage is checked across the load resistor. Fig. 5.1. Block diagram consisting of main components, ICs & connectors for the NPP module evaluation Circuit arrangement, description & working The DSP TMS320F28335 is programmed to produce the gate signals with switching frequency-2kHz, Vpeak-to-peak=3.44 V (0-3.44 V switching pulse) and duty cycle-50 % based on the switching modes, shown in table 5.1, in which ‘ON’ represents a full pulse with 100 % duty cycle, ‘OFF’ represents the switching pulse with 0% duty cycle and ‘SW’ represents a switching pulse of user’s choice of duty cycle (as the purpose is evaluation of the prototype). Enhanced Pulse Width Modulator (ePWM) 1-6 refers to six pins in the General Purpose Input/Output (GPIO) of the DSP device [80], specially designed for taking the PWM signals to the driver, once it is programmed in Code Composer Studio (CCS) [81], installed in a 39 computer or laptop. ePWM1A (at GPIO0) is used as T1, ePWM1B (at GPIO1) is used as T2, ePWM3A (at GPIO4) is used as T3 and ePWM3B (at GPIO5) is used as T4. Fig. 5.2. Circuit arrangement showing DSP connected to the IGBT driver board Table 5.1 Switching modes of AT-NPC 3level IGBT module (a three level NPP converter leg) SW mode A1 B1 A2 B2 T 1 SW OFF OFF OFF T 2 OFF OFF SW OFF T3 OFF SW ON ON T 4 ON ON OFF SW Table 5.2 Pin configuration of Input connectorsCN1 & CN101 for each IGBT driver board Pin Signal Connector 1 PWM signal for high side IGBT(T 1 ) CN1 2 PWM signal for RB - IGBT(T 4 ) CN1 3 PWM signal for RBIGBT(T 3 ) CN1 4 PWM signal for low side IGBT(T 2 ) CN1 5 GND CN1 6 GND CN1 7 GND CN1 8 GND CN1 9 GND CN1 10 Fault detection output IGBT (T 1 , T 2 ) CN1 1 VDC (15 V) CN101 2 NC CN101 3 GND (0 V) CN101 40 The four switching pulses obtained from DSP are sent to the IGBT driver board via the connector CN1. The driver board is powered by a 15 V DC source via CN101. The pin configuration of these two connectors i.e. CN1 & CN101 are furnished in the table 5.2. The foremost components where the PWM signals enter the IGBT driver board via CN1 connector are the Complementary MOSFET (CMOS) inverters (2 no.s) [82], which provides a buffered output with high noise immunity and stable output. These components are followed by optocouplers (4 no.s), which are used to drive, turn-on and off the power semiconductor switches. These dual outputs driven optocoupler (ACPL-339J) [83] contains a AlGaAs LED each, which is optically coupled to an integrated circuit with two power output stages with active timing control to prevent cross conduction at external MOSFET buffer. It is also integrated with features such as VCE detection, under voltage lockout (UVLO), ‘soft’ IGBT turn-off and isolated open collector fault feedback to provide maximum circuit protection and integrity. It is also noted that the DESAT protection is the highlighting feature of these type of optocouplers, which makes turns off the IGBT shortly whenever a DESAT (or short circuit) fault is detected. These optocouplers are followed by the ultralow resistive dual N and P channel MOSFETs (4 no.s) [84], which deliver superior power density and lower switching losses to shrink the PCB size and improve the overall system efficiency. These MOSFETs are combined with excellent thermal performance and low on-state resistance. There is a common mode choke to ensure protection between the MOSFET and the output terminal connectors-CN2, CN3, CN4, CN5, CN6 & CN7 of the IGBT drivers. Table 5.3 shows the pin configuration of these connectors. Figure 5.3 shows the connections between the output terminal of the IGBT driver and the connectorsCN8, CN9 & CN10. These connectors have space for components like active clamp and resistors, which are used for protection during short circuit. These connectors are mounted on the IGBT module. It should be noted that the active clamp diode are not initially connected, as only few IGBT module needs it. There is a DC/DC converter in the left end of the board, which ensures appropriate power supplies to the ICs. During single mode operation (connecting only one IGBT module) the common mode choke area is short circuited and the connector CN3 should not be used. Either of the connectorsi.e. CN5 or CN4 and CN6 or CN 7 can be used during single mode operation. Care should be taken that the IGBT is not operated without connecting T1C and T1 collector terminal. Table 5.3 Pin configuration of Output connectorsCN2, CN3, CN4, CN5, CN6 & CN7 for each IGBT driver board Pin Connector Remarks Remarks 1 CN2/CN3 RB-IGBT Gate (T4G) connected to CN8-1 2 CN2/CN3 high side IGBT & RB-IGBT Emitter (T1/T4E) connected to CN8-2 3 CN2/CN3 high side IGBT Gate (T1G) connected to CN8-3 4 CN2/CN3 No Connection - 5 CN2/CN3 No Connection - 6 CN2/CN3 high side IGBT Collector (T1C) connected to CN8-6 1 CN4/CN5 low side IGBT Emitter (T2E) CN1 2 CN4/CN5 low side IGBT Gate (T2G) CN1 1 CN6/CN7 RB-IGBT Emitter (T3E) CN1 2 CN6/CN7 RB-IGBT Gate (T3G) CN1 41 Figure 5.3 Connection between the output terminals of IGBT driver board and the connectors-CN8, CN9 & CN10 Drivers and First Fault Detection (FFD) Initially, the components shown in table 5.4 are detected to be not working, since the components outputs are not the desired one, which varied from those of the working drivers. Table 5.4 List of Faulty components during FFD Fig. 5.4 IGBT Driver 1 IGBT Drivers Number of Optocouplersnot working Number of MOSFETnot working Driver 1 - - Driver 2 2 (for T4 and T1) 1 (for T2) Driver 3 1 (for T2) - 42 Fig. 5.5 IGBT Driver 2 Fig. 5.6 IGBT Driver 3 Fig.5.7 Faulty Optocoupler’s High side voltage output Fig.5.8 Faulty Optocoupler’s Low side voltage output Progress of work in fixing the Drivers i. When the faulty optocoupler (T2) in driver 3 is replaced with the one of the working optocouplers of driver 2, the same results were observed as shown in figure 5.7 & 5.8. During this process, the soldering station is used to unsolder the IC and the temperature of the soldering station ranges from 200-450 °C. So, the replaced optocouplers are suspected to have damaged LED during this replacement process. ii. After replacing a new MOSFET at T2 in driver 2, still the same results were obtained. Now, when checking the resistor, R36 (10 Ω) at the output of the MOSFET, it has been observed that the resistance value is too high in kΩs (open-circuited). When the resistor R36=10 Ω is replaced, the T2 of driver 2 works well. So, now the T2 of driver 2 is fixed. 43 A= C5, C7, C9, C11 (1 μF) B= C6, C8, C10, C12 (10 μF) C= C13, C14, C15, C16 (1 μF) VE= Common (IGBT Emitter) output supply voltage VCC2= Positive output supply voltage VEE= Output supply voltage Fig.5.9 Optocoupler secondary side power supplies-outline iii. When the new optocouplers of T1 and T4 of driver 2 & T2 of driver 3 are replaced, same results were obtained. Now, the voltage supplies of the optocoupler are examined and found that the voltage across VCC2-VE is not the desired value. Table 5.5 shows the rating of the output side power supply of the optocoupler and table 5.6 shows the observed values in the faulty optocouplers. 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