A Generalized Predictive Controlled T-type power inverter with a deterministic dc-link capacitor voltage balancing approach

A Gene alized P edic i e Con olled T- ype Powe In e e wi h a de e minis ic dc-link capaci o ol age balancing app oach A PROJECT REPORT Submi ed by CHARANRAJ MOHAN In he pa ial ul illmen o he awa d o he deg ee o MASTER in ELECTRONICS, SIGNAL PROCESSING & COMMUNICATION ESCUELA TECNICA SUPERIOR DE INGENIERIA UNIVERSIDAD DE SEVILLA SEVILLE 41092 JULY 2015 ACKNOWLEDGEMENT Fi s and o emos , I since ely hank ou belo ed di ec o P o . Jaime Dominguez Abascal, depu y di ec o o s udies, P o . F ancisco Rod iquez Rubio, Sec e a y, P o . F ancisco Ja ie Gu ie ez O iz and head o he elec onics enginee ing depa men , P o . An onio Jesus To alba Silgado o Escuela Supe io de Ingenie ia, Uni e si y o Se ille a his high ime o p o iding he necessa y acili ies o comple e my p ojec success ully. I would like o exp ess my since e hanks o he HERITAGE conso ium- eam and i s coo dina o s o p o iding me an oppo uni y o do Mas e s unde he HERITAGE-E asmus Mundus p ojec . I am g a e ul o P o . Leopoldo Ga cia F anquelo, Depa men o Elec onics Enginee ing o his ancho ing suppo and guidance in doing his p ojec . I exp ess my since e hanks o Associa e P o . Se gio Vazquez, Associa e P o . Jose Ignacio Leon Gal an and M . Ab aham Ma quez om he depa men o Elec onics Enginee ing o hei cons an guidance, high pa ience, cons uc i e c i icism and encou agemen h oughou he p ojec wo k. I also hank all he eaching, non- eaching s a s, iends, colleagues and amily who had di ec ly and indi ec ly helped in b inging ou he p ojec in a success. CHAPTER NO. TITLE PAGE NO. ABSTRACT i LIST OF TABLES ii LIST OF FIGURES i LIST OF ABBREVATIONS iii 1. INTRODUCTION 1 2. MULTILEVEL INVERTERS 3 2.1. INVERTER TOPOLOGIES 4 2.1.1. NEUTRAL POINT CLAMPED MULTILEVEL INVERTER 4 2.1.2. CASCADED H-BRIDGE INVERTER 5 2.1.3. FLYING CAPACITOR MULTILEVEL INVERTERS 6 2.2. MODULATION SCHEMES 8 2.3. CONTROL STRATEGIES 9 3. NEUTRAL POINT PILOTED (NPP) POWER INVERTER 11 4. SYSTEM DESCRIPTION, MODELING & CONTROL DESIGN 13 4.1. GPC STRATEGY FOR OUTPUT VOLTAGE CONTROL 13 4.2. T-TYPE INVERTER SYSTEM WITH INDIVIDUAL VOLTAGE SOURCES 19 4.3. T-TYPE INVERTER SYSTEM USING INDIVIDUAL DC LINK CAPACITORS 22 4.3.1. REDUNDANCY DC LINK CAPACITOR VOLTAGE BALANCING APPROACH 22 4.3.2. DETERMINISTIC DC LINK CAPACITOR VOLTAGE BALANCING APPROACH 24 4.4. COMPARISON OF THE DC LINK CAPACITOR VOLTAGE BALANCING APPROACHES 36 5. DESIGN OF A NPP POWER INVERTER 38 6. ADVANTAGES & APPLICATIONS 47 7. CONCLUSION & FUTURE WORK 48 8. REFERENCES 49 i ABSTRACT The hesis consis s o implemen ing a Gene alized P edic i e Con ol (GPC) s a egy o con olling he ou pu ol age o he T- ype con e e wi h ou pu LC il e , whose con ol signals a e modula ed by a as h ee-dimensional Space Vec o Modula ion (SVM). The GPC s a egy used o he T- ype con e e in ol es de eloping a sys em o dynamic equa ions om he ou pu LC il e and load, which is ans o med o a Con olled Au o-Reg essi e and Mo ing-A e age (CARIMA) model in o de o ob ain a sequence o con ol signals, so ha a cos unc ion is op imized and he e e ence is acked. The co e o he hesis add esses he main p oblem o dc-link capaci o balancing. This is done by modeling he con e e and deploying a ma hema ical analysis o he capaci o ol age di e ence dynamics, by singula pe u ba ion app oach. This analysis esul s in an explici sinusoidal dis u bance. Now, classical con ol heo y is applied by using a Luenbe ge Obse e (LO) in o de o es ima e he dis u bance and encoun e i , he eby keeping he dc-link capaci o ol age balanced in he due low o he modula ion and ou pu ol age con ol. By his me hod, he ou pu ol age ac oss he il e capaci o is con olled, he dc-link capaci o ol age is balanced and he low- equency ol age ipples p esen in he dc-link o he T- ype con e e a e educed o an accep able le el. ii LIST OF TABLES TABLE DESCRIPTION PAGE NO. Table 2.1 Swi ching s a es o a Th ee le el single phase NPC 4 Table 2.2 Swi ching s a es o a single phase h ee le el H- B idge con e e 5 Table 2.3 Swi ching s a es o a Fi e le el single phase H- B idge Con e e 6 Table 2.4 Swi ching s a es o a h ee le el single phase FCC 7 Table 3.1 Swi ching s a es o a single phase T- ype con e e 11 Table 4.1 Sys em Va iables and Pa ame e s 16 Table 4.2 Model & Simula ion Pa ame e s o GPC 16 Table 4.3 GPC ecu si e polynomial calcula ion ac oss ho izons 17 Table 4.4 Redundancy con ol s a egy o balance he dc link capaci o ol ages 22 Table 4.5 Model pa ame e s used in he equi alen ideal swi ch 25 Table 4.6 Resol ing he inpu cu en s lowing owa ds he swi ches in o quad a ic unc ion 27 Table 4.7 Space ec o sequence & swi ching imes o 3D- SVM 32 Table 4.8 Space ec o sequence & swi ching imes o 3D- FFSVM 35 Table 5.1 Swi ching modes o AT-NPC 3-le el IGBT module (a h ee le el NPP con e e leg) 39 Table 5.2 Pin con igu a ion o Inpu connec o s- CN1 & CN101 o each d i e boa d 39 Table 5.3 Pin con igu a ion o Ou pu connec o s- CN2, CN3, CN4, CN5, CN6 & CN7 o each IGBT d i e boa d 40 Table 5.4 Lis o Faul y componen s du ing FFD 41 Table 5.5 Ra ings o ou pu side powe supply o op ocouple 43 iii Table 5.6 Obse ed alues in he aul y op ocouple s 43 Table 5.7 Summa y o aul s in d i e & i s co ec ion 44 i LIST OF FIGURES FIGURE DESCRIPTION PAGE NO. Figu e 2.1 Di e en mul ile el con e e opologies 3 Figu e 2.2 A single phase NPC 4 Figu e 2.3 Con en ional H-b idge (3 le el, single phase) con e e 5 Figu e 2.4 Fi e-le el single phase H-b idge con e e 6 Figu e 2.5 Th ee-le el single phase lying capaci o con e e 7 Figu e 2.6 Va ious modula ion schemes o mul ile el con e e s 8 Figu e 3.1 Leg schema ic o a h ee-le el T- ype powe in e e : (a) bidi ec ional swi ch wi h con en ional IGBT, (b) bidi ec ional swi ch wi h RB-IGBT 11 Figu e 3.2 Leg schema ic o a single phase h ee le el T- ype module 11 Figu e 4.1 Scheme o T- ype con e e connec ed o load ia LC il e 15 Figu e 4.2 Block diag am o he T- ype in e e sys em wi h sepa a e dc ol age sou ce 20 Figu e 4.3 Pa allelog am comp ising wo equal iangles 20 Figu e 4.4 Two dimensional Space Vec o Modula ion algo i hm 21 Figu e 4.5 Ou pu ol age- e e ence and con olled wa e o ms o he T- ype in e e sys em wi h indi idual dc ol age sou ces 21 Figu e 4.6 Block diag am o he T- ype in e e sys em wi h edundancy dc link capaci o ol age balancing app oach 22 Figu e 4.7 Swi ching s a e ec o s o a h ee le el con e e 23 Figu e 4.8 DC link capaci o ol ages c1 & c2 balanced by edundancy app oach wi h ini ial imbalance condi ion 23 Figu e 4.9 Ou pu ol age- e e ence and con olled wa e o ms o Redundancy app oach 24 Figu e 4.10 DC link capaci o ol ages c1 & c2 o edundancy app oach 24 Figu e 4.11 Block diag am o de e minis ic capaci o ol age balancing app oach using 3D SVM 25 Figu e 4.12 Block diag am o de e minis ic capaci o ol age balancing app oach using 3D FFSVM 25 Figu e 4.13 Equi alen ci cui o a 3L T- ype con e e wi h ideal swi ches 26 Figu e 4.14 De e minis ic dc link capaci o ol age balancing app oach 30 Figu e 4.15 3D-SVM algo i hm o selec ion o each e ahed on o co esponding s a e ec o s 32 Figu e 4.16 DC link capaci o ol ages c1 and c2 balanced by de e minis ic app oach using 3D SVM wi h ini ial imbalance condi ion 33 Figu e 4.17 DC link capaci o ol ages c1 and c2 balanced by de e minis ic app oach using 3D SVM wi h ini ial imbalance condi ion by ine uning 33 Figu e 4.18 Ou pu ol age- e e ence and con olled wa e o ms o de e minis ic app oach using 3D SVM 33 Figu e 4.19 DC link capaci o ol ages c1 & c2 o de e minis ic capaci o ol age balancing app oach using 3D SVM 33 Figu e 4.20 3D- eed o wa d SVM algo i hm o selec ion o each subp ism o co esponding s a e ec o s 34 Figu e 4.21 DC link capaci o ol ages c1 & c2 balanced by de e minis ic app oach using 3D FFSVM wi h ini ial 35 2 consequen ly sol es he dc link capaci o ol age balancing p oblem. In ou p ojec a simple edundancy app oach is used when he con ol s a egy is de ined in he αβ s a iona y ame; whe e as a de e minis ic app oach is used when he con ol s a egy is de ined in he αβγ ame. In he con ol s a egy de ined in αβγ ame (o h ee componen con ol), he γ-componen is used o balance he dc-link capaci o ol ages and o emo e he lowe o de ha monics, occu ed du ing capaci o swi ching o an accep able le el. The hesis wo k p ima ily add esses he wo possible cases in he T- ype in e e sys em, i.e. he case o using sepa a e DC ol age sou ces and he case o in oducing he dc link capaci o s. The o me case does no need a dc link capaci o ol age balancing s a egy and a simple wo dimensional SVM scheme is used. The la e one needs a sepa a e con ol s a egy o balancing he dc link capaci o s. This case is again discussed in o wo s a egies o balancing he dc link capaci o ol ages i.e. he edundancy app oach and he de e minis ic app oach. In edundancy app oach a simple s a ic ela ion is conside ed o sol e he dc link capaci o ol age balancing issue, whe eas in de e minis ic app oach a Luenbe ge Obse e con ol scheme is used. In edundancy app oach a wo dimensional SVM is used, whe eas in de e minis ic app oach bo h h ee dimensional SVM and h ee dimensional FFSVM a e he possible modula ion schemes. I is o be no ed ha in all he cases a Gene alized P edic i e Con ol (GPC) app oach is used o acking ou pu ol age. The GPC calcula es he con ol signals o ack he desi ed ou pu il e capaci o ol ages. A compa ison o he T- ype in e e sys em’s pe o mance is made o he di e en app oaches, in o de o unde s and, in es iga e and ealize he impo ance o he de e minis ic app oach o capaci o ol age balancing me hod. The hesis epo mainly comp ises eigh chap e s including he in oduc o y chap e . The 2nd chap e gi es a basic idea o mul ile el in e e s, i s opologies, a ious modula ion and con ol schemes. The nex chap e h ows ligh on he NPP powe in e e , he eby s a ing i s impo ance. The 4 h chap e , named ‘Sys em desc ip ion, modeling and con ol design’ is he co e wo k o he hesis, which ini ially desc ibes he GPC s a egy. I also discusses he T- ype in e e sys em in case wise including i s modula ion-cum-con ol me hodologies. This u he includes modeling he in e e sys em o bo h GPC design and o de i ing he dc link capaci o and induc o dynamics, which a e he key concep s in de e minis ic app oach. A he end o his chap e a compa ison o he edundancy and he de e minis ic app oaches a e discussed. The 5 h chap e desc ibes he p o o ype design o he NPP con e e and i s e alua ion. The ad an ages and applica ions a e discussed in chap e 6. Chap e 7 is in e ed wi h ew conclusions and u u e wo k. Chap e 8 comp ises he e e ences ci ed. 3 CHAPTER 2 MULTILEVEL INVERTERS Indus ial applica ions u ilize bo h high and medium powe le els and his is ai ly possible only wi h mul ile el con e e s. So, one can ex ac many ol age le els om mul ile el con e e s based on his/he applica ion need o in e es . The o emos easons o go o mul ile el in e e s a e o a oid s ep up ans o me du ing each s age o powe con e sion and o educe ou pu ha monics. Such mul ile el con e e s a e widely used in in eg a ion o enewable ene gy esou ces, ships, a ia ion, ac ion, Unin e up ible Powe Supplies (UPS), High Vol age Di ec Cu en (HVDC) sys ems, Flexible AC T ansmission Sys em (FACTS), a iable- equency d i es, elec ic ehicle d i es and ai condi ioning applica ions. By de ini ion, ‘Mul ile el in e e s a e powe con e e s composed by an a ay o semiconduc o s and capaci o ol age sou ces, ha when p ope ly con olled, can gene a e wa e o m ou pu ol ages wi h adjus able equency and ampli ude’. Since he incep ion o mul ile el con e e s [19] du ing 1975, esea ch and de elopmen in mul ile el con e e s ha e e olu ionized much. Fi s ly, i all began wi h a simple h ee le el powe con e e , which la e led o de elopmen o di e en opologies and con ol me hods [20]. These e olu ions ha e mainly esul ed in possible up-g ada ions o di e en opologies, modula ion schemes, con ol me hodologies, ha monics educ ion possibili ies and balancing o dc link capaci o ol ages. The basic idea o mul ile el con e e is o ge di e en ou pu ol age le els by swi ching he semiconduc o swi ches in an o de ly ashion, esul ing in a s ai case ou pu ol age, which is la e in e ed by a il e ci cui o p oduce an AC ou pu o be u ilized by he load. Tu ning o a semiconduc o swi ch is called commu a ion and his commu a ion is done in an o de ly ashion, such ha a di e en ol age le els a e achie ed a he ou pu . Swi ching sequences o hese semiconduc o swi ches a e gene a ed by modula o s, which a e discussed in de ail in sec ion 2.2. Fig. 2.1. Di e en mul ile el con e e opologies The mul ile el powe con e e s ha e he ollowing ad an ages:  Reduced d /d s esses and elec omagne ic compa ibili y (EMC) p oblems, which imp o es he s ai case wa e o m quali y.  Smalle Common Mode (CM) ol age 4  Low dis o ion o inpu cu en  Ope a es a bo h undamen al and high swi ching equencies  Highe ol age ope a ion (abo e classic semiconduc o limi s)  Lowe ol age dis o ion (mo e sinusoidal wa e o ms)  Mul ile el con e e s a e well sui able o eac i e powe compensa ion. Al hough mul ile el con e e s a e ma u e echnologies, he e is always a ising demand in new opologies, modula ion schemes and con ol s a egies o coun e ac one o mo e d awbacks o con en ional one and o go on wi h a newly p oposed con e ing echnology. 2.1. INVERTER TOPOLOGIES Al hough many opologies and i s indus ial applica ions a e ound in li e a u e [21] [22], he h ee majo mul ile el con e e ypes a e Neu al Poin Clamped (NPC) con e e , Cascaded H-B idge (CHB) con e e and Flying Capaci o Con e e (FCC). Figu e 2.1 shows he classi ica ion o mul ile el con e e s [23]. 2.1.1. NEUTRAL POINT CLAMPED MULTILEVEL INVERTER The Neu al Poin Clamped (NPC) con e e was ini ially p oposed by Nabae, Takahashi, and Akagi in 1981 [24], which laid a ounda ion o he e a o ol age sou ce mul ile el high powe con e e s. Figu e 2.2 shows a single phase NPC o which he swi ching s a es a e gi en in Table 2.1. The lowe leg swi ches a e he complemen a y o hose o he uppe leg swi ches. The clamping diodes allow he connec ion o he phase ou pu o he midpoin o he dc link i.e. neu al (N) and his pa es a way o h ee ol age le els. I is o be no ed ha i ‘L’ is he numbe o le els in phase o neu al ol age (VaN), hen he numbe o s eps in phase o phase ol age (Vab) is ‘2L-1’. The blocking ol age o he powe de ices is equal o Vdc/(L-1). NPCs a e used o medium and high ol age applica ions. In eg a ed Ga e Commu a ed Thy is o s (IGCT) o Insula ed Ga e Bipola T ansis o (IGBT) is comme cially used as swi ching de ices. I he con e e is o high ol age and high cu en applica ions, IGCT is a good choice o op ion. I is o be no ed ha IGBT has lowe commu a ion losses and easy d i e s, bu i has high conduc ion losses.. Comme cial NPCs include ACS 1000, SINAMICS SM120, Al i a 1000, e c. whose maximum powe anges om 10 o 40 MW. Ad an ages o mul ile el diode-clamped in e e s:  As all o he phases sha e a common dc bus, he capaci ance equi emen o he con e e ge s educed. Due o his, NPC a o s back- o-back egene a i e applica ions.  The capaci o s can be p e-cha ged in a g oup.  Fo undamen al swi ching equency, he e iciency is high. Fig. 2.2. A single phase NPC Table.2.1 Swi ching s a es o a h ee le el single phase NPC Vol age VaN Swi ching s a es S1 S2 S1’ S2’ Vdc/2 1 1 0 0 0 0 1 1 0 - Vdc/2 0 0 1 1 5 Disad an ages o mul ile el diode-clamped in e e s:  Real powe low is di icul o a single in e e because he in e media e dc le els will end o o e cha ge o discha ge wi hou p ecise moni o ing and con ol.  The inne mos de ices a e swi ched on o mos o he ime. To o e come his and main ain a nominal uni o mi y, he Ac i e Neu al Poin Clamped (ANPC) we e in oduced.  The o al numbe o clamping diodes equi ed is quad a ically ela ed o he numbe o le els, which can be mo e complex o uni s wi h a high numbe o le els. 2.1.2. CASCADED H-BRIDGE INVERTER The cascaded H-B idge con e e s a e i s in oduced du ing la e 1960s [25], [26], which pa ed a way o hink o using a sepa a e DC sou ce in mul ile el con e e s. As he name ‘CHB’ de ines he use o mul iple uni s o H-b idge powe cells, which a e connec ed in se ies such ha he ou pu ol age is he sum o each in e e ou pu s. Each Sepa a e DC Sou ce (SDCS) is connec ed o a single-phase ull-b idge o H-b idge in e e . A con en ional H-b idge cell is shown in he igu e 2.3, whose swi ching s a es a e gi en in able 2.2. The lowe leg swi ches in each CHB cell a e he complemen a y o he uppe leg swi ches. The H-b idge cells a e connec ed in se ies o o m mul ile el cascaded con e e s. The connec ion can be symme ical (using same dc sou ce alues) o asymme ical (using di e en dc sou ces). Figu e 2.4 shows he leg-scheme o a symme ical i e-le el CHB con e e , whose swi ching s a es a e gi en in he able 2.3. I is o be no ed ha , o a ‘m’ le el symme ical cascaded H-b idge con e e he numbe o dc sou ces needed is (m-1)/2 & he maximum numbe o le el o line- o-line ou pu ol age is (2m-1). CHB con e e s a e bes sui able o la ge PV-plan s, when used wi h an isola ed DC-DC con e sion s age [27]. They a e ideal o enewable ene gy in eg a ion and ac ion sys ems. Comme cial CHB con e e s a e a ailable in ABB, A ow speed & Siemens (Pe ec ha mony). Fig. 2.3. Con en ional H-b idge (3 Le el, single phase) con e e Table.2.2 Swi ching s a es o a single phase h ee le el H-B idge con e e Vol age, VaN Swi ching s a es S1 S2 Vdc/2 1 0 0 0 0 0 1 1 - Vdc/2 0 0 Ad an ages o cascaded H-b idge in e e s:  The modula s uc u e o he mul iple uni s o iden ical H-b idge powe cell educes he manu ac u ing cos .  The numbe o possible ou pu ol age le els is mo e han wice he numbe o dc sou ces.  Less ol age THD and d /d when compa ed o wo le el con e e s ope a ing a he same 6 ol age a ing and swi ching equency.  H-b idge cells a e cascaded o p oduce high AC ol ages, which elimina es he p oblem o equal ol age sha ing o se ies-connec ed de ices. Fig. 2.4. Fi e-le el single phase H-b idge con e e Table.2.3 Swi ching s a es o a Fi e le el single phase H-B idge Con e e Vol age, VaN Swi ching s a es Indi idual cell ou pu ol age S1 S2 S3 S4 Va1 Va2 2Vdc 1 0 1 0 Vdc Vdc Vdc 1 0 1 1 Vdc 0 0 0 1 1 1 0 0 Vdc 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 0 1 Vdc -Vdc 0 1 1 0 -Vdc Vdc -Vdc 0 1 0 0 -Vdc 0 1 1 0 0 0 1 0 -Vdc 1 1 -2Vdc 0 1 0 1 -Vdc -Vdc Disad an age o cascaded H-b idge in e e s:  A la ge numbe o sepa a e dc sou ces a e equi ed o CHB, which a e usually ob ained om a mul i-phase diode ec i ie by employing an expensi e phase shi ing ans o me . 2.1.3. FLYING CAPACITOR MULTILEVEL INVERTER The lying capaci o s we e i s in oduced by Meyna d and Foch in 1992 [28]. As he name sugges s, a capaci o is connec ed be ween he uppe and he lowe leg o be ween he wo cells. In o he wo ds, he ee-wheeling diodes in NPC a e eplaced by a capaci o . Figu e 2.5 shows a h ee le el single phase FC, which has wo cells. Addi ional cells can be added o inc ease he numbe o ou pu le els, bu he nominal powe o he con e e emains he same. I is o be no ed ha o ‘m’ ol age le el, lying capaci o needs 2(m-1) semiconduc o swi ches, (m-1) DC bus capaci o s and (m-1)(m-2)/2 numbe o balancing capaci o s pe phase. Table 2.4 shows he swi ching s a es o a h ee-le el single phase FC. The phase edundancy swi ching s a e-ze o ol age is used o con ol he loa ing capaci o ol age. A well-known comme cial lying capaci o con e e is Als om VDM 6000. ABB’s ACS 2000 is an example o hyb id FCC, which is a combina ion o a 3L-ANPC and a FCC. 7 Ad an ages o lying capaci o in e e s:  Unlike o he in e e s, swi ching combina ion edundancies e en in inne ol age le els makes balancing he ol age le els o he capaci o s easie and lexible wi h mo e swi ching combina ions.  Real and eac i e powe low can be con olled making a possible ol age sou ce con e e candida e o high ol age dc ansmission [29], [30].  La ge numbe o capaci o s enables he in e e o ide h ough capabili ies du ing powe age. Fig. 2.5. Th ee-le el single phase lying capaci o con e e Table.2.4 Swi ching s a es o a h ee le el single phase FCC Vol age, VaN Swi ching s a es S1 S2 Vdc/2 1 1 0 1 0 0 0 1 -Vdc/2 0 0 Disad an ages o lying capaci o in e e s:  Con ol is complica ed o egula e he ol age le els o all o he capaci o s. Also, p echa ging all o he capaci o s o he same ol age le el and s a up a e complex.  In e e con ol will be e y complica ed and he swi ching equency and swi ching losses will be high o eal powe ansmission.  The la ge numbe s o capaci o s a e bo h mo e expensi e and bulky han clamping diodes in mul ile el diode-clamped con e e s. Packaging is also mo e di icul in in e e s wi h a high numbe o le els. Apa om he abo e opologies, he e a e Modula Mul ile el Con e e (MMC) [31], Cascaded Ma ix Con e e (CMC) [32], [33] and Neu al Poin Pilo ed (NPP) con e e [34]. The e also exis s symme ical opologies like n-le el Cascaded Cell Mul ile el Con e e (CCMC) [35], [36], which do no ha e a common dc link; ins ead hey a e made o s ages, connec ed in se ies, which comp ises wo basic cells in pa allel connec ion. These basic cells sha e a common DC sou ce o capaci o . Asymme ic opologies also p e ail, like Hyb id Mul ile el Con e e (HMC) [37] whe e di e en s ages a e connec ed in se ies, ha has di e en alues o DC ol ages and Cascade Asymme ic Mul ile el Con e e (CAMC) [38], which is a combina ion o ANPC and FC. In he p ojec wo k, he NPP o T- ype in e e is used & he emphasis lies on i , which is discussed in chap e 3 in de ail. 8 2.2. MODULATION SCHEMES The majo modula ion schemes a e Pulse Wid h Modula ion (PWM), Space Vec o Modula ion (SVM) & ha monic con ol. Focus on new and hyb id modula ion schemes ely on encoun e ing o he issues like using less numbe o swi ches, op imizing ou pu ol age con ol, sol ing he dc link capaci o ol age balancing p oblem, educing o elimina ing he ha monic con en s, inc easing obus ness & aul ole ance capabili y, e c. Figu e 2.6 shows he majo modula ion ypes in mul ile el con e e s [39]. Fig. 2.6. Va ious modula ion schemes o mul ile el con e e s Pulse Wid h Modula ion (PWM): The basic idea in PWM is o compa e a e e ence signal wi h a ca ie signal in o de o ob ain a cons an equency PWM signal, which is used as i ing pulses o he semiconduc o swi ches. Nume ous de elopmen s in op imizing he PWM echnique ha e been done since i s incep ion [10]. In Bipola PWM (Two le el ol age case), a simple iangula ca ie signal is compa ed wi h a sine e e ence and hose o e lapping wi h he uppe and lowe ca ie signals a e gi en as swi ching pulses o he lowe and uppe swi ches espec i ely. In Unipola PWM (used o single phase, h ee le el ol age con e e ) a iangula ca ie signal is compa ed wi h wo e e ence sine wa es o 180⁰ shi ed om each o he . The swi ching pulses ob ained om he posi i e sine wa e o e lapping a e applied o one leg and he swi ching pulses ob ained om he nega i e sine wa e o e lapping a e applied o he o he leg. In Phase shi ed PWM (used o FCC o CHB con e e ) n-1 iangula ca ie signals a e used wi h op imal displacemen 180⁰/m (whe e ‘n’ is he numbe o ol age le els and ‘m’ is he numbe o cells) a e o e lapped using a e e ence sine wa e and he swi ching pulses a e gi en o he con e e s. The numbe o ca ie signals depends on he numbe o cells used. Fo example: In a h ee le el FCC wo ca ie signals a e used whe eas in a ou le el FCC h ee ca ie signals a e used. In Le el shi PWM he ca ie signals a e a anged in a e ical shi . Fo a m-le el in e e , (m-1) ca ie signals a e needed. The below con ol logics a e used in he le el shi ed PWM used o a h ee le el con e e :  I he e e ence is abo e he ca ie s he uppe swi ches a e u n on.  I he e e ence is be ween bo h ca ie s he ou pu is connec ed o he neu al poin .  I he e e ence is unde bo h ca ie s he lowe swi ches a e u ned on. In phase disposi ion, he ca ie signals a e aligned in a simila ashion, whe eas in opposi ion disposi ion, he lowe ca ie signals a e 180⁰ phase shi ed om he uppe signals, whe eas 9 in al e na e opposi ion disposi ion, he ca ie signals a e 180⁰ phase shi ed om each o he . Space Vec o Modula ion (SVM): The basic idea o SVM is o swi ch he semiconduc o swi ches, by loca ing a e e ence signal on he Space Vec o (SV) o app op ia e le el and inding he nea es swi ching ec o s and hei co esponding swi ching imes. In a 2D SVM [11], he h ee phase e e ence is ans o med o g-h coo dina e sys em and he closes h ee ec o a e ound and swi ched, whe eas in a 3D SVM [12], a no malized phase ol age e e ences a e loca ed in a h ee-dimensional space and he closed ou ec o s a e swi ched. The eed o wa d 3D SVM [13] akes in o accoun he ac ual dc-link capaci o ol age imbalance and uses a modula ion scheme simila o 3D wi h sligh changes. The 1DM o single phase mul ile el con e e s uses he 1-D con ol egion o iden i y he possible swi ching s a es and hei du y cycles [40]. The mul idimensional modula ion echnique is a gene alized modula ion scheme o cascaded mul ile el con e e s, which de e mines he swi ching s a es on a mul idimensional con ol egion [41]. He e, he DC ol age con ol s a egy is used on a 2D con ol egion. One can conside he eal alues o dc-link capaci o ol ages and ex end he eed o wa d mD-PWM scheme o cascaded con e e s. (whe e m is he numbe o cells). In SVPWM echnique, he e e ence ol age ec o is esol ed by ime- a e aging wi h he nea es ac i e swi ching ec o s. In Mul ile el mul iphase SVPWM [42], he concep o pe mu a ion ma ix is in oduced, which de e mines he swi ching ime o he swi ches. Hyb id mul ile el modula ion: Modi ied ca ie -based PWM a e used in Ac i e NPCs, whe e n-1 iangula ca ie s a e used which a e phase-shi ed by 90⁰(whe e n is he numbe o ol age le el). Such modula ion schemes a e ad an ageous o balance he dc link capaci o ol ages inhe en ly in medium ol age powe in e e s. In 5L-ANPC a undamen al swi ching is used o ANPC cell and a phase-shi ed PWM is used o he lying-capaci o cell [43]. Space ec o con ol o mul ile el con e e s: The basic idea o space ec o con ol is when using mul ile el in e e s wi h high numbe o le els (which esul s in high space ec o densi y) he e is no need o modula ion. Space ec o con ol app oxima es he e e ence ec o by he closes space ec o gene a ed by he in e e . The app oxima ion is compensa ed by ou e loop con olle s and he in e e wo ks wi h low swi ching equency. Ha monic con ol: In Selec i e Ha monic Elimina ion (SHE) [44] he ‘n’ lowe -o de odd, non iplen (non-mul iple o 3) ha monics a e elimina ed by sol ing a se o m= n+1 equa ions o undamen al ampli ude and ‘m’ angles. The Selec i e Ha monic Mi iga ion (SHM) [45] is based on SHMPWM, ha gene a es swi ching h ee-le el PWM pa e ns o mee g id codes wi h high quali y om ha monic pe spec i e, he eby a oiding he elimina ion o some speci ic ha monics. La e an op imized SHM [46] is iden i ied by, which a e applied o high powe con e e s wi h low swi ching equency. In bo h he cases he objec i e unc ions a e op imized by algo i hms like Gene ic Algo i hm (GA), simula ed annealing, e c. The modula ion schemes used in he p ojec a e 2D SVM, 3D SVM and 3D FFSVM, which a e explained in de ail in he chap e 4. 2.3. CONTROL STRATEGIES The con ol s a egies comp ise concep s like di ec powe con ol [47], [48], [49], Model P edic i e Con ol (MPC) [50], [51], hys e esis/non-hys e esis con ol o cu en [52], using con en ional con olle s like PI [53], uzzy PID [54], neu al ne wo k & uzzy logic me hods 10 [55] e c. and o he ad anced con ol echniques. Mos new wo ks ely and emphasize on s a egies like ha monics educ ion, dc link capaci o ol age balancing, less compu a ion e o , new e icien con ol me hods, ha can sol e one o mo e o he issues and inc eased sys em pe o mance. Fo his, one has o unde go a modeling app oach o he con e e sys em which is discussed in de ail in chap e 4. All hese modeling s a egies need a p io knowledge o undamen al Cla ke [56] & Pa k [57] ans o ma ion. Bo h he ans o ma ions a e basically used o simpli y he analysis o h ee phase ci cui s. The Cla ke’s ans o ma ion is used in he p ojec , which acili a es he inclusion o he hi d con ol componen i.e. he gamma (γ) o ze o (0) componen . This γ componen is used o sol e he dc link capaci o issue in he de e minis ic app oach, which is discussed in de ail in chap e 4. 11 CHAPTER 3 NEUTRAL POINT PILOTED (NPP) POWER INVERTER The Neu al Poin Pilo ed con e e [58], [59] o he T- ype con e e is an ex ension o he con en ional wo-le el Vol age Sou ce Con e e (VSC) wi h an ac i e bidi ec ional swi ch o he dc-link midpoin , which blocks only hal o he dc link ol age. Figu e 3.1 (a) shows he leg schema ic o a h ee-le el T- ype powe con e e , whose bidi ec ional swi ches a e con en ional IGBTs. Hence, i can be implemen ed wi h de ices ha ing a lowe ol age a ing. Due o his ea u e, he con e e shows e y low swi ching losses, accep able conduc ion losses and lowe numbe o semiconduc o de ices, when compa ed o con en ional opologies like NPC and FCC. Al hough he T- ype con e e s we e in oduced du ing 1985 [60], owing o demand in ise o compac and e icien low powe con e e s, a ious de elopmen s a e made in hese T- ype con e e s o be mo e eliable and aul ole an [61], [62]. La e hese con en ional AC swi ches we e eplaced by Re e se blocking IGBT (RB- IGBT) [63] which has low swi ching losses and be e e e se blocking capabili y. When seen om ab ica ion pe spec i e, he module wi h RB-IGBT has only one pn-junc ion and his educes he e e se eco e y. Figu e 3.1(b) shows he leg schema ic o a h ee-le el T- ype powe con e e , whose bidi ec ional swi ches a e RB-IGBT. Fig. 3.1. Leg schema ic o a h ee-le el T- ype powe in e e : (a) bidi ec ional swi ch wi h con en ional IGBT, (b) bidi ec ional swi ch wi h RB-IGBT Table 3.1. Swi ching s a es o a single phase T- ype con e e Vol age, VaN Swi ching s a es T1 T2 T3 T4 Vdc/2 1 0 0 0 0 0 0 1 1 -Vdc/2 0 1 0 0 Fig. 3.2. Leg schema ic o a single phase h ee le el T- ype con e e 18 The p edic ed ou pu calcula ed o alues om j=1 o j=6 and is gi en by, =0++0E∆−1 wi h                     = 0490.01892.04039.06697.09589.02427.1 00490.01892.04039.06697.09589.0 000490.01892.04039.06697.0 0000490.01892.04039.0 00000490.01892.0 000000490.0 G;                     − − − − − − = 6743.131496.294752.16 9580.100958.241378.14 0446.83740.183294.11 2212.55385.123173.8 7756.21738.73982.5 9672.08369.28697.2 F;                     = ′ 6856.0 5494.0 4034.0 2618.0 1392.0 0485.0 G whe e 0′ is he ma ix o coe icien s o he igh -mos backwa d shi ope a o o Gj, whe e j akes he alue 1 o Nh o N2 (p edic ion ho izon). K = i s ow o TT GIGG 1 )( − + λ = i s ow o TT                                                               +                                        − 0490.01892.04039.06697.09589.02427.1 00490.01892.04039.06697.09589.0 000490.01892.04039.06697.0 0000490.01892.04039.0 00000490.01892.0 000000490.0 100000 010000 001000 000100 000010 000001 95.0 0490.01892.04039.06697.09589.02427.1 00490.01892.04039.06697.09589.0 000490.01892.04039.06697.0 0000490.01892.04039.0 00000490.01892.0 000000490.0 0490.01892.04039.06697.09589.02427.1 00490.01892.04039.06697.09589.0 000490.01892.04039.06697.0 0000490.01892.04039.0 00000490.01892.0 000000490.0 1 = i s ow o                     −−−−− −−−−− −−−− −−−− −− 0256.00172.00099.00048.00017.00003.0 0817.00274.00467.00230.00084.00017.0 1349.00001.00688.00609.00230.00048.0 1654.00485.00334.00688.00467.00099.0 1646.01061.00485.00001.00274.00172.0 1317.01646.01654.01349.00817.00256.0 K= ( ) 1317.01646.01654.01349.00817.00256.0 Exp ession o con ol law is gi en by, )()( wK u − = ∆ = ( )                                         −+−−+−∆ −+−−+−∆ −+−−+−∆ −+−−+−∆ −+−−+−∆ −+−−+−∆ −                     + + + + + + )2(6743.13)1(1496.29)(4752.16)1(6856.0 )2(9580.10)1(0958.24)(1378.14)1(5494.0 )2(0446.8)1(3740.18)(3294.11)1(4034.0 )2(2212.5)1(5385.12)(3173.8)1(2618.0 )2(7756.2)1(1738.7)(3982.5)1(1392.0 )2(9672.0)1(8369.2)(855.2)1(0485.0 )6( )5( )4( )3( )2( )1( 1317.01646.01654.01349.00817.00256.0 y y y u y y y u y y y u y y y u y y y u y y y u w w w w w w 19 = ( )                     −−−+−−∆−+ −−−+−−∆−+ −−−+−−∆−+ −−−+−−∆−+ −−−+−−∆−+ −−−+−−∆−+ )2(6743.13)1(1496.29)(4752.16)1(6856.0)6( )2(9580.10)1(0958.24)(1378.14)1(5494.0)5( )2(0446.8)1(3740.18)(3294.11)1(4034.0)4( )2(2212.5)1(5385.12)(3173.8)1(2618.0)3( )2(7756.2)1(1738.7)(3982.5)1(1392.0)2( )2(9672.0)1(8369.2)(855.2)1(0485.0)1( 1317.01646.01654.01349.00817.00256.0 y y y u w y y y u w y y y u w y y y u w y y y u w y y y u w =                     −−−+−−∆−+ +−−−+−−∆−+ +−−−+−−∆−+ +−−−+−−∆−+ +−−−+−−∆−+ +−−−+−−∆−+ )2(80090531.1)1(83900232.3)(16978384.2)1(09029352.0)6(1317.0 )2(8036868.1)1(96616868.3)(32708188.2)1(09043124.0)5(1646.0 )2(33057684.1)1(0390596.3)(87388276.1)1(06672236.0)4(1654.0 )2(70433988.0)1(69144365.1)(12200377.1)1(03531682.0)3(1349.0 )2(22676652.0)1(58609946.0)(44103294.0)1(01137264.0)2(0817.0 )2(02476032.0)1(07262464.0)(073088.0)1(0012416.0)1(0256.0 y y y u w y y y u w y y y u w y y y u w y y y u w y y y u w )( u ∆ =         +++++++++++ +−−−+−−∆− )6(1317.0)5(1646.0)4(1654.0)3(1349.0)2(0817.0)1(0256.0 )2(89103567.5)1(19439835.13)(00687319.8)1(29537818.0 w w w w w w y y y u No e: A simila calcula ion is ca ied ou o p edic ion ho izons 5, 7, 8 & 9 wi h a ange o weigh ing ac o s λ and he compa ison is made o ex ac he one wi h bes pai o weigh ing ac o s and p edic ion ho izon. The ou pu o GPC yields o he con ol componen δαβ, which is used as e e ence o modula ion. 4.2. T-TYPE INVERTER SYSTEM WITH INDIVIDUAL VOLTAGE SOURCES In his case sepa a e dc ol age sou ces o each 200 V is used a he dc link ins ead o capaci o s, so ha he e is no necessi y o using a sepa a e con ol s a egy o balancing he dc link capaci o ol ages. Figu e 4.2 shows he block diag am o he T- ype in e e sys em, when indi idual dc ol age sou ces a e used. The con ol signal δabc, ob ained om he GPC- s a egy, discussed in he sec ion 4.1 is i s ans o med o δαβ, which is hen ans o med o δgh using he ans o ma ions (17) & (18) and no malized o H IJ , whe e n(=3) is he numbe o le els o he in e e & dc (= dc1+ dc2=400 V) is he DC sou ce ol age. I is o be no ed ha as δγ is no needed he e in he case o T- ype in e e sys em wi h indi idual ol age sou ces. Hence, i is neglec ed. KLMN OPQ=R A S T T T U 1 − −  0√A −√A   √ √ √ W X X X Y (17) KOP Z[= 1 √A 0 √A] (18) (17) is he powe a ian o m o Cla ke’s ans o ma ion, whe e he gain isR A. In o dina y Cla ke’s ans o ma ion he gain is 2/3. In o de o make he ans o ma ion ma ix uni a y i.e. 20 he in e se ma ix coincides wi h i s anspose and o p ese e he ac i e and eac i e powe one has o conside powe in a ian o m o Cla ke’s ans o ma ion. Fig. 4.2. Block diag am o he T- ype in e e sys em wi h sepa a e dc ol age sou ces Once he con ol signal (o e e ence o modula o ), δgh is ob ained, i is sen o he modula o o ge he i ing pulses o he semiconduc o swi ches. The modula ion s a egy used he e is wo-dimensional SVM [11]. This in ol es inding he nea es h ee coo dina es in he wo-dimensional space ec o coo dina e sys em and swi ching he co esponding ec o s, wi h hei espec i e du y cycles. I is done by ounding he alues and doing a simple compa ison in he wo dimensional coo dina e sys em. A e inding he diagonal ec o s o he pa allelog am, ano he simple compa ison is done o ind i he e e ence, δgh is in he uppe iangle o in he lowe iangle, as shown in he igu e 4.3. Once all he h ee coo dina es in he g-h coo dina e sys em a e ob ained, he du y cycles a e compu ed and he swi ching pulses a e gene a ed o he IGBT swi ches. Figu e 4.4 shows he 2D SVM algo i hm. Fig. 4.3. Pa allelog am comp ising wo equal iangles 21 Fig. 4.4. Two dimensional Space Vec o Modula ion algo i hm I is o be no ed ha he wo dimensional SVM is e y as and compu a ionally e icien , which can be ex ended o n-le el h ee phase con e e s. Figu e 4.5 shows he e e ence and he ac ual ou pu ol age o GPC con ol du ing simula ion, which e eals he e iciency in acking he e e ence and he pe o mance o GPC o ackle he misma ch o model pa ame e . Fig. 4.5 Ou pu ol age- e e ence and con olled wa e o ms o he T- ype in e e sys em wi h indi idual dc ol age sou ces 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 -200 -100 0 100 200 Time (ms) ca & ca * (V) ca ca * 22 4.3. T-TYPE INVERTER SYSTEM USING INDIVIDUAL DC LINK CAPACITORS In his case he dc sou ces a e eplaced by sepa a e dc link capaci o s and his needs a sepa a e con ol s a egy o balancing he dc link capaci o ol ages. The e iciency o he con ol s a egy elies on sys em pe o mance pa ame e s like compu a ional e o , ha monic educ ion and good acking o he ou pu ol age. The e a e wo dc link capaci o ol age balancing app oaches i.e. he edundancy app oach and he de e minis ic app oach, whose pe o mances a e simula ed and compa ed. 4.3.1. REDUNDANCY DC LINK CAPACITOR VOLTAGE BALANCING APPROACH In his app oach, an ex a edundancy block is used, ha acili a es a simple s a ic compa ison [70], [71], [72] o he dc link capaci o ol ages and cu en as shown in he igu e 4.6. Acco ding o his compa ison esul , he edundancy o he inne le el swi ching ec o s in a h ee le el con e e is used and app op ia e swi ching is done as shown in he able 4.4. Figu e 4.7 shows he possible swi ching s a es o a h ee le el con e e . The in e e has h ee s a es pe phase and as he e a e h ee phases, 33=27 di e en swi ching s a es exis s. I is o be no ed ha he edundancy exis s in he inne le el ec o s- V1, V2, V3, V4, V5 & V6 in a h ee le el space ec o . Fo example- conside he ec o V7 (+, 0, -), which deno es ha , phase a is connec ed o he posi i e e minal, phase b is connec ed o he dc link mid-poin and phase c is connec ed o he nega i e e minal. In ze o ec o (V0) he magni ude o ol age is 0V. In he in e nal ec o s (V1 o V6) he magni ude o ol age is IJ A V. The middle ec o s (V7 o V12) ha e magni ude o IJ √AV, whe eas he ex e nal ec o s (V13 o V18) ha e he magni ude o IJ √AV. Fig. 4.6. Block diag am o he T- ype in e e sys em wi h edundancy dc link capaci o ol age balancing app oach Table 4.4 Redundancy con ol s a egy o balance he dc link capaci o ol ages Vol age imbalance DC link cu en In e nal edundancy ( c1- c2) < 0 idc < 0 Posi i e edundancy (0) idc > 0 Nega i e edundancy (1) ( c1- c2) > 0 idc < 0 Nega i e edundancy (1) idc < 0 Posi i e edundancy (0) 23 Fig. 4.7. Swi ching s a e ec o s o a h ee le el con e e I is o be no ed ha a wo-dimensional SVM is used, as discussed in he sec ion 4.2. The GPC s a egy used is he same as he one discussed in sec ion 4.1. On pe o ming a se ies o simula ion expe imen s, i is ound ha he GPC pe o ms well when p edic ion ho izon, Nh=6 and weigh ing ac o , λ=0.242. This pe o mance o he sys em is assessed by he Roo Mean Squa e (RMSe o ) and To al Ha monic Dis o ion (THD) alues, which a e discussed in sec ion 4.4. The RMSe o is gi en by, ^_`aaba%=de J,ghJJ,ghJ ∗ J,ghJ ∗|de ×100 % whe e /N,LMN is he ac ual ou pu ol age /N,LMN ∗ is he e e ence ou pu ol age & /N,LMN ∗|^_` is he RMS ol age e e ence =120 V, 50 Hz Fig. 4.8 DC link capaci o ol ages c1 & c2 balanced by edundancy app oach wi h ini ial imbalance condi ion 0 0.1 0.2 0.3 0.4 100 150 200 250 300 Time (ms) c1 & c2 (V) c1 c2 24 Fig. 4.9 Ou pu ol age- e e ence and con olled wa e o ms o Redundancy app oach Fig. 4.10 DC link capaci o ol ages c1 & c2 o edundancy app oach Figu e 4.8 shows ha an ini ial imbalance condi ion o dc link capaci o ol ages is en o ced and a e some ime ins an he edundancy app oach is ac i a ed. The capabili y o he app oach o handle he imbalance si ua ion and balance i la e wi hin he gi en s ipula ed ime is obse ed. Figu e 4.9 shows he GPC acking he ou pu e e ence ol age. Figu e 4.10 depic s he balanced dc link capaci o ol ages. Al hough his app oach is simple wi h less compu a ional e o s, i has i s own d awbacks like high RMSe o alues and THD alues o he ou pu ol age & exis ence o lowe o de ha monics in he dc link capaci o ol age di e ence which a e o e come by he de e minis ic dc link capaci o ol age balancing app oach. The compa isons o hese s a egies a e discussed in de ail in sec ion 4.4. 4.3.2. DETERMINISTIC DC LINK CAPACITOR VOLTAGE BALANCING APPROACH Two se ious p oblems in NPC and NPP con e e s a e he capaci o ol age balancing issue and he sinusoidal dis u bances in he dc link capaci o s du ing swi ching. Such dis u bances ha e pulled esea che ’s in e es , which a e encoun e ed by basic con ol sys em design. Al hough many dc link capaci o ol age balancing app oaches we e ound in li e a u e [73], [74], s ill ocus p e ails on e adica ing o he issues along wi h balancing dc link capaci o s. The con ol componen , δγ se es a eedom deg ee o sol ing he capaci o ol age imbalance and he educ ion o he low- equency oscilla ions. The de e minis ic app oach o dc-link capaci o ol age balancing app oach is based on using a s a e obse e , called Luenbe ge obse e [75], which es ima es he sinusoidal oscilla ion a each sampling ins an and minimizes ce ain le el o lowe o de ha monics o dc link capaci o ol age di e ence, he eby egula ing he dc link capaci o ol ages [18]. The applica ion o such con ol s a egy couldn’ be possible unless we model he con e e and de i e he phase cu en dynamics and he dc link capaci o ol age di e ence dynamics, which a e e ec i ely used in he de e minis ic app oach [76]. Such pa ame e aids he con olle and obse e o keep he ou pu ol age o go allied wi h he de e minis ic con ol app oach. The block diag am consis s mainly o an ou pu ol age con ol block (GPC), dc link capaci o ol age balancing block and he modula ion block, which is depic ed in he igu es 4.11 & 4.12. The di e ence be ween hese wo igu es is, in 3D FFSVM he eal alues o he dc link capaci o ol ages a e conside ed, which is discussed in de ail in he modula ion pa o his sec ion. 0 0.02 0.04 0.06 0.08 -200 -100 0 100 200 Time (ms) ca & ca * (V) ca ca * 0 0.1 0.2 0.3 0.4 185 190 195 200 205 210 215 Time (ms) c1 & c2 (V) c1 c2 25 Fig. 4.11. Block diag am o de e minis ic dc link capaci o ol age balancing app oach using 3D SVM Fig. 4.12. Block diag am o de e minis ic dc link capaci o ol age balancing app oach using 3D FFSVM In o de o model he con e e , he h ee le el equi alen ci cui model o T- ype powe in e e is conside ed wi h he ideal swi ches [77], as shown in he igu e 4.13. Table 4.5 Model pa ame e s used in he equi alen ideal swi ch Va iable Desc ip ion dc Sou ce ol age idc dc-link cu en C1, C2 dc-link capaci ance L Fil e induc ance C Fil e capaci ance idc1, idc2, idc3 Cu en s a op, middle and bo om connec ion poin s o capaci o s abc Injec ed ol age e e ed o ‘B’ iabc Induc o cu en s δabc Swi ching posi ion RL Load esis ance LL Load induc ance 26 Fig. 4.13. Equi alen ci cui o a 3L T- ype con e e wi h ideal swi ches Table 4.5 shows he model pa ame e s o he equi alen ideal swi ch. By applying KCL, idc1 + ic1 = idc → idc1 = idc – ic1 (19) idc2 + ic2 = ic1 → idc2 = ic1 – ic2 (20) idc3 + idc = ic2 → idc3 = ic2 – idc (21) idc1+idc2+idc3 = 0 (22) whe e C1 = C2 = C d d C=i 1c 1C d d C=i 2c 2C Sub ac ing equa ion (19) om (21), dc 2i+ii=i+i 1dc3dc2c1c - (23) (20) → dc2 i- =ii 2c1c A ela ionship be ween he cu en s idc1k, idc2k, idc3k in e ms o he h ee possible swi ch posi ions δk and o e e y k ϵ {a, b, c} is es ablished, whe e idc1k, idc2k, idc3k a e he inpu cu en lowing owa ds he swi ches om he dc link capaci o s connec ed o a DC ol age sou ce as shown in he igu e 4.13. Thus, o a gi en k ϵ {a, b, c} h ee poin s a e known, and a quad a ic unc ion ela ing idc1k, idc2k, idc3k and δk can be designed o i all h ee poin s as shown in able 4.6. No e: The abo e equi alen ci cui is simila o a h ee le el con e e , in gene al. 27 Table 4.6 Resol ing he inpu cu en s lowing owa ds he swi ches in o quad a ic unc ion 2 iδ )1+δ(=i kk kk1dc o k ϵ {a, b, c} kk2dc i)δ1(=i 2 k - o k ϵ {a, b, c} 2 iδ )δ(=i kk kk3dc 1- o k ϵ {a, b, c} j N    ! L  1  k g l g                 ! M  1  khlh                 ! N  1  kJlJ  (24) j N    1  ! L   j L                1  ! M   j M   1  ! N   j N !LjL!MjM!NjN (25) Since j L  j M  j N  0 j N A   ! L  1  k g l g                 ! M  1  khlh                 ! N  1  kJlJ  (26 ) Subs i u ing (24), (25) & (26) in (20) & (23) , m+  J+  J)  !LjL!MjM!NjN2jN (27) m)  J+  J)  !LjL!MjM!NjN (28) whe e x2 = c1- c2 & x1 = c1+ c2 Applying powe in a ian o m o Cla ke’s ans o ma ion (17) o (27) & (28), (27)→ no!LMN pjLMN2jN no1K!OPQ2pKjOPQ2jN no!OP pjOP2jN As jLjMjN0→ jQ0, he gamma componen is emo ed. As he alue no becomes ze o, since /N/N is always cons an , he abo e equa ion can be w i en as, q s u wqu x (29) (28)→no#!L!M!N'jLMN no#!L!M!N'KjOPQ noRA#!L1kh )ykJ)2 √A !M!N √!L!M!N'jOPQ z{ox| √}3 u x xx u <qu x √~ wqu  (30) whe e  34 This is done by compa ing he posi ion o elemen s in Von and Vs ec o s. Fo example, o phase a i Oa=0 and Osa=δ1, as hese alues occupy he 1s and 2nd posi ion in Von ec o , he same posi ioned alues o Vs ec o s gi es he co esponding swi ching s a e. So, in he abo e example he 1s and 2nd posi ion in he Vs ec o s a e 0 and 1. So, Opa=0 & OSpa=1 a e he swi ching s a e o phase a in he pa icula example discussed. Figu e 4.20 shows he 3D- eed o wa d SVM algo i hm o selec ion o sub-p ism. I is o be no ed ha , in 3D eed o wa d SVM, he second o de ha monic dis o ion and he To al Ha monic Dis o ion (THD) a e quickly and d as ically educed o lowe alues e en when using a lesse ol age imbalance. I is also o be signi ican ly no ed ha , in 3D eed o wa d SVM, he dynamic esponse achie es he same good ope a ion compa ed o he s eady s a e esponse. This pa es a way o educe he capaci ance o he dc link capaci ance, as possible oscilla ions and imbalance o he dc ol age alues will no a ec he ou pu ol ages and cu en s o he con e e . Fig. 4.20. 3D- eed o wa d SVM algo i hm o selec ion o each subp ism o co esponding s a e ec o s Table 4.8 S a e sequence & swi ching imes o 3D-FFSVM 35 Simula ion esul s o de e minis ic dc link capaci o ol age balancing app oach using 3D FFSVM also depic s imp o ed GPC pe o mance. Figu e 4.21 shows he dc link capaci o ol ages when an ini ial imbalance condi ion is en o ced. He e =0.5, l=525, ´=25 & N=0.1. As he e a e ew ansien s ini ially, a pe ec uning p ocedu e can be done o ob ain a less se ling ime. Figu e 4.22 depic s he ou pu ol age acked wi h he e e ence and igu e 4.23 shows he dc link capaci o ol ages. Fig. 4.21 DC link capaci o ol ages c1 & c2 balanced by de e minis ic app oach using 3D FFSVM wi h ini ial imbalance condi ion Fig. 4.22 Ou pu ol age- e e ence and con olled wa e o ms o de e minis ic app oach using 3D FFSVM Fig. 4.23 DC link capaci o ol ages c1 & c2 o de e minis ic capaci o ol age balancing app oach using 3D FFSVM 0 0.5 1 1.5 160 180 200 220 240 Times (ms) c1 & c2 (V) c1 c2 0.01 0.02 0.03 0.04 0.05 0.06 -200 -100 0 100 200 ca ca * 0 0.1 0.2 0.3 0.4 0.5 0.6 185 190 195 200 205 210 215 c1 & c2 (V) Time (ms) c1 c2 Ca ses Space ec o sequence Swi ching imes Sa Sb Sc 1 2 3 4 1 2 3 4 1 2 3 4 D1 D2 D3 D4 A Oa OSa OSa OSa Ob Ob Ob OSb Oc Oc OCa OCa 1-μa μa-μc μc-μb μb B Oa Oa OSa OSa Ob Ob Ob OSb Oc OCa OCa OCa 1-μc μc-μa μa-μb μb C Oa Oa a OSa Ob Ob OSb OSb Oc OCa OCa OCa 1-μc μc-μb μb-μa μa D Oa Oa a OSa Ob OSb OSb OSb Oc Oc OCa OCa 1-μb μb-μc μc-μa μa E Oa Oa OSa OSa Ob OSb OSb OSb Oc Oc Oc OCa 1-μb μb-μa μa-μc μc F Oa OSa OSa OSa Ob Ob OSb OSb Oc Oc Oc OCa 1-μa μa-μb μb-μc μc 36 4.4. COMPARISON OF THE DC LINK CAPACITOR VOLTAGE BALANCING APPROACHES The simula ion esul s o compa ing a ious dc link capaci o ol age balancing s a egies comp ises bo h he single-sided ampli ude equency spec um o he dc link capaci o ol age di e ences and he RMSe o -cum-THD alues o de e minis ic and he edundancy app oaches which a e depic ed below. The ha monics in he dc link capaci o ol age di e ence a e obse ed o all he h ee app oaches i.e. edundancy, de e minis ic-using 3D SVM and de e minis ic using 3D FFSVM. A se o simula ions a e pe o med o di e en alues o weigh ing ac o , λ and p edic ion ho izon, Nh and he esul s o bo h RMSe o and THD a e compa ed o he edundancy and he de e minis ic app oaches. RMSe o is gi en by, ^_`aaba%  de J,ghJJ,ghJ ∗ J,ghJ ∗|de ×100 % whe e /N,LMN is he ac ual ou pu ol age /N,LMN ∗ is he e e ence ou pu ol age & /N,LMN ∗|^_` is he RMS ol age e e ence =120 V, 50 Hz Fig. 4.24 Single sided ampli ude equency spec um o n /N − /N o edundancy capaci o ol age balancing app oach Fig. 4.25 Single sided ampli ude equency spec um o n /N − /N o de e minis ic capaci o ol age balancing app oach using 3D SVM Fig. 4.26 Single sided ampli ude equency spec um o n /N − /N o de e minis ic capaci o ol age balancing app oach using 3D FFSVM 0 100 200 300 400 500 600 700 800 900 1000 0 2 4 6 8 10 12 14 F equency (Hz) |x 2 ( )| (V) 0 100 200 300 400 500 600 700 800 900 1000 0 2 4 6 8 10 12 14 F equency (Hz) |x 2 ( )| (V) 0 100 200 300 400 500 600 700 800 900 1000 0 2 4 6 8 10 12 14 F equency (Hz) |x 2 ( )| (V) 37 Fig. 4.27 A zoom p e iew o single sided ampli ude equency spec um o n /N − /N o de e minis ic capaci o ol age balancing app oach using 3D SVM Fig. 4.28 A zoom p e iew o single sided ampli ude equency spec um o n /N − /N o de e minis ic capaci o ol age balancing app oach using 3D FFSVM Fig.4.29 RMSe o alues be ween he e e ence and he measu ed ou pu ol ages o di e en alues o p edic ion ho izons and weigh ing ac o s using edundancy and de e minis ic (3D SVM) app oaches Fig.4.30 THD alues o measu ed ou pu ol ages o di e en alues o p edic ion ho izons and weigh ing ac o s using edundancy and de e minis ic (3D SVM) app oaches Simula ion esul s e eal ha , in de e minis ic app oach, he e is ai educ ion o low equency ipples in he single-sided ampli ude equency spec um o he dc link capaci o ol age di e ence, which a e shown in he igu e 4.24, 4.25 & 4.26. These low equency ipples a e caused by he swi ching o he dc link capaci o s. In o de o ha e a be e compa a i e iew, he igu es 4.27 & 4.28 a e depic ed, which shows a zoom p e iew o he single-sided ampli ude equency spec um o he dc link capaci o ol age di e ence o de e minis ic app oach using 3D SVM and 3D FFSVM. The simula ion esul s also e eal ha he de e minis ic app oach o capaci o ol age balancing has low RMSe o and THD alues, han he edundancy app oach, which a e depic ed in he igu e 4.29 & 4.30. I is o be no ed ha in igu es 4.29 and 4.30 he 3D SVM is used in he de e minis ic app oach. 0 100 200 300 400 500 600 700 800 900 1000 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 F equency (Hz) |x 2 ( )| (V) 0 100 200 300 400 500 600 700 800 900 1000 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 F equency (Hz) |x 2 ( )| (V) 56789 0 1 2 0 2 4 6 P edic ion ho izon(N h ) Weigh ing ac o ( λ λλ λ ) E o (% ) Redundancy app oach De e minis ic app oach 56789 0 1 2 0 1 2 3 P edic ion ho izon(N h ) Weigh ing ac o ( λ λλ λ ) THD(%) Redundancy app oach De e minis ic app oach 38 CHAPTER 5 DESIGN OF A NPP POWER INVERTER The o emos s ep in designing he p o o ype o NPP powe in e e is e alua ing he IGBT module. The main componen s used in his p ocess a e he Digi al Signal P ocesso (DSP) de ice (TMS320F28335), IGBT d i e boa d & i s I/O connec o s, IGBT module, a esis i e load (say 300 Ω), a Ca hode Ray Oscilloscope (CRO), a compu e /lap op wi h ins alled Code Compose S udio (CCS) , egula ed DC powe sou ce o con e e inpu , a 15 V DC powe sou ce o IGBT d i e boa d and ew connec ing wi es. Figu e 5.1 shows he block diag am o he main componen s including In eg a ed Ci cui s (ICs) & connec o s and hei connec ions o he NPP module e alua ion. The swi ching pulses ac oss he ga e-emi e e minal and he ou pu ol age ac oss he load esis o a e obse ed by CRO du ing e alua ion. Al hough he IGBT d i e is used o d i e wo modules in pa allel, only one module (single mode ope a ion) is used o e alua ion pu pose. The main aim o he e alua ion o he AT-NPC 3-le el 4in1 IGBT module [79] is o ensu e, ha he PWM pulses (T1, T2, T3 and T4), which a e gene a ed by he DSP p ope ly i es he semiconduc o swi ches in he IGBT module, ia he IGBT d i e boa d and he ou pu ol age is checked ac oss he load esis o . Fig. 5.1. Block diag am consis ing o main componen s, ICs & connec o s o he NPP module e alua ion Ci cui a angemen , desc ip ion & wo king The DSP TMS320F28335 is p og ammed o p oduce he ga e signals wi h swi ching equency-2kHz, Vpeak- o-peak=3.44 V (0-3.44 V swi ching pulse) and du y cycle-50 % based on he swi ching modes, shown in able 5.1, in which ‘ON’ ep esen s a ull pulse wi h 100 % du y cycle, ‘OFF’ ep esen s he swi ching pulse wi h 0% du y cycle and ‘SW’ ep esen s a swi ching pulse o use ’s choice o du y cycle (as he pu pose is e alua ion o he p o o ype). Enhanced Pulse Wid h Modula o (ePWM) 1-6 e e s o six pins in he Gene al Pu pose Inpu /Ou pu (GPIO) o he DSP de ice [80], specially designed o aking he PWM signals o he d i e , once i is p og ammed in Code Compose S udio (CCS) [81], ins alled in a 39 compu e o lap op. ePWM1A (a GPIO0) is used as T1, ePWM1B (a GPIO1) is used as T2, ePWM3A (a GPIO4) is used as T3 and ePWM3B (a GPIO5) is used as T4. Fig. 5.2. Ci cui a angemen showing DSP connec ed o he IGBT d i e boa d Table 5.1 Swi ching modes o AT-NPC 3- le el IGBT module (a h ee le el NPP con e e leg) SW mode A1 B1 A2 B2 T 1 SW OFF OFF OFF T 2 OFF OFF SW OFF T3 OFF SW ON ON T 4 ON ON OFF SW Table 5.2 Pin con igu a ion o Inpu connec o s- CN1 & CN101 o each IGBT d i e boa d Pin Signal Connec o 1 PWM signal o high side IGBT(T 1 ) CN1 2 PWM signal o RB - IGBT(T 4 ) CN1 3 PWM signal o RB- IGBT(T 3 ) CN1 4 PWM signal o low side IGBT(T 2 ) CN1 5 GND CN1 6 GND CN1 7 GND CN1 8 GND CN1 9 GND CN1 10 Faul de ec ion ou pu IGBT (T 1 , T 2 ) CN1 1 VDC (15 V) CN101 2 NC CN101 3 GND (0 V) CN101 40 The ou swi ching pulses ob ained om DSP a e sen o he IGBT d i e boa d ia he connec o CN1. The d i e boa d is powe ed by a 15 V DC sou ce ia CN101. The pin con igu a ion o hese wo connec o s i.e. CN1 & CN101 a e u nished in he able 5.2. The o emos componen s whe e he PWM signals en e he IGBT d i e boa d ia CN1 connec o a e he Complemen a y MOSFET (CMOS) in e e s (2 no.s) [82], which p o ides a bu e ed ou pu wi h high noise immuni y and s able ou pu . These componen s a e ollowed by op ocouple s (4 no.s), which a e used o d i e, u n-on and o he powe semiconduc o swi ches. These dual ou pu s d i en op ocouple (ACPL-339J) [83] con ains a AlGaAs LED each, which is op ically coupled o an in eg a ed ci cui wi h wo powe ou pu s ages wi h ac i e iming con ol o p e en c oss conduc ion a ex e nal MOSFET bu e . I is also in eg a ed wi h ea u es such as VCE de ec ion, unde ol age lockou (UVLO), ‘so ’ IGBT u n-o and isola ed open collec o aul eedback o p o ide maximum ci cui p o ec ion and in eg i y. I is also no ed ha he DESAT p o ec ion is he highligh ing ea u e o hese ype o op ocouple s, which makes u ns o he IGBT sho ly whene e a DESAT (o sho ci cui ) aul is de ec ed. These op ocouple s a e ollowed by he ul alow esis i e dual N and P channel MOSFETs (4 no.s) [84], which deli e supe io powe densi y and lowe swi ching losses o sh ink he PCB size and imp o e he o e all sys em e iciency. These MOSFETs a e combined wi h excellen he mal pe o mance and low on-s a e esis ance. The e is a common mode choke o ensu e p o ec ion be ween he MOSFET and he ou pu e minal connec o s-CN2, CN3, CN4, CN5, CN6 & CN7 o he IGBT d i e s. Table 5.3 shows he pin con igu a ion o hese connec o s. Figu e 5.3 shows he connec ions be ween he ou pu e minal o he IGBT d i e and he connec o s- CN8, CN9 & CN10. These connec o s ha e space o componen s like ac i e clamp and esis o s, which a e used o p o ec ion du ing sho ci cui . These connec o s a e moun ed on he IGBT module. I should be no ed ha he ac i e clamp diode a e no ini ially connec ed, as only ew IGBT module needs i . The e is a DC/DC con e e in he le end o he boa d, which ensu es app op ia e powe supplies o he ICs. Du ing single mode ope a ion (connec ing only one IGBT module) he common mode choke a ea is sho ci cui ed and he connec o CN3 should no be used. Ei he o he connec o s- i.e. CN5 o CN4 and CN6 o CN 7 can be used du ing single mode ope a ion. Ca e should be aken ha he IGBT is no ope a ed wi hou connec ing T1C and T1 collec o e minal. Table 5.3 Pin con igu a ion o Ou pu connec o s- CN2, CN3, CN4, CN5, CN6 & CN7 o each IGBT d i e boa d Pin Connec o Rema ks Rema ks 1 CN2/CN3 RB-IGBT Ga e (T4G) connec ed o CN8-1 2 CN2/CN3 high side IGBT & RB-IGBT Emi e (T1/T4E) connec ed o CN8-2 3 CN2/CN3 high side IGBT Ga e (T1G) connec ed o CN8-3 4 CN2/CN3 No Connec ion - 5 CN2/CN3 No Connec ion - 6 CN2/CN3 high side IGBT Collec o (T1C) connec ed o CN8-6 1 CN4/CN5 low side IGBT Emi e (T2E) CN1 2 CN4/CN5 low side IGBT Ga e (T2G) CN1 1 CN6/CN7 RB-IGBT Emi e (T3E) CN1 2 CN6/CN7 RB-IGBT Ga e (T3G) CN1 41 Figu e 5.3 Connec ion be ween he ou pu e minals o IGBT d i e boa d and he connec o s-CN8, CN9 & CN10 D i e s and Fi s Faul De ec ion (FFD) Ini ially, he componen s shown in able 5.4 a e de ec ed o be no wo king, since he componen s ou pu s a e no he desi ed one, which a ied om hose o he wo king d i e s. Table 5.4 Lis o Faul y componen s du ing FFD Fig. 5.4 IGBT D i e 1 IGBT D i e s Numbe o Op ocouple s- no wo king Numbe o MOSFET- no wo king D i e 1 - - D i e 2 2 ( o T4 and T1) 1 ( o T2) D i e 3 1 ( o T2) - 42 Fig. 5.5 IGBT D i e 2 Fig. 5.6 IGBT D i e 3 Fig.5.7 Faul y Op ocouple ’s High side ol age ou pu Fig.5.8 Faul y Op ocouple ’s Low side ol age ou pu P og ess o wo k in ixing he D i e s i. When he aul y op ocouple (T2) in d i e 3 is eplaced wi h he one o he wo king op ocouple s o d i e 2, he same esul s we e obse ed as shown in igu e 5.7 & 5.8. Du ing his p ocess, he solde ing s a ion is used o unsolde he IC and he empe a u e o he solde ing s a ion anges om 200-450 °C. So, he eplaced op ocouple s a e suspec ed o ha e damaged LED du ing his eplacemen p ocess. ii. A e eplacing a new MOSFET a T2 in d i e 2, s ill he same esul s we e ob ained. Now, when checking he esis o , R36 (10 Ω) a he ou pu o he MOSFET, i has been obse ed ha he esis ance alue is oo high in kΩs (open-ci cui ed). When he esis o R36=10 Ω is eplaced, he T2 o d i e 2 wo ks well. So, now he T2 o d i e 2 is ixed. 43 A= C5, C7, C9, C11 (1 μF) B= C6, C8, C10, C12 (10 μF) C= C13, C14, C15, C16 (1 μF) VE= Common (IGBT Emi e ) ou pu supply ol age VCC2= Posi i e ou pu supply ol age VEE= Ou pu supply ol age Fig.5.9 Op ocouple seconda y side powe supplies-ou line iii. When he new op ocouple s o T1 and T4 o d i e 2 & T2 o d i e 3 a e eplaced, same esul s we e ob ained. Now, he ol age supplies o he op ocouple a e examined and ound ha he ol age ac oss VCC2-VE is no he desi ed alue. Table 5.5 shows he a ing o he ou pu side powe supply o he op ocouple and able 5.6 shows he obse ed alues in he aul y op ocouple s. The capaci o A (C5, C7 o d i e 2 and C9 o d i e 3) is checked, because i can also ail o main ain he ol age ac oss VCC2-VE. So, new capaci o s we e eplaced in A o he aul y op ocouple s. Figu e 5.9 shows he ou line o op ocouple ’s seconda y side powe supplies. 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