Switched-capacitor neural networks for linear programming

observed in an ordinary asymmetric reflectivity DFB laser without L/4 phaseshift was due to a mode partition between the DFB mode and Fabry-Perot modes caused by insufficient AR coating at one end of the laser. So far TE-TM mode partition as shown in Fig. 3 has not been observed. In the 44 shifted DFB laser the threshold gain difference AaL among TE modes or among TM modes is around 0.7 when optimally de~igned,~ i.e., KL is 1.25, while the mode selection between TE and TM mode provided by the difference in the coupling coefficient and the mode confinement factor is very small. Theoretical calculation assuming a rectangular shaped corrugation using a model by Streifer et aL4 showed that there was no difference in the coupling coefficient between TE and TM modes for the active layer thickness d, of 0.15pm. For a thinner d, of 0.1 pm there was a slight difference. However, even in this case, the AKL for optimum KL of 1.25 was only 0.06, which corresponded to the threshold gain difference AaL between TE and TM mode of only 0.07. The difference in mode loss owing to the mode confinement factor could not be as large because of the small absorption coefficient of the cladding layers. The mode selection between TE and TM mode in a 1/4 shifted DFB laser is much smaller than that in an ordinary asymmetric reflectivity DFB laser in which TE-TM mode selection is provided by the facet reflectivity. Fig. 4 shows the time averaged spectra of a 1/4 shifted DFB laser under modulation measured using a polariser. We can identify a small amplitude TM emission. This small amplitude TM emission is evidence of TM mode lasing with a very small probability, of the order of IO-’’, under modulation due to the gain overshoot. n TM h I I I wavelength, p m 1 30 131 132 Fig. 4 Time averaged spectra under modulation TM spectrum was measured using a Clan-Thompson polariser We have developed a very-low-threshold-current highefficiency i/4 shifted DFB laser having bandwidth of 11 GHz. However, transmission experiment revealed that there existed a mode partition between TE and TM mode. This mode partition is due to a small threshold gain difference between TE and TM mode. To make full use of the attractive feature of the 1/4 shifted DFB laser, Le., the large threshold gain difference between modes, we must incorporate a strong mode selection mechanism between TE and TM mode. This is especially important for a laser to be used in several Gbit/s systems under a direct modulation scheme. The authors wish to thank M. Matsuda for his fabrication of the 144 shifted corrugations, and S. Isozumi, T. Kusunoki, T. Tanahashi, H. Sudo and M. Sugano for their co-operation in this work. They also wish to thank T. Misugi, M. Kobayashi, and T. Sakurai for their encouragement. H. ISHIKAWA K. KAMITE K. KIHARA H. SODA H. IMAI Fujitsu Laboratories Ltd. 10-1 Morinosato- Wakumiya, Atsugi, Japan 496 26th February 1988 References ISHIKAWA, H., SODA, H., WAKAO, K., KIHARA, K., KAMITE, K., KOTAKI, Y., MATSUDA, M., SUDO, H., YAMAKOSHI, s., ISOZUMI, s., and IMAI, H.: ‘Distributed feedback laser emitting at 1.3 pm for gigabit communication systems’, J. Lightwave Technol., 1987, LT-5, pp. 848-855 KAMITE, K., sum, H., YANO, M., ISHIKAWA, H., and IMAI, H.: ‘Ultrahigh speed InGaAsP/InP DFB lasers emitting at 1.3pm wavelength, IEEE J. Quantum Electron., 1987, QE-23, pp. 10561058 SODA, H., KOTAKI, Y., sum, H., ISHIKAWA, H., YAMAKOSHI, s., and IMAI, H.: ‘Stability in single longitudinal mode operation in GaInAsP/InP phase-adjusted DFB lasers’, IEEE J. Quantum Electron., 1987, QE-23, pp. 804-814 STREIFER, w., SCIFRES, D. R., and BRUNHAM, R. D.: ‘TM-mode coupling coeficients in guided-wave distributed feedback lasers’, IEEE J. Quantum Electron., 1976, QE-12, pp. 7478 SWITCH ED-CAPACITOR NEURAL NETWORKS FOR LINEAR PROGRAMMING Indexing terms: Neural networks, Switched-capacitor networks, Linear programming solvers, Circuit theory and design A circuit for online solving of linear programming problems is presented. The circuit uses switched-capacitor techniques and is thus suitable for monolithic implementation. The connection of the proposed circuit to analogue neural networks is also outlined. Introduction: It has been shown that both linear and nonlinear programming problems can be solved by using analogue circuits with a neural-like structure.’,’ These circuits exhibit strong potential for those applications where online optimisation is required as is the case in robotics, satellite guidance, etc. Breadboard prototypes have been built using off-the-shelf circuit components. ‘G~ Since the required component-count is very high even for simple examples, it makes sense to explore the possible realisation of these circuits using fully integrated techniques. Nonlinear programming solvers are particular examples of the broader family of analogue neural networks, which is of increasing interest because it seems to pave the way for analogue artificial intelligence circuit^.'.^ However, the field of analogue neural networks is just emerging and very little has been done on the practical implementation of the different classes of such networks. In a very recent letter, Tsividis and Anastassiou’ proposed a technique for the VLSI implementation of a type of analogue neural network using a switchedcapacitor neural cell. The proposed technique is adequate for solving optimisation problems that can be formulated in an explicit form,’ but not readily applicable to linear and nonlinear programming problems. A different strategy is required for this type of analogue neural network, since the equations describing mathematical programming problems are implicit in nature and do not admit to being cast in an explicit form.’ In this letter we propose a method for the realisation of linear programming solvers using switched-capacitor techniques. The proposed circuits are members of the general family of analogue neural networks, being more adequate for monolithic implementation than previous linear programming solver proposals. Problem formulation and proposed circuit structure: The general linear programming problem can be stated as follows.6 Minimise a scalar cost function @(x) = 1 aixi i= 1 subject to a set of p constraints, n LXx) = 1 bji xi 2 0 i= 1 l<j<p (2) where x is the vector of variables for the problem, p and n are integer numbers and a and bj, for each j, are vectors of coefficients. ELECTRONICS LETTERS 14th April 1988 Vol. 24 NO. 8 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 31,2020 at 14:34:02 UTC from IEEE Xplore. Restrictions apply. By using the concept of the penalty function' and applying a gradient strategy we obtain the following numerical algorithm to solve the above general linear programming problem, where a is an arbitrary positive constant, q is an integer number for the iteration count and functions w(f) and pj are defined as follows, 1 0 otherwise iffj 2 0 for every j w(n = { (4) where Note that the introduction of the function w(f) means a modification of the traditional way of combining f and @ to define penalty functions.' This modification is important to improve the convergence of the algorithm. Using eqns. 4 and 5 and eqns. 1 and 2 in eqn. 3 we obtain the following relationship for each component of x: is an arbitrary positive constant. where sgn (.) is the well-known sign function. IV I ll II 'qdd phose Fig. 1 Block diagram of proposed linear programming solver Fig. 1 shows the conceptual block diagram for the implementation of the general linear programming problem using switched-capacitor techniques. Note that one integrator is required per program variable. The p constraint functions are obtained via a set of summers whose inputs are the integrator outputs. The nonlinear functions w(f) given in eqn. 4, and = +(I - sgn (L)) are respectively obtained from the outputs of the summers via the block at the bottom of the Figure on the right, henceforth called the constraint block. Fig. 2 shows a detail of the ith integrator block. A twophase clock signal is used to control the analogue switches. The input switches are directly controlled by one of the phases (the even clock phase) and the switches connected to the op-amp negative input lead are controlled by the outputs of the constraint block. These outputs are defined during the odd clock phase. By elementary analysis involving charge conservation principles it is clear that the circuit in Fig. 2 implements eqn. 6. The summer block appearing in Fig. 1 can be implemented by using techniques reported elsewhere.' Fig. 2 Detail of integrator block Practical results: The proposed circuit has been computer simulated using DIANA' and a detailed macromodel for the op-amps.' The simulated programming problems are listed in Table I, where both the theoretical solution and the one computed by DIANA are shown for every example. Also included in Table 1 is the number of clock periods required for the circuit to reach its final state. In all the cases, the initial state was the origin of the program variable space. As can be seen it is possible to obtain a very approximate solution in relatively few clock periods. Conclusions: A circuit structure is proposed for implementing linear programming problems using switched-capacitor techniques. This structure is based on a reduced set of basic cells that are interconnected following a dense regular pattern. The resulting circuits exhibit a very high modularity and in this sense can be considered as members of the general family of analogue neural networks. The method is valid for any linear programming problem and is also suitable for monolithic implementation, a significant advantage as compared to previous analogue neural linear programming solvers.'*2 Acknowledgments: This research has been supported by Spanish CICYT under contract no. ME87-0004. A. RODRIGUEZ-VAZQUEZ 9th February 1988 A. RUEDA J. L. HUERTAS R. DOMINGUEZ-CASTRO Departamento de Electricidad y Electrbnica Facultad de Fisica Universidad de Seuilla Anda. Reina Mercedes sjn, 41012-Sevilla, Spain Table 1 THEORETICAL AND SIMULATION RESULTS FOR TWO PROBLEMS Scalar function Simulated Number of constraints solution DIANA periods and Theoretical solution using clock @ = v, + v2 f2 = 5 + u, f2 = 5 - u2 @ = 3v, + (1/2)v, - (1/2)v3 fl = 35/12 - (5/12)v1 + ~2 v1 = -5 ~1 = -4.99 f 0.03 40 f2 = 3512 - (5/2)~1 - VZ u2 -5 02 = -5.03 0.08 f, = 6 + v1 + v2 + v3 01 = -6 VI = -5.88 f 0.3 f2 = 6 - V, - 02 - ~3 v2 = 0 v2 = -0.04 f 0.11 40 f3 = 6 + v1 + v2 - 2v3 f4 = 6 - 01 - 02 + 203 fs = 6 + VI - 2~2 + 03 f6 = 6 - 01 + 2~2 - 03 vj = 0 v3 = -0.01 f 0.15 ELECTRONICS LETTERS 14th April 1988 Vol. 24 No. 8 497 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 31,2020 at 14:34:02 UTC from IEEE Xplore. Restrictions apply. References 1 TANK, D. w., and HOPFIELD, J. J.: ‘Simple “neural” optimization networks: an A/D converter, signal decision circuit, and a linear programming circuit’, IEEE Trans., 1986, CAS33, pp. 53>541 KENNEDY, M. P., and CHUA, L. 0.: ‘Unifying the Tank and Hopfield linear programming circuit and the canonical nonlinear programming circuit of Chua and Lin’, IEEE Trans., 1987, CAS-34, pp. 21G214 3 WILSON, G. : ‘Quadratic programming analogs’, IEEE Trans., 1986, 4 TSIVIDIS, Y.: ‘MOS analog IC design-new ideas, trends and obstacles’. Proceedings of the 1986 European Conf. on Solid-state Circuits, 1986, pp. 113-115 5 TSIVIDIS, Y., and ANASTASIOU, D.: ‘Switched-capacitor neural networks’, Electron. Lett., 1987, 23, pp. 958-959 6 VANDERPLAATS, G. v.: ‘Numerical optimization techniques for engineering design: with applications’ (McGraw-Hill, New York, 1984) 7 GREGORIAN, R., and TEMFS, G. c.: ‘Analog MOS integrated circuits for signal processing’ (Wiley-Interscience, 1986) 8 ARNOUT, G., REYNAERT, PH., CLAESEN, L., and DIJMLUGOL, D.: ‘DIANA V7E user’s guide’. ESAT Laboratory, Katholieke Universiteit Leuven, 1983 PBREZ-VERDI~, B., HUERTAS, J. L., and RODRIGUEZ-V~ZQUEZ, A.: ‘A new nonlinear time-domain op-amp macromodel using threshold functions and digitally-controlled network elements’, IEEE J. Solid-state Circuits, 22, to be published 2 CAS-33, pp. 907-91 1 9 second structure (58N). We have measured for the third structure (SON) sheet concentrations as high as 8 x 10” cm-’ with mobilities of 3500cmZ/Vs. The processing of these MESFETs was similar to that reported previously.6 The MESFETs had a gate length of 0.7 pm with a 4.0pm source/drain spacing. The 1/V characteristics of 58N-structure MESFET having a 100pm gate width are shown in Fig. 1. A drain saturation current of 870mA/mm and complete pinch off at a gate voltage of -3.5V is achieved. For the 48N structure MESFET, a drain current of 680mA/mm with a pinch off voltage of - 3.0V was measured. For devices on the SON-structure with a sheet concentration of 8.0 x 1012cm-z, we measured currents as high as l.OA/ mm but they could not be pinched-off. Fig. 2 shows the variation of the transconductance with gate voltage for the 58N-structure MESFET. The large bandgap AlInAs confines the carriers in the channel, resulting in the broad peak in the transconductance against gate voltage and improved linearity for high-power FETs. Extrinsic transconductances as high as 325 mS/mm were achieved. For the 48N-structure MESFETs, we achieved transconductances between 250 and 3 10 mS/mm. A gate/drain breakdown voltage of 3.2V was measured at a leakage current of 0.5 pA/pm of gate width for the 58N structure. Higher breakdown voltages can be obtained with thicker undoped AlInAs layers, but at a sacrifice of transconductance. vg=o - HI G H - C U R R E NT P U LS E - DOPED Ga I n As MESFET Indexing terms: Semiconductor devices and materials, Fieldeffect transistors, Gallium compounds We report the DC and microwave performance of pulsedoped GaInAs power MESFETs. For a 0.7pm gate-length device, a maximum drain-current density of 870mA/mm and a peak transconductance of 325 mS/mm were measured. A maximum stable gain of ll.7dB at 26GHg and an extrapolatedf, of 33 GHz were obtained. These values are the highest reported for MESFETs having gates as long as 0.7 pm. Power amplifiers based on GaAs/AlGaAs HEMTs suffer from low drain-saturation current. Recently, multichannel and pseudomorphic HEMTs have been developed to increase current densities,‘-4 but the low thermal conductivity of the GaAs substrate limits the maximum achievable power of these devices. Improved performance can be obtained by using AlInAs/GaInAs heterostructure FETs, which combine high mobility with high sheet-carrier concentration. In addition, the InP substrate offers higher thermal conductivity than GaAs. The microwave performance of AlInAs/GaInAs HEMTs is beginning to surpass that of GaAs/AIGaAs HEMTs.*’ We recently reported nt-pulse-doped GaInAs MESFETs of 0.7pm gate length with excellent maximum stable gains of 14dB at 26.5 GHz, and a maximum frequency of oscillation of greater than 100GHz.6 In this letter, we report the fabrication and performance of n+-GaInAs-channel MESFETs with both high current densities and high gains. The pulse-doped GaInAs MESFET structure was grown by MBE on a semi-insulating InP substrate. The device structure consisted of a 2500A AlInAs buffer layer, lOOA of undoped GaInAs, a 200A n+-GaInAs layer, 500A of undoped AIInAs, and a l00A n+-GaInAs cap. All the layers were lattice matched to InP. The undoped AlInAs layer reduces the gate leakage current and increases the barrier height. We have grown three structures with varying electron concentration. For the first structure (48N), a Hall mobility of 4100cm2/Vs with an electron concentration of 4.8 x 10’2cm~Z was measured at 300K. A Hall mobility of 4100cm2/Vs with an electron concentration of 5.8 x 10’2cm-2 was measured for the * FATHIMULLA, A,, ABRAHAM, J., and LOUGHRAN, T.: ‘High performance InGaAs/InAlAs HEMTs and MESFETs’. Submitted for publication (IEEE Electron. Device Letts.) 498 / vs I- 2 5v vg = -3 ov vg =-3 5v ::e,;, 10 0 05 10 15 20 25 source drain voltage, V Fig. 1 IIV characteristics of a pulse-doped GalnAs MESFET The microwave performance of these MESFETs for different source/drain voltages and gate voltages was measured over the frequency range 0.5-26.5 GHz using an automated Cascade wafer probe and an HP 8510 network analyser. Fig. 3 is a plot of the maximum stable gain (MSG) against frequency computed from the measured S-parameters. An MSG of ll.7dB at 26.0GHz and an extrapolated fmx of over 100GHz was obtained. The current gain was also computed from the measured S-parameters. Extrapolating a 6 dB/octave roll-off, a current-gain cutoff frequency Cf,) of 33GHz was obtained. The microwave-gain measurements were performed both before and after isolating the gates from the edge of the mesa.* After gate isolation, we measured an increase in the MSG, which we attributed to a decrease in the gate-leakage current. 350r lOOV , I I I I I -3 5 -3 0 -2 5 -2 0 -1 5 -1 0 -0 5 0 gate voltage, V 111312/ Fig. 2 Transconductance against gate voltage for pulse-doped GalnAs MESFET ELECTRONICS LETTERS 14th April 1988 Vol. 24 No. 8 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on March 31,2020 at 14:34:02 UTC from IEEE Xplore. Restrictions apply.