Low-cost digital detection of parametric faults in cascaded ΣΔ modulators

1 Low-Cost Digital Detection of Parametric Faults in Cascaded Σ∆ Modulators Gildas L´ eger, and Adoraci´ on Rueda, Member, IEEE Abstract—The test of Σ∆ modulators is cumbersome due to the high performance they reach. Moreover, technology scaling trends raise serious doubts on the intra-die repeatability of devices. Increase of variability will lead to an increase in parametric faults difficult to detect. In this paper, a designoriented testing approach is proposed to perform simple and low-cost detection of variations in important design variables of cascaded Σ∆ modulators. The digital tests could be integrated in a production test flow to improve fault coverage and bring data for silicon debug. A study is presented to tailor signature generation, with test time minimization in mind, as function of the desired measurement precision. The developments are supported by experimental results that validate the proposal. Index Terms—Σ∆ modulation, Design for testability, testing, fault diagnosis. I. INTRODUCTION IN the field of analog to digital conversion, Σ∆ converters manage to push much of the hardware to the digital domain. As a result, this type of converter benefits of technology scaling in a major amount than other architecture. The vast success of Σ∆ converters has motivated extensive research which has driven Σ∆ modulators to their limits. As technology shrinks to the nanometer scale, the scientific community agrees to state that intra-die variability (i.e. device mismatch) will become a major bottleneck if it is not properly handled [1]. From a test viewpoint, an important increase of parametric faults can thus be expected. For Σ∆ modulators, that have gained much interest because of their low sensitivity to the performance of their analog parts, such an evolution might be critical. Indeed, ADC black-box functional tests may fail to detect parametric deviations that could evolve as reliability issues. Interesting functional Built-In Self-Test (BIST) techniques can be found in the literature. In [2] is shown how to compute in a simple manner the gain error, offset and 3rd order distortion of the ADC transfer function. On the other hand, [3] implements an on-chip histogram test, and [4] uses digitally (c) 2009 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. This work has been partially funded by the Junta de Andaluc´ ıa project EXC/2005/TIC-927 and by the Spanish Government project TEC-2007-68072. Dr. L´ eger is with the Instituto de Microlectr´ onica de Sevilla, Centro Nacional de Microelectr´ onica, Consejo Superior de Investigaciones Cient´ ıficas (CSIC), 41012 Sevilla, Spain. Pr. Rueda is with the Instituto de Microlectr´ onica de Sevilla, Centro Nacional de Microelectr´ onica, Consejo Superior de Investigaciones Cient´ ıficas (CSIC) and Universidad de Sevilla, 41012 Sevilla, Spain. encoded sine-waves to perform FFT tests. In the original work, a filter is used to remove the quantization noise. However, several works have proposed to directly use the Σ∆ encoded sine-wave as a test stimulus for Σ∆ modulators. In [5], the authors propose to use a sine-wave encoded at the same order as the modulator under test but to scale down the resulting stimulus with respect to the full-scale. In this way, they ensure that the quantization noise of the test stimulus remains below that of the modulator. In [6] and [7], the authors propose to use a sine-wave encoded at a higher order, so that the portion of the test stimulus quantization noise that lays in the baseband of the test stimulus is lower than that of the modulator under test. These techniques have proven useful to evaluate functional metrics at reasonable cost but with, at best, the same precision as the standard functional test they are based on. In particular, it is shown in [7] that the test accuracy is limited for signals close to full-scale. Similarly a fault simulation in [6] demonstrates that the proposed test underestimates the distortion in some cases. In that sense, they can help reducing the cost of a functional test flow but do not provide added value in terms of fault coverage. On the other hand, purely defect-oriented approaches usually lack of faithful validation. Indeed, it is not possible to physically model and simulate all the possible defects (including electrical deviations) and to estimate their probability of occurrence. The validation of defect-oriented approach is thus limited to fault coverage [8], where accuracy has to be sacrificed for computability. In switched capacitors circuits, only shorts, opens and deviations in the capacitor ratios are often considered [9], [10]. In previous papers [11] and [12], the authors have proposed a fully digital BIST scheme that allows to measure important design variables of the main building block of Σ∆ modulators: namely, the integrator pole error and its settling error. In this paper, we show how the digital tests could be integrated in a production test flow to improve fault coverage and bring data for silicon debug. Indeed the requirement of hardware simplicity can be relaxed if the target is not a full-BIST scheme, and better test signature can be built. Relying on experimental results from an integrated prototype, it is shown how the signature generation can be tailored to reach an adequate precision on the measurement of integrators leakage and settling errors. The fully digital nature of the test allows the use of a low-cost digital tester and enables parallel test, while test time remains greatly lower than conventional FFT-based functional test. The test scheme is a good complement to functional test, as it brings important information on building blocks. In that 2 sense, it could be compatible with the functional BIST scheme proposed in [6] that performs an SNDR test using a 1-bit digital stimulus like in [4], leading to noticeable agreement with standard SNDR test for small amplitudes. The injection of this digital stimulus relies on the same principle as for our method. As was said previously, one drawback of the approach in [6] is that it cannot detect small THD induced by near fullscale signals. Our approach would not only improve the defect coverage for this case, due to the good sensitivity to integrator settling error, but also enhance diagnosing capability. The paper is organized as follows: Section 1 reviews the digital tests and presents the Σ∆ modulator prototype fabricated to prove their feasibility. Section 2 demonstrates how test signature can be effectively generated to provide diagnosis capability in a reduced time. Section 3 addresses the possibility to use the decimation filter for test purpose if the bit-stream is not accessible, and provides interesting comparison with functional test results. Section 4 discusses possible improvements of the method, and Section 5 draws the conclusions of the paper. II. THE DIGITAL TESTS A. Test concept and prototype The idea behind the proposed tests is to evaluate the nonidealities of the building blocks that compose a cascaded Σ∆ modulator. Principally, tests have been developed to evaluate the pole error and the settling error in the different integrators, because these design variables are key to the overall performance of Σ∆ modulators. This approach can be applied to any cascaded combination of 1st and 2nd order stages. Work is still necessary to extend the proposal to higher order singleloop architectures. While 1st and 2nd order modulators are inherently stables, higher order modulators can have bounded states only for a limitted range of inputs [13]. The digital stimuli used for test purpose in our proposal induce higher internal states than DC levels [14]. Stability during test mode may thus be a concern for modulators of order higher than 2. Multibit quantizers are usually used only in the last (and less critical) stage of cascaded modulators. We will thus limit the scope of this paper to single-bit quantizer, but the reader can refer to [11] and [14] for multi-bit tests. The procedure is common to all the tests, and the generic setup is shown in Fig.1 for a cascaded modulator. Under test mode, the modulator operating conditions are set such that the DC component of the response deviates from the DC component of the test stimulus in an amount that is proportional to the non-ideality under test. The test stimulus is a digital sequence that can be periodic (with a short period of less than 10 samples) or pseudorandom. The output bit-stream (Yi) is acquired by the test equipment (i.e. a simple digital ATE) and the signature computed off-chip. The modifications of the modulator operating conditions affect exclusively control signals of the switches. As a result, a configuration register has to be introduced to control the different test modes. It is important to notice that no additional switch is introduced, so that the signal path remains unaffected ADC DAC DAC ADC DAC reconstruction filter decimation filter X Y1 Y2 SEQ Yt configuration register Conf master clock modulator under test test resources Fig. 1. Generic setup for cascaded Σ∆ modulator digital test with two dedicated test inputs: one for configuration and another for the digital stimulus by the DfT modifications and no particular optimization is needed for the building blocks. The switch control modifications require some clock gating, in a way similar to what is proposed in [7]. In any case, this is not a critical point from a jitter perspective, because the gated switches are not those that define the sampling instant. More details can be found in [12] and [14] about practical implementation. Among other modifications, each summing node is modified such that the direct input (i.e. the positive input in Fig.1) can be disabled and the feedback DAC can be re-used to send the test sequence. In this way, the different stages of the cascaded modulator can be considered individually. In order to give experimental support to our approach, a prototype has been integrated in a CMOS 0.35 µm technology. This prototype is the 2-1 cascaded modulator shown in Fig.2. The three integrators are driven by the same sampling and feedback phases (Φ1and Φ2, respectively) at a nominal frequency of 2MHz. On the left side, the z-domain and switched capacitor implementation is presented for nominal operation. It can be noticed that the switches that form the feedback DACs are driven by the stage output. On the right side an example of test configuration has been illustrated. The 2nd and the 3rd integrators are tested in parallel. The switch of the direct path of the integrator under test is maintained open while the feedback DAC is re-used during the sampling phase (Φ1) to send the test stimulus. It can be appreciated how the test configuration for the 2nd integrator actually reconfigures the stage as a first order for test purpose. In order to test the first integrator, the digital stimulus would be fed through the first DAC, and the nominal input switches dsiconnected. The rest of the modulator could remain unchanged with respect to nominal operation, though the second stage (i.e. the 3rd integrator) could also be disconnected and tested in parallel. It is known that the performance of a Σ∆ modulator is more sensitive to the first integrator than to those located further in the loop which can be simplified. However, for the sake of design time reduction, the same integrator has been re-used in our prototype. This also brings us the possibility to directly compare the results obtained for the 3 integrators. 3 0.5 z-1 1-z-1 Y1 Y2 C 1 C 2 Y1 Y2 C 1 C 2 C 1 C 2 a) Vrefp Vrefn Vrefp Vrefn Y 1 Y 1 Y 1 Y 1 Y 2 Y 2 Y 1 Y 1 Y 1 Y 1 Y 2 Y 2 0.5 z-1 1-z-1 0.5 z -1 1-z -1 Vrefp Vrefn Vrefp Vrefn Vrefp Vrefn Vrefp Vrefn 0.5 z-1 1-z-1 Y1 Y2 Y1 Y2 C 1 C 2 C 1 C 2 b) Y 1 . Φ 2 +SEQ. Φ 1 Y 1 . Φ 2 +SEQ. Φ 1 0.5 z-1 1-z-1 0.5 z -1 1-z -1 Vrefp Vrefn Vrefp Vrefn Vrefp Vrefn Vrefp Vrefn test input SEQ φ1 φ1 φ2 φ2 φ1 φ1 φ2 φ2 φ1 φ1 φ2 φ2 Y 1 . Φ 2 +SEQ. Φ 1 Y 1 . Φ 2 +SEQ. Φ 1 Y 2 . Φ 2 +SEQ. Φ 1 Y 2 . Φ 2 +SEQ. Φ 1 Y 2 . Φ 2 +SEQ. Φ 1 Y 2 . Φ 2 +SEQ. Φ 1 Fig. 2. Σ∆ modulator prototype: a) in nominal configuration; b) in leakage test mode for the 2nd and 3rd integrators, the nominal integrator input switch remains open and the feedback DAC is re-used to input the test sequence during phase Φ1 The prototype includes all the DfT modifications required to perform the proposed tests: few logic gates and a configuration register to properly control the switches and the feedback DAC. The test sequence and the master clock are generated externally. Similarly, the output bit-streams of the two stages are shifted off-chip, which means that both the reconstruction and decimation filters have to be emulated in software. This option has been preferred in order to get a major flexibility on the post-processing. Apart from these necessary test-purpose modifications, the prototype also includes a simple mechanism to induce parametric deviations in the behaviour of the integrators. Namely, an external tuning voltage has been considered to control the bias currents of the 3 amplifiers. Though such a mechanism cannot model all the possible parametric defects that may arise in an integrator, a similar effect would be obtained, for instance, from a mismatch in a current mirror. In any case, there is no doubt that varying the bias current modifies the performance parameters of the amplifier. This is illustrated in Fig.3 that displays electrical simulation results of the amplifier DC gain, Slew-rate and Gain-Bandwidth product versus the included tuning voltage [12]. B. Integrator leakage test An integrator pole error causes the leakage in the modulator base-band of a portion of the quantization noise shaped at an 1.8 22.2 2.4 50 60 70 80 90 100 tuning voltage DC gain (in dB) 1.8 22.2 2.4 2 6 10 14 tuning voltage GBW (in Hz) 1.8 22.2 2.4 0 1 2 3 tuning voltage Slew–Rate (in V/s) Nominal tuning voltage Nominal tuning voltage Nominal tuning voltage 10 7 10 7 Fig. 3. Amplifier characteristics versus tuning voltage order lower than the modulator order. As a consequence, the modulator SNR is reduced. This phenomenon is more severe for cascaded modulators than for single-loop modulators, due to improper noise cancellation in the reconstruction filter. We have proposed tests to measure the amplifier DC gain (i.e. the integrator pole error) in 1st and 2nd order modulators [11] and we present here a brief summary. 4 For the 1st integrator of a 2nd order modulator, the proposed test is very simple. It consists in sending a digital sequence (SEQ) of mean value Qdifferent from 0 to the modulator and checking how the mean value of the output bit-stream (Y) deviates from the input sequence mean value. To get rid of an eventual input-referred offset, another acquisition (quoted with a star symbol in (1)) has to be performed with an input sequence of mean value −Q. A zdomain analysis shows that the obtained signature is equal to, s1=1 N"N X i=1 seqi−yi#−1 N"N X i=1 seqi−yi#∗ (1) = 4Q∆p±4 N where ∆pis the integrator pole error and Nthe number of averaged samples. The behaviour of a 1st order modulator is strongly driven by non-linear dynamics. This implies that a z-domain analysis using the approximation of a linearized quantizer cannot be performed. It has been shown in [15] that the 1st order modulator output bit-stream follows exactly the input, when that input is a digital sequence. This behaviour is even strengthened by integrator pole error. Hence, a slightly different test was necessary for 1st order modulators. The proposed test consists in adding an extra delay in the feedback loop of the modulator (in the digital part of the loop), and using as a test stimulus a digital periodic sequence formed by a number M−1of 1s and a single -1. The sequence period Mhas to be strictly higher than 5. For instance, a sequence of period [1 1 1 1 1 −1] could be used. Notice that the extra delay is introduced only during test mode and does not impact the modulator nominal behavior. Under these conditions, it can be shown that the integrator output follows a fixed pattern. An integrator pole error manifests as a slow exponential-like decay of the pattern. It can be shown that such decay causes periodic transitions in the integrator pattern and that such transitions cause a deviation in the mean value of the modulator output. Hence, the test signature is computed in the same way as for the 2nd order modulator, giving in this case, s2=1 N"N X i=1 seqi−yi#−1 N"N X i=1 seqi−yi#∗ (2) =4∆p ln 3M−5 M−5±4 N C. Integrator settling error test For the proper behavior of a Σ∆ modulator, the dynamics of the amplifiers are also of utmost importance. Indeed, improper settling will cause a noise increase in the base-band and also harmonic distortion. In [16], a test has been proposed to measure such settling errors. However, such test required some slow arithmetic operation to build the signature. A modification was later introduced [12] such that the same signature elaboration as for the leakage test can be used. A digital sequence, preferably of mean value 0, is sent to the integrator under test. Moreover, the modulator master clock is modified such that the clock period is doubled when a logic 0 is sent and remains nominal when a logic 1 is sent. In this way, it can be shown that the integrator settling error that occurs for a step corresponding to a logic 1 input sample and a logic 0 feedback sample can be referred as a DC level at the modulator input. To get rid of possible offset contributions, another acquisition has to be performed with the same test sequence but inverting the clock period modification (double for a logic 1 and nominal for a logic 0). As demonstrated in [12] the signature can be written as, s3=P2+P∗ −2×er2±4 N(3) where er2is the settling error under test (normalized to the modulator full-scale) and P2and P∗ −2are the probability of occurrence of having a 1 input sample and a 0 feedback sample (for the 1st acquisition) or a 0 input sample and a 1 feedback sample (for the 2nd acquisition), respectively. Using a random digital sequence as an input allows to estimate a-priori the term P2+P∗ −2as being equal to 1/2. The signature thus simplifies to, s3=1 2×er2± 4 N+ 3er2rN 2!(4) The error term in the expression of the signature is increased with respect to (3) by the 3σcontribution of the approximation of the actual value of the term P2+P∗ −2to 1/2. III. TIME-PRECISION TRADE-OFF For the digital tests summarized above, the signatures represent a measurement of the DC level deviation of the modulator output bit-stream from the expected value. This measurement can be performed by simple counters for the sake of hardware simplicity in a BIST focus. However, a simple counter is a 1st order filter, which is obviously not optimum to remove the shaped quantization noise of a Σ∆ modulator. Actually, according to (1), (2) and (4), the precision on the different signatures is always in the order of ±4/N, where Nis the number of averaged samples. As our purpose is to retrieve the DC component of the output bit-stream, we should ideally select the sharpest filter with the lowest cut-off frequency. One drawback is the increased complexity, which may not be a limiting factor if the filter is implemented in an ATE. But a major concern is test time. Indeed, the filter order (and thus sharpness) and cutoff frequency are closely linked to the filter settling time. As a matter of fact, it is usually considered that an order L+1 is sufficient to properly filter a modulator of order L[13]. The proposed tests apply to 1st and 2nd order sections, so filters of order greater than 2 and 3 respectively would be more suitable to build the signature than simple counters. For the sake of simplicity, we will limit our study to comb filters, which are widely used to remove quantization noise in Σ∆ modulators [17]. The transfer function of a comb filter of order L+ 1 is, 5 H(z) = 1−z−fs 2fc 1−z−1!L+1 (5) where fsis the modulator sampling frequency and fcis the filter cut-off frequency. The oversampling ratio (OSR) is related to the filter cut-off frequency by, OSR =fs 2fc (6) For such a filter, the number of samples required for proper settling is, Nset = (L+ 1) ×fs 2fc (7) For an ideal modulator of order L, under the assumption that Bennetts conditions [18] are fulfilled, the transfer function can be written as, Y=z−LX+1−z−1LE(8) where Yis the output bit-stream, Xthe input signal, and Eis a random variable that represents the linearized quantizer error. Its variance is, σ2 E=∆2 12 (9) where ∆is the quantizer step (∆=2for one-bit quantizer). For an ideal filtering, the quantization noise in the baseband can be calculated as, σ2 noise =π2Lσ2 E (2L+ 1) fs 2fc2L+1 (10) Provided that two acquisitions have to be performed to get rid of the offset, the variance of the test signature should be twice that of a single acquisition. A. The first order Σ∆ case In what has been exposed previously, it has been assumed that the quantization noise is a random variable, shaped to high frequency. While this is a common assumption to describe Σ∆ modulators under normal operation, its validity range may not extend to the proposed tests. Indeed, the stimuli are not lowfrequency continuous waves but digital sequences with short periods. It is demonstrated in [15] that the response of an ideal 1st order modulator to a digital sequence is the same digital sequence: in other words, there is no noise-shaping. Moreover, it has been shown in [11] that, during the leakage test, the output bit-stream follows a fixed pattern of the same mean value as the test sequence but twice the period. Integrator leakage perturbs this pattern and introduces periodic transitions that modify the overall DC level. Fig.4 shows the integrator output for a simulation of a leakage test for a 1st order Σ∆ modulator with a pole error ∆p= 5.10−3. Notice that the modulator output bit-stream is actually the quantized version of the integrator output (i.e. its sign), but the effect of leakage 290 300 310 320 330 340 -2 0 2 4 sample index integrator output 0200 400 600 800 1000 -2 0 2 4 sample index integrator output a) b) 369 samples Fig. 4. Integrator output during a leakage test: a) over 1000 samples, the exponential decay of the envelope can be appreciated; b) the zoom on a transition shows how the repeating pattern is broken when the central level crosses 0 is best appreciated at the integrator output. The exponential decay of the envelope that can be seen in Fig.4-a) is due to leakage. When the central markers cross 0 a sharp transitions occurs. It can be seen in Fig.4-b) how the integrator output pattern is locally modified for a transition. The number of samples between two transitions has been shown to be, Ns= ln 3M−5 M−5 ∆p(11) where Mis the period length of the test sequence and ∆pis the integrator pole error. In our case, for M=8 and ∆p= 5.10−3, we obtain Ns= 369, which is verified by the simulation. The filter has to sense more than one transition to retrieve the information of interest. In order to illustrate this with experimental results, we performed a leakage test for the second stage of the prototype (which is a 1st order modulator), with a test sequence of period [1 1 1 1 1 0] and mean value 2/3(taking into account that the logic 0 is converted to an analog -1, normalized to the Full- Scale). A total number of 40000 samples were acquired for this sequence and its opposite. Then the output bit-streams have been post-processed using Matlab to study the use of several filters. Fig.5 shows the evolution in time of the signatures obtained with a 2nd order filter for 3 different values of the cut-off frequency: fs/288,fs/720 and fs/3240. For the highest cutoff frequency, the filtering is not sufficient to average several transitions. Periodic peaks can be appreciated that correspond to the train of transitions (which is approximately a train of Dirac pulses) convoluted by the filter impulse response. For a cut-off frequency of fs/720, the impulse response of the filter is of a length similar to the transition period and for the smallest cut-off frequency, the filtering is sufficient to 6 2000 2500 3000 3500 4000 4500 5000 0 0.01 0.02 sample index filter output a) b) c) Fig. 5. Filter output for a 1st order modulator leakage test at 3 different cut-off frequencies: a)fc=fs/288; b)fc=fs/720; c) fc=fs/3240. 10-4 10-3 10-2 10-1 -120 -100 -80 -60 -40 -20 0 20 normalized frequency output bitstream PSD fc=fs/720 fc=fs/288fc=fs/3240 Fig. 6. Output bit-stream spectrum of a 1st order modulator during leakage test. The filter cut-off frequency must be sufficient to remove the tonal components. effectively remove the tonal contribution and isolate the DC component (i.e. the pole error information). Fig.6 also illustrates the above effects, showing the normalized bit-stream spectrum together with the 3 filter cut-off frequencies. First of all, it can be verified from it that the base quantization noise is shaped, but is well under the tonal contribution that is due to the leakage-induced periodic transitions. Secondly, it can be verified that for fc=fs/288, some tones fall in the pass-band. The cut-off frequency fc=fs/720 is located close to the fundamental tone of the transitions and for fc=fs/3240, all the tones are filtered out. This is coherent with the time-domain observations commented above. Finally, Fig.7 shows the signature standard deviation versus the filter impulse response length, for both a simple counter (case a) and a second order filter (case b). The 3 cases mentioned above are quoted on the figure with cross markers. It can be seen that for low filtering, the results of the simple counter and the 2nd order filter are similar. Notice that the dashed line corresponds to the expected 4/N scaling for the simple counter. The standard deviation scaling significantly improves for the 2nd order filter if the cut-off frequency of the 102103 10-6 10-5 10-4 10-3 10-2 10-1 filter length signature standard deviation fc=fs/720 fc=fs/288 fc=fs/3240 a) b) Fig. 7. Standard deviation of 1st order modulator leakage test signature versus filter length: a) for a simple counter; b) for a 2nd order filter 10-3 10-2 10-1 -60 -50 -40 -30 -20 -10 0 normalized frequency power density b) a) sigma2=3.5 sigma2=0.33 Fig. 8. Spectrum of the quantizer error Ein a 2nd order modulator: a) for a small DC input; b) for a digital sequence of mean value Q= 2/3 filter is smaller than the transition frequency. As a conclusion of the above study, it can be said that, in order to design an efficient filter for the test signature, the procedure should be the following: i) estimate the minimum pole error that must be detected, ii) use (11) to evaluate the transition periodicity, iii) select a filter OSR higher than the transition period (for instance, the double). B. The second-order Σ∆ case In principle, the higher the modulator order, the more decorrelated is the quantization error from its input, which implies that the validity conditions for the linearization of the quantizer are fulfilled. Hence, it can be expected that the test signature improvement due to better filtering be noticeable for a2nd order modulator. In order to verify this assumption, we performed two high level simulations in Matlab: the first one for a 2nd order modulator with a small DC input and the second one with a digital sequence input. Fig.8 shows the spectrum of the quantizer error in the two cases. The linear model assumes that this error is a white noise of variance expressed as (9). It can be seen that the spectrum 7 102103 10-6 10-5 10-4 10-3 10-2 10-1 filter length signature standard deviation a) b) Fig. 9. Standard deviation of 2nd order modulator leakage test signature versus filter length: a) for a simple counter; b) for a 3rd order filter is truly white in none of the two cases but is reasonably random. What is more important is the value of the variance. For a small DC input, the simulation gives a variance of 0.33, which is very close to the expected value, while for the digital sequence, the quantizer is clearly overloading and the variance increases by an order of magnitude. As a result, this increased error should be taken into account in the linearized model during test and we should write it as, σ2 E≈10∆2 12 (12) Fig.9 shows experimental results obtained for a leakage test of a second order modulator. Two acquisitions were performed over 40000 samples, with an test sequence of period [1 1 1 1 1 0] and mean value Q= 2/3(taking into account that the logic 0 is converted to an analog -1, normalized to the Full-Scale). On these two acquisitions, we varied the filtering options. First, we considered a simple counter (case a) and we varied the number of averaged samples. Next we applied a3rd order filter (case b) and varied the cut-off frequency (i.e. the OSR) and thus the impulse response of the filter. In both cases, the signature standard deviation can be derived once the filter has properly settled. The graph represents the obtained standard deviation versus the filter length (i.e. the settling time). The dashed lines correspond to the expected value. For a simple counter, the agreement is almost perfect. For the 3rd order filter, the trend is the expected. The lowest dashed line corresponds to limit given by the ideal expression with (9), while the upper one corresponds to the increased variance due to quantizer overloading derived by simulation (12). Finally, for filters of high length (i.e. low cut-off frequency), it can be seen in Fig.9 that the rate of the signature standard deviation scaling with filter length is lower than expected. Indeed, at some point that depends on the actual performance of the modulator under test, white thermal noise dominates over quantization noise. In any case, it can be seen how the signature standard deviation for a 3rd order filter is significantly lower than that of the signature with a simple 0 1 2 pole error 1.7 1.8 1.9 22.1 2.2 2.3 2.4 10-6 10-4 10-2 tuning voltage pole error precision a) b) Fig. 10. a) Pole error versus amplifier tuning voltage; b) measurement 3σ dispersion and process corner variability counter of same length. C. Diagnosis capability The proposed tests allow to digitally measure important design variables of all the integrators in a 2nd order and a 1st order modulator, or any cascaded combination of such stages. Moreover, adequate filtering leads to a signature precision that enables the localization of the modulator in the design space, which can be very valuable for diagnosis and silicon-debug, and thus for yield learning. This subsection tries to demonstrate it with our prototype. We vary the tuning voltage of the amplifiers in order to induce parametric deviations and perform the proposed tests on the three integrators. In order to validate the measurements against a reference, we also performed electrical simulations of the integrator to determine the expected leakage and settling error as function of the tuning voltage. Furthermore, we repeat these simulations for the different process corners. Fig.10-a) shows the evolution of the integrator pole error as a function of the tuning voltage. The solid line corresponds to the electrical simulation of the typical mean corner, while the dashed lines represent the maximum and minimum values reached by the different process corners. The round markers stand for the pole error measured for the 1st integrator (in a 2nd order modulator configuration), while the square markers stand for the pole error measured for the 2nd and the 3rd integrators. Indeed, these integrators are identical and are both measured in a 1st order modulator configuration and hence produce the same results. The dashed line on Fig.10 b) represents the process variability (i.e. it corresponds to the difference between the two dashed lines in Fig.10 a). The markers show the measurements 3σprecision. The square markers are obtained for the 2nd and the 3rd integrators with a 2nd order filter of cut-off frequency fs/9000. The round markers are obtained for the 1st integrator 8 -1.5 -1 -0.5 0 0.5 settling error 2.4 2.45 2.5 2.55 100 10-2 10-4 10-1 10-3 tuning voltage settling error dispersion a) b) Fig. 11. a) Settling error versus amplifier tuning voltage; b) measurement 3σdispersion and process corner variability with a 3rd order filter of cut-off frequency fs/2000. It can be seen how in both cases the measurement 3σdispersion is between 1 and 2 orders of magnitude below the process variability, even in the worst case (i.e. for the smallest pole error). Fig.11 shows the same graphs obtained for the settling error. The cut-off frequencies are the same as for the leakage tests. Here again, it can be seen how the settling error tests reach a precision that is close to 2 orders of magnitude below process variability, even for the small settling error obtained for a tuning voltage of 2.4V. Let us study how much test time is necessary to obtain this diagnosis capability. Four acquisitions are necessary for each integrator (two for leakage test and two for settling test). However, we can consider that the test of the 2nd and the 3rd integrators can be performed in parallel because they involve different Σ∆ stages (see Fig.2). Taking into account that the filter settling time is related to the cut-off frequency though (7), the total number of samples required to perform the proposed tests on the 3 integrators is thus, Nsamples = 4 ×3×2000 + 4 ×2×9000 = 96000 (13) Notice that the filtering is performed in real-time and there is thus no more post-processing than the subtraction of the two acquisitions results for each test. The time needed to load the modulator configuration filter can be neglected with respect to the acquisition time. Moreover, as the test stimulus is purely digital, no additional settling time has to be considered. The acquisition time is thus a good approximation of the total test time by, Ttest =Nsamples fs (14) where fsis the modulator sampling frequency. This is quite competitive with respect to functional tests that do not offer the same diagnosis capability. Indeed, for an OSR of 100, a single FFT over 1024 samples would require the acquisition of roughly 102400 samples. This number is comparable to our result but FFT requires important post-processing and nonnegligible setup time. Indeed, as shown in [19], the test time for FFT-based tests is not dominated by acquisition time but by other factors like setup time, data transfer time and FFT- processing time. In this reference, the actual test time is 93ms. Our prototype uses a quite slow sampling frequency of 2MHz. The test time for 96000 samples would be of the order of 50ms, which is still lower than the 93ms of an FFT test. For the same modulator working at 20MHz, the test time would scale down to 5ms. Finally the digital nature of the proposal also enables massive parallel testing, which further reduces the effective test-time. IV. DECIMATION FILTER RE-USE In some cases, Σ∆ modulators are sold as stand-alone parts and the output bit-stream is directly accessible for test purpose. An optimum filter can thus be designed for each test, as explained in previous section. In some others, the Σ∆ modulator is integrated together with a decimation filter, and the output bit-stream is not directly accessible. This is not necessarily impairment, as this decimation filter can be used to build the test signatures if two conditions are met: i) The settling error test requires that the modulator master clock be modified as function of the test sequence. This modified master clock must be used to drive the decimation filter. ii) For cascaded modulator, the reconstruction filter must be configurable such that it can by-pass the output of the different stages directly to the decimation filter. In what follows, we will study the possibility to build the test signatures with only one valid sample of the decimation filter for each acquisition. In such case, the test time would be determined by the settling time of the decimation filter, and in any case would be order(s) of magnitude below functional (FFT-based) test time. In order to determine whether the decimation filter provides sufficient filtering, we will consider a functional criterion: the tests must be able to unambiguously detect the given parameter (pole error or settling error) even if the deviation does not imply performance degradation. In other words, the sensitivity of the proposed test to the targeted defect must be greater than that of a functional test. It is well known that the performance of a Σ∆ modulator is much more sensitive to the performance of the 1st integrator than to the integrators located further in the loop. The worst case for our study is thus to consider deviations in the 1st integrator. A. Leakage test versus functional test Let us consider the case of a simple 2nd order modulator. The leakage test signature for a second order modulator is given by (1). In order to be detectable at the output of 9 the decimation filter, the variation of the DC component (i.e. 4Q∆p1) must be greater than the signature precision. Moreover, the variance of the signature is twice the variance for a single acquisition, which is given by (10). The minimum detectable pole error can thus be determined as, ∆pmin =3p2σ2 noise 4Q(15) Introducing (10) and (12) (with ∆=2) in (15), and taking into account that the decimation filter cut-off frequency is related to the OSR through (6), it comes, ∆pmin =3 2Qrπ4 3OSR5(16) Furthermore, the amount of quantization noise that leaks into the baseband for a given pole error ∆pcan be calculated as, Pnoise(dB) = 10log 1+∆p2×OSR2 π2×10 3(17) Substituting ∆pby ∆pmin in (17), the minimum detectable leakage corresponds to a noise degradation of, Pmin(dB) = 10log 1 + 5 2×π2 Q2OSR3(18) At the pole error detection limit, the noise degradation is higher for lower values of the OSR. However, even for a low OSR for instance 16, the decimation filter should be sufficient to detect a leakage that would cause a 0.06dB SNR loss with an input sequence of mean value Q= 2/3. This means that for a stand-alone second-order modulator, the decimation filter is sufficient to build an adequate signature with only one valid sample for each acquisition. The leakage test time reduces to twice the settling time of the decimation filter. For a cascaded modulator of order L, with a 2nd order modulator as first stage, the quantization noise leaking into the baseband due to a pole error in the first integrator can be calculated as, Pnoise(dB) = · · · (19) 10log ∆1 ∆n1 + 2∆p2 π2L−2×OSR2L−2 d2×2L+ 1 3 where ∆1and ∆nare the quantizer step of the first and last stage, respectively; and dis a factor greater than unity that depends on the branch coefficients of particular cascaded architecture [20]. Substituting ∆pby ∆pmin in (19), the SNR loss associated to the minimum detectable pole error is, Pmin(dB) = · · · (20) 10log ∆1 ∆n1 + 2L+ 1 20d2Q2×OSR2L−7×π6−2L Here, things are different than for a 2nd order modulator alone. Indeed (20) shows that the SNR loss associated to the minimum detectable pole error will increase with the OSR if the order of the cascaded modulator is higher than 3. For 1.7 1.8 1.9 22.1 2.2 2.3 2.4 2.5 -0.5 0 0.5 1 1.5 2 2.5 x 10-3 tuning voltage measured pole error Fig. 12. Measured pole error versus amplifier tuning voltage, with the confidence interval corresponding to the 3σdispersion of the signature taking a single sample of the decimation filter. instance, taking d= 2,Q= 0.5and ∆1= ∆n= 2, it comes that the SNR loss associated to the minimum pole error detectable with the decimation filter at OSR = 64 would be 0.02dB for a 3rd order modulator, 6dB for a 4th order and 32dB for a 5th order. Hence, it can be concluded that the detection of pole errors that have a significant impact on performance in cascaded modulator of order higher than 4 would require more filtering than the one provided by the decimation filter. These results can be verified, at least partially, with our prototype. For that purpose we considered a 4th order decimation filter, with an OSR of 50. The first valid sample is thus obtained after 200 modulator samples according to (7), which in our case corresponds to 0.1ms. Then, we have varied the tuning voltage of the amplifiers to induce parametric deviations. For each tuning voltage, we performed a leakage test with an input sequence of mean value 2/3, and also a functional test. This functional test consists in sending a lowfrequency sine-wave (1.6kHz) with an amplitude of 70% of the modulator Full-Scale and performing an FFT on the output of the decimation filter. Actually, the reconstruction and filtering is emulated in software, so we can perform the functional test on the complete 3rd order modulator but also on the 1st stage only, which is a 2nd order modulator. Fig.12 shows the pole error, evaluated with only one valid sample, for the different tuning voltages. The experimental 3σ confidence interval of the measurement is also displayed and is around 6×10−4. It can be seen that for tuning voltages below 2.1V, the pole error is detected (because 0 is not contained in the confidence interval). Fig.13 shows the modulator SNR as a function of the 1st integrator pole error for a 2nd order modulator (case a) and for a 3rd order modulator (case b). The markers correspond to experimental result, that is to say the measured SNR versus the measured pole error. The curves correspond to high level Matlab simulations. The dashed line corresponds to a simulation without thermal noise, while the solid lines correspond to simulations with an additive Gaussian noise source of variance 8.3×10−6at the modulator input, that we