Low Computational Burden Model Predictive Control for Single-Phase Cascaded H-Bridge Converters Without Weighting Factor

Depósito de investigación de la Universidad de Sevilla https://idus.us.es/ This is an Accepted Manuscript of an article published IEEE Transactions on Industrial Electronics available at: 10.1109/TIE.2022.3167133 “© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other Works” IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Low Computational Burden Model Predictive Control for Single-Phase Cascaded H-Bridge Converters Without Weighting Factor Tingting He, Member, IEEE, Mingli Wu, Ricardo P. Aguilera, Member, IEEE, Dylan Dah-Chuan Lu, Senior Member, IEEE, Qiujiang Liu∗, Sergio Vazquez, Fellow, IEEE Abstract—In this paper, a low computational burden model predictive control (MPC) strategy without weighting factor is proposed for the single-phase cascaded H-bridge CHB converters. To reduce the switching state candidates, a hierarchy control algorithm is proposed. The grid current is controlled by selecting a sub-region from the designed two-dimensional control plane, instead of the entire area. Two vectors are chosen in one sampling period for more accurate tracking. Then, the voltage balancing is achieved by selecting the optimal switching state from the sub-region candidates to form the above two vectors. The cost function can be constructed of one variable: load voltage. Therefore, the weighting factor can be eliminated. No tuning or retuning processes are required in the proposed method. To reduce the computational time further, the principle of eliminating the switching state candidates operating the same voltage balancing performance is proposed. Conventional and proposed MPC methods are verified by experimental tests via a laboratory setup of a three-cell connected CHB converter. Steady-state and transient operations demonstrate that the proposed method guarantees less distortion grid current and shorter execution time (reduced from 15 µs to 3 µs). Fast response speed to variations in voltage reference and load resistance can be achieved. Index Terms—Cascaded H-bridge, model predictive control, low complexity, weighting factor, tuning process I. INTRODUCTION MULTI-LEVEL converter is widely used in high power applications due to its high power level and high voltage level [1]. Cascaded-H bridge (CHB) converter, one of the main topologies of the multi-level converter, is well-known for its prominent characteristics. These advantages include the low harmonic distortion of the ac output voltage, low electromagnetic emissions, and high efficiency [2]- [4]. One This work was supported by the Fundamental Research Funds for the Central Universities (2021RC257), the National Key Research and Development Program of China (2021YFB2300200), and the Australian Government through the Australian Research Council (Discovery Project No. DP210101382). (*Corresponding author: Qiujiang Liu.) T. He, M. Wu and Q. Liu are with School of Electrical Engineering, Beijing Jiaotong University, Beijing, 100044, P.R.China (e-mail: [email protected], [email protected], [email protected]). R. P. Aguilera and D. D. Lu are with the School of Electrical and Data Engineering, University of Technology Sydney, Broadway, NSW 2007, Australia. (email: [email protected], [email protected]). S. Vazquez is with the Laboratory of Engineering for Energy and Envorinmental Sustainability, Universidad de Sevilla, Sevilla, C.P. 41092 Spain (e-mail: [email protected]). distinctive feature of CHB converter is that several cells are connected with isolated dc-link voltages [5]. These isolated cells can be controlled with balanced voltage demands or specific power references. This makes it suitable for medium- and high-voltage applications, such as traction application, photovoltaic inverter [6], and static synchronous compensators [7]. The main control targets of CHB converters are the grid current and dc-link voltages. Many control strategies have been applied in CHB converters, e.g., PI, hysteresis, deadbeat and selective harmonic elimination controller, predictive control, etc. [8]. These control strategies can be based either on modulation with or without carriers, which are also called high or fundamental switching frequency methods, respectively. For the high frequency approaches, i.e., phase-shift pulse width modulation (PWM) and level-shift PWM, the switching loss is high [9]. Besides, the number of the carriers is increasing when more cells are connected in CHB. This will lead to the carrier synchronization problem in digital communication. Those fundamental or low switching frequency methods, such as the staircase modulation, selective harmonic elimination and space vector modulation, can achieve a low switching loss [10]. However, the lower frequency harmonics are introduced and hard to be filtered. Therefore, these control methods are not suitable for CHB. Thanks to the rapid development of fast microprocessors, model predictive control (MPC) is emerged as an alternative control strategy for power converters [11]. MPC has a series of advantages: simple, easy to implement and include constraints, online optimization with multi-variable and multi-objective control, and so on [12]- [13]. The discrete-time model is used to predict the future values for the next sampling time. A cost function is constructed of different forms of multi-variable errors between the predicted and expected values [14]. An optimal switching state is selected to minimize the cost function. Good robustness to changes in internal parameter values can be accomplished easily in MPC [15]. An enumerationbased MPC is proposed for CHB converter in [16]. However, since all the possible switching combinations are considered, the computational time is high and will increase in an exponential rate when more cells are connected. To reduce the computational burden, several methods are studied to limit the candidate in one sampling period. In [17], a cell-by-cell MPC which divides the sampling period into Ntime intervals for This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3167133 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS each cell is proposed. In [18], the redundant voltage vector elimination principle is applied in a multilevel asymmetric H- bridge inverter. However, the calculation time is still high for the above schemes, especially when a large number of cells are added, and the switching frequency is variable. Therefore, the high computational time is still one of the problems for MPC application in CHB. Generally, when it comes to multi-objectives, the weighting factor tuning process is another issue [19]- [20]. In terms of CHB converters, a weighting factor is used to establish a tradeoff between the grid current and dc-link voltages [21]. A nontrivial value for this weighting factor is designed to achieve balanced control of these multi-objective performances. A guide for weighting factor design and tuning procedure is introduced for different control targets [22]. It can be seen that as a critical and sensitive coefficient in MPC, its design or tuning procedure is a tedious and time-consuming task in most cases. Several methods have been proposed to overcome the drawbacks caused by the weighting factor. One common solution is to design the weighting factor as the radio between two control variables for equal importance control [16]. However, in practical application, the system performances are limited by the designed value. Other methods can be divided into two groups according to the inherent relationship between the control variables. For the relevant variables, a vector synthesis or new designed variable can be used as a replacement of the original variables [23]- [25]. For example, a voltage vector error is used to replace the speed and currents in [23], or to represent the torque and stator flux in [24]. Similarly, an equivalent reference vector of stator flux is proposed to replace the stator flux and electromagnetic torque in [25]. However, there is no inherent equation to express the relationship between the AC current and DC voltage in CHB. Thus, CHB is not suitable the above “replace” algorithm. For irrelevant variables, the cascaded control strategy to separate the control variables is proposed [26]- [29]. To balance the neutral point voltage, offline tables are designed in the second step to regroup the voltage vector candidates. However, these redesigned tables will increase the algorithm complexity and the table size. Besides, the execution time is not considered in the aforementioned methods. Therefore, how to reduce the CHB calculation time with a one-variable cost function becomes an essential issue for MPC in CHB multiobjective application (e.g., reduced execution time, eliminated weighting factor, and improved current performance). In this paper, to reduce the execution time and eliminate weighting factor simultaneously, a two-dimensional control region is defined based on the switching function frame (Sa, Sb). According to the ac input voltage level of the converter, the entire operating area is divided into 2N+ 2 sub-zones. The current control is achieved by selecting the sub-control region in the first step. By this, the switching state candidates can be reduced, and the current tracking can be controlled separately. A cost function constructing with only one variable, i.e., load voltage error, is then defined. An optimal switching pair consisting of two voltage vectors is selected to minimize the cost function. To reduce the computational burden further, the principle of redundant switching pair elimination is proposed. Fig. 1. Topology of the single-phase CHB converter. Therefore, the number of switching state candidates is reduced dramatically, compared to search one over the entire control plane. The weighting factor can be removed in this hierarchy control algorithm. Furthermore, the experimental results show that, compared to conventional MPC, the calculation time of the proposed method can be reduced to 20% of the conventional one. Much better current performance can be observed in the proposed scheme. No tuning or retuning procedure of the weighting factor is required. II. MPC FOR CHB CONVERTER A. Model of CHB Fig. 1 shows a detailed circuit topology of the single-phase CHB converter. The CHB converter consists of Nserialconnected H-bridge cells. The upper switching states of the two legs on nth H-bridge, denoted as San and Sbn (n= 1, 2, · · · ,N), are defined as San, Sbn ∈ {0,1}.(1) Since the switches on each leg operate complementary, the lower switching states on leg aand bare written as San and Sbn, respectively. By using the Kirchoff’s voltage law and the forward Euler, the discrete-time dynamic model for the grid current can be described as is(k+ 1) = Ts Ls (vs(k)−Rsis(k)−vin(k)) + is(k),(2) where Tsis the sampling time, vs(k)the source voltage, is(k)the source current, and vin(k)the input voltage of the converter. The DC output voltage of nth cell can be predicted as vd,n(k+ 1) = Ts Cn (id,n(k)−iRn(k)) + vd,n(k),(3) This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3167133 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS where id,n is the DC output current through the capacitor and resistance, iRnthe load current, and vd,n the load voltage. Based on (2) and (3), the dynamic system model of the CHB converter can be written as x(k+ 1) = Ax(k) + BS(k) + Cw(k),(4) where x(k)=[is(k)vd,n(k)]T, S(k)=[S1(k),· · · , Sn(k),· · · , SN(k)]T, Sn(k) = San(k)−Sbn(k), w(k)=[vs(k)iRn(k)]T, A=       1−TsRs Ls0 0 · · · 0 0 1 0 · · · 0 0 0 1 · · · 0 . . .. . .. . ..... . . 0 0 0 ··· 1        , B=Ts          −vd,1(k) Ls−vd,2(k) Ls· · · −vd,N (k) Ls is(k) C10· · · 0 0is(k) C2· · · 0 . . .. . ..... . . 0 0 ··· is(k) CN          , C=         Ts Ls0 0 · · · 0 0−Ts C10· · · 0 0 0 −Ts C2· · · 0 . . .. . .. . ..... . . 0 0 0 · · · − Ts CN         . B. Cost function design A cost function is designed in the standard MPC to select an optimal switching state from all the possible candidates to minimize the control variable errors. Therefore, the cost function, denoted as J, is constructed to track the grid current and load voltages, written as J(k) =(is(k+ 1) −i∗ s(k+ 1))2 +λ N X n=1 ((vd,n(k+ 1) −v∗ d,n(k+ 1))2.(5) The predicted values of current isand DC output voltage vd,n are compared with their reference values, i∗ sand v∗ d,n, respectively. The quadratic error form is used to guarantee the system stability range [19]. Due to the multi-objective optimization problem, a weighting factor λis usually applied to balance the current and voltages performance. Since balanced voltages are expected in the dc-side for CHB converters, the load voltages are equally important. In the standard MPC for CHB converter, a voltage vector is selected as the optimal one in a sampling period to achieve minimum error tracking. To obtain the good system performance, the weighting factor should be designed carefully [22]. Unfortunately, the tuning of weighting factor is a complex task. When unexpected disturbance or new system parameters are applied, a re-tuning action is required in some cases, which is also time-consuming. To avoid the weighting factor tuning process, a cost function (5) for equally important terms [16] is developed as J(k) =(is(k+ 1) −i∗ s(k+ 1))2 i2 s,rated + N X n=1 ((vd,n(k+ 1) −v∗ d,n(k+ 1))2 v2 d,rated , (6) where is,rated and vd,rated are the rated values of the grid current and DC voltage, respectively. It can be seen that the system performance depends on the rated values strongly and becomes worse if improper rated values are selected. For simplicity, the standard MPC algorithms using (5) and (6) as the cost function are denoted as “MPC I” and “MPC II”, respectively. III. PROPOSED LOW COMPUTATIONAL BURDEN MPC FOR CHB A hierarchy MPC strategy to reduce the calculation time is proposed in this section. Meanwhile, the current and load voltages are controlled separately to eliminate the weighting factor. According to the current expression in (2), its predicted value is(k+ 1) only depends on the input voltage of the converter vin. Therefore, a control region map is designed to locate these input voltage candidates. The optimal subregion is selected, where the expected converter input voltage is located. For the constant switching frequency and accurate control performance, two voltage vectors in the sub-region are used to generate the predicted converter input voltage. By now, the grid current control can be accomplished in the first place. Then, a cost function constructed by the dc-link voltage errors is applied to choose the optimal switching state. With the designed two-step control strategy, the weighting factor is no longer required. The detailed algorithm process is expressed in the following text. A. Two-dimensional control region design The input voltage of the converter can be expressed in terms of the switching states, given by vin = N X n=1 Snvd,n =S1vd,1+· · · +Snvd,n +· · · +SNvd,N = (Sa1−Sb1)vd,1+· · · + (San −Sbn)vd,n +· · · + (SaN −SbN )vd,N = (Sa−Sb)vd, (7) where the load voltage vdis the same for all cells to achieve balanced power flow for each cell, i.e., vd=vd,n (n= 1,2,· · · , N). The switching functions Saand Sbsatisfy (Sa=Sa1+· · · +San +· · · +SaN Sb=Sb1+· · · +Sbn +· · · +SbN .(8) This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3167133 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Fig. 2. Voltage vectors represented by (Sa, Sb). TABLE I ALL POSSIBLE SWITCHING STATES FOR (1,2) (Sa, Sb)Sa1Sb1Sa2Sb2Sa3Sb3 (1, 2) 1 1 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 0 0 1 1 1 A new frame of the control region is constructed by the switching functions Saand Sbrepresenting x- and y-axis, respectively. Taking a three-cell H-bridge converter as an example, the control region can be presented in the new designed coordinator, as shown in Fig. 2, with 16 switching pairs (Sa, Sb). When it comes to Ncells connected in series, the switching pair number (SPN) is (N+ 1)2. For each H- bridge, there are four switching states, i.e., (1, 0), (0, 1), (1, 1) and (0, 0), leading to 4Nfor the switching state number (SSN) in a N-cell CHB converter. For the three-cell CHB converter, the number of switching states for each switching pair (Sa, Sb) is summarized (see Fig. 2), as shown in the box next to the corresponding switching pair. Overall, there are 64 switching states in the entire control area. Table I shows the switching states when (Sa, Sb) is equal to (1, 2). In the standard MPC, an enumeration-based strategy is applied to select an optimal switching state from all the candidates (64 for 3 cells) minimizing the cost function. However, the computation time is rising in an exponential rate when the cell number is increasing. Taking into account (2), some switching pairs result in same value of vin, leading to equivalent control signals. Connecting these equivalent switching pairs (as the green dash line in Fig. 3), the control region in the SaSbcoordinator can be divided into 2N+2 subcontrol regions (8 for 3 cells: zone I ∼VIII). These dotted Fig. 3. Sub-control zone. lines represent different voltage levels of vin (-3vd, -2vd,· · · , 3vd). To reduce the complexity of the algorithm, one subcontrol region is applied in one sampling time to select the voltage vector candidate. This makes it possible to get the independent control of current and dc-link voltages. B. Grid current tracking To avoid weighting factor tuning process, the grid current and load voltages are controlled separately in the proposed MPC. Since the grid current is only determined by the converter input voltage vin, its reference v∗ in is used to choose the optimal sub-control region in the first stage, given by v∗ in =vs−Rsis−Ls Ts (i∗ s−is),(9) where v∗ in and i∗ sare the references of the converter input voltage and grid current. The selected optimal control zone is denoted as Zopt, where the selected zone number zcan be calculated by z=floor(v∗ in/vdc) + N+ 2,(10) where Nis the total cell number. To improve the system performance, a two-vector based MPC is proposed. In one sampling period, two adjacent voltage vectors are used to achieve the expected values, denoted as v1and v2. Deducing from (2), the grid current changing rate of each voltage level is given by fis,ρ =1 Ls (vs−Rsis−vin,ρ),(11) where ρ∈ {1, 2}. Then, the predicted grid current can be calculated via is(k+ 1) = is(k) + fis,1t1+fis,2t2,(12) where t1and t2are application times for voltage level v1and v2, respectively. This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3167133 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS A cost function to minimize the grid current error is constructed, written as Ji(k) =(i∗ s(k+ 1) −is(k+ 1))2.(13) To obtain the optimal operation times t1and t2, one can be achieved by solving the partial derivative of the cost function [20], i.e., ∂Ji ∂t1Zopt = 0.(14) Substituting (12) and (13) into (14), it yields ∂Ji ∂t1 = 2(i∗ s(k+ 1) −is(k+ 1))(−dis(k+ 1) dt1 ) =−2fis,1(i∗ s(k+ 1) −is(k+ 1)) = 0. (15) It can be analysed that the system has a unique solution only when i∗ s(k+ 1) −is(k+ 1) = 0. Considering (12) and the actual-system constraints, we can get (i∗ s(k+ 1) −is(k)−fis,1t1,opt −fis,2t2,opt = 0 t1,opt +t2,opt =Ts .(16) Then, the optimal application times are presented by    t1,opt =i∗ s(k+ 1) −is(k)−fis,2Ts fis,1−fis,2 t2,opt =Ts−t1,opt .(17) For instance, if voltage v∗ in lies in zone III, i.e., z= 3, the voltage vectors v1= -2vdand v2= -vdare selected, with the corresponding application time t1,opt and t2,opt, respectively. If zone I or VIII is selected, then v1=v2= -3vdor 3vdwith t1,opt =Tsand t2,opt = 0, respectively. C. Load voltages balancing Once the optimal control zone is selected, the grid current can be tracked effectively. In the next stage, the load voltages are required to be balanced by designing the cost function, as follows Jv(k) = N X n=1 ((v∗ d,n(k+ 1) −vd,n(k+ 1))2.(18) The cost function is used to select the optimal switching states to obtain v1and v2. Continuous with the previous example, when v∗ in lies in zone III, v1is chosen from the switching states which enables v∗ in = -2vd. This means the switching state satisfying the switching pair {2 ,3 } minimizes the cost function (18) is chosen. Then, v2is selected from switching states under the switching pair {4 ,5 ,6 }, as shown in Fig. 3. The total numbers of switching candidates for -2vdand - vdare 6 = 3+3 and 15 = 3+9+3 (see Fig. 2), respectively. Therefore, the effective SPN and SSN during this sampling period are 5 and 21, respectively. To reduce the calculation time further, a principle of eliminating the redundant switching state candidates is proposed. According to (3), the predicted voltage can be rewritten as vd,n(k+ 1) = vd,n(k) + Ts Cn (Sn(k)is(k)−vd,n(k) Rn ).(19) Fig. 4. Sub-control region for proposed MPC IV. TABLE II SPN AND SSN IN SUB-CONTROL REGIONS FOR ALL METHODS Methods I II III IV V VI VII VIII SPN MPC I 16 MPC II 16 MPC III 1 3 5 7 7 5 3 1 MPC IV 1 2 2 2 2 2 2 1 SSN MPC I 64 MPC II 64 MPC III 1 7 21 35 35 21 7 1 MPC IV 1 4 12 18 18 12 4 1 Since the model predictive control has a strong robustness of system parameters, such as Lsand Cn, as analysed in [30], the predicted voltage in (19) is only determined by the switching function Sn=San −Sbn. Therefore, the redundant switching pairs (San, Sbn) leading to a same value of Snare eliminated. For example, the switching pairs (0, 1), (1, 2) and (2, 3), marked as 4 ,5 , and 6 , respectively, all generate one value of Sn= 1. To reduce the redundant candidates, the switching pairs (0, 1) and (2, 3) are removed. Following this principle, the retained switching pairs are shown in Fig. 4, the red circled ones. Only one switching pair is remained for each level of the input voltage vin. SPN can be reduced from 16 to 7. For simplicity, the proposed method using 16 and 7 switching pairs are denoted as “MPC III” and “MPC IV”, respectively. Compared with the proposed MPC III, when v∗ in lies in zone III, the switching states are only selected from switching pair 3 and 5 to generate v1and v2, respectively. The switching state number can be reduced from 21 to 12, as well as the calculation time. Finally, SPN and SSN during one sampling time for all methods are listed in Table II. Compared with 64 in the standard MPC I&II, SSN can be reduced dramatically in the proposed two strategies. The effective SPN for the proposed MPC IV is only 1 or 2. SSN obtained from proposed MPC IV is around half of that from the proposed MPC III, which can This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3167133 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Fig. 5. Effective switching pair numbers with N-cell connected. Fig. 6. Flowchart for the proposed methods. reduce the calculation time further. Fig. 5 shows the maximum effective SPN for all methods when Ncells are connected, which are (N+ 1)2for MPC I&II, 2N+ 1 for MPC III, 2for MPC IV, respectively. The superiority of the proposed method MPC IV is more obvious especially when the cell number increases. Noted that, the proposed hierarchy control algorithms consider the current tracking as a priority when selecting the sub-control region. D. Controller design procedure The flowchart of the proposed methods is shown in Fig. 6, where aand brepresent the starting and ending positions of the switching states for v1in the optimal sub-control zone, while cand dfor v2, given by          a=pv1(z) b=pv1(z+ 1) −1 c=pv2(z) d=pv2(z+ 1) −1 ,(20) where pv1and pv2are the switching state position matrices. zis obtained from (10). Taking the three-cell CHB as an example, pv1and pv2for the proposed methods are presented as MPC III (pv1= [1; 1; 2; 8; 23; 43; 58; 64] pv2= [1; 2; 8; 23; 43; 58; 64; 64] , MPC IV (pv1= [1; 1; 2; 5; 14; 23; 32; 35] pv2= [1; 2; 5; 14; 23; 32; 35; 35] . Therefore, the variables a,b,cand dare different in the proposed MPC III and IV methods. The design procedure of the proposed method can be summarized as the following steps: 1) Set parameter matrices A(N+1)×(N+1),B(N+1)×N, C(N+1)×(N+1),w(N+1)×1, and x(N+1)×1from (4). 2) Define matrix S4N×2Nfor all the possible switching states, where S(k, :) = [Sa1, Sb1,· · · , SaN , SbN ],k∈ {1,· · · ,4N}. 3) Define the matrix V(2N+2)×2presenting the two voltage levels in the corresponding sub-control region. 4) Calculate the converter voltage reference v∗ in using (9). 5) Calculate the zone location zfrom (10). 6) Obtain the optimal application times t1,opt and t2,opt for two vectors v1and v2. 7) Determine the effective switching pairs, as well as the effective switching states. Introduce variables to label the location ranges of the possible switching states for v1and v2from S, respectively. 8) Set initial values for Jv,opt. 9) Select the optimal switching states for v1and v2using cost function Jvin (18), respectively. Then, the operating times for switches on the upper leg for nth cell (San and Sbn) can be calculated as (tSan =S(iv1,opt,2n−1) ∗t1,opt +S(iv2,opt,2n−1) ∗t2,opt tSbn =S(iv1,opt,2n)∗t1,opt +S(iv2,opt,2n)∗t2,opt . (21) IV. SIMULATION AND EXPERIMENTAL RESULTS Experimental tests have been carried out to verify the effectiveness of the proposed methods with the sampling frequency at 10 kHz. Fig. 7 shows the laboratory prototype of a single-phase three-cell CHB multilevel converter. The parameters of the experimental setup are shown in Table III. The control strategies (conventional MPC I&II, proposed MPC III&IV methods) are implemented in a dSPACE board DS1007 with a FPGA board for driving signals. A controllable voltage source (RAGATRON TopCon TC.ACS) connected on the grid side is used to generate the ac voltage (RMS) vs= 110 V. The peak current |is|is generated from the sum of the dc-link This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3167133 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Fig. 7. Experimental setup. TABLE III SYSTEM PARAMETERS Variable Description Value vsGrid voltage (RMS) 110 V LsFilter inductor 8 mH C1, C2, C3DC capacitor 4.7 mF R1, R2, R3Load resistance 20 Ω v∗ dLoad voltage reference 50 ∼60 V fsSampling frequency 10 kHz kp/kiPI coefficients 0.3/10 voltage errors via a PI controller. Then, a phase-locked-loop (PLL) is applied to track the grid voltage phase. The output of this PLL block multiplies |is|to provide the grid current reference. A. Weighting factor effects A tuning and re-tuning processes are required in the standard method MPC I in some conditions. A proper value of the weighting factor λis needed to achieve current and voltage tracking targets simultaneously, as shown in the simulation result (Fig. 8). The load voltage performance depends strongly on the weighting factor. Experimental tests on the transient response of MPC I & III are investigated. As shown in Fig. 9(a), a weighting factor λ = 0.03 is selected to track the voltage reference 60 V for the standard MPC I method. When a voltage drop is applied (v∗ d from 60 to 50 V), it can be seen that the dc-link voltages can not be controlled within the new reference. The gap between the voltage reference and its measured values becomes worse when a smaller λis applied (similar result can be observed in Fig. 8). At t= 3 s, the standard MPC I is turned off and the proposed MPC III method is turned on. Fig. 9(a) indicates that the divergence of three DC capacitor voltages is missing immediately. The dc-link voltages can track effectively at 50 or 60 V as expected. Similar results can be found when a voltage increase is applied, as shown in Fig. 9(b). If λ= 4 is selected for the initial working condition v∗ d= 50 V, the DC voltages keep vibrating at the new reference value 60 V for the standard method. When the controller changes to the proposed Fig. 8. Weighting factor effect in MPC I. Fig. 9. Comparison results for two methods when voltage changes between 50 and 60 V: (a) λ= 0.03, (b) λ= 4, for MPC I. strategy, a balanced control is turned on. The results from two methods indicate that a tuning process is required to meet the initial requirements in the standard method. When a voltage change is applied, a re-tuning procedure is unavoidable if the weighting factor value is not suitable for the new working condition. In the proposed method, both tuning and re-tuning tasks can be abandoned. B. Steady-state performance The results obtained from the conventional MPC I, MPC II and proposed MPC III, MPC IV schemes are included in Fig. This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3167133 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS Fig. 10. Steady state performance: vs: 100 V/div, is: 5 A/div, vin: 100 V/div, vd: 20 V/div, t: 10 ms/div. (a) MPC I, (b) MPC II, (c) MPC III, (d) MPC IV. Fig. 11. Dynamic performance for voltage variation operation: 20 V/div, 5 A/div, 100 ms/div. (a) MPC I, (b) MPC II, (c) MPC III, (d) MPC IV. 10. Grid voltage, current, input voltage of the converter and dclink voltages are compared in this figure. A tradeoff between the grid current and dc-link voltages is taken in the standard MPC I scheme by selecting the weighting factor λequal to 0.3. In the steady-state test, the cell voltage target v∗ don the dc-side is set to be 60 V. In this case, all four methods can track their references effectively, as depicted in Fig. 10. The grid current is controlled in phase with its voltage. The grid current total harmonic distortion (THD) is 3.6%, 3.7%, 2.8% and 2.7% for MPC I, MPC II, MPC III, MPC IV, respectively. The converter input voltage vin presents a 7-level waveform as expected. All the cell-voltages can reach a balanced condition at 60 V. C. Voltage step change A step-up change in the value of the cell-voltage reference v∗ dfrom 50 to 60 V is applied at t=t1time instant, as presented in Fig. 11. The above four methods are able to track the new working target quickly and effectively. A settling time of around 40 ms is observed for all the methods. The grid current is increased due to the rise in the power This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3167133 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.