Chaos in a Switched-Capacitor Circuit

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-32, NO. 10, OCTOBER 1985 1083 where P=blockdiagonal(Z,,Z,;~~,~~,,Pi,Zi+,,~~~,ZP) (1.4 where Zk is k X k identity matrix, and k is the dimension of component 2,. Using the component connection approach, a model for the interconnected system Z is described with i=(F+GLH)z+GMu Wa) y=Hz W) where F=blockdiagonal(A,,A,;..,A,_,,~,A,+,,...,A,) (I3c) G=blockdiagonal(B,,B,,...,Bi_,,Gi,Bi+,,...,B,) (134 H=blockdiagonal(C,,C,;..,C,-,,H,,C,+,,...,C,). Equations (3c), (lOc), (12), and (13~) imply FP= PA. Equations (3d), (3e), (lOd), (lOe), (12), and (13d) imply ( GLH) P = PBLC. Therefore, (14a) and (14b) imply (F+GLH)P= P(A+BLC). Similarly G=PB HP=C. (13e) (144 WI (154 (15b) (154 b) Necessity: The condition stated in the theorem results from the definition of the component connection model. In this framework the state vector of the composite system is obtained by stacking the state vectors of the individual components. Remark: If (lb) is modified to y, = C,x, + D,v; then, (8b) needs to be modified to y = Hz + Ju and conditions (9) will include J= D. (94 Consequently, the theorem still holds and the composite system model is described by [6] i=(A+BQLC)x+BQMu y=(Z+DQL)Cx+DQMu where Q=(Z-LD)-‘. The aggregate model for the composite system is described by i=(F+GQLH)z+GQMu y=(Z+DQL)Hz+DQMu where the aggregate model state variables z are as defined above. V. CONCLUSION Whenever dealing with interconnected large-scale systems the size of the system becomes an issue. Model reduction techniques are used to alleviate these difficulties. Most of the techniques are applied to the linearized model of the composite system model. ’ In this paper, it is shown that in the component connection model framework the composite system is aggregable if and only if at least one of its components is aggregable. Because of the relatively small size of the individual components, it is easier to aggregate the component model rather than the composite system model. The important consequence of this result is that when dealing with interconnected large scale systems in the component connection model framework one does not need to aggregate the large-scale composite system but rather can consider the aggregation of each, relatively smaller scale component, independently. 111 I21 [31 [41 PI I61 PI REFERENCES H. H. Happ, Diakoptics und Networks. New York: Academic, 1971. E. J. Davison, “Decentralized stabilization and regulation in large multivariable systems,” in Directions in Large SC& Systems, H. and Mitter, Eds., pp. 303-323, 1975. A. Feliachi and A. P. Meliopoulos, “Modeling and Sim&ation of Large Scale Interconnected Systems,” Advances in Modeling and Simulution, AMSE Press, France, vol. 1, no. 1, pp. 33-49, 1984. N. R. Sandell, P. Varaiya, M. Athens, and M. G. Safonov, “Survey of decentralized control methods for large scale systems,” IEEE Trans. Automar. Contr., vol. AC-23, pp. 108-125, Apr. 1978. 0. Wasynczuk and R. A. DeCarlo, “The component connection model and structure preserving model order reduction,” Automutica, vol. 17, no. 4, pp. 619-626,198l. R. A. DeCarlo and R. Saeks, Interconnected Dynomiccrl System. New York: Marcel Dekker, 1981. M. A&i, “Control of large scale dynamic systems by aggregation,” IEEE Truns. Automat. Contr., vol. AC-13, pp. 246-253, 1968. Chaos in a Switched-Capacitor Circuit ANGEL B. RODRIGUEZ-VAZQUEZ, JOSE L. HUERTAS, AND LEON 0. CHUA Abstract -We report chaotic phenomena observed from a simple nonlinear switched-capacitor circuit. The experimentally measured bifurcation tree diagram reveals a period-doubling route to chaos. This circuit is described by a first-order discrete equation which can be transformed into the logistic map whose chaotic dynamics is well known. Several nonlinear circuits which exhibit various types of chaotic phenomena have been reported recently [l]--[5]. Our objective in this letter is to report an experimental result showing the ubiquitous chaotic phenomena can also occur in a switchedcapacitor circuit. Since switched-capacitor circuits are important in VLSI technology, any potential anomaly or failure mechanisms Manuscript received May 28,1985. This paper was supported in part by the Office of Naval Research under Contract NOOO14-76-C-0572, by the National Science Foundation under Grant ECS-8542885, and by the Spain CAICYT under Contract 0245/81. A B. Rodrigua-Vazquez and J. J. Huertas are with the Department of Electrical and Electronic Engineering, University of Secille, Seville, Spain. L. 0. Chua is with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720. 0098-4094/85/1000-1083$01.00 01985 IEEE Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 01,2020 at 16:18:45 UTC from IEEE Xplore. Restrictions apply. 1084 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-32, NO. 10, OCTOBER 1985 +T,Y (b) Fig. 1. A nonlinear switched-capacitor circuit and its associated timing diagram. due to the onset of chaos should be fully analyzed. This chaotic circuit is also of circuit-theoretic interest because its dynamic equation is equivalent to the well-known logistic map [6] whose chaotic dynamics have been extensively studied and is now well understood. Since the logistic map is the simplest chaotic polynomial discrete map, the chaotic circuit to be described below is the simplest chaotic circuit described by a first-order discrete map. Consider the switched-capacitor circuit in Fig. l(a): it is made of a battery I’,, a linear capacitor C,, a nonlinear switched-capa- citor component [7], [8], and three analog switches. The state (on or off) of the switches is controlled by a standard two-phase clock defined by the timing diagram shown in Fig. l(b). The switches labeled S’ (resp., So) turn on in synchronization with the rising edge of the clock signal @’ (resp., +‘). The nonlinear switched-capacitor component-henceforth called an FESC (forward. Euler switched capacitor) resistor-is defined by Q, -Q,-, = kV,2_, A AQ, (1) where AQ, is the net charge flowing into the FESC resistor during the nth clock period, V,-, is the voltage sampled across the FESC resistor during the (n - 1)th period, and K is an arbitrary positive constant. We have built the circuit in Fig. l(a) with C, =l nF and k = 0.5 nF/V using off-the-shelf components and observed the steady-state voltage waveform samples V for different values of the battery voltage v,. Contrary to our intuitive expectation for a single-valued relationship between V and V,, we found the relationship to be multiple-valued over some ranges of the “parameter” y , and undefined i.e., chaotic, for other ranges. This observation is summarized by the bifurcation tree measured experimentally from this circuit. The familiar cascades preceding the chaotic region implies a period-doubling route to chaos [6]. To derive a recursive relationship for V,, we note that the net charge AQ, + i flowing into the FESC resistor during the (n + 1)th clock period must be equal to the net charge flowing out of the linear capacitor C, (charge conservation principle), and hence: V n+l = v, - g v,‘. (4 s We can transform (2) into several more familiar equivalent forms by defining X n+l = uV,+~ + b. If we choose a = l/y and b = 0, we would obtain (3) X n+I =lxx, Fig. 2. Bifurcation tree. + V 4 Fig. 3. Off-the-shelf realization of the FESC resistor in Fig. l(a). where X=kr/;/C,. If we choose and b = i, we would obtain the well-known logistic map X n+1=4Gl(1- 41) where (5) k XP- 4aC, . Both equations, (3) and (5) have been intensively studied [6] and their global qualitative behaviors are now well classified and understood. Consequently, Fig. l(a) represents the first real physical circuit whose chaotic dynamics can be compIetely analyzed. For readers interested in repeating our experiments, the FESC resistor in Fig. l(a) can be realized by the circuit shown in Fig. 3. ACKNOWLEDGMENT The authors would like to thank Greg Bernstein for stimulating discussions which led to this paper. REFERENCES [l] Y. S. Tang, A. I. Mees, and L. 0. Chua, “Synchronization and chaos,” IEEE Trans. Circuits Syst., vol. CAS-30, pp. 620-626, Sept. 1983. [2] A. Azzouz, R. Duhr, and M. Hasler, “Transition to chaos in a simple nonlinear circuit driven by a sinusoidal voltage source,” IEEE Trans. Circuits Syst., vol. CAS-30, pp. 913-914, Dec. 1983. [3] T. Matsumoto, L. 0. Chua, and S. Tanaka, “Simplest chaotic nonautonomous circuit,” Phys. Reu. A, vol. 30, pp. 1155-1157, Aug. 1984. [4] T. Matsumoto, “A chaotic attractor from Chua’s circuit,” IEEE Truns. Circuits Syst., vol. CAS-31, pp. 1055-1058, Dec. 1984. [5] G-Q. Zhong and F. Ayrom, “Experimental confirmation of chaos from Chua’s circuit,” Int. J. Circuit Theory Appt., vol. 13, pp. 93-98, 1985. [6] P. Cvitanovich (Ed.), University in Chaos: A Report Selection. Bristol, England: Adam Hilger, 1984. [7] J. L. Huertas, L. 0. Chua, A. B. Rodriguez-Vazquez, and A. Rueda, “Nonlinear switched-capacitor networks: Basic principles and piecewiselinear design,” IEEE Trans. Circuits Syst., vol. CAS-32, pp. 305-319, Apr. (4) 1985 Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 01,2020 at 16:18:45 UTC from IEEE Xplore. Restrictions apply. [8] A. Rodriguez-Vazquez, J. L. Huertas and L. 0. Chua, “On a class of SC resistors and its application to the synthesis of nonlinear driving-point and transfer-characteristic plots,” Int. J. Circuit Theory Appl., to be published. [9] A. Rodriguez-Vazquez, J. L. Huertas, and L. 0. Chua: “Rational SC networks,” in preparation. Nodal Voltage Simulation of Active RC Networks P. V. ANANDA MOHAN, V. RAMACHANDRAN, AND M. N. S. SWAMY Abstract --It is shown that the floating nodes present in active RC networks can he eliminated by nodal voltage simulation, leading to new active RC networks. The new active RC networks thus generated can be easily used to realize stray-insensitive SC networks. Fqivalence of certain active RC topologies, resulting from application of this method, is also demonstrated. I. INTRODUCTION The theory and design techniques of active RC filters are considerably mature at present. Integrated circuit implementation necessitated circuits using grounded capacitors, to eliminate the effect of bottom-plate parasitic capacitances [l]. With the advent of switched-capacitor technique, it has become necessary to eliminate the effect of parasitic capacitances altogether, since predistortion as well as trimming are unattractive [2]. It is natural, therefore, to attempt to derive stray-insensitive SC topologies from active RC filters using grounded capacitors. Three techniques viz., parasitic compensation [3], [4], nodal voltage simulation [5], [6], and stray-capacitance eliminating transformations [7] have been reported in the literature. In this letter, we examine the second approach in detail. It may be noted that this approach has been used in deriving bilinear SC ladder filters from doubly terminated LC filters [8]. Other variations such as nodal transfer function simulation [9], [lo] are also available in the literature. II. NODALVOLTAGESIMULATION METHOD We study the nodal voltage simulation technique with reference to specific active RC networks, in what follows, in order to demonstrate its utility. A. Application to Multiple Feedback Type Single -Amplifier Low - Pass Filters Consider the multiple-feedback active RC low-pass filter of Fig. l(a). The internal node x in this network is described by KCL as Y v, [ 1 1 1 F+F=v” x+R+R+SC,. I (1) 1 3 1 2 3 It is easy to realize V, using OA’s with grounded noninverting input as shown in Fig. l(b), by the circuit within dotted lines. Augmenting this network by the remaining circuit consisting of Manuscript received April 10, 1984. P. V. Ananda Mohan was with the Department of Electrical Engineering, Concordia University, Montreal, Canada. He is now with Transmission R&D, Indian Telephone Industries, Bangalore, India. V. Ramachandran and M. N. S. Swamy are with the Department of Electrical Engineering, Concordia University, Montreal, Canada. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, VOL. CAS-32, NO. 10, OCTOBER 1985 1085 L-------------l (b) Fig. 1. (a) Multiple feedback low-pass filter. (b) Active RC network equivalent to Fig. l(a). R,, C, and OA A, to realize V, from V,, we obtain the network of Fig. l(b), which interestingly, is the well-known Tow-Thomas biquad [ll]. The availability of band-pass output at node x and low-pass output at V0 in the circuit of Fig. l(a) is transferred to the network in Fig. l(b). Note that, both these circuits are based on inductance simulation [12], [13]. Further, we observe that the circuit of Fig. l(a) is having damping due to resistors R,, R,, and R,. This damping can be reduced by multiplying the effect of R, and R, through a negative resistance to ground at node x [14]. The resulting active RC filter is shown in Fig. 2(a). Proceeding in the same manner as in the case of Fig. l(a), we obtain the equivalent RC active filter of Fig. 2(b). The transfer function realized is given by Kl - l/R, -= K (4 s2ClC2 R, -t SC, R, Thus both low-pass and band-pass transfer functions are still available, while large Q’s can be obtained through the use of nearly equal R, and R, values. The Q-sensitivities are thus large: and $--=1-F. 5 Note that Fischer and Moschytz [15] used such a modification for Fleischer-Laker’s biquad [16] for reducing the capacitance spread. In applications where equal capacitor values are preferred in the circuit of Fig. l(a), positive feedback can be applied [17]. This leads to the modification of the Tow-Thomas biquad, as shown in Fig. 3(a). The transfer function realized is v, l/R, -= Y s2ClC2 R, t s s!p$)+(&AL) (3) Note, however, that the band-pass transfer function is not realizable at the outputs of the OA’s A, and A,. The design equations 0098-4094/85/1000-1085$01.00 01985 IEEE Authorized licensed use limited to: Universidad de Sevilla. Downloaded on April 01,2020 at 16:18:45 UTC from IEEE Xplore. Restrictions apply.