A Model for VLSI implementation of CNN image processing chips using current-mode techniques

A Model for VLSI Implementation of CNN Image Processing Chips Using Current-Mode Techniques S. Espejo, A. Rodriguez-VBzquez, R. Dominguez-Castro, B. Linares and J.L. Huertas Dept. of Analog Circuit Design. Centro Nacional dc Microelectr6nica-Univcrsidad dc Scvilla Edificio CICA. Cnarfia sn. 41012-Sevilla, SPAIN Phone # 34 5 46238 1 1. FAX # 34 5 4624506. email: [email protected] Abstract- A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. Current-mode building hlocks are presented for the design of CMOS image preprocessing chips (feature extraction, noise filtering, compound component detection, etc.) using the cellular neural network paradigm. Area evaluation for the new model shows a reduction of about 50% as compared to the use of current-mode techniques with conventional models. Experimental measurements of CMOS prototypes designed in a 1.6pm n-well double-metal single-poly technology are reported. I. INTRODUCTION Cellular Neural Networks (CNN) consist of arrays of clcmentary processing units (cells). each one connected only to a set of adjacent cells (iwighhors). The reduced conncctivity allows high cell density in terms of silicon area. and Eicililatcs CNN physical design. For thc class of tmislotioiicill~ iir\wri(iirt CNNs. in which all inner cells rue identical. programm;ibilily can be incorporated withour a significant routing cost. by just adding a few global control lines. onc pcr weight. CNN properties. and its application to image processing. pattcrn recognition. motion detection. etc.. have bccn covered in different papers. for instance [ 1-91. This communication focuses on CNN VLSI implementation. of which little literaturc is available [10.11]. First. a new CNN mathematical modcl is presented which exhibits some advantages for VLSI implcmentation as compared to the conventional model duc to Chua and Yang [I]. Then. we consider Ihc implementation of this model in current domain. Since CNN's are basically rrimcd lo image processing applications. and primary output of image sensor deviccs (phototransistors [ 121) is currcnt. this implcmentation style is advantageous as compared to previous proposals. wherc cell input signals arc voltages. Thc results obtained show better arca. power and spccd Ligurcs than prcvious CNN implementation techniques. 11. EXTENDED RANGE CNN MODEL Previously reported CNN IC dcsign approachcs focuscd on the use of gn,-C techniques for thc implemcnlation of thc Chua-Yang's cell circuit model [I]. shown in Fig.1. whosc 0-7803-1254-6/93$03.00 Q 1993 IEEE dynamic is givcn by Ihc following sct of nonlinciu statc-equa- lions, VCE g!D where N,.(c) represents thc cpII rreighhortrood. including cell I' itself. qD is thc nct grid dottitiin. and thc cdl oiitpiits (J~) arc obtained from the store wriohli~s, .id, by thc following nonlincar function. The coefficicnls A/ mu/ R; . with d E N,(r), can bc arranged in two matriccs A' and I)'. callcd thcfiw1htic.k and wiitrol /mplotes rcspcclivcly. whilc il' is known ;IS thc 0fl.w term. Thc lime constant T is assumcd invari;int from ccll to ccll. For translalionally invariant CNNs. thc offsct tcrm and Ihe entries of A and I3 arc also ccll-invariant. Compulational propcrtics of this modcl rcly on its ability to yicld. forArr>l. Iwo slahlc cquilihrium points separated by an inslahilily rcgion. and in Ihc possibility of modifying the stablc point allraction rcgions hy changing thc ncighbor contribulions, d ?t r .. ....... ...... .... ....... - - - - - Fig. 1: Cliua-Yiing CSN Ccll Circuil Modcl (1 I. 970 This is illustrated in Fig.2. showing the ~(d?/dt) vs. f characteristic for the different qualitative situations possible. The displayed dynamic mutes show that the attraction region for the equilibrium point on the right (equilibrium points are at the intersection of the characteristics to the horizontal axis) becomes narrower for I decreasing; for /=Il. this point becomes virtual. A similar situation happens for the equilibrium point on the left, in case I increases. Analog VLSI implementation of (1) must handle different variation ranges for the state and the output variables. as illustrated in Fig.2: while output variables are restricted to [-1.11 by (2). state variable excursions are not constrained. although it can be shown [ 11 that they remain bounded by the following normalized maximum value, which. for typical templates, ranges between 5 and 10. Thus, in the previously reported g,-C circuits [ 10, 111. where all resistive components in Fig.1 are realized by differential input transconductors. largely different biasing conditions and design equations must be considered for the transconductors, thus complicating the sizing process and yielding non-opti- mum power consumption and area figures. A new continuous time (CT) CNN cell model is proposed here to overcome drawbacks of (1) while preserving its computational properties. The cell state equation for this new model is given by. VC€ ip where g(.) is a three pieces piecewise linear characteristics given by. --NZ(XC+1) +1 sr<-l - nz (XC - 1) - 1 .IC > 1 g (xC) = lim { -s otiierwise (6) This model yields two stable equilibrium points separated by an instability region. as (1) does. Also as in (1). the attracm -+ - Fig. 3: Dynamic Routes for the proposed CNN model: /,</,cO<13c/,. tion region for the stable equilibria can bc modified by changing the I parameter. This is illustrated in Fig.3. As a difference to (1). in the new model all variables have the same variation range, what. when it comes to silicon. is very appealing to reduce power and ccll area and to simplify thc design process. Larger produclion yields are also found for circuits based on this new model. specially when dealing with low voltage technologies. 111. CURRENT MODE BASIC BUILDING BLOCKS The operations required for the implcmentation of (5) and (6) are: sirmntntioti. weighted replication. rionlinenr linutatioa and ititegrotioti. In current-modc. summation is simply achieved by routing signals to a common node. Weighted replication is obtained by using ritrretit niirrws. In MOS technologies. the scaling factor is controlled by lransistor sizes. Since in current mirrors currents always flow in the .same direction, bias-shifting is required to allow for the symmetric existenceinterval of the variables. These concepls arc illustrated in FigA(a) and (b). Scvcral output currents with Ihc same or different scaling factors can be obtained by using different output transistors. Nonlinear limilalion is also obtained using current mirrors. In FigA(b). a saturation nonlinearity appears as a result of the cut-off of thc inpul Icinsistor. By cascading two of these structures. the nonlinenrity in (2) is obtained. as shown in Fig5 Finally. a current-mode lossy integrator can be easily implcmentcd by exploiting reactive parasitic behavior of a current mirror. as illustralcd in Fig.6. whose small signal behavior is dcscribcd by the following equation, where '5 is givcn by '5=CIg,,,, g,,, bcing the small signal transconductance of the transistors in the current mirror. Under Fig. 2: Dynam'ic Routes for the Chua-Yang CNN model: /,</<Ocf,</,. Fig. 4: a) MOS cument mirror: h) MOS current mirror with hias shifting. 97 1 fQ .......... $+ lit, .......... .-IQ Fig. 5: Implementation of the nonlinear operator/(*) large signal operation, the lossy integrator time constant becomes a function of the output current (through g,,,). However. it can be shown that this nonlincarity does not alter thc computational properties of current-mode CNNs. but just produces slight changes in the transient response. Current saturation at the lossy integrator output can bc exploited for the implementation of the nonlincarity requircd in the new model. given by (6). Notc that bias currcnt in thc integrator of Fig.6 determines the lower extreme of the state variable range (I, > -IQ). The upper extreme is determined by the loading device. Thus. by using the same bias currcnt la for this loading device, we force the integrator output current to remain confined inside the interval [-/a. la]. thus having a very simple way to implement (6). Notc also that. sincc output and state variables are confined to thc s;imc interval. the physical implementation of (2) is not required. The above mentioned building blocks can also be realized by enhanced CMOS mirrors (sclf-biased cascodc. cascodc. servo-mirrors. etc.), as can be required to reduce crrors due to finite Early voltages. The resulting area and speed penahtions arc usually not severe. IV. CELL ARCHITECTURE Fig.7 shows a conceptual diagram for a CNN cell, according to either (1) or (5). Weighted replication is achieved with the circuit in Fig.4(b). When sign inversion is required. an additional replication stage is cascaded. For the realization of (5). the nonlinear operator is implcmentcd by properly 1o;iding the inlegrator block, and hence, the nonlinear opcraor block is not required. For simplicity, 1/0 circuitry has not been included in thc diagram in Fig.7. Initial state values ~"(0) and extenlid inputs 14' can be electrically set, or optically transmitted using photoaclive devices [ 121. Output of each cell can be evaluated wilh thc help of an additional replication branch. Furthcr I/O considerations are needed to reduce pinagc of 1;ugc-ncl chips. DYNAMIC .f NONI.IM:AK I" OPERATOR OPERATOR WEIG'lTE -L I SR' Fig. 7: Generic currcnt-nioclc CNS ccll architecture Note that weighted replication is pcrformcd at the output of each cell. In other words. cach ccll produccs a different output. with the required weight. for each neighbor. At each cell. neighbor contributions arc added at thc input node as they are rcceived. In order to avoid confusion whcn dcsigning currcntmode CNNs. it is convenient to work with ncw template m:itrices. obtaincd interchanging A;' by A," and R," by Bde. Fig.8(a) shows the complete cell schcmatic of ;i conncctcd componcnt detection (CCD) CNN 161. using singlc transistor mirrors. For thc sakc of illustration. T;ihlc I givcs thc tolal ccll ;irca for differcnt tcmplatcs in ;I I .6pm CMOS technology, corresponding to the usc of currcnt-mode techniques for the implemcntalion of both thc Chu;i-Yang and the extended rangc model. Cascodc transistors with Wdpm and L=.3.2pm arc used for the currcnt mirror building blocks. as illustratcd in Fig.S(b). Although data in Triblc I docs not includc thc arcs occupied by thc initializ;i1ion circuilry; approximatc pixcl-dcn- sitics r:vigc from 60 to 160 cclls/mm- (dcpcnding on thc parlicular lemplalc) whcn the proposcd inodcl is uscd. V. EX IW I MENTA I. Rlisui :Is Experimental rcsults of ;I CCD CNN prototype, dcsigned in a 1.6pm double-mct;il singlc-poly CMOS technology, arc summarizcd hcrc. Thc dcsign actually includes two prototypes. cach with sixtccn cclls in ;I row. First protolypc (PI) corrcsponds to thc schcm:rtic in Fig.#(:!) whilc thc second otlc (P2) corresponds lo Ihc convcntion;rl CNN model by Chua and Yang. Both prototypes wcrc dcsigned using thc currcnl-modc tcchniquc describcd :rbovc. Design proccss bcgins by choosing ;I rorirrrr? birrs riirtm/ (Iq) which in our casc W;IS 2pA. A cuimil mirror capable of driving ?la and a IQ currcnt sourcc must thcn bc dcsigned. C:iscodc structurcs wcrc uscd in our dcsign to implcmcnt both the currcni mirror and rhc currcnl sourcc. All transistors had Fig. 6: Lossy integrator. Fig. 8: a) Schcnwtic id ;I CSS ccll for CCI): h) CilsciXIc struclure. 972 REFERENCES L.O. Cua and 1.. Yang: "Cellular Neural Networks: Theory". lEEE Trotis. Circrtirs orid Sysfenrs. Vol. CAS-35. pp 1257-1272. 1988. L.O. Cua and L. Yang: "Cellular Neural Networks: Applications". /EEE Trorrs. Circrtirs and Svsrcnrs. vol. CAS-35. pp 1273-1290. 1988. L.O. Chua and I. Roska: "Stability of a Class of Nonreciprocal Cellular Neural Networks". /EEE Trarrs. Circrrirs orrd S,vsrenrs. Vol. L.O. Chua and F'. Thiran: "An Analytical Method for Designing Simple Cellular Neural Networks". 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Hole Filling Noise Filtering TABLE I CELL AREA FOR DIFFERFN TEMPLATES AND CNN MODELS 10921 24774 5460 14258 Area (pm') Area (pin') C.C. Detector. 1269 1 Shadow Detector. 16533 Borders Extrac. 1537 1 26291 I CornersExtrac. I 16381 I 28212 1 a) b) Fig. 9: Cell layouts: a) prototype PI : b) prototype P? I1OlJ.M. CNZ and I..O. Chua: "A CNN Chip for Connected Component Detection". /EEE l'rarw. Circrtirs arid Systenrs. Vol. CAS-38. pp 812- 817.1991. 11 11K. Halonen et ai: "V1,SI lniplcnientation of a Reconfigurahle Cellular Neural Network Containing Local Logic". /!if. -1. Circrrif Theory Applicarinris. 1992 (to appear) I12JA.H. Sayles and J.P. Uyemura: "An Optoelectronic CMOS Memory Circuit for I'aralell Iktcction and Storage of Optical Ilata". EEE J. Solid-Sfafr C'rrcrtirv. Vol. SC-26. pp 1 110-1 115. 1991. [ 1.31s. Espejo: PIi.D. /~rssc*rroriort. University of Seville. Spain. (In t'rog rcss. ) I I I Fig. 10: Experimental nieasurenients froni prototype PI. 973