Design Contributions to high-end low-noise CMOS image Sensors

1 DOCTORAL THESIS DESIGN CONTRIBUTIONS TO HIGH-END LOW-NOISE CMOS IMAGE SENSORS JOSÉ ÁNGEL SEGOVIA DE LA TORRE Doctorate Program Physical Sciences and Technologies Advisor: Prof. Ángel Rodríguez Vázquez Tutor: Prof. Ángel Rodríguez Vázquez Sevilla, 2024 2 3 To my wife Eve for always supporting me To my children Pilar, Rafael and Fernando 4 ACKNOWLEDGMENTS The development of a doctoral thesis and the linked research project linked is a long journey, with many difficulties, unfruitful results but with also quite important and satisfactory achievements that are the result of a continuous collaborative work in an adequate environment. It is even more important, in the doctoral thesis developed in the company in collaboration with the University which is the case of this work. Nonetheless, apart from the results is very important the knowledge and the strong and professional relationship developed along this journey. This thesis can be seen as an individual dream that could not become real without the collaboration, the support and the friendship of these people that have been along with me in this journey. First of all, I would like to express my gratitude to Ángel Rodríguez Vazquez as professor and advisor of this Thesis. He has help me not only with the technical teaching, advice and support but also he has encouraged me to follow and to push to achieve this goal. Additionally, I would like to say thanks, lot of thanks, to my professor, tutor, and friend Fernando Medeiro, who unfortunately passed away at the beginning of the Thesis, and we could not continue this journey together, I will be always grateful for the mark he provided on me as a professional and as a person, thanks Fernando. Secondly and with same level of gratitude, I want to thank for the support obtained by Ana Gonzalez and Rafael Romay for this Thesis, as managers in my company Teledyne Anafocus. They are doing a very good job supporting and encouraging individuals to achieve their own targets, as my case. As friends I have to say I am lucky to be along with them working and trying to address new markets, to achieve ultimate devices and to build outstanding team and enjoying with all of that. The third and not less important, I would like to say lot of thanks to my wife, Eva, who encouraged me to have the decision of doing the Thesis when I expressed my interested on that. Also, I would like to say lot of thanks to my daughter Pilar, who also took care of my other two children Rafael and Fernando, she is very responsible even at her age. Thanks to all of them, especially Eva, who has supported me, taking care of the children along with my mother in Law, Mari, and to the children for the time I have stolen them, I am in debt. Additionally, I want to say thanks to many colleagues in Teledyne Anafocus: Alex Charlet, the first person I started working with in microelectronic design. Rafael Dominguez thanks for the endless discussions and the continuous learning from him. Alberto Villegas who also has collaborated in the projects related with this Thesis, his kindness and good job are impressive. Loli Pardo who is leading the design team and being participant in the digital design of many projects. Jesus Ruiz, Antonio Ortiz de Galisteo, Paco Benavides who are leading the technical projects with persistence and hard work. The rest of the analog team: Joao Borrelho, Jesus Aguado, Blanca Piñero, Nuria Porcel, and the rest. I would like to say thanks for all the good conversations and good relationship in Teledyne Anafocus. The people in the characterization team, who also help in this Thesis: Gema Valles, Marta Salamanca and Mario Guerra. And in the rest of teams in Teledyne Anafocus: Luis Salas, Juan Listan, Cayetana Utrera, Walter Iandolo, Carlos Mendoza, Luis Alba, Rafa Payseo with all of them I have shared discussions and technical exchanges, I would like to say thanks to them as well. And finally, I would like to express my gratitude to my parents and siblings, they have taught me the effort, resilience and hard work brings fruitful results, and also they have been supporting me from the moment I left home to start University studies. 5 ABSTRACT The main objective of this thesis consists of providing a new readout architecture able to meet two of the most demanding specifications in image sensor: low noise and speed. The presented readout channel provides 1.3 eRMS noise images with a conversion time shorter than five microseconds, with the availability of exchange precision and speed achieving 0.7 eRMS when extending the time up to 80 microseconds. Additionally, a pixel optimization procedure has been developed based on experimental data and a model to extrapolate the empirical data to the expected performances with the new readout architecture. On top of that, an architecture modification for the readout channel is provided to work with dual conversion gain pixels in order to provide high dynamic range images. It has been proved, that the readout channel is valid for large scale wafer devices and one reticle devices, two prototypes are described with the readout channel described in this Thesis. In these prototypes, not only the readout features are described, but also other techniques to reduce glow effect, improve yield and the readout calibration process. Finally, a bench mark is provided to show a comparison of the noise speed comparison with other publications in the state of the art showing the benefits of the proposed architecture. The chapters in this Thesis are organized as follows: • Chapter 1 a brief snapshot about the status and trends of the microelectronics and microsystems and the important position of the image sensors in microelectronic nowadays. Also, it provides the evolution of image sensors along the last decades to the current situation where mobile leads the current market, but other emerging applications demands new functionalities from the CIS technology. After that, the types of noise in image sensors are described with emphasis in temporal noise sources, where the pixel noise contributors are described in detail. • Chapter 2 presents the pixel noise and linearity optimization study based on a 6.5 um 4T CMOS pixel with a native source follower. This optimization procedure involves designing and characterizing a low-noise noise chip with several pixel variants where transistor dimensions and other changes are tested and characterized. The optimization of operation voltages has been shown to improve noise and linearity performances. A semi-empirical model has been developed to extrapolate data from the characterization test chip to the new readout channel presented in this Thesis. The Chapter ends with the selection of a pixel variant. • Chapter 3 describes the proposed low-noise readout channel based on two stages of ADC: Incremental ADC and Single-Slope ADC. The Chapter also shows the functional and implementation descriptions and noise analysis for every ADC stage. The readout channel can operate with internal analog CDS and external digital CDS. The Thesis discusses the two operation modes, showing the noise performances in simulation and data measurements. The analog ramp generation base in the current steering DAC is also presented. Finally, the two stages of ADC need calibration to align the ranges and avoid missing codes or gaps in the conversion. A technique for calibration is outlined, and the method for implementing this technique in real devices for online calibration is discussed. • Chapter 4 presents a variation of the readout channel for high dynamic range applications that employs a dual conversion gain of 10 μm pixels with optimized readout. This chapter starts by revising the state-of-the-art regarding high dynamic range techniques to support selecting the methods developed in this Thesis. The pixel architecture with dual conversion gain is presented and the optimization based on a test-chip is shown. Optimization relies on varying device dimensions to optimize maximum FWC and minimum temporal noise. Finally, the ADC architecture optimization based on the previous readout for dual conversion gain is described. • Chapter 5 presents two image sensor prototypes incorporating the low noise and high dynamic range described in this Thesis. The first image sensor is a 5.3 Megapixel device with 6.5 μm 4T CMOS pixel delivering images with 0.7 e-RMS of temporal noise and 15000 electrons of full well capacity. The 6 second image sensor is a large-scale, 66 Megapixel device with 10um dual conversion pixels. This device can collect more than 100000 electrons with 1 e-RMS noise achieving 100 dB dynamic range. These two devices use different techniques to reduce undesirable effects, such as the thermionic emission from the peripheral circuitry, known as the glow effect. Additionally, methods to improve yield in large size devices are presented. During the development and characterization of those image sensor prototypes important milestones have been addressed as follows: • Glow Effect: The glow is a limiting phenomenon that doesn’t allow reducing the dark current when cooling the image sensor even with negatives temperatures. In this thesis a process fabrication and a methodology has been developed to minimize at very low levels the glow contribution. It is based on the use of aluminum layer in order to cover all the active circuits that may emit light, and additionally create a vertical trench covered with the same aluminum layer to block the light with is travelling through the silicon to the pixel array. This glow effect is quite important in BSI devices since the multidirectional emission create multipaths for the light that reach the pixel array. • Yield improvements: This point is important specially for wafer scale large image sensors, where one defect in the wafer means a defective device. A scalable repairing circuitry has been proposed and incorporated in the image sensor to improve yield. Additionally, special DFM rules have been used in the pixel array as using only one metal line per metal layer and using always it is possible two contacts and two vias minimum. • Quantum efficiency: Very high quantum efficiency has been achieved using BSI devices. This achievement is mainly driven by the technology, but the pixel design has been done compatible with BSI technology. It is remarkable the lack of etaloning (interferometry due to interference with metal layers), which can be very important for applications like spectroscopy. • Operation Modes: multiple operation modes and functions are implemented to increment the image sensor flexibility and to provide a tailored operation mode for each application. Finally, a benchmark comparison of this work with other contributions in the state-of-the-art has been developed. This benchmark shows the image sensor and readout channel provide very low noise results at high-speed considering a very appropriate option for the low noise applications. In fact, the readout noise is providing very low noise, and then if we were able to provide with a better pixel in terms of noise, the resultant image sensor would provide better performances with any change in the readout channel. 7 TABLE OF CONTENTS CHAPTER 1 ........................................................................................................................................................ 13 1. INTRODUCTION TO LOW NOISE IMAGE SENSORS ......................................................................................... 13 1.1 A glimpse on microelectronic and microsystem trends ................................................................... 14 1.2 Snapshots about CIS Evolution ....................................................................................................... 16 1.2.1 Introduction .............................................................................................................................. 16 1.2.2 Overview of CIS evolution milestones ..................................................................................... 21 1.3 Noise in image sensors ................................................................................................................... 25 1.3.1 Pixel noise analysis ................................................................................................................. 27 1.3.2 Source follower noise .............................................................................................................. 29 1.3.3 Photon shot noise .................................................................................................................... 31 1.3.4 Dark Current noise ................................................................................................................... 32 1.3.5 Transfer Noise ......................................................................................................................... 34 1.3.6 Reset noise .............................................................................................................................. 34 1.4 Readout architectures in image sensors ......................................................................................... 36 1.4.1 Common noise source in ADCs............................................................................................... 36 1.4.2 Column amplification ............................................................................................................... 40 1.4.3 Correlated double sampling ..................................................................................................... 41 1.5 Thesis outline and organization ....................................................................................................... 42 CHAPTER 2 ........................................................................................................................................................ 45 2. PIXEL NOISE OPTIMIZATION ........................................................................................................................ 45 2.1 Test structures pixel variants and characterization results .............................................................. 46 2.1.1 Description of pixel variants and waveforms ........................................................................... 46 2.1.2 Test vehicle chip architecture .................................................................................................. 48 2.1.3 Characterization results ........................................................................................................... 50 2.2 Pixel voltage optimization ................................................................................................................ 56 2.2.1 Voltage optimization for dark noise ......................................................................................... 56 2.3 Pixel source-follower noise semi-empirical model ........................................................................... 58 2.3.1 Pixel noise Thermal and 1/f Noises after CDS operation ........................................................ 58 2.3.2 Pixel noise in CMS operation ................................................................................................... 63 2.4 Model extrapolation for proposed ADCs architecture ...................................................................... 64 CHAPTER 3 ........................................................................................................................................................ 65 3. TWO STAGES ADC FOR LOW NOISE CMOS IMAGE SENSORS ...................................................................... 65 3.1 Introduction ...................................................................................................................................... 66 3.1.1 Motivation ................................................................................................................................. 66 3.1.2 Outline of proposed readout architecture ................................................................................ 68 3.2 First stage: incremental ADC ........................................................................................................... 70 3.2.1 Functional description .............................................................................................................. 70 3.2.2 Implementation ........................................................................................................................ 71 3.2.3 Noise Analysis ......................................................................................................................... 71 3.3 Second stage: SS-ADC ................................................................................................................... 72 3.3.1 Functional description .............................................................................................................. 73 3.3.2 Implementation ........................................................................................................................ 74 3.3.3 Noise Analysis ......................................................................................................................... 74 3.4 Analog ramp generator .................................................................................................................... 75 3.5 Readout working in external CDS mode ......................................................................................... 76 3.5.1 Functional description and implementation ............................................................................. 76 3.5.2 Noise Analysis ......................................................................................................................... 77 3.6 Readout channel performance ........................................................................................................ 78 3.6.1 Linearity ................................................................................................................................... 78 3.6.2 Noise ........................................................................................................................................ 80 3.7 Readout working in correlated multisampling with external CDS .................................................... 81 3.8 Readout calibration on-chip ............................................................................................................. 84 CHAPTER 4 ........................................................................................................................................................ 85 4. TWO STAGES ADC EXTENSION FOR DUAL CONVERSION GAIN HDR .............................................................. 85 4.1 High Dynamic Range state-of-the-art review ................................................................................... 86 4.1.1 Multiple exposures HDR methods ........................................................................................... 86 4.1.2 Multiple gains HDR method ..................................................................................................... 89 4.1.3 Logarithmic pixel ...................................................................................................................... 96 4.1.4 Techniques based on per-pixel ADCs ................................................................................... 100 4.1.5 Time to saturation pixel .......................................................................................................... 102 4.1.6 HDR techniques comparative ................................................................................................ 103 4.2 Pixel architecture ........................................................................................................................... 104 4.2.1 Pixel schematics and waveforms........................................................................................... 104 4.2.2 Test chip ................................................................................................................................ 106 4.2.3 Pixel performance .................................................................................................................. 106 4.3 ADC architecture ........................................................................................................................... 110 4.3.1 Dual conversion ADC functional description ......................................................................... 110 CHAPTER 5 ...................................................................................................................................................... 113 5. LOW NOISE CISS WITH OPTIMIZED PIXELS,,DUAL GAIN AND OVERSAMPLED ADCS .................................. 113 5.1 Low noise sensor with 5.3 Mpixel and 0.7erms dark noise ........................................................... 114 5.1.1 General description ................................................................................................................ 114 5.1.2 Sensor Architecture ............................................................................................................... 117 5.1.3 Operation modes ................................................................................................................... 119 5.1.4 ULN5.3 Sensor characterization ............................................................................................ 126 5.1.5 Optical performances in 14 bits rolling-shutter mode ............................................................ 131 5.1.6 Optical performances in 16 bits rolling-shutter mode ............................................................ 132 5.1.7 Performances in 14 bits multisampling (M = 16) rolling-shutter mode .................................. 133 5.1.8 Dark current ........................................................................................................................... 134 5.1.9 Glow effect and mitigation techniques ................................................................................... 135 5.1.10 Low light benchmark comparison .......................................................................................... 135 5.2 Large scale 66 Mpixel 10 mm pixel low noise and high ................................................................ 139 5.2.1 Sensor Architecture ............................................................................................................... 141 9 5.2.2 Operation modes ................................................................................................................... 143 5.2.3 Sensor functions .................................................................................................................... 148 5.2.4 Sensor yield improvement ..................................................................................................... 148 5.2.5 Optical performances measurements .................................................................................... 149 5.2.6 ULN66 in the active cooling camera ...................................................................................... 157 5.3 Low Noise Benchmark comparison ............................................................................................... 159 6. CONCLUSIONS, CONTRIBUTIONS AND FUTURE WORK ................................................................................ 163 Chapter 1 Introduction to Low Noise Image Sensors 16 Previous paragraphs can be summarized in a simple statement: Images and the visual sense (extraction of information from images) are crucial for artificial sensing-interacting microsystems Modern daily life provides multiple examples supporting the previous statement. In modern Society, most of us carry personal electronic appliances that embed CMOS Image Sensor (CIS) devices. We use them customarily to take photos and videos to capture and retain our memories. The sectors of mobile phones and personal electronics demand huge amounts of silicon wafers being processed by the semiconductor foundries. However, CISs are present in many other applications, from molecular imaging to astronomy observation, including automotive, medical diagnosis, brain-machine interfacing, industrial inspection lines, surveillance, etc. Furthermore, many unexpected application scenarios will likely be opened, prompted by emerging paradigms like the Internet of Things, among others. Finally, the ability yielded by CMOS to combine detectors with processing circuitry enables incorporating image analysis features in the same silicon substrate where images are captured, thus paving the way for the implementation of CVISs (CMOS VIsion Sensors), an evolution of CISs capable of completing vision tasks on-chip [Rodri17]. The increased maturity of 3D, wafer-stacked technologies leverages CISa and CVISs capabilities by enabling the distribution of non-sensing circuit resources (processing, calibration, control, memory, etc.) and, thus, allowing to reduce the pixel pitch and increase the fill factor 3 . Fig. 4 at the right inset, of Yole Development, illustrates the wide deployment of CISs devices. ILLUSTRATING CIS SECTORS (https://www.yole.fr) 1.2 SNAPSHOTS ABOUT CIS EVOLUTION 1.2.1 Introduction From early imaging to CCD “A picture tells a thousand words.” This idiom highlights the importance of images and optical scenes as information carriers in modern microsystems. Using images to convey information is a human practice since the early ages of mankind. With a bit much larger sophistication than primitive schematic drawings, the first approach of a camera was the camera obscura which principles are rooted to 470 BC and the works of the Chinese philosopher Mozi. This camera operates on the realms of the phenomena occurring when the light goes through a small hole and the image in one side is projected in the opposite surface and generate the inverted image [Newha82]. Already in the 11th century the Arab physicist Ibn Al-Haytham wrote the book 3 Pixel pitch and fill factor should not require definitions in a specialized monograph like this Thesis. However, CVISs compromise both features as they include more non-active circuits at the pixel level, i.e., circuits not dedicated to capturing photons, than CISs. Thus, pixel dimensions (pitch) and fill factor (percentage of the active circuitry per pixel) get penalized. 3D stacking is particularly relevant to CVISs, enabling better pitch and fill factors through active and non-active circuitry vertical distribution per layer. 1.2 Snapshots about CIS Evolution _ 17 of optics (Book of Optics - Wikipedia). This early standout work in optics states the first fundamentals laws of reflexion and refraction along with the analysis and construction of first lenses. At the beginning of the 19th c century, Nicéphore Niépce a French inventor and photographer (Nicéphore Niépce - Wikipedia) obtained the first photograph by using a small camera, with a small hole 4 and silver chloride film, which became darkened when it was exposing to the light. After that, some progress by using other materials and process were done up to the dry plate, which increases the sensitivity allowing the socalled “instantaneous snapshot”. These progresses lead to the invention of the the photographic film camera in 1885. The inventor of this key milestone, George Eastman called his first camera: KODAK It was offered for sale in 1988 [Kodak19] . Kodak company developed the first true color film in 1942 for still photography. The roll film camera has been extensively used until the end of the 20th century when the electronic photography replaced them. Modern physics has brought many advances concerning analyzing the dual nature of light, which is both an electromagnetic wave and a stream of photon particles that are the quantum of light. These new concepts and theories were contributed by many geniuses, from Huyggens and Maxwell to Max Planck and Albert Einstein, among many other characters. Maxwell’s equations can describe electromagnetic fileds and are very useful for studying propagation, but objects absorb and emit light in quantized energy packets associated to photon particles. These advances converged with solid-state electronics during the 20th century to support the invention of Charge Coupled Device (CCD) detectors in 1969 [Boyle70] – an invention awarded the Nobel Prize in Physics in 2009. CCDs employ structures similar to modern CISs, namely capacitors supporting the transfer of charge packets and depleted MOS structures as photodetectors. They experienced many significant advances over the years [Smith09]; however, they are intrinsically limited by the difficulties of embedding processing circuitry besides the detectors. Thus, they have been progressively replaced by CISs [Fossu97][Fossu14], although they still have some niche in astronomy and scientific instrumentation applications [Janes01]. From CCDs to CISs CISs have evolved to progressively replaced CCDs fueled by: • The possibility to embed multiple functions together with the detectors. Thus, modern CISs are complete systems, nearly camera-on-chip, capable of delivering fully digital images instead of « just » analog raw data. As mentioned, CVISs go far in this direction by including even image analysis on the chip – readers are cautioned that CVISs are not targeted in this Thesis. • The invention of the Pinned Photo Diode (PPD) by Nippon Electric Co Ltd researchers in 1980. This key invention by N. Teranishi, H. Shiraki and Y. Ishihara overcame image quality drawbacks of previous CMOS-compatible photodiodes, thus permitting to achieve acquisition quality closer to that of CCDs in terms of noise, dark current (leading to images with no illumination) and other performance features[Fossu14] . CISs deliver images when irradiated by light at frequencies covering roughly the visible and the near infrared bands of the electromagnetic spectrum: [400nm <  < 1000nm]. Image capture by CIS involves, among other processes, photon absorption and photon-to-charge transformation; these processes happen both at photo-sensor devices embedded into a silicon semiconductor substrate. Therefore this substrate becomes an active, photosensitive “plane” where light gets focused by optical lenses. This is the reason why this active semiconductor plane is sometimes called focal plane. The focal plane also includes non-sensitive circuits employed for different purposes. Fig. 5, which corresponds to a sensor conceived in this Thesis, illustrates the conceptual block diagram of a modern CIS 4 Interestingly, pin-hole lenses are still used today for some low-cost camera modules in some applications [Gomez23]. Chapter 1 Introduction to Low Noise Image Sensors 18 chip designed to deliver digitally-encoded images. When implemented in planar technologies, all these blocks are embedded in the focal plane, although only the pixel array. This core part in Fig. 5(a) consists of a regular arrangement of photo-sensitive structures that create mathematical representations of the incoming images comprised of a matrix of voltages “proportional” to the light energy absorbed at the spatial region occupied by each pixel (spatial image samples) 5 . The pixel array (see the illustration in Fig. 5(b)) comprises a regular arrangement of photo-sensitive devices each capturing a spatial sample of an incoming image. The rest of chip functions are customarily located in the chip periphery and must be masked to reduce the impact of parasitic photon-induced electron-hole generation outside the photosensitive area. (a) (b) EXAMPLE OF DIGITAL CMOS IMAGE SENSOR: (A) BLOCK DIAGRAM; (B) ILLUSTRATION OF PIXEL ARRAY ARRANGEMENT CIS chips can be illuminated either at the top (Front Side Illumination – FSI) or at the bottom (Back Side Illumination – BSI). Differences between these two cases are illustrated for a color pixel in Fig. 6. In the case of BSI, optical lenses are placed at the bottom surface of a back thinned semiconductor wafer (down to 4-10 m thickness) and the light reaches directly the silicon (where photosensors are placed) without interfering with IC layers employed for interconnection and isolation. In the case of FSI, optical lenses are placed at the top surface and light must propagate throughout the top chip layers and structures before reaching the photosensitive silicon. BSI technologies have the advantage of providing better quantum efficiency ((the number of impinging photons that produce electron-hole pair – see footnote 1 and fill factor, since there are no metals blocking the light. Additionally other advantages of BSI is the sensitivity to UV waveforms can be much more higher since these energetic waveforms are recombined very close to the surface and then out of the silicon region in FSI devices. Chips reported in in this Thesis are compatible with illumination options. 5 The proportionality of the response is a target in most cases, although some applications demand a non-linear compressive response to support a higher dynamic range. Regarding sampling, most modern CISs sample across space (array plane) and throughout time (images composed of a sequence of Frames). However, new classes of CISs are merging where temporal is asynchronous, driven by events happening in the image sequence [Leñe18]. ... ... ... ... ... ... ... ... ... ... ... ... A/D Readout A/D Readout A/D Readout A/D Readout A/D Readout A/D Readout Pixel Array Outputs Pixel control buffers 1.2 Snapshots about CIS Evolution _ 19 ILLUSTRATING FSI AND BSI TECHNO OPTIONS Despite the application, CIS pixels include sensitive and non-sensitive devices and circuits. Fig. 7 at the right inset shows a conceptual foot-print of a modern BSI CIS pixel where the active, photo-sensitive area (in yellow) amounts typically to ~60% of the total pixel area. Note in this illustration that the BSI sensing wafer is bonded to a support wafer made of glass or silicon and placed at the top surface of the sensor wafer. ILLUSTRATING PIXEL FOOTPRINT FOR A BSI CIS Pixel foot-print can be optimized by resorting to 3D-stacked technologies. Fig. 8 illustrates this concept by showing the splitting of the sensor of Fig. 5 in two wafers, namely: • A sensing wafer; • A logic wafer. In this particular example, 3D stacking aims to the optimum distribution of the pixel array, on the one hand, and control-memory-processing functions, on the other hand. However, the same concept can be used to optimize the foot-print at the pixel level, inside the pixel itself, as it happens in CVISs [Rodri17] and the newest class of Dynamic Vision Sensors (DVS) [Kodam23]. “Citius, altius, fortius”, the Olympic motto, applies to the evolution of imagers fueled by CIS processes, convergent packaging, and heterogeneous integration technologies. Thus, although it is always a bit risky to cluster and compartimentalize technology evolution, some significant trends can be identified as described in the bullet points below: • One trend is related to the prevalent decrease of the pixel pitch, the increase of the fill factor, and the increase of the resolution (number of pixels) and the speed (measured in Frames-per-second in conventional CISs). Prevalent trends of CIS industry include decreasing the pixel pitch and increasing the fill factors. The pitch of last-generation consumer sensors is below 1 m, although other applications, including machine vision and scientific imaging, use larger pixel pitch. For instance, this Thesis presents sensors with a pitch of 6.5m and a fill factor of 78%. • Another major trend is the progressive incorporation of image-depth acquisition to pixels and sensors. Different methods can be used for that purpose, including indirect and direct time-of-flight measurement. Suitable pixel architectures enable even combining the acquisition of intensity maps Chapter 1 Introduction to Low Noise Image Sensors 20 (conventional 2D images) with image depths (3D images), thus creating more detailed representations of the scenes [Bhand16]. Sensor wafer Logic wafer SPLITTING OF THE SENSOR ARCHITECTURE OF FIG.2 FOR A 3D-STACKAED TECHNOLOGY • The last trend identified in this limited clustering concerns embedding image analysis and, eventually, vision task capabilities in every artificial system. Meeting this target may require nonconventional approaches departing from the conventional strategy of full image digitization and von Neumann processing architectures. Indeed, many modern approaches are somewhat inspired by the operation of natural retinas [Roska01] [Airag20], the most efficient imaging front-ends known to date. CVISs based on the behavioral features of retinas obtain outstanding energy efficiencies and data throughputs, much better than those achieved with conventional Von-Neumann´s architectures based on number-crunching [Rodri17]. Fig. 9 illustrates major activity areas summarized in the bullet points above. ILLUSTRATING CMOS IMAGE AND VISION SENSOR ACTIVITY AREAS 1.2 Snapshots about CIS Evolution _ 21 1.2.2 Overview of CIS evolution milestones Early CISs One first relevant milestone of MOS image sensors dates from 1967, when Weckler reported an arrangement composed of p-n junctions and scanning switches in: G. Weckler, “Operation of p-n Junction Photodectors in a Photon Flux Integration Mode.” IEEE JOURNAL OF SOLIDSTATE CIRCUITS, Vol. 2, pp. 65–73, 1967. The inset at the right illustrates this early contribution, which employed pixels without embedded amplification. Hence, it is a Passive Pixel Sensor (PPS). The lack of in-pixel amplification penalizes both image quality, because noise in the readout path is not attenuated and speed as there is no gain available to boost transient behaviors. Some of the PPS´s drawbacks were overcome by the proposal of the first Active Pixel Sensor (APS) by Noble: P. J. W. Noble, “Self-Scanned Silicon Image Detector Arrays.” IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 15, pp. 202–209, April 1968. As the figure inset at the right illustrates, APSs include active devices and amplify right at the pixel, thus helping attenuate noise impact. Modern CIS pixels are of the APS type, although much more complex than Noble's initial proposal. Early CISs and indeed some modern ones were read in a process that involved: 1) the sequential selection of rows, 2) the sequential scanning of columns within each selected row. In these early devices, all columns were connected to a common line amplifier that processed voltage columns sequentially. Modern CISs customarily employ per-column amplifiers so that reading is semiparallel, as is the case for the CISs in this Thesis. CIS Exposure employs either of the following methods: • Rolling shutter, involving the simultaneous exposition of all pixels in a row and the sequential exposure of rows; • Global shutter, where all pixels are exposed simultaneously [Nakam06]. Global shutter precludes artifacts caused by objects moving across the scene during exposure. CISs conceived in this Thesis employ both exposure types and, indeed, different global shutter types to reduce errors. Overview of come major CIS evolution milestones Fig. 10 summarizes some major milestones observed during the evolution of CISs since Noble´s APS proposal. The identification of one or another milestone is a matter of opinion, and the selection of milestones in this figure does not attempt to support a theory but to illustrate a trend under a subjective view. Although Fig. 10 does not explicitly highlight the invention of the PPD, this invention by NEC researchers and the adoption of the so-called 4-T APSs, based on PPDs, was instrumental for CIS development. 4T-APSs separate the nodes where charges are accumulated, on the one hand, and where they are transformed into voltages, on the other hand. Both nodes are electrically connected by a switching transistor (transfer gate). This separation creates some challenges, but 4T-APSs are widely used today. These pixels and some variants are at the core of the CISs in his Thesis. Chapter 1 Introduction to Low Noise Image Sensors 22 REPRESENTATIVE CIS EVOLUTION MILESTONES: A SUBJECTIVE VIEW Period 1968 → 2000 As Fig. 11 illustrates, significant milestones during this period included major achievements that have already been mentioned, namely: • The invention of the pinned photodiode in 1980, and the proposal of the so-called 4T-APS. • The embedding of processing circuitry together with the photo-detectors and the evolution of the concept of camera-on-chip. SOME MAJOR MILESTONES IN THE PERIOD 1968 → 2000 1.2 Snapshots about CIS Evolution _ 23 PPD was instrumental in achieving image quality. The so-called 4-T pixel, illustrated at the bottom of Fig. 11, based on PPDs, is customarily adopted for modern CISs as it enables quality levels that were previously attainable only with CCDs. Once the image quality barrier was surmounted, CISs were practically unbeatable owing to their advantages to combine detecting and processing circuitry into a single device, thus paving the way for true sensing-processing system-on-chip implementation. Todays, CCDs are barely used for some specialized, niche applications particularly in astronomy. Period 2000 → 2007 Besides many other concurrent activities during this period, system integrators gradually transitioned from CCD-based cameras to CIS-based ones driven by SWaP and cost motivations. Semi-parallel reading and encoding of the information, through per-channel readout paths and ADCs were also maturing during this period. Interestingly enough, many camera manufacturers were reluctant to adopt these solutions owing to the risk of producing image artifacts (pattern noise) caused by mismatches among parallel amplifiers and ADC instances. These issues are there and cannot be ignored. However, they can be confronted by adopting digitally-assisted analog design methods, on-chip calibration, and error correction. Again, the potential of CISs to incorporate processing circuitry is instrumental for these solutions. SOME MAJOR MILESTONES IN THE PERIOD 2000 → 2007 Period 2008 → > 2020 Doubts, if any, regarding the wide acceptance of CISs for imaging were removed during this period, where two significant milestones are highlighted, namely: • The generalized adoption of BSI options following improvement and maturity of wafer thinning methods; • The transition towards vertically-integrated, 3D-stacked technologies for improved pixel layout and enlarged camera on-chip functionality. As highlighted in the figure, the first commercial BSI CISs and the first commercial BSI-stacked CISs were released during this period. The vast majority of future CISs will likely adopt these strategies. Indeed, CISs employ both of them in this Thesis. Concurrently to CIS progress, CVISs also experienced significant progress during this period – see Fig. 14. Particularly: Chapter 1 Introduction to Low Noise Image Sensors 24 • The first commercial fully programmable vision system-on-chip was released by ANAFOCUS company before its acquisition by Teledyne. • SONY and OMNIVISION released the first commercial DVSs. This Thesis does not deal with CVIS. However, referring to these milestones is relevant because of the vast expected impact of this technology in the forthcoming year. SOME MAJOR MILESTONES IN THE PERIOD 2008 → >2020 SOME MAJOR CVISS MILESTONES IN THE PERIOD 2008 → >2020 1.3 Noise in image sensors _ 25 1.3 NOISE IN IMAGE SENSORS A general, broad definition of circuit noise would read as follows: Any alteration of the nominal values of a circuit's voltages, currents, charges or magnetic fluxes. Of course, such a broad definition includes errors caused by parasitic components, non-linearities, leakages, and the like that are not technically noise, although in the context of CISs, sometimes we refer to them as noise as they produce artifacts in the captured images. For instance, per-column ADCs may operate at different speeds due to non-uniform reactive parasitic, and these different operation paces may result in image quality degradation. Detailed coverage of image quality metrics and noise types can be found elsewhere [EMVA21] [Kriss15] [Janes07] [Nakam06]. Roughly speaking, noise sources can be classified in two large clusters depending of the phenomena causing them: • Fixed pattern noise; • Temporal noise. Fixed Pattern Noise Fixed Pattern Noise (FPN) FPN refers to the spatial variation pixel to pixel over the array which manifest clearly as changes in the pixel outputs under uniform illumination conditions. These spatial variations can be different from chip to chip, but are the same for all images grabbing from the same chip. Errors result in different transfer functions or responsivities for each pixel and different transmittances for each channel (see Fig. 15) and have a global component equal for all pixels and readout channels and a random component due to this mismatch of device behavior. The last one generates FPN on the sensed image so that the resulting image presents spatial variations under uniform illumination. This spatial noise remains superimposed on the picture in a video sequence. Among other reasons these errors are due to: • device mismatches, • non-uniform routing, • non-uniform loading, • mismatch in the optical stack, • etc. ILLUSTRATING PIXELS AND READOUT CHANNELS NON-UNIFORMITY These and other similar phenomena are usually characterized both under illumination and in dark conditions and are described by two main parameters: • DSNU: Dark Signal Non-Uniformity. The pixel-to-pixel variation in dark conditions removing the temporal component, which is usually achieved averaging certain number of images to remove the temporal noise. • PRNU: Photon Response Non-Uniformity. It is the pixel-to-pixel variation in presence of light, and it is measured as the gain variation of the photo response from pixel to pixel. Chapter 1 Introduction to Low Noise Image Sensors 32 Then, the photon shot noise responds to this kind of process, when in average a number λ of photons arrive to the pixel during interval [0,t], it follows a Poisson distribution, where the probability of receiving n photons in the interval [0,t] is given by 𝑝𝑛(𝑡)=(𝜆∙𝑡)𝑛 𝑛! ∙𝑒−𝜆∙𝑡 (1.2) An statistical variable following a Poisson law of probability is characterized by the fact that the variance of the statistical process is equal to the average of said process. Then, in an image sensor which is integrating a photon flux during the time Tint with an average number of photons N the variance is given by 𝑉𝑎𝑟[𝑠ℎ𝑜𝑡 𝑁𝑜𝑖𝑠𝑒 𝑁]=𝑁 (1.3) The variance versus the average output signal is called the Photon Transfer Curve (PTC) [Janes07]. From the PTC the conversion gain, CG, from the collected electrons to the image sensor output can be obtained measuring the slope of this curve in the linear part. Additionally, the point the PTC curve starts decaying is considered the saturation capacity [EMVA21], the saturation can come from the photodiode, the pixel sense node or the readout channel, typically input range of readout channel is adjusted to the pixel output range to maximize dynamic range. Fig. 24 shows one example of PTC of one image sensor developed in the scope of this thesis. The curve shows the shot noise dominates in the linear part of the curve as expected, and the CG measured with this image sensor operating in this mode is CG= 4.27 DN/e-, where DN stands for digital number since the output is delivered in digital words of 16 bits in this example. PHOTON TRANSFER CURVE 1.3.4 Dark Current noise Dark current is the parameter used to quantify the amount of charge generated and accumulated in the pixel photodiode in the absence of light. This phenomenon is intrinsic to the semiconductor device, any defect in the semiconductor structure can create an energetic step in the band gap of the semiconductor, that allows a thermal generation or recombination of the free minority carriers. This effect has been modelled in the Shockley-Read-Hall (SRH) equation [Shock52]: 𝑈𝑆𝐻𝑅=𝜎𝑝𝜎𝑛𝑣𝑡ℎ𝑁𝑇(𝑛𝑝−𝑛𝑖2)2 𝜎𝑛(𝑛+𝑛𝑖𝑒𝐸𝑡−𝐸𝑖 𝑘𝑇 )+𝜎𝑛(𝑝+𝑝𝑖𝑒−𝐸𝑡−𝐸𝑖 𝑘𝑇 ) (1.4) where USHR is the net carrier generation/recombination, NT is the concentration of defect at energy level Et, Ei is the intrinsic Fermi level, 𝑣𝑡ℎ the thermal velocity of the carriers, 𝜎𝑛 and 𝜎𝑝 are the electron and hole cross section, and n and p are the number of free electrons and holes. The equation (1.4) shows that a few main conditions drive the dark current in the pixel. First, a thermal de-equilibrium must occur to generate a current. In dark conditions, after the photodiode reset, the depleted area if a diode is a typica case of non-equilibrium, because we have n=p=0, since the photodiode is depleted. Next, the current will be linear with the defect density NT. The energy level of defect Et also determine the defect activity: the closer to the intrinsic Fermi energy level Ei, the higher the probability of recombination 1.3 Noise in image sensors _ 33 between electrons from the conduction band and holes from the valance band. Finally, the Fermi level Ei will determine the n and p density and fix the filling probability of these defects. Then, the dark current generation is dependent on the process, the higher number of defects the higher dark current is generated [Carre14]. In fact, the pinned photodiode (PPD) introduced an important improvement in the dark current thanks to the reduction of defects on the photodiode surface [Teran14] , becoming a primary technology element in CMOS image sensor. New strategies are developed in order to reduce the number of defects surrounding the photodiode, as reducing the shallow trenches isolation region around the photodiode [Teran14] . SRH model has been used to identify the main root cause of the dominant contributors for the dark current of the moment during the last decades. This has successfully been used to reduce metallic contamination in the process through improved cleanliness and gettering. It has eliminated the generation of the interfaces by passivation and by process and robust design [Park10][Theuw03]. These improvements permit reducing the dark current and change the nature of the main contributors to the temperature dependence, and consequence the doubling coefficient varies from typical values of 11⁰C to 6 ⁰C for example. Fig. 25 provides a common cross-section of pixel photodiode with the possible locations where the different mechanism and root causes for dark current generation appear: 3) TX edge: diffusion from interface (Eg ); lucky drift from interface (Eg /2); interface stress (Eg ); 4) FD injection: blooming forward bias; 5) Other junction: forward bias or carrier injection; 6) STI interface: diffusion from interface (Eg ); interface stress (Eg ); 7) Pinning layer: diffusion from interface (Eg ); interface stress (Eg ); doping-based SRH (Eg ); 8) Deep depletion: SRH from contamination (Eg /2); 9) Lightly doped region: diffusion from weak SRH (Eg /2 or Eg); 10) Back interface: diffusion from weak interface SRH (Eg ); 11) Contact substrate current (Eg) DARK CURRENT MECHANISMS AND ROOT CAUSES [MCGRA17] Chapter 1 Introduction to Low Noise Image Sensors 34 The dark current is the parameter limiting the integration time of any image sensor, since the dark current has an associated noise which follows same statistical behavior as shot noise, the dark current noise stanrdar deviation is square root of the dark current average: 𝜎𝑑𝑎𝑟𝑘 𝑐𝑢𝑟𝑟𝑒𝑛𝑡=√𝜇𝑑𝑎𝑟𝑘 𝑐𝑢𝑟𝑟𝑒𝑛𝑡=√𝐼𝑑𝑎𝑟𝑘 𝑐𝑢𝑟𝑟𝑒𝑛𝑡∙𝑡𝑖𝑛𝑡 (1.5) Then, for long integration time low dark current are required along with colling systems in order to reduce the noise introduced by this phenomenon. 1.3.5 Transfer Noise Transfer noise might be often a limiting factor in the performance of low noise image sensors when the target read noise is very low, bellow 1 eRMS. In order to optimize and reduce the charge transfer noise, understanding the sources and how they can be reduced is needed for the design of low noise image sensors. Transfer noise has been analyzed extensively in CCDs [Janes01] [Omura80][Omura80]. These works obtained a model for the charge noise generated by surface trapping and detrapping while signal charge is moved from the photogate pixel to the output amplifier. This model is valid for CCDs with a large number of charge transfer stages and a large number of traps [Fossu03]. A more precise model is derived for the case of 4T CMOS image sensor [Fowle07]. In a typical 4T CMOS image sensor pixel, there are two main causes for transfer noise, the first is the incomplete charge transfer between the pinned photodiode and the floating sense node, and the second is charge trapping in the interface photodiode and transfer gate, SiSiO2 interface. Incomplete charge transfer results in variations in the thermionic emission and quantum mechanical tunneling from a potential barrier or a potential pocket between the pinned photodiode and the floating diffusion node, it has been also analyzed with the lag, since it refers to the incomplete charge transference from the photodiode to the sense node. In order to estimate the contribution from incomplete charge transfer source in 4T CMOS pixels, the average time required to empty the charge from small potential barrier or small potential pocket in the photodiode is analyzed resulting that this time is less than 1 nanosecond considering the thermionic emission is the dominant source of electron transport for a typical process. This time is much faster than typical charge transfer that should be larger than hundreds of nanoseconds. Therefore, incomplete charge transfer is not a significant source of transfer noise, as it was in CCDs. Charge trapping and detrapping at the Si-SiO2 interface is the dominant source of charge transfer noise in 4T CMOS image sensors. In addition, while the transfer gate voltage is high electrons from the floating diffusion can interact with the surface traps as well in the transfer channel. Both mechanisms enable charge trapping and or detrapping during the charge transfer. A large positive voltage can be applied to the transfer gate in order to create voltage difference and accelerate the diffusion of the accumulated charges to the sense node. But this positive voltage can attract the electrons to the Si-SiO2 interface allowing some electrons to be trapped during the transfer process. Unlike the noise introduced by the incomplete charge transfer, by lag, the variance of this fluctuation is not easy to measure and practical optimization is needed with regards the high voltage of the transfer signal in order to optimize the transfer noise ( see section 562.2.1 ). 1.3.6 Reset noise Every time a voltage is sampled in a capacitor, not only the nominal voltage level in the capacitor but also the noise coming from this voltage is integrated in the capacitor. KT/C noise stands for the noise stored in a capacitor when it is charged through a resistor. The thermal noise appears in any conductive material when the absolute temperature is higher than 0°K, as described previously. When a capacitor is charged by a resistor the noise calculation can be done using an ideal model of resistor in series with the equivalent noise voltage sources. 1.3 Noise in image sensors _ 35 RC NOISE MODEL The total power of Vo(t) is given by the integrated spectral density of power multiply by squared module of transfer function seen by Vo(t) signal as shown in equation equation (1.6) rendering in a total output power equal to kT/C. 𝑃𝑜𝑢𝑡=∫ 𝑆𝑉(𝑓)∙|𝐻(𝑓)|2𝑑𝑓 ∞ 0=∫ 4𝑘𝑇𝑅∙1 (2𝜋𝑅𝐶)2+1𝑑𝑓 ∞ 0 (1.6) 𝑃𝑜𝑢𝑡=𝑘𝑇 𝐶 (1.7) Same result is reached using the equivalent noise bandwidth, Bn, as the band width of an ideal low pass filter which produces the same integrated noise power as the actual filter or system transfer function. In the case of one pole system, the equivalent noise bandwidth is equal to π/2 times the pole frequency. 𝑃𝑜𝑢𝑡=𝑣𝑛2    ∙𝐵𝑛=4𝐾𝑇𝑅∙ 1 2𝜋𝑅𝐶 ∙ 𝜋 2=𝑘𝑇 𝐶 (1.8) When MOS switch sample a data in a capacitor the stored voltage value, the switch goes from a low value resistor, Ron, to a very high value, Roff, frozen the voltage level in the capacitor. The voltage noise sampled in the capacitor is equal to the calculated in equation (1.7), being the voltage noise equal to √𝑘𝑇 𝐶. SWITCH CAPACITORS NOISE MODEL It is the noise stored in the sense node every time the reset transistor is activated to set the reset voltage in the floating sense node. The reset noise can be reduced using soft reset, that consists of operating the reset transistor in subthreshold region [Teran16]. To perform a proper reset of the floating diffusion node the soft reset operation is preceded by a hard reset operation where the reset transistor is working in ohmic region to set the reset voltage independently on the initial value prior to the reset operation, this operation is known as hard-soft reset as depicted in Fig. 28. Chapter 1 Introduction to Low Noise Image Sensors 36 RESET OPERATION (A) HARD RESET (B) SOFT RESET (C) HARD-SOFT RESET In 4T-APS CISs working in rolling shutter operates following the next sequence: • first the reset of the floating diffusion, secondly reset level is read; • then the charge is transferred to the floating diffusion; and • finally the signal level is read. To get rid of the reset noise the correlated double sampling operation is performed subtracting the signal level from the reset level, removing totally the reset noise since the charge integration is done over the unique sampled reset (see section 1.4.3 ). However, 3T CMOS image sensors used in large pixels with large full well capacity are subjected to the reset noise and analysis and optimization is needed. The reset noise becomes out of the scope of this Thesis as if focuses low-noise 4T-APS CISs. 1.4 READOUT ARCHITECTURES IN IMAGE SENSORS The pixel signal should be adapted and digitalized through the readout channel. The readout channel could be composed by only one ADC converting the pixel reset level and signal level to perform the correlated double sampling in digital domain, which is named Digital Double Sampling (DDS). Another option, is using a CDS analog stage which can be sampling the pixel output and subtraction the reset and signal level in the analog domain prior to the digitalization. Additionally, a programmable gain amplifier (PGA) can be inserted to provide analog gain to the pixel output signal. In this section, we will consider the main device noise sources and the contribution in the two main process in the pixel output signal conditioning and conversion: sampling process and comparators. After that, column amplification is presented, and finally, the correlated double sampling operation employed in image sensors is presented. The ADC architecture developed in this Thesis is described in detail in Chapter 3. 1.4.1 Common noise source in ADCs 1.4.1.1. NOISE IN SAMPLING CAPACITORS Switched capacitors circuits are commonly used in image sensors ADCs in order to sampling the data coming from the pixels and digitalize the value after CDS operation. It is important to recognize the noise stored in the capacitors when a voltage is sampled in it. When there is only a MOS switch sampling the signal, the noise is given by equation (1.8) described in Section 1.3.6 . However when an active element like an Operational Transconductance Amplifier (OTA) is present in the signal sampling, the noise contributions and the equivalent noise bandwidth change, resulting in a different formula for this sampled noise. For exampling, in the case of the single edge common source amplifier showed in Fig. 29 the MOS switches are designed with low enough equivalent resistance, in order to ensure that the system bandwidth is given by the pole coming from the amplifier and with noise spectral density is much lower than the said amplifier. In this case, when the MOS switch passes to “OFF” state, the signal is frozen in the capacitor. The noise voltage per unit frequency at the output is given by equation (1.9). To be referred at the input of the OTA the noise is divided by the gain rendering in the result given in equation (1.10). When this OTA is used Readout Reset Readout Reset Readout Reset SEL RST SEL RST SEL RST (a) (b) (c) 1.4 Readout architectures in image sensors _ 37 in a switched capacitor circuits the input referred noise should be multiplied by the equivalent bandwidth noise when the switch and the capacitor are connected to the OTA, in this case the unit gain bandwidth (GB) is 𝑔𝑚𝑎𝑚𝑝𝑛 𝐶1 rad/s if the pole introduced by the switch resistance is far away from the dominant pole, and it has been sized to fulfill this condition. The equivalent noise bandwidth Bn=GB·π/2= GB·π/2, being the total integrated noise in the capacitor given by the expression (1.12). The total noise is a value named alpha equal to 𝛾(1+ 𝑔𝑚𝑏𝑝 𝑔𝑚𝑎𝑚𝑝𝑛), which is dependent on the technology through the parameter 𝛾 and on the design by the factor 𝑔𝑚𝑏𝑝 𝑔𝑚𝑎𝑚𝑝𝑛. SC AMPLIFIER EMBODIMENT 𝑣𝑛,𝑜𝑢𝑡 2         =4𝐾𝑇𝛾(𝑔𝑚𝑎𝑚𝑝𝑛+𝑔𝑚𝑏𝑝) (𝑔𝑑𝑠𝑎𝑚𝑝𝑛+𝑔𝑑𝑠𝑏𝑝)2 (1.9) 𝑣𝑛,𝑖𝑛 2       =𝑣𝑛,𝑜𝑢𝑡 2         𝐺𝑂𝑇𝐴2=4𝐾𝑇𝛾 (𝑔𝑚𝑎𝑚𝑝𝑛+𝑔𝑚𝑏𝑝) (𝑔𝑑𝑠𝑎𝑚𝑝𝑛+𝑔𝑑𝑠𝑏𝑝)2∙(𝑔𝑑𝑠𝑎𝑚𝑝𝑛+𝑔𝑑𝑠𝑏𝑝)2 𝑔𝑚𝑎𝑚𝑝𝑛2 𝑣𝑛,𝑖𝑛 2       =4𝐾𝑇𝛾 1 𝑔𝑚𝑎𝑚𝑝𝑛(1+ 𝑔𝑚𝑏𝑝 𝑔𝑚𝑎𝑚𝑝𝑛) (1.10) 𝑉𝑛,𝑜𝑢𝑡,𝑡𝑜𝑡 2            =4𝐾𝑇𝛾 1 𝑔𝑚𝑎𝑚𝑝𝑛(1+ 𝑔𝑚𝑏𝑝 𝑔𝑚𝑎𝑚𝑝𝑛)∙𝑔𝑚𝑎𝑚𝑝𝑛 2𝜋∙𝐶1∙𝜋 2 (1.11) 𝑉𝑛,𝑜𝑢𝑡,𝑡𝑜𝑡 2            =𝛾(1+ 𝑔𝑚𝑏𝑝 𝑔𝑚𝑎𝑚𝑝𝑛)𝐾𝑇 𝐶1 (1.12) In summary, the power noise in sampling capacitors is a factor of the kT/C noise. The larger number of transistors composing the OTA or the system, the factor of noise can be larger. Additionally, generally speaking, in order to optimize noise the amplification transistors should maximize the transconductance, while the load transistors should minimize the transconductance by increasing the overdrive voltage (VGS - VT) as much as possible. 1.4.1.2. NOISE IN COMPARATORS Many analog to digital architectures use comparators to digitalized the analog word. In particular, single slope ADC is a well-known architecture where the noise of comparators has an important contribution to the total noise. A detailed noise analysis for comparator is described in [Sepke09]. Common frequency domain noise analysis assumes that the amplifier is in steady state, but comparators do not necessarily reach steady state and add noise during their transients. Therefore, the usual assumption of wide-sense-stationary noise source is not always valid. The nonstationary noise analysis of a first order transconductance amplifier when driven by an input ramp (Fig. 30), used in single-slope ADC, is described in this section. Chapter 1 Introduction to Low Noise Image Sensors 38 INPUT RAMP IN FIRST ORDER TRANSCONDUCTANCE AMPLIFIER COMPARATOR The step ramp input and the impulse response for the transconductance amplifier are given by: 𝑣𝐼𝐷=(𝑑𝑣𝑥 𝑑𝑡)∙𝑡∙𝑢(𝑡) (1.13) ℎ(𝑡)=𝐺𝑚 𝐶𝐿∙𝑒−𝑡/𝜏𝑜∙𝑢(𝑡) (1.14) where the last one is coming from the equivalent circuit shown in Fig. 31. LINEAR SMALL SIGNAL TRANSCONDUCTANCE AMPLIFIER EQUIVALENT CIRCUIT The response of the amplifier to the step ramp input is: 𝑣𝑂𝐷(𝑡)=𝐴0𝑀𝑠𝑙𝑜𝑝𝑒[𝑡−𝜏0(1−𝑒−𝑡 𝜏0 ⁄)]𝑢(𝑡) (1.15) where 𝐴0=𝐺𝑚𝑅0 is the dc gain, 𝜏0=𝑅0𝐶𝐿 is the output time constant and 𝑀𝑠𝑙𝑜𝑝𝑒=𝑑𝑣𝑥/𝑑𝑡 is the input ramp slope. Therefore, the slope of the output of the amplifier is: 𝑑𝑣𝑂𝐷 𝑑𝑡 (𝑡)=𝐴0𝑀𝑠𝑙𝑜𝑝𝑒[1−𝑒−𝑡 𝜏0 ⁄]𝑢(𝑡) (1.16) If we consider that 𝑡≪𝜏0, then the slope simplifies to: 𝑑𝑣𝑂𝐷 𝑑𝑡 (𝑡)=𝐴0𝑀𝑠𝑙𝑜𝑝𝑒 𝑡 𝜏0𝑢(𝑡)=𝐺𝑚 𝐶𝐿×𝑀𝑠𝑙𝑜𝑝𝑒×𝑡=𝐺𝐵×𝑀𝑠𝑙𝑜𝑝𝑒×𝑡 (1.17) The impulse response from the noise current source to the output voltage is ℎ𝑛(𝑡)=1 𝐶𝐿𝑒−𝑡 𝜏0 ⁄𝑢(𝑡) (1.18) being 𝑆𝑥0 the white noise PSD of the noise process and the impulse response ℎ𝑛(𝑓) in frequency, from the noise source to the output. The output variance simplifies to 𝜎𝑦2(𝑡)=𝑆𝑥0∫|ℎ𝑛(𝑓)|2𝑑𝑓 +∞ −∞ (1.19) Vx(t) t Gm + - Vx Vin CL 1.4 Readout architectures in image sensors _ 39 Modeling the noise current PSD of the transconductance amplifier as 𝑆𝑥0=4𝑘𝑇𝐺𝑛 as the thermal noise from an equivalent noise conductance 𝐺𝑛, and substituting this value in (1.19), the noise at the output of the amplifier is: 𝑣𝑜𝑛 2      (𝑡)=(𝐺𝑛 𝐺𝑚)𝑘𝑇 𝐶𝐿(𝐺𝑚𝑅𝑜)[1−𝑒−2𝑡 𝜏0 ⁄]𝑢(𝑡) (1.20) If we consider that 𝑡≪𝜏02 ⁄, then the noise simplifies to: 𝑣𝑜𝑛 2      (𝑡)=2𝑘𝑇𝐺𝑛 𝐶𝐿2𝑡 (1.21) The jitter at the output of the amplifier can be expressed as the output noise divided by the square of the output slope at the moment of the transition, 𝑣𝑂𝐷=𝑣𝑀𝑜, then 𝜎𝑡𝑖 2(𝑡)=𝑣𝑜𝑛 2     (𝑡)|𝑑𝑣𝑂𝐷 𝑑𝑡 (𝑡)|−2𝑣𝑂𝐷=𝑣𝑀𝑜 (1.22) By using formula of the noise and slope at output of amplifier, we get the variance of the jitter: 𝜎𝑡𝑖 2(𝑡)=2𝑘𝑇(𝐺𝑛 𝐺𝑚)(1 𝐺𝑚×𝑡×𝑀𝑠𝑙𝑜𝑝𝑒2) (1.23) The response of the amplifier to the step ramp input can be approximated in second order as: 𝑣𝑂𝐷(𝑡)≈𝐴0𝑀[𝑡−𝜏0(1−(1−𝑡 𝜏0 ⁄+(𝑡 𝜏0 ⁄ )2 2))]𝑢(𝑡) (1.24) 𝑣𝑂𝐷(𝑡)≈𝐴0𝑀𝑠𝑙𝑜𝑝𝑒[𝑡2 2𝜏0]𝑢(𝑡) (1.25) We are interested for the jitter at a particular point of the transient response. Let’s call 𝑉𝑄 the threshold voltage of the gate driven by the amplifier and 𝑡𝑄 the time when the amplifier reaches such threshold 𝑉𝑄. 𝑉𝑄=𝑣𝑂𝐷(𝑡𝑄)≈𝐴0𝑀𝑠𝑙𝑜𝑝𝑒[𝑡𝑄2 2𝜏0] (1.26) 𝑡𝑄=√𝑉𝑄×2 𝐺𝐵×𝑀𝑠𝑙𝑜𝑝𝑒=√𝑉𝑄×2×𝐶𝐿 𝐺𝑚×𝑀𝑠𝑙𝑜𝑝𝑒 (1.27) Then the variance of the jitter at point (𝑡𝑄,𝑉𝑄) is: 𝜎𝑡𝑖 2(𝑡𝑄)=√2𝑘𝑇(𝐺𝑛 𝐺𝑚)( 1 (𝑉𝑄)12 ⁄×(𝐺𝑚)12 ⁄×(𝐶𝐿)12 ⁄×(𝑀𝑠𝑙𝑜𝑝𝑒)32 ⁄) (1.28) From the expression of the standard deviation of jitter 𝜎𝑡𝑖(𝑡𝑄), it can be concluded that: Chapter 1 Introduction to Low Noise Image Sensors 40 • 𝑀𝑠𝑙𝑜𝑝𝑒 has a bigger impact on jitter that any other parameters because of the power 3/2. • 𝐺𝑚 and 𝐶𝐿 have the same impact on reducing the jitter, but increasing 𝐶𝐿 also increases the delay 𝑡𝑄. • 𝐺𝑛 𝐺𝑚 can be minimized by using an amplifier with the minimum number of transistors contributing to the noise. Therefore, the amplifying transistor should have its 𝑔𝑚 maximized while the 𝑔𝑚 of the load/current source should be minimized. • 𝑉𝑄 should be also maximized. This analysis provides with a first estimation of the noise coming from the comparators. In order to obtain a precise value transient noise simulations are needed considering all the noise contributions in the conversion: the noise in the analog ramp and the noise in the comparator. 1.4.2 Column amplification The column amplifier is a commonly used and important block in the readout channel. It is the first block after the pixel output in the readout chain, it is located between the pixel and the analog-todigital conversion. Therefore, by applying analog gain at the very beginning of the readout chain, all the noise introduced by the blocks connected behind the column amplifier is attenuated by the analog gain [Schan00]. Additionally, the column level amplifier can be used to control and limit the bandwidth reducing the thermal noise introduced by the pixel source follower and pixel current source [Kryms03]. Fig. 32 shows two examples of column amplifier block based on switch capacitor amplifier. The gain is given by the ratio between capacitors C1/ C2, it renders in two gains: • High Gain: GHG= C1/C2HG, where C2HG is lower value than C1. In fact, C1 and C2 used to be composed of unitary elements, that are combined to achieve the target gain. • Low Gain: GLG= C1/C2LG, in this case C2LG is selected to achieve the unitary gain or to adapt the pixel output range to the maximum ADC input range. (a) (b) COLUMN GAIN AMPLIFIER (A) PROGRAMMABLE GAIN AMPLIFIER (B) DUAL GAIN AMPLIFIER The amplifier is reset in every readout activating the auto-zero switch. It has an important effect of reducing the low frequency noise contribution for the amplifier circuitry[Enz96]. However, using high analog gain has the drawback of limiting the maximum signal coming from the pixel which is translated into a reduction of the maximum number of electrons that can be finally converted, and then a reduction of the dynamic range. For this reason, using the combination of low gain and high gain value 1.4 Readout architectures in image sensors _ 41 for the pixel output is used to minimize noise (high gain) and maximize the saturation capacity (low gain), 0a. It means two conversions are needed, which requires extending the conversion time, and then reducing the frame rate. To overcome this issue, two conversions for high and low gain can be done in parallel, 0b, conserving the conversion time but requiring larger area and power consumption. Adaptative column gain amplifier can be used to reduce the conversion time using only one programmable gain amplifier [Sakak05]. This solution uses an additional comparator to check if the pixel output overpass certain threshold level of the signal to select the optimum gain and apply this gain to the pixel signal. A digital post processing is needed to combine the low gain and high gain components to obtain the output word with optimum noise and dynamic range. 1.4.3 Correlated double sampling The Correlated Double Sampling (CDS) operation is a common technique used in CMOS image sensor to reduce spatial (FPN) and temporal noise coming from the pixel. The CDS operation is depicted in Fig. 33, it consists of sampling the pixel output twice, the first sampling is done after resetting the floating diffusion (FD) without any charge coming from the photodiode, it is called reset level (VRST), the seco nd sampling is done after transferring all the charge from the photodiode to the floating diffusion, it is called signal level (VSIG). The time between the two samples is call CDS time, To. After that, the signal level is subtracted from the reset level reducing the noise contributions as follows: • Spatial Noise (FPN): The mismatch variation in pixel transistors like the threshold voltage in the source follower transistor generates voltage variation in the order of cents of mV of standard deviation at pixel output. With the CDS operation, this voltage mismatch is cancelled at first order eliminating the dependence from pixel transistor parameters. • Temporal Noise: The CDS operation is similar to the autozero operation, then there is a reduction to the low frequency noise components that is more efficient when To is shorter. A detailed analysis is done in section 2.3.1 . PIXEL CDS OPERATION WAVEFORMS Fig. 34 illustrates the readout column CDS circuitry. The CDS operation can be done either in the digital domain, Fig. 34a, or in the analog domain, Fig. 34b. When the CDS operation is done in the digital domain, the reset level is sampled in one capacitor, CR, the signal level is sampled in another capacitor, CS, the two analog levels are converted and the subtraction is done in the digital domain, also called Digital Double Sampling (DDS). There are multiples architectures to perform this operation [Kawah18][Kawah18], it can be done using two ADCs in parallel or the same ADC in a sequential mode, it is the case of the well know single slope ADC with up/down counter [Wei20]. When the CDS operation is done in the analog doming an specific block can precede the ADC, this block is a switched-capacitor circuit in charge of doing the subtraction in the analog domain. For the example provided in Fig. 34b the reset level, VRST, is sampled in C1 and the reference voltage is sampled in the C2 capacitor as SHR sampling phase is active. After that, SHS phase becomes active and the signal level, VSIG, is now sampled in C1 transferring charge from C1 to C2 rendering the output of CDS block as Vo=Vref-C1/C2(VSIG-VRST). The analog CDS can be implemented as well embedding the analog Chapter2 Pixel Noise Optimization 48 PIXEL OPERATION WAVEFORMS 2.1.2 Test vehicle chip architecture A chip test vehicle has been used to measure the performance of the different pixel variants. This test chip has been designed to feature low-noise readout, namely, it has a readout noise of 112 Vrms that allows obtaining low noise pixels measurements. Additionally, it allows multisampling testing when one row is selected. The test chip includes 8 variants for every type of pixel 4T/5T and one or two supplies, namely: • 4T type structure, • 4T type structure 2 supplies, • 5T type structure, • 5T type structure 2 supplies. Pixel array distribution in the test chip Fig. 39 shows the pixel array distribution and the subarrays definition. • There are 4 main columns of sub arrays for: • 4T pixel one supply, • 4T pixel two supplies, • 5T pixel one supply and • 5T pixel two supplies. • Every column consists of 8 subarrays. • Furthermore, there are two additional columns on the left and on the right that are similar to the 4T pixel one supply but with the metal covering in order to check the optical black corrections. 2.1 Test structures pixel variants and characterization results _ 49 Fig. 40 shows an image read out from the sensor chip. Note that the image includes different regions, each one coming from a corresponding subarray. PIXEL ARRAY DISTRIBUTION REAL IMAGE FROM THE TEST CHIP Chapter2 Pixel Noise Optimization 50 2.1.3 Characterization results All sub-arrays described in previous sections have been characterized regarding noise performance for the different supply combinations. As a preliminary step, the readout channel noise contributed by the ADC has been measured for an input full scale of 1.5 V. Entries labelled Channel Noise in the Tables below include this metric. This channel noise power must be removed from the total noise to obtain the pixel noise contribution. One relevant consideration regarding dark temporal noise in image sensors concern the quantitative metric employed. Fig. 41 shows a generic dark noise distribution from a typical low-noise image sensor device. Depending of metric used to provide the final value: median, mean or Root Mean Squared (RMS), the final value can change a lot. In this Thesis, all the reported values are given in RMS since it is a more realistic parameter for quality although despite providing more pessimistic estimates as Fig. 41 illustrates. READOUT NOISE DISTRIBUTION AND DARK NOISE DEFINITIONS 2.1.3.1. 4T PIXEL WITH 1METAL_1EXT OPTION Table 2 provides the performances for the 4T pixel variant with one supply and connected to external voltage supply. According to the measurement results: the pixel version v2, with a temporal noise of 1.0 e− is the best performing regarding noise. It is worth mentioning that this version has the largest source follower gate: W=0.8 m/L=0.8 m. As a counterpart, this pixel version shows significant non-linearity at the low-part of integrated signal region of the responsivity curve − see Fig. 42 (a), where images are obtained with constant illumination and sweeping exposure time. Indeed, this version has smaller responsivity than the other within that region and can hence provide worse images under these conditions despite having lower temporal noise. The Fig. 42 (b) shows the dark noise distribution that corresponds with the pixel noise histogram [Woo99] of every pixel array. Table 2. 4T PIXEL PERFORMANCES FOR THE 1METAL_1EXT OPTION v0 v1 v2 v3 v4 v5 v6 v7 Units Microlens 1 1 1 1 1 1 1 1 - H-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um V-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um FSR 1.43 1.38 1.37 1.46 1.40 1.25 1.43 1.29 V DR 79.6 79.4 82.2 79.8 77.1 75.9 79.8 79.0 dB SNRmax 40.64 40.61 40.88 41.02 40.99 40.36 40.75 40.28 dB CG 125.72 121.68 109.17 116.95 116.43 121.09 121.59 122.31 uV/eFWC 11396 11307 12573 12489 12042 10312 11782 10542 ePRNU 0.16 0.16 0.29 0.15 0.16 0.18 0.16 0.18 % DSNU 0.56 0.53 0.84 0.51 0.50 0.58 0.51 0.57 e150 147 107 149 195 199 147 144 uVrms 1.2 1.2 1.0 1.3 1.7 1.6 1.2 1.2 e118.23 118.23 118.23 118.23 118.23 118.23 118.23 118.23 uVrms 0.94 0.97 1.08 1.01 1.02 0.98 0.97 0.97 eLinearity Error 0.88 0.92 2.15 0.79 0.36 0.58 0.46 0.69 ±%FS Temporal noise (dark) Channel Noise 2.1 Test structures pixel variants and characterization results _ 51 (a) (b) 4T PIXEL WITH 1 SUPPLY (A) RESPONSIVITY AND (B) DARK NOISE DISTRIBUTION [FOWLE15][FOWLE15] Rightful comparison among pixel versions must take this non-linearity into account. To that purpose, the responsivity is linearized, and the noise from pixels with larger non-linearity is re-calculated using the gain applied to linearize the low-exposure region. Fig. 43 shows the outcome of linearization. The linearization procedure involves applying a third order polynomial fitting to obtain the approximated curve and then linearizing using a piece-wise method to apply the respective gain. mended noise values are obtained after multiplication by the gain obtained by dividing the slope of the linearized response by the slope of the actual response at low exposure. PIXEL RESPONSE LINEARIZATION Table 3 shows the recalculated noise metrics after linearization. In this table, only suitable pixel versions with low noise and good linearity are included. According with these results v2 version might be discarded at that point. However, as will be seen in posterior section further validations may be needed for final decision. Table 3. 4T PIXEL NOISE PERFORMANCES AFTER LINEARIZATION v0 v1 v2 v3 v4 v5 v6 v7 Units CG 139.32 130.91 129.35 132.75 130.67 uV/e234.81 226.96 226.74 225.59 230.42 uVrms 1.69 1.73 1.75 1.70 1.76 e217.23 212.95 213.38 211.62 216.72 uVrms 1.56 1.63 1.65 1.59 1.66 e250.69 238.17 238.41 237.62 242.17 uVrms 1.80 1.82 1.84 1.79 1.85 eTemporal noise (dark) MEAN Temporal noise (dark) MEDIAN Temporal noise (dark) RMS Chapter2 Pixel Noise Optimization 52 2.1.3.2. 4T PIXEL WITH 2METAL_1EXT OPTION Table 4 provides pixel performances for the 4T pixel variant with two supplies and connected to an external voltage supplyAll two-supplies pixel implementation showed higher compression than 1-supply ones at low exposure, as Fig. 45 illustrates. Hence, this enlarged non-linearity results in higher noise after linearization as highlighted by the data in Table 5. Table 4. 4T PIXEL PERFORMANCES FOR THE 2METAS_1EXT OPTION (a) (b) 4T PIXEL WITH 2 SUPPLIES (A) RESPONSIVITY AND (B) DARK NOISE DISTRIBUTION Table 5. 4T NOISE PERFORMANCE OF THE VALID PIXEL OPTIONS AFTER LINEARIZATION v0 v1 v2 v3 v4 v5 v6 v7 Units Microlens 1 1 1 1 1 1 1 1 - H-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um V-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um FSR 1.46 1.42 1.22 1.45 1.39 1.24 1.46 1.33 V DR 81.3 81.3 80.7 80.9 79.1 78.2 81.5 80.7 dB SNRmax 40.95 41.03 40.46 41.27 41.42 40.95 41.07 40.59 dB CG 116.36 113.80 103.64 107.56 107.10 110.12 112.57 114.34 uV/eFWC 12556 12474 11792 13468 12977 11264 13014 11599 ePRNU 0.31 0.26 0.37 0.21 0.23 0.26 0.26 0.33 % DSNU 0.85 0.73 1.02 0.65 0.67 0.78 0.75 0.97 e126 122 113 130 153 153 123 123 uVrms 1.1 1.1 1.1 1.2 1.4 1.4 1.1 1.1 e118.23 118.23 118.23 118.23 118.23 118.23 118.23 118.23 uVrms 1.02 1.04 1.14 1.10 1.10 1.07 1.05 1.03 eLinearity Error 1.55 1.31 2.28 1.46 0.71 1.05 0.96 1.10 ±%FS Temporal noise (dark) Channel Noise v0 v1 v2 v3 v4 v5 v6 v7 Units CG 141.69 132.76 141.36 124.46 125.19 127.34 134.68 136.27 uV/e336.24 281.89 962.30 238.19 287.45 294.86 292.51 326.88 uVrms 2.37 2.12 6.81 1.91 2.30 2.32 2.17 2.40 e316.45 269.61 855.85 227.05 278.42 286.51 278.04 308.68 uVrms 2.23 2.03 6.05 1.82 2.22 2.25 2.06 2.27 e355.24 293.24 1065.56 247.72 295.89 303.28 305.76 343.34 uVrms 2.51 2.21 7.54 1.99 2.36 2.38 2.27 2.52 eTemporal noise (dark) MEAN Temporal noise (dark) MEDIAN Temporal noise (dark) RMS 2.1 Test structures pixel variants and characterization results _ 53 4T PIXEL WITH 2-SUPPLIES VS 1-SUPPLY LINEARITY AT LOW INTEGRATED LIGHT LEVEL 2.1.3.3. 4T PIXEL WITH 1METAL_1BUFFER OPTION Table 6 shows the pixel performances for the one supply pixel version connected to internal buffer. These options are showing good linearity at low response for version v0, v1, v3, v6 and v7 as showed in Fig. 46. Then, noise performances do not significantly change after linearization. Table 6. 4T PIXEL PERFORMANCES FOR THE 1METAS_1BUFFER OPTION RESPONSIVITY AND DARK NOISE DISTRIBUTION FOR THE 4T PIXEL WITH ONE SUPPLY CONNECTED TO BUFFER v0 v1 v2 v3 v4 v5 v6 v7 Units Microlens 1 1 1 1 1 1 1 1 - H-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um V-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um FSR 1.37 1.31 1.28 1.39 1.33 1.23 1.41 1.22 V DR 78.2 78.0 81.8 78.4 75.2 74.3 78.7 77.3 dB SNRmax 40.66 40.65 40.69 40.96 40.87 40.51 40.88 40.20 dB CG 124.00 120.33 108.12 116.04 114.83 117.04 120.10 121.07 uV/eFWC 11063 10913 11794 11983 11612 10542 11732 10061 ePRNU 0.15 0.14 0.30 0.12 0.12 0.14 0.12 0.17 % DSNU 0.51 0.48 0.79 0.43 0.55 0.72 0.43 0.58 e169.39 166.24 103.47 167.76 232.91 239.18 163.70 165.53 uVrms 1.37 1.38 0.96 1.45 2.03 2.04 1.36 1.37 e153.90 155.83 101.97 155.69 226.64 233.09 151.73 155.14 uVrms 1.24 1.30 0.94 1.34 1.97 1.99 1.26 1.28 e182.33 175.24 105.85 177.44 239.27 245.33 173.42 174.43 uVrms 1.47 1.46 0.98 1.53 2.08 2.10 1.44 1.44 e127.74 127.74 127.74 127.74 127.74 127.74 127.74 127.74 uVrms 1.03 1.06 1.18 1.10 1.11 1.09 1.06 1.06 eLinearity Error 0.59 0.65 1.34 0.56 0.24 0.30 0.41 0.43 ±%FS Temporal noise (dark) MEAN Channel Noise Temporal noise (dark) MEDIAN Temporal noise (dark) RMS Chapter2 Pixel Noise Optimization 54 2.1.3.4. 4T PIXEL WITH 2METAL_1BUFFER_1EXT OPTION Table 7 provides the pixel performances from the option with two supplies connecting the drain of reset transistor to the internal buffer and the drain of source follower to external supply. Fig. 47 shows the responsivity and dark noise distribution for the pixel variant with two supplies connected to internal buffer and external supply. The internal voltage and the external voltage are both set to 3.3 V in these measurements. Table 7. 4T PIXEL PERFORMANCES FOR THE 2METALS_1BUFFER_1EXT OPTION RESPONSIVITY AND DARK NOISE DISTRIBUTION TO THE 4T PIXEL WITH TWO SUPPLIES CONNECTED TO BUFFER AND EXTERNAL VOLTAGE SUPPLY 2.1.3.5. 5T PIXEL WITH ANTIBLOOMING TRANSISTOR AND ONLY ONE SUPPLY Table 8 shows pixel performances for 5T pixel version with antiblooming transistor and only one supply. This version presents higher noise than 4T pixel and similar values regarding the other performance metrics. Responsivity and dark noise distribution are showed in Fig. 48, where the reference version (v0) shows early saturation due to the presence of antiblooming, for the rest of variants the saturation appear earlier than 4T pixel versions. Similar performances are compiled in Table 9 and Fig. 49, corresponding to the 5T pixel with two supplies. Based on these characterization results 5T pixels are discarded for future analysis in this chapter owing to their combined noise and non-linearity performances. v0 v1 v2 v3 v4 v5 v6 v7 Units Microlens 1 1 1 1 1 1 1 1 - H-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um V-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um FSR 1.42 1.37 1.33 1.43 1.38 1.24 1.46 1.28 V DR 78.7 78.2 80.3 78.5 75.3 74.1 79.1 77.9 dB SNRmax 41.17 41.19 41.43 41.53 41.53 40.98 41.38 40.78 dB CG 113.15 109.39 96.56 104.87 102.48 105.58 108.79 110.68 uV/eFWC 12534 12489 13798 13635 13435 11701 13382 11556 ePRNU 0.13 0.10 0.15 0.09 0.10 0.11 0.11 0.15 % DSNU 0.50 0.52 0.57 0.39 0.40 0.43 0.43 0.67 e165 168 129 170 237 243 162 163 uVrms 1.5 1.5 1.3 1.6 2.3 2.3 1.5 1.5 e150.93 156.38 123.34 157.89 229.94 236.49 150.30 151.68 uVrms 1.33 1.43 1.28 1.51 2.24 2.24 1.38 1.37 e176.40 176.93 134.39 179.00 243.60 249.57 170.76 171.76 uVrms 1.56 1.62 1.39 1.71 2.38 2.36 1.57 1.55 e127.74 127.74 127.74 127.74 127.74 127.74 127.74 127.74 uVrms 1.13 1.17 1.32 1.22 1.25 1.21 1.17 1.15 eLinearity Error 0.77 0.70 1.33 0.54 0.26 0.26 0.40 0.46 ±%FS Temporal noise (dark) MEAN Channel Noise Temporal noise (dark) MEDIAN Temporal noise (dark) RMS 2.1 Test structures pixel variants and characterization results _ 55 Table 8. 5T PIXEL PERFORMANCES FOR THE 1METAL_1EXT OPTION RESPONSIVITY AND) DARK NOISE DISTRIBUTION FOR THE 5T PIXEL WITH ONE SUPPLY CONNECTED TO EXTERNAL VOLTAGE SUPPLY Table 9. 5T PIXEL PERFORMANCES FOR THE 2METALS_1EXT OPTION v0 v1 v2 v3 v4 v5 v6 v7 Units Microlens 1 1 1 1 1 1 1 1 - H-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um V-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um FSR 0.65 1.00 0.85 0.98 0.99 1.05 1.45 1.01 V DR 69.7 73.6 75.5 73.5 71.6 71.6 76.6 73.8 dB SNRmax 38.30 39.94 39.72 39.98 39.90 40.19 41.06 40.00 dB CG 125.70 114.28 118.17 116.02 111.61 113.77 116.20 110.57 uV/eFWC 5177 8783 7151 8452 8878 9224 12440 9091 ePRNU 0.11 0.07 0.22 0.08 0.07 0.07 0.05 0.07 % DSNU 0.53 0.40 0.81 0.39 0.39 0.38 0.36 0.40 e213 210 142 208 261 275 213 206 uVrms 1.7 1.8 1.2 1.8 2.3 2.4 1.8 1.9 e120.49 120.49 120.49 120.49 120.49 120.49 120.49 120.49 uVrms 0.96 1.05 1.02 1.04 1.08 1.06 1.04 1.09 eLinearity Error 0.22 0.42 1.54 0.40 0.36 0.51 0.82 0.31 ±%FS Temporal noise (dark) Channel Noise v0 v1 v2 v3 v4 v5 v6 v7 Units Microlens 1 1 1 1 1 1 1 1 - H-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um V-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um FSR 0,83 1,15 0,97 1,12 1,13 1,13 1,48 1,08 V DR 72,4 75,1 77,0 75,1 74,8 75,1 77,6 74,8 dB SNRmax 40,17 41,12 40,92 41,33 41,38 41,28 41,86 40,91 dB CG 113,26 102,58 106,38 107,59 106,09 108,86 106,13 109,12 uVrms/eFWC 7333 11172 9155 10374 10627 10390 13966 9919 ePRNU 0,12 0,10 0,18 0,09 0,08 0,09 0,09 0,11 % DSNU 0,50 0,39 0,69 0,39 0,40 0,40 0,38 0,43 e199 201 138 195 206 198 195 197 uVrms 1,8 2,0 1,3 1,8 1,9 1,8 1,8 1,8 e128,15 128,15 128,15 128,15 128,15 128,15 128,15 128,15 uVrms 1,13 1,25 1,20 1,19 1,21 1,18 1,21 1,17 eLinearity Error 0,40 0,40 1,44 0,51 0,55 0,32 0,93 0,34 ±%FS Temporal noise (dark) Channel Noise Chapter2 Pixel Noise Optimization 56 RESPONSIVITY AND DARK NOISE DISTRIBUTION FOR THE 5T PIXEL WITH TWO SUPPLIES AND EXTERNAL VOLTAGE SUPPLY 2.2 PIXEL VOLTAGE OPTIMIZATION 2.2.1 Voltage optimization for dark noise Table 10 illustrates the empirical dependence of the pixel dark noise with the high level of the transfer gate voltage, VGON. Table 10. DARK NOISE VS 𝑽𝑮𝑶𝑵 FOR THREE TYPES OF PIXELS. Pixel type SF W/L [μm] CG [mV/e] VGON [V] Dark Noise [eRMS] Pixel 4T v0 0.42/0.65 112 3.3 1.84 3.2 1.49 3.1 1.47 Pixel 4T v1 0.42/0.8 108 3.3 1.96 3.2 1.48 3.1 1.46 Pixel 4T v2 0.8/0.8 95 3.3 1.79 3.2 1.47 3.1 1.46 Table 11 shows the pixel performances when pixel voltage adjustments are made with a twofold purpose: • to improve linearity; • to improve noise. Fig. 50 shows the responsivity and dark noise distribution. As already explained in the previous section, dark noise pixel measurements are corrected by considering that the test chip channel readout noise is temporal noise and taking into account its measured value of the which amounts to: 118 Vrms The pixel noise is obtained by subtracting this channel noise power from the measured temporal noise power. Following this procedure: the total temporal noise noise v0 has been improved up to 153.9 Vrms (Table 11) when the high level of the transfer is set to 3.1 V . 2.2 Pixel voltage optimization _ 57 Table 11. 4T PIXEL PERFORMANCES WITH TWO SUPPLIES, RESET SUPPLY 3.0 V, SF SUPPLY 3.3V AND VGON 3.1 V (a) (b) 4T PIXEL WITH RESET SUPPLY AT 3.0V, SOURCE FOLLOWER SUPPLY AT 3.3V AND VGON=3.1V: (A) RESPONSIVITY AND (B) DARK NOISE DISTRIBUTION Table 12 collects the overall noise contributions of the different multi-supplies 4T pixel options and shows the pixel noise after subtracting the measured channel power noise from the test chip readout. Table 12. 4T PIXEL NOISE v0 v1 v2 v3 v4 v5 v6 v7 Units Temporal Noise 153.91 151.11 134.15 153.60 248.86 257.57 150.57 151.28 Vrms Channel Noise 118.64 118.64 118.64 118.64 118.64 118.64 118.64 118.64 Vrms Pixel Noise 98.05 93.59 62.61 97.54 218.75 228.61 92.71 93.85 Vrms CG 112.07 108.39 95.63 103.58 102.77 104.43 107.97 108.89 Vrms Pixel Noise 0.87 0.86 0.65 0.94 2.13 2.19 0.86 0.86 ev0 v1 v2 v3 v4 v5 v6 v7 Units Microlens 1 1 1 1 1 1 1 1 - H-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um V-Pixel size 6.5 6.5 6.5 6.5 6.5 6.5 6.5 6.5 um FSR 1.48 1.42 1.45 1.37 1.23 1.10 1.39 1.36 V DR 79.7 79.5 80.7 79.0 73.9 72.6 79.3 79.1 dB SNRmax 41.38 41.24 41.90 41.25 41.11 40.74 41.14 41.09 dB CG 112.07 108.39 95.63 103.58 102.77 104.43 107.97 108.89 uV/eFWC 13215 13103 15181 13215 11967 10540 12878 12531 ePRNU 0.04 0.03 0.05 0.02 0.03 0.04 0.04 0.04 % DSNU 0.33 0.29 0.32 0.29 0.29 0.29 0.29 0.32 e153.91 151.11 134.15 153.60 248.86 257.57 150.57 151.28 uVrms 1.37 1.39 1.40 1.48 2.42 2.47 1.39 1.39 e141.13 140.84 126.81 143.64 244.63 254.07 139.72 140.99 uVrms 1.26 1.30 1.33 1.39 2.38 2.43 1.29 1.29 e164.52 158.59 139.36 161.28 253.86 262.43 158.61 159.01 uVrms 1.47 1.46 1.46 1.56 2.47 2.51 1.47 1.46 e118.64 118.64 118.64 118.64 118.64 118.64 118.64 118.64 uVrms 1.06 1.09 1.24 1.15 1.15 1.14 1.10 1.09 eLinearity Error (EMVA) 0.15 0.17 0.27 0.11 0.16 0.17 0.14 0.20 ±%FS Linearity Error (Full Scale) 0.29 0.30 0.46 0.19 0.23 0.27 0.27 0.34 ±%FS Temporal noise (dark) MEAN Channel Noise Temporal noise (dark) MEDIAN Temporal noise (dark) RMS Chapter2 Pixel Noise Optimization 64 𝒗𝒏,𝒕𝒉,𝑪𝑴𝑺 𝟐            ≈𝑴 𝑺𝑵,𝒕𝒉𝝎𝒄 𝟐 (2.45) The input referred thermal noise power of the CMS operation is given by: 𝒗𝒏,𝒕𝒉,𝑪𝑴𝑺𝒊𝒏𝒑𝒖𝒕 𝟐                  )𝒗𝒏,𝒕𝒉,𝑪𝑴𝑺 𝟐            /𝑴𝟐 (2.46) Hence, the thermal noise power is M-times smaller than the value corresponding to a simple CDS operation. 𝒗𝒏,𝒕𝒉,𝑪𝑴𝑺𝒊𝒏𝒑𝒖𝒕 𝟐                  ≈ 𝑺𝑵,𝒕𝒉𝝎𝒄 𝟐∙𝑴 (2.47) Low-frequency noise Although CMS effectively attenuates the impact of thermal noise, it is not so effective for the low frequency noise because the higher the number of samples M, the longer the time interval between reset and signal: (M·To+TG). Hence, the low frequency noise contribution increases with M and the decorrelation of low frequency noise contributions to reset and signal increases as well. This raises a trade-off concerning M selection which is also constrained by the requirement not to reduce readout speed inefficiently. The pixel test chip can be operated with non-destructive readout for multisampling technique. It has been used to measure the efficiency of multisampling technique for the pixel variants. Fig. 61 shows the noise measurement when varying the M parameter from 1 to 28, the dash line is showing the theorical dark noise if the noise contribution would be all thermal noise, and then it would be divided by M. These experimental data reveal that: Most of the pixel variants in the test chip have and optimum value of M=8. PIXEL VARIANTS WITH CMS FOR DIFFERENT M PARAMETER 2.4 MODEL EXTRAPOLATION FOR PROPOSED ADCS ARCHITECTURE This section is in blank because it is containing confidential information. 65 CHAPTER 3 3. TWO STAGES ADC FOR LOW NOISE CMOS IMAGE SENSORS ABSTRACT This chapter describes the architecture, optimization and the performances of a two-stage ADC conceived for low noise and high Dynamic Range (DR) applications. The predecessor of the presented two stage ADC has been published in [Gonza15] where the first stage consists of a sigma-delta ADC [Chae10] and the second stage is the well-known single slope ADC [Yoshi06][Toyam11]. The architecture presented in this chapter optimizes the area and noise since the sample-and-hold is removed from the readout chain, the Correlated Double Sampling (CDS) operation is embedded into the first stage of the ADC and the sigma-delta architecture optimizes the trade-off between capacitors size and input referenced noise. The power consumption of the complete readout chain including all sub-blocks is 610 µW to convert the pixel signal with a noise of 72 uVrms in a row time of 5 microseconds with 14 bits resolution in a standard 0.18 µm CMOS technology. The ADC architecture is fully flexible and can increase the ADC resolution extending the row time up to 15 and 16 bits, reducing the noise when increasing resolution. In the literature [Kwon18], several Figures of Merit (FoM) are defined to compare column ADC performances and cost. This ADC architecture presents a FoM value of 0.006 Vrms·fJ, according to the following expression: 𝐹𝑜𝑀=𝑁𝑠∙𝑃𝑜𝑤𝑒𝑟 2𝑁𝑏𝑖𝑡𝑠∙𝑓𝑠 (3.1) This FoM value is much smaller than those achieved with a typical single-sope ADC, such as the CIS in [Lim10] whose FoM is 0.041 Vrms·fJ. This chapter is organized as follows. Section 3.1 will present the motivation of this readout architecture based in two stages ADC. Section 3.2 describes the first stage of the ADC and the Section 3.3 describes the second stage of the ADC, and the Section 3.4the analog ramp generator used in the second stage of the ADC. The readout can work in non-destructive mode, delivering the data for reset level and signal level, it is described in Section 3.5. Section 3.6 shows the readout channel performances. The readout working in multisampling is described in Section 3.7, and finally. the description of the needed calibration and correction is given in Section 3.8. Chapter 3 Two stages ADC for low noise CMOS Image Sensors 66 3.1 INTRODUCTION 3.1.1 Motivation In many applications, as the speed requirements increase, the number of readout channels (each one conceptually composed of one CDS amplifier plus an ADC) needs to be increased as well. Theoretically, the achievable frame rate of a CIS linearly increases with the number of readout elements working in parallel. In fact, these can be seen as a single readout channel with effective speed boosted by the number of replicas. In practice, this parallelism can be increased as much as needed, although after the ADC the data should be serialized and send to the receiver, where it is faced another factual limitation; the data throughput, which is defined by the total number of feasible data ports by the allowable data rate throw every port. Today many CIS employ a readout element per pixel column, so that such readout element is in charge of processing the signal coming from pixels in a single column. The tradeoff between accuracy and speed of this solution can be addressed in two manners: on the one hand, high-speed CIS clearly benefit from the enhanced overall bandwidth; on the other, in high resolution application, the increase in parallelism with the consequent relaxation of the individual ADC bandwidth allows improving the accuracy of each unit element. The ability to trade power, noise and speed is intrinsic to all ADC topologies but it becomes particularly evident in the so-called integrating ADC topologies. In particular, the single-ramp ADC has been found very appropriate for CIS, with column-level readout parallelism, because the content in circuitry per columns is small, thus rendering it compatible with very low pixel pitch [Nie20] [Sukew13]. In these ADCs the number of clock cycles required to digitize with B-bit resolution is proportional to 2B. For example, in case of the well-known and extensively used single-slope ADC the 10-bit resolution would require 1024 clock cycles to obtain a single digitized data, while 4096 clock cycles are required to code 12 bits, etc., which illustrates the theoretical accuracy-speed tradeoff: solving one more bit amounts to doubling the conversion time in case of single-slope ramp ADC. However when increasing the resolution and reducing consequently the quantization noise, other noise sources should scale down in order to get actual benefit from the increment of resolution. Among these, sampling noise must also be reduced. In Switched Capacitor (SC) circuits, the natural way to achieve such a reduction consists of increasing the value of the sampling capacitor. However, sampling noise RMS value scales with square root of the capacitance, which soon requires huge capacitors to be compliant with the increment of ADC resolution. This leads to very inefficient per-column implementations, both in power consumption and area occupation, especially for very low pixel pitch. Using oversampled ADCs has been proposed In this context [Kim12]. They employ oversampling to lower the sampling noise for given capacitance. Moreover, noise-feedback techniques can be applied to reduce the quantization noise of low-resolution quantizers. This is the case for example of the traditional first-order sigma-delta ADC [Pelgr13], which may use a single-bit quantizer. Note that this topology is very simple in terms of analog content because it requires just one SC integrator besides the comparator used in the single-ramp ADC. The oversampling sigma-delta ADC architecture, depicted in Fig. 62, has been used intensively in audio, communications and instrumentation applications [Manga12] [Medei99]. This architecture takes advantage of two basic properties to reduce the quantization power noise inside the signal band and increase the in-band ADC equivalent resolution, namely: 3.1 Introduction _ 67 OVERSAMPLING ƩΔ ADC ARCHITECTURE AND BLOCK DIAGRAM 1. Oversampling: it is based on sampling the signal at higher frequency than its Nyquist frequency. The ratio between the sampling frequency and the Nyquist frequency defines the oversampling ratio, OSR=fs/(2fb), where fb is the bandwidth frequency of the signal. The oversampling implies two main advantages: • Since fs /2 is higher than fb, the components in the range [fb, fs - fb] are not folded into the signal band after the sampling process. As consequence the demands for the anti-aliasing filter at the input of the ADC are much more relaxed in the transition from the pass band to the rejection band. • In the quantization of an oversampled signal, only a part of the quantization error is in the band of the signal, and then power in the band is: 𝑃𝑄=∫ 𝑆𝐸(𝑓)𝑑𝑓= 𝑓𝑏 −𝑓𝑏∫𝛥2 12𝑓𝑠𝑑𝑓= 𝑓𝑏 −𝑓𝑏𝛥2 12𝑂𝑆𝑅 (3.2) Then the higher the oversampling ratio the lower is the quantization noise. 2. Noise shaping: with certain processing the quantization noise can be pushed to higher frequencies out of the signal band, and then it can be reduced using low-pass filtering in the digital domain. ANTI-ALIASING IN OVERSAMPLING CONVERTERS However, in image sensors readout channel the sigma-delta architecture cannot be applied directly since the pixel signal is changing from one pixel to the next pixel to be readout, and additionally the pixel readout operation needs to perform the CDS operation in order to cancel the mismatch between pixel source follower threshold voltage variation out. In fact, Incremental ADCs (IADC), see [Chen15], are suitable for image sensor readouts. IADCs are a special subclass of sigma-delta ADCs, where the operation is periodically reset using a finite memory. The IADCs are restarted in every conversion. They offer similar advantages as high accuracy, stability and low quantization noise allowing the possibility of multiplexing the signals coming from different pixels. Like the sigma-delta modulation, IADC´s operation is robust in the presence of circuit non idealities and interferences, whose effects are in essence attenuated by the number of times the input signal is sampled to get a single conversion. We call oversampling ratio OSR to such a figure. A straight-forward analysis [Rio06] shows that the sampling noise for an oversampled case equals kT/(OSR·Cs), where Cs stands for the sampling capacitor value. Note that OSR and the capacitance values are exchangeable in terms of noise. fbfs-fb xs(t) S/H fs Ʃ xs(n) H(z) DAC Bfb OSR Y(n) Yf(n) Yd(n) BN Decimation Digital filter Down sampling Modulator ƩΔ anti-aliasing filter - fbfs fs/2-fsfs-fb Anti-aliasing filter Chapter 3 Two stages ADC for low noise CMOS Image Sensors 68 For fully exploiting the benefits of the reduced sampling noise (brought through a high M instead of a large capacitor), it is clear that noise sources before the ADC must be minimized, which is not always achieved. For example, in [Bisia17] a CDS amplifier precedes the sigma-delta ADC, or in [Gonza15] whose ADC is composed by a oversampled ADC and it is preceded by two Sample-and-Hold (SH) circuits, one to sample the reset level and another to sample the signal level as shown in Fig. 64. As highlighted through the noise metrics included in the figure, the noise contribution from the previous stages may mask the benefits of the sigma-delta topology, unless huge capacitor are used in the CDS block frontend. ADC ARCHITECTURE COMPOSE OF 1ST STAGE SIGMA-DELTA PRECEDED BY SAMPLE-AND-HOLD A possible solution consists in removing the analog CDS block, replacing it by a digital subtraction section 1.4.3 This consist of performing individual conversions of the pixel reset and signal levels, by using the per-column ADC and, once in the digital domain, subtracting them from each other to get the video signal [Chen18]. In combination with oversampled sigma-delta techniques, this kind of digital CDS brings two clear advantages: • on the one hand, sampling noise is determined by the product M·Cs rather than by the sampling capacitance itself; • on the other, whatever noise source preceding the ADC is also oversampled, with the subsequent attenuation by M. As a drawback, in digital CDS operation the conversion noise is doubled in power but significant area and power can be saved if the analog sampling and other noises are attenuated, because small capacitors are usable. Besides that, the digital CDS has two obvious penalties: • on the one hand, it doubles the conversion time (because two conversions per pixel are actually needed); • on the other, it requires digital data storage and subtraction or doubling the through-put in case the digital CDS is decided to be done in external receiver. 3.1.2 Outline of proposed readout architecture The new technique presented in this Chapter embeds analog CDS in the IADC operation without requiring a preceding CDS block. The incremental ADC is implemented in the first stage of the = 3.1 Introduction _ 69 readout channel, as shown in Fig. 65, where the relevant noise metrics are included for comparison to Fig.3. This first stage incorporates the CDS function directly along with the oversampling function inherit to the IADC architecture. The first stage ADC generates the Most Significant Bits (MSB) of the digitized outputs and produces an analog residue which is converted by the second stage, the Single-Slope ADC (SS-ADC). Finally, the SS-ADC generates the Least Significant Bits (LSB) of the digitized pixel word. The pixel outputs digitized version including CDS video are obtained with no extra digital memory or post-processing needed, it reduces the overall power consumption and required area. TWO STAGE ADCS INCREMENTAL AND SINGLE-SLOPE WITHOUT NEITHER S&H NOR CDS BLOCKS This architecture optimizes the conversion time because it works in the so-called overlap mode, as Fig. 66 illustrates. The first ADC operates at the same time the pixel is outputting the reset and signal pixel levels, after that the analog residue coming from the first stage ADC is sampled by the second stage ADC and eventually converted into the digital domain. The conversion of the N-th data in the second ADC is performed in parallel at the same time the data N+1 is converted by the first stage ADC. This parallel operation reduces the row time to the conversion time needed by the first ADC and the pixel operation. The digital output word is composed by the combination of the two digital words coming from the two ADCs as shown in: 𝐷𝑜𝑢𝑡=𝐷1∙2𝑁2+𝐷2 (3.3) where the output of the first ADC is scaled by the number of bits of the second stage (𝑁2) powered by 2. TWO STAGE ADCS OVERLAP OPERATION data column line Pixel SF sel Prog. Current Source + Prog. Offset 1st stage ADC 2nd stage ADC 7,6,5,4 10,9 MSBs LSBs CDS Analog Buffer Residue 61.44uVrms 25.8uVrms Readout channel noise = 75.4uVrms Reset settling Signal settling Residue out SEL RST TRF 4.74usec 1st stage ADC Residue CONV2nd stage ADC 4.74usec 4.74usec On-Chip SIGNAL integrationRESET integration 4.74usec Output Word=D1·2N2+D2 Reset settling Signal settling Residue outSIGNAL integrationRESET integration Chapter 3 Two stages ADC for low noise CMOS Image Sensors 70 3.2 FIRST STAGE: INCREMENTAL ADC This work uses the first-order sigma-delta ADC topology shown in Fig. 67. It is basically composed of an integrator that each phase cycle accumulates the difference between the input signal and the feed-back signal, and a comparator that compares the integrator output with a voltage reference Vr/2. FIRST-ORDER INCREMENTAL ADC In a conventional IADC, in case the comparator output is high (1), a voltage Vr is fed back. Otherwise, if the comparator output is low (0), ground voltage is fed back. In the herein proposed architecture, the feedback signal is modified as explained below in accordance with the pixel level being processed, in order to perform the CDS and avoid any saturations. Contrary to general purpose IADCs, at the beginning of each conversion, both the integrator and the digital accumulator are reset. This reset is needed in order to cope with the high-frequency components associated to the pixel-to-pixel transitions. After the reset, during each conversion, the output of the comparator (0 or 1) is accumulated digitally, and the output code is formed of the sum of the consecutive comparator decisions. For example, given a number 4 of consecutive comparisons, possible digital outputs are: • 0000 -> digital code 0 • 1000 or 0100 or 0010 or 0001 -> digital code 1 • 1100 or 0110 or 0011 -> digital code 2 • 1110 or 0111 -> digital code 3 • 1111 -> digital code 4 which allows resolving for 5 digital levels. It follows that the number of digital levels obtained with a number of consecutive comparisons, nC, is nC +1, so that the equivalent resolution equals to N1=log2(nC +1), where N1 stands for the number of bits delivered by the first stage of the ADC. 3.2.1 Functional description The first stage implementation consists of employing signal inversion to perform the CDS operation as the sigma-delta processing is being carried out. So, the final code at the counter represents the subtraction between the two pixel levels. In particular, first the pixel reset level will be accumulated (by the integrator) a number of times and then the signal level will be accumulated the same number of times, but with inverted polarity so that actual multiple subtraction take place. Along this process, the accumulated comparator decisions will form a digital representation of the difference. In order to keep the appropriate feedback so that the integrator output remains bounded by Vr, during the processing of the reset level the DAC output is Vr when the comparator is high (0 otherwise). However, g DAC − Counter Integrator Adder Input Reset Output Comparator Vr/2 Vr Y 3.2 First stage: incremental ADC _ 71 while the negated signal level is being converted, the DAC output becomes 0 for a high comparator output and Vr for a low one. Fig. 68 shows the implementation of the first stage of the ADC (the digital counter is not shown). It consists of a SC integrator and a latched comparator. Clock phases required for operation are also included at the bottom. C1 C2 Vr − + + − Vcomp pha AND phb ph0 ph2 OTA NOT(ph2) ph0 ph1 ph2 YTo counter ph1 From pixel pha phb nC Integrations of the reset level nC Integrations of the signal level AND XOR phc phc Vcm Vzero Vzero FIRST STAGE IMPLEMENTATION The rest of section is in blank because it is containing confidential information. 3.2.2 Implementation This section is in blank because it is containing confidential information. 3.2.3 Noise Analysis Part of this section is in blank because it is containing confidential information. Table 1 shows the input referenced noise computation for different bit resolution in first stage of the ADC, and the noise contribution assuming pixel conversion gain (CG) equal to 100uV/e-. Table 1. NOISE POWER ANALYSIS VS NUMBER OF BITS Bits in 1st stage ADC Power Noise (Vrms2) Voltage noise (Vrms) Noise contribution (CG=100V/e-) in e4 4.46E-9 66.8E-6 0.67 5 2.17E-9 46.6E-6 0.47 6 1.07E-9 32.7E-6 0.33 Chapter 3 Two stages ADC for low noise CMOS Image Sensors 72 3.3 SECOND STAGE: SS-ADC Fig. 69 shows the concept of the single slope ADC in the second AD stage. Data coming from the first stage are sampled and then compared with an analog ramp reference. Initially, the analog ramp and a digital counter starts the count simultaneously, after a programmable delay. When the analog ramp reference crosses the analog input level, the comparator toggles, and the digital count is sampled in the digital register. The programmable delay allows inserting digital offset between the analog ramp and the digital count, and hence in the final digital word. Fig. 70 (a) shows the schematic design for the second stage ADC. Typical clock phase and waveforms are shown in Fig. 70 (b). SECOND STAGE ADC ARCHITECTURE. (A) SECOND STAGE ADC SCHEMATIC; (B) ASSOCIATED WAVEFORMS (a) (b) 3.3 Second stage: SS-ADC _ 73 3.3.1 Functional description There are two main operating phases in the SS-ADC: the sampling phase and the comparison phase. • During the sampling phase, the comparator is operating in close-loop, so vp node is set to the input common mode voltage (Vcmi ), and the vn node is connected to the output of the operational amplifier in a unitary gain configuration setting the common mode voltage plus the operational amplifier offset: Vcmi +VOTAoffset . At the end of the sampling phase, capacitor CSA_ADC2 stores the residue from first stage of the ADC, minus the amplifier offset. This sampling operation is including auto-zero operation improving the amplifier operation offset dependence and the low noise contribution [Enz96]. • During the comparison phase, the comparator is operating in open-loop, so CSA_ADC2 capacitor is keeping the stored charge during the sampling phase. It can be resolved that the voltage in vn and vp nodes during comparison phase are as follows: 𝑣𝑛=𝑣𝑐𝑚𝑖+𝑣𝑜𝑓𝑓 1+1 𝐴𝑂 ⁄+𝛼(𝑣𝑟𝑎𝑚𝑝𝑛−𝑣𝑑𝑎𝑡𝑎) 𝑣𝑝=𝑣𝑟𝑎𝑚𝑝𝑝 (3.4) where Vcmi is the voltage at the vp node when sampling (comparator common-mode voltage), voff is the comparator offset voltage, CP is the parasitic input capacitance at the input nodes of the comparator, vramp_p, vramp_n are the positive and negative ramp voltages and vdata is the sampled voltage stored during the phi_sa phase;  is the scale factor given by next expression: 𝛼= 𝐶𝑆𝐴𝐴𝐷𝐶2 𝐶𝑃+𝐶𝑆𝐴𝐴𝐷𝐶2 (3.5) Assuming an ideal comparator, the differential voltage at the input of the comparator can be approximated as: ∆𝑉=𝑣𝑝−𝑣𝑛=𝑣𝑑𝑎𝑡𝑎−𝑣𝑑𝑎𝑡𝑎−(𝑣𝑟𝑎𝑚𝑝𝑛−𝑣𝑟𝑎𝑚𝑝𝑝) (3.6) The sampled voltage (vdata) is always positive and stands for the information whereas the difference voltage (vramp_p - vramp_n) is linearly decreasing. Therefore, the initial output of the comparator would be a high voltage and this would change its decision to a low voltage when the difference ramp voltage would be such that ∆v≤0. The signal can be codified by using a digital counter that initializes when the analog ramp start decreasing. The bigger the number of counted cycles, the bigger the input signal is. Assume that the expressions for vramp_p and vramp_n are: 𝑣𝑟𝑎𝑚𝑝𝑝=𝑣𝑐𝑚𝑖2 𝑣𝑟𝑎𝑚𝑝𝑛=𝑣𝑚𝑖𝑛+𝑚·𝑡 𝑣𝑟𝑎𝑚𝑝𝑝∈[𝑣𝑚𝑖𝑛,𝑣𝑚𝑖𝑛+𝐹𝑆𝐴𝐷𝐶2] (3.7) where vmax corresponds to the lowest voltage programmed in the analog ramp reference, 𝑣𝑐𝑚𝑖2 is the voltage reference generated at 𝑣𝑝 node and the 𝐹𝑆𝐴𝐷𝐶2 is the input full scale range of the second stage of the ADC. Then, the expressions of vn and vp (during comparison) are: 𝑣𝑛=𝑣𝑐𝑚𝑖+𝑣𝑜𝑓𝑓 1+1 𝐴𝑂 ⁄+𝛼(𝑣𝑚𝑖𝑛+𝑚·𝑡−𝑣𝑑𝑎𝑡𝑎) 𝑣𝑝=𝑣𝑐𝑚𝑖2 (3.8) It can be deduced from previous equation, that if vcmi and vcmi2 are not equal, vp is shifted from vcmi (during sampling) to vcmi2 (in comparison), and it introduces and analog offset equal to vcmi − vcmi2. When vn reaches the vcmi2 value, the comparator will toggle. It must be ensured that the comparator works properly for this input voltage and in any case the 𝑣𝑝,𝑣𝑝 voltage do not over pass the supply and ground rail voltages. Fig. 71 shows the transient evolution of the vp and vn voltages depending of the input signal (vdata), assuming an ideal comparator (A0→∞, voff=0). The maximum and minimum values for vn will be given by: 𝑣𝑛,𝑚𝑎𝑥=𝑣𝑐𝑚𝑖+ 𝛼(𝑣𝑚𝑖𝑛+𝐹𝑆−𝑣𝑑𝑎𝑡𝑎) 𝑣𝑛,𝑚𝑖𝑛=𝑣𝑐𝑚𝑖+𝛼(𝑣𝑚𝑖𝑛−𝑣𝑑𝑎𝑡𝑎) (3.9) Chapter 3 Two stages ADC for low noise CMOS Image Sensors 80 3.6.2 Noise Table 5 and Table 6 show the noise simulation results and the noise measurements respectively, for the internal CDS readout mode. The noise simulation and calculation is very similar to the measurements validating the methodology to calculate and optimize the noise which is very important in low noise applications. Considering a conversion gain of 100uV/e the readout contribution to the total noise would be 0.72e in 14bits, 0.48 in 15 bits and 0.33 when using 16bits. Table 7 shows the simulated noise calculation for the complete readout noise when it operates in external CDS. In this case, the noise contribution from the first stage is lower since the number of integrations is the half due to the CDS operation is done externally at the digital domain. However, the final noise calculation should consider the data after CDS, and then it results in the double of power noise of one component either it is coming from the reset level or the signal level. Table 5. NOISE POWER ANALYSIS FOR COMPLETE READOUT IN INTERNAL CDS MODE Readout mode #Iter ADC1 Noise ADC2 Noise Ramp Noise Quantization Noise Readout Noise Readout Noise [bits] [Vrms] [Vrms] [Vrms] [Vrms] [Vrms] CG=100 V/e [e] 14 16 66.80 17.84 25.75 26.43 78.37 0.78 15 32 46.60 12.49 12.88 13.21 51.65 0.52 16 64 32.70 6.25 6.44 6.61 34.55 0.35 Table 6. NOISE MEASURE IN CHARACTERIZATION Readout mode #Iter Readout Noise Readout Noise [bits] [Vrms] CG=100V/e [e] 14 16 72.32 0.72 15 32 48.06 0.48 16 64 32.73 0.33 Table 7. NOISE POWER ANALYSIS FOR COMPLETE READOUT IN EXTERNAL CDS MODE Readout mode [bits] #It ADC1 Noise [VRms] ADC2 Noise [VRms] Ramp Noise [Vrms] Quan. Noise [Vrms] Readout Noise One sample [Vrms] Readout Noise After CDS [Vrms] Readout Noise CG=100V/e [e] 14 16 49.30 17.84 25.75 26.43 64.11 90.66 0.91 15 32 33.91 12.49 12.88 13.21 40.58 57.38 0.57 16 64 23.66 6.25 6.44 6.61 26.16 36.99 0.37 3.6 Readout channel performance _ 81 The readout external CDS mode has been measured working at 14 bits, the result is given in Table 8. In case, of requesting higher precision in this mode multisampling mode can be used, this mode is described in next section. Table 8. NOISE MEASURE IN CHARACTERIZATION FOR EXTERNAL CDS MODE Readout mode #Iter Readout Noise one conversion Readout Noise after CDS Total Readout Noise [bits] [Vrms] [Vrms] CG=100V/e [e] 14 16 70.5 81.4uVrms 0.81 3.7 READOUT WORKING IN CORRELATED MULTISAMPLING WITH EXTERNAL CDS The external readout CDS mode (Section 3.5) is also the basis for the multisampling mode with external CDS, this mode is also known as Non Destructive Readout (NDR). In contrast to the normal readout, when the NDR mode is performed, either the reset level or the signal level is converted and digitalized from the pixel in each conversion time. The pixel levels are converted with respect to on-chip reference. Such a reference level is sampled by automatically selection the operation mode, as described in Section 3.5.1 , where the reference is 𝑉𝑧𝑒𝑟𝑜. Basic noise estimation The operation does not overwrite the sense node of the pixel, hence either the reset level or the signal level can be read (with respect the same reference) a predefined number of times, thus providing the multiple NDR (mNDR), also known as correlated multisampling technique. Fig. 79 depicts the readout channel working in correlated multisampling mode, where after done the settling of the reset signal first stage of the ADC starts converting the first time, after that the residue is converting by the second stage of the ADC and in parallel the first stage converts the second sample of the reset, and this operation is done up to the M conversions of the reset. After that, the charge is transferred from the photodiode to the floating diffusion and the signal level starts doing the settling. Similar to the reset level, the first stage of the ADC converts the first sample, and the second sample is converted in parallel with the conversion of the residue by the second stage of the ADC, up to the M conversions of the signal. This architecture only needs M times the conversion time. This feature represents a great advantage with respect to the typical implementations that need 2∙M times the conversion time. It is possible due to the inherent parallelism introduced by the two stages ADC. External processing can be used in order to lower a part of the readout know by averaging the samples of the reset and the signal before being subtracted. In particular all wide-band noise contributions generated in the readout path including the in-pixel source follower transistor are reduced by √𝑀 in voltage (RMS) or by M in power noise. Then, after the CDS subtraction (signal minus reset), the reset kTC-noise is removed and the final noise contribution coming from white noise contributors can be estimated as: 𝑁𝑚𝑁𝐷𝑅=√2 𝑀𝑁𝑟𝑜 (3.12) where 𝑁𝑟𝑜 stands for the voltage noise introduce by the noise of all white noise contributors in the readout path when converting one component, either the reset or the signal, the factor √2 comes from the double readout required to perform the digital double sampling for reset noise removal. This expression highlights Chapter 3 Two stages ADC for low noise CMOS Image Sensors 82 the impact of the number of conversions (M) done per every pixel level. For example, with a readout noise of 𝑁𝑟𝑜=1e-, with a multisampling of M=1 the total noise would be 1.41e-, whereas with M=2, the noise is 1e- , and with M=4 it is 0.7e-. Low-frequency noise impact The above estimation for the noise in multisampling mode does not take into account the effect of lowfrequency noise components in the readout pixel path. Flicker noise (1/f) and Random Telegraph Signal noise (RTS) are generated significantly in the pixel source follower since typical the transistor size is small in order to achieve high conversion gain . The pixel source follower low frequency noise sources are sampled twice and subtracted from each other, reducing the total contribution. However, it depends on the elapsed time between the two samples, the low frequency contribution will be larger as soon as the time between the two samples is larger. It works in opposite direction with the multisampling technique, the larger multisampling factor M the longer the time between the reset sampling and the signal sampling. It renders in the result that increasing the M factor does not reduce the total noise since the white noise contribution reduction by M times averaging is compensated by the increment to the low frequency components due to the larger time between the correlated double sampling operation. READOUT IN CORRELATED MULTISAMPLING, CMS, MODE The ADC noise performance has been measured using a test row to set the input of the ADC. This test row is consisting of a row of test pixels. This test pixel is based on a source follower transistor equal to the active pixel source follower whose input and outputs has been short circuit between all test pixels. The input of the test pixel is connected to a reference and the output is connected to every column ADC. Therefore, this measurement is not including the pixel noise, since all the pixel noise contribution is averaged by all the test pixel source followers. Table 9 shows the noise measurements to every component considering a multisampling of M=1 to M=16. It can be observed, the effectiveness of multisampling is reduced along the multisampling factor M, due to the low frequency noise components are not so effectively reduced when increasing M. 3.7 Readout working in correlated multisampling with external CDS _ 83 Table 9. NOISE MEASURE IN CHARACTERIZATION FOR CORRELATED MULTISAMPLING WITH EXTERNAL CDS MODE Readout mode M Readout Noise one conversion Readout Noise after CDS Total Readout Noise [bits] [Vrms] [Vrms] CG=100V/e [e] 14 CMS 1 73.60 89.04 0.89 14 CMS 2 69.03 64.80 0.65 14 CMS 3 59.88 51.88 0.52 14 CMS 4 54.39 47.20 0.47 14 CMS 5 47.00 43.47 0.43 14 CMS 6 46.69 41.15 0.41 14 CMS 7 45.47 39.52 0.40 14 CMS 8 41.89 37.14 0.37 Chapter 3 Two stages ADC for low noise CMOS Image Sensors 84 3.8 READOUT CALIBRATION ON-CHIP This section is in blank because it is containing confidential information. 85 CHAPTER 4 4. TWO STAGES ADC EXTENSION FOR DUAL CONVERSION GAIN HDR ABSTRACT This chapter describes the extension of the two stages ADC described in the previous chapter in order to digitalize the two components coming from the dual conversion gain pixel architecture and operation. Dual conversion operation is a well-known technique implemented to increase the dynamic range over the limitation coming from either the input full scale of the ADC or the maximum voltage swing in the sense node. The dual conversion operation, described in Section 4.1.2.2, it provides two pixel data: • the low gain component and • the high gain component. The ADC architecture presented is an extension the two stated ADC to optimize the efficiency of the conversion based on the assumption of the low gain component does not need low noise conversion, since the low gain component is containing the noise contribution coming from the shot noise. The optimization consists of reducing the area, the power consumption and time needed to converts the high gain component with low ADC noise and high precision, and the low gain component with enough noise level to not affect to the total signal to noise ratio (SNR). This chapter is organized as follows. Section 4.1 presents the state-of-the-art review for high dynamic range techniques and the reason for dual conversion gain selection. Section 4.2 is presenting the dual conversion gain pixel and the pixel performances for several variants in a test chip. Finally, the Section 4.3 describes the ADC architecture used to convert the two components from the dual gain pixel, and the optimization done to perform low noise and high Full Well Capacity (FWC) with high efficiency in terms of power, area and timing. Chapter 4 Two stages ADC extension for dual conversion gain HDR 86 4.1 HIGH DYNAMIC RANGE STATE-OF-THE-ART REVIEW The native Dynamic Range (DR) of standard CMOS Image Sensors (CIS), i.e. the range captured for still images and assuming that no DR enhancement technique is employed, is around 60-65 dB, although it is dependent on the pixel size and the maximum charge the sensor can accumulate [Teled23]. However, the luminance dynamic range of the natural world is much larger; indeed, the human eye can capture this dynamic range because it can adjust its response to a wide range of light conditions. Natural scenes often span a DR of 90 dB and over. High Dynamic Range (HDR) scenes are commonplace in outdoor applications. For instance, in automotive, large dynamic range is fundamental to recognize traffic signals, pedestrians, and road signals in extreme conditions of luminescence, like when going across a tunnel or night traffic lights. Indoor applications may also involve HDR scenes; for instance, in scientific applications, it is pretty standard to have very bright areas coexisting in the same scene with dimly illuminated areas. Similar situations are encountered in machine vision applications, among many others. The dynamic range refers to the illuminance interval that sensors can adequately capture. Limitations impacting this interval on the low side and high side are, respectively: • on the low side, the minimum illuminance is limited by the dark current noise, • on the high side, the maximum illuminance is limited by the amount of charge the pixel can integrate and read out. Rigorously speaking, enhancing DR requires acting on both sides of the range. However, some compression techniques focus only on the high side, thus masking tiny contrast in the tiny illuminated regions. Several HDR technologies have been proposed to enhance CIS capabilities to capture the highlights and shadows simultaneously and thereby increase their operating illumination range. This section summarizes a qualitative overview of different HDR techniques attending to the following three main performance parameters: 1) Dark conditions performances, dark noise. 2) DR, quantified as the ratio between the maximum and minimum detectable illuminances 3) SNR, Signal to Noise Ratio: quantified as the ratio between signal and the noise along the complete illuminance range. Depending on the application, extending the dynamic attending in one, two, or the three central performances listed above might be necessary. For example, DR itself is essential for visual applications since it allows us to recognize scenes with high contrast. However, both DR and dark noise levels are relevant in scientific applications like microscopy because low illuminance conditions are applied when working with biological samples, for example. Furthermore, in applications like ground astronomy, where the same scene might include dimly illuminated pixels corresponding to Astros surrounded by high-illuminance regions, the three performances mentioned above are worth addressing to detect and visualize the relevant objects and distinguish them from the surrounding background. 4.1.1 Multiple exposures HDR methods A direct approach to DR enhancement consists of merging multiple exposures captured with standard (low dynamic range) image sensors into a single linear HDR image, which has a much larger dynamic range than a single exposure image. Fig. 80 illustrates this concept. The first image, Fig. 80 (a), corresponds to a short exposure time, and the second, Fig. 80 (b), shows the same scene but with a longer exposure time. Hence, dimly illuminated regions are better defined in the latter case at the cost of saturating the highly illuminated areas. On the contrary, the former image better represents the highly illuminated areas because the shorter exposure precludes saturation but hides details 4.1 High Dynamic Range state-of-the-art review _ 87 of the low illuminated regions. Fig. 80(c) shows the outcome of combining these two images to obtain a HDR image. Once the HDR image is merged, the number of bits needed to represent the data must increase as, roughly speaking N ~ DR/6, where N is the number of bits and DR is the dynamic range in dBs. However, this formula corresponds to a linear encoding rule that would force using many bits in the readout channel, which is impractical due to area occupation and power consumption. Hence, nonlinear encoding techniques are advisable in this scenario. Expressly, a nonlinear transformation process called tone mapping permits the conversion of composed images back to the original image format and enables the display of these composed images using the usual 8-bit displays. TONE MAPPING deals with reducing the large contrast from the real scene to the displayable range while preserving the image details and color appearance, keeping the important information to appreciate the original scene content. (a) (b) (c) HIGH DYNAMIC RANGE THROUGH MULTIPLE EXPOSURES. (A) SHOT EXPOSURE CAPTURE; (B) LONG EXPOSURE CAPTURE ; (C) TONE MAPPED COMBINED IMAGE. Several tone mapping algorithms have been developed in the last decades [Debed07][Merte07][Rober99]. They are based on the response of the image sensor along the exposure range to combine several exposure images, enhance the details, and compress the detailed information. Some contributions have also addressed incorporating tone mapping directly at the pixel level based on nonlinear light-to-time conversion [Varga14] with single exposure and tone mapping based on previous frame histogram evaluation. Chapter 4 Two stages ADC extension for dual conversion gain HDR 88 Fig. 81 represents the invert response function for two algorithms: • The one at the left was reported by Debevec in [Debed07] ; • The one at the right was reported by Robertson in [Rober99]. These graphs show that the maximum intensity is represented by the maximum displayable code, 255, and rapidly decay to compress the high levels of intensity, until it reaches almost linear behaviour for low levels of intensity. (a) (b) INVERSE CAMERA RESPONSE FUNCTION FROM :(A) DEBEVEC AND (B) ROBERTSON ALGORITHMS In [Rodri11] an algorithm is presented based in a histogram created during exposure time to determine the shape of the tone-mapping curve which is applied to create the final image as shown in Fig. 82. This algorithm is very suitable for hardware implementation in Focal Plane Processors (FPP) since it only requires a comparator, reduced local memory and small logic per pixel. The histogram adapts to the light conditions in only one frame. Therefore it is very useful for HDR real-time cameras under moderate speed changing demands on the scene. Every pixel is codified with 4-bits Histogram data plus 7-bits of the tone mapped image. HISTOGRAM AND TONE MAPPED IMAGE 4.1 High Dynamic Range state-of-the-art review _ 89 However HDR techniques based on multiple exposures are not well suited for applications where scene objects move between shots, since images with different exposures must be stored and aligned. Additional drawbacks appear when illumination conditions change between the different exposures. The main performances of this HDR technique are given in Table 1. Table 1. MAIN PERFORMANCES IN MULTIPLE EXPOSURE HDR TECHNIQUE Dark Noise Dynamic range, DR Signal to Noise ratio, SNR Dark Noise performances is given by image sensor used. The increament in the dynamic range is given by the ratio between exposure time(Tint): ∆𝐷𝑅=𝑇𝑖𝑛𝑡𝑙𝑜𝑛𝑔 𝑇𝑖𝑛𝑡𝑠ℎ𝑜𝑟𝑡 The SNR is not realy enhanced with this technique. The maximum SNR will come from the maximum photons that can be accumulate in the pixel, either in the long or short exposure For example, considering an image sensor device with 2 e-RMS of dark noise and 10 KeFWC (Full Well Capacity), the native dynamic range would be, DR = 73.98 dB. If we use the multi exposure technique to extend the dynamic range, with a exposure integration ratio of 8 the effective dynamic range would be DR = 92 dB, in case increasing to ratio 16 the dynamic range is increased in 6dB, DR = 98 dB. However, not only the signal but also the shot noise is amplified by the ratio of exposure times, and it has an effect in the SNR curve in the inflection point when the ratio change is applied the noise is amplified as well and the SNR drops abruptly. For this reasons, multi exposure with number of exposures higher than two is frequently used to extend the dynamic range with high ratios of exposures. Again, it adds even more complexity to the problem of the moving objects in the scenes during sequential integrations. SNR CURVE FOR THE MULTIEXPOSURE HDR METHOD, RATIOS 8 AND 16 4.1.2 Multiple gains HDR method As an alternative to the multi-exposure method, several authors have explored DR extension by applying other methods, such as for instance: • multiple gains techniques • logarithmic compression at pixel level, • multi-sampling pixel-level ADCs, Chapter 4 Two stages ADC extension for dual conversion gain HDR 96 Fig. 91 shows the SNR for two cases of Split photodiode case, one with a ratio of sensitivity of 8 and other with a ratio the sensitivity of 16. When the ratio is higher, the gain to recover the data is higher and the shot noise from the small photodiode becomes higher introducing higher drop in the SNR curve. SNR CURVE FOR SPLIT PHOTODIODE PIXEL 4.1.3 Logarithmic pixel Fig. 92 shows a logarithmic pixel architecture combining the 3T pixel with a standard column readout circuit. The transistor M1 works is connected in a diode configuration and hence works as a resistor. Thus, it converts the photogenerated current into a voltage vpd. Assuming operation in the weak inversion regime where the current fits an exponential function of the voltage, this resistor has a logarithmic characteristic [Enz06]. Hence, the voltage vpd is proportional to the logarithm of the drain current, and the dynamic range gets compressed in the voltage output. Indeed, this voltage must remain low enough to guarantee the M1 keeps working in the weak inversion regime, limiting its excursion. Owing to the nonlinear dependence, digital processing is needed to linearize the pixel output. Furthermore, the resistor characteristics depend on locally varying technological parameters; this feature means that sensors designed according to this principle may require dedicated techniques to correct the bidimensional Fixed Pattern Noise (FPN). Another way of producing a logarithmically compressed voltage is by using photo-diodes in the photovoltaic regime an using the open-circuit voltage to encode light intensity [Ferna24]. Either case, This method can be used in rolling shutter mode. During each row readout the pixel voltage is read through the LOGARITHMIC PIXEL 4.1 High Dynamic Range state-of-the-art review _ 97 Logarithmic compression enlarges the number of photons the pixel can absorbed before saturation, achieving values larger than 120 dB. One drawback of this technique is high read noise due to 3T architecture. The fixed pattern noise is also much higher than standard 3T or 4T CIS due to sub-threshold transistor operation M1, generating non-linear variations from pixel to pixel, limiting this architecture to monochrome applications. Table 6 summarizes the primary performance of this HDR technique Table 6. MAIN PERFORMANCES IN LOGARITHMIC PIXEL HDR TECHNIQUE Dark Noise Dynamic range, DR Signal to Noise ratio, SNR Dark Noise performances is poor since it is similar to 3T pixel including reset noise (kTC) as major contributor. The increament in the dynamic range is given by maximum photocurrent can be integrated before saturating and the minimum photocurrent equivalent to read noise, 𝑣𝑛. K stands for M1 subthreshold efficiency. ∆𝐷𝑅=𝑖𝑚𝑎𝑥 𝑖𝑚𝑖𝑙 =𝑒(𝑣𝑑𝑑−𝑣𝑡ℎ)𝐾/𝑣𝑡ℎ 𝑒(𝑣𝑑𝑑−𝑣𝑛)𝐾/𝑣𝑡ℎ The SNR maximum will come from the maximum photocurrent that can be absorved before reaching saturation, imax.The shape of the SNR is given by the graph bellow, it shows is almost plain for higher values. Fig. 93 illustrates the SNR for the logarithmic pixel where it is showed that for the higher part of the SNR curve is almost flat, since the major part of the reconverted photons are drained to the supply through the M1 transistor in subthreshold state. SNR CURVE FOR LOGARITHMIC PIXEL 4.1.3.1. HDR BY ADJUSTING WELL CAPACITY The well-capacity adjustment technique consists of adjusting the equivalent capacity of the floating diffusion node through a lateral overflow charge path that drains charge in excess in that node, thus precluding voltage saturation [Yang99b] [Decke98]. This lateral overflow charge path can be implemented by using the reset transistor and adequately controlling the voltage at the reset transistor gate terminal – node RST in Fig. 94 . The voltage applied at this gate terminal determines the well-capacity. During the integration, the well- Chapter 4 Two stages ADC extension for dual conversion gain HDR 98 capacity is changed using this control voltage to drain the excess photogenerated charge via this overflow gate, clipping the collected charge to that level. After some time, the well capacity is increased, the voltage is moved down, and the photodiode can now integrate more charge into the memory node. M2 gate voltage establishes a potential barrier to the electron flow. When photo-charge are accumulating on the sense node, the charge level rises and if the charge level exceeds the barrier level, the extra charge flows to the drain. The dynamic range is increased by moving down the reset gate voltage over the integration period, as shown in Fig. 95. For low illumination, the integrated charge is unaltered by the barrier when decreasing VR, and then the pixel collects all the photo charges in the sense node. For high illumination, photo-charges go into the sense node and exceed the barrier going to the M2 drain during the time intervals defined by the time instants involved in the algorithm, namely: [ t0 , t1, ]; [t1 , t2]; etc. PIXEL SCHEMATICS The final integrated charge is reduced between the dashed and solid line. As illumination increases, a greater proportion of the photocurrent is drained to the supply. Depending on the defined steps of VRST and timing, any arbitrary compression characteristic can be achieved, generating the pixel voltage showed in Fig. 96. GATE VOLTAGE WAVEFORM AND CHARGE INTEGRATION CURVES FOR LOW AND HIGH ILLUMINATION The well adjusting HDR technique extends the dynamic range of the pixel creating a compression nonlinear pixel response, consisting in a piece-wise curve due to the mechanism of draining charge due to the moving barrier creates through the lateral overflow transistor achieving values larger than 100 dB. One pro 4.1 High Dynamic Range state-of-the-art review _ 99 of this technique is the straight forward implementation and compatibility with classical pixel control and response. Counters include high read noise since the charge is integrated in the sense node. Besides, FPN may be larger than typical 4T transistor since variations in lateral overflow transistor may change the compression curve from pixel to pixel. Fig. 96 shows the main performances of this HDR technique. Fig. 97 shows the SNR the well adjustment technique, where the SNR drops in the inflexion points as consequence of draining the charge. PIXEL OUTPUT RESPONSE Table 7. MAIN PERFORMANCES IN WELL ADJUSTING HDR TECHNIQUE Dark Noise Dynamica range, DR Signal to Noise ratio, SNR Dark Noise performances is poor since it is similar to 3T pixel including reset noise (kTC) as major contributor. The increament in the dynamic range is given by maximum photocurrent can be integrated when applying the well adjustment and the maximum photocurrent in linear standard mode. ∆𝐷𝑅=𝐼𝐿max(𝑤𝑎) 𝐼𝐿max(𝑙𝑖𝑛) The SNR maximum will come from the maximum photocurrent that can be absorved in linear mode. As the charge is drained when exceeds the barrier the SNR drops in the inflexion points. SNR CURVE FOR WELL ADJUSTMENT TECHNIQUE Chapter 4 Two stages ADC extension for dual conversion gain HDR 100 4.1.4 Techniques based on per-pixel ADCs 4.1.4.1. MULTIPLE SAMPLED PIXEL LEVEL ADC This architecture combines a photodiode with a Sample and Hold (S&H) plus ADC that converts every sample during the integration. As example, a single-slope ADC at pixel and a simple digital readout circuit at column level, as showed in Fig. 98(a). The signal vramp is the reference for the ADC which is shared between pixels. The sensor can be readout several times during each integration period if the frame rate is low enough. This allows the true correlated double sampled and the extension of dynamic range [Totsu16] [Yang99a]. Fig. 98(b) shows an example of the sensor’s response with multiple sampling and exponential increasing exposure times: T, 2T, 4T …2KT. Each sample pixel output is digitized to m bits, and then these values are combined to generate m+k number with higher resolution, and then extension of dynamic range. (a) (b) MULTIPLE SAMPLED PIXEL LEVEL ADC PIXEL This architecture requires a significant amount of memory and digital signal processing to produce HDR image data. In addition, it should store all the frames captured during an integration period and perform pixel by pixel processing to minimize noise and maximize DR. Pros of this architecture include: • the possibility to increase dynamic range over 100 dB, • the peaks in the SNR is small and • the linearity is good. Counters include high cost, large pixel required and high power consumption. Table 8 summarizes main features of this technique. Fig. 99 shows the SNR of multiple sampled pixel technique, where the SNR drops every time the exposure time is multiplied by w (two). Table 8. MAIN PERFORMANCES IN MULTIPLE SAMPLED PIXEL HDR TECHNIQUE Dark Noise Dynamica range, DR Signal to Noise ratio, SNR Dark Noise performances may be poor since reset noise (kTC) is included. The increament in the dynamic range is given by ratio between the maximum exposure time and the minimum (standard) one. ∆𝐷𝑅=2𝐾 The SNR maximum will come from the maximum photocurrent that can be absorved in every conversion. 4.1 High Dynamic Range state-of-the-art review _ 101 SNR CURVE FOR MULTIPLE SAMPLED PIXEL LEVEL ADC 4.1.4.2. PIXEL LEVEL SIGMA DELTA ADC The sigma delta ADC per pixel with residue readout through source follower is a HDR architecture that combines a sigma delta ADC with a source follower output within the pixel and a mixed mode analog and digital column readout circuit. It is a case of multiple sampled pixel level, where the pixel is converted at the same time it is sampled. The column readout circuitry processes the source follower analog signal output and the digital output for the digitalization and readout of the one bit pixel memory. Fig. 100 shows the schematic of the sigma delta ADC pixel with residue readout in pixel. The pixel charge is integrated from the photodiode on to Cfb using a Capacitive Trans-Impedance Amplifier (CTIA). Then the output integrated voltage surpass the threshold vmax the comparator toggles and it is latched by the 1 bit memory with the clock clk rising edge. Additionally, when the memory output is 1, charge is dumped into Cfb from Cdump forcing the output of CTIA to fall. Clk is a global signal for all pixels, storing one bit every time this operation occurs. The pixels are read out multiple times during each integration period. During each readout, except the last one, only the digital memory is read out. In the final readout, the digital output and analog output from source follower are read out. The number of ones that are readout out during one integration time is equivalent to FWC·Nones charges that was collected by the photodiode. The voltage at the output of the SF is the residue that is less than the FWC of the pixel. This architecture requires digital memory per pixel to hold all of the binary digital pixel outputs during one integration period, and it also requires digital signal processing of data to create the final image data and correct offset and gain. SIGMA DELTA ADC WITH RESIDUE READOUT IN PIXEL Chapter 4 Two stages ADC extension for dual conversion gain HDR 102 This implementation allows capturing data in a global shutter mode. At the beginning of each frame all of the charge integrators in the array are reset in parallel by activating RST1 switch. Every clock period one binary image is coming from the array, and after N-1 binary images the final binary image along with the analog residue is readout. Pros of this architecture are high dynamic range higher than 100 dB, excellent linearity, large photocurrent can be integrated, and SNR increases monotonically as photocurrent increases. The disadvantages of this architecture include: large pixel size, low fill factor (although it can be relaxed using 3D stacking technology [Kagaw19]) and poor low light performance due to the lack of true CDS and high-power consumption. Main performances and SNR curve are similar to the multiple samples pixel since same HDR technique is used. 4.1.5 Time to saturation pixel The time to saturation pixel with residue readout is a combination of a time to saturation pixel with two source followers: • one for time to saturation digitalization ; • another for the residue readout digitalized with an analog column readout circuit. The column circuitry is processing the data from the two source followers, and then digitized and combined into the final high dynamic range pixel data. Fig. 101 shows the schematic of time to saturation pixel with residue readout. The pixel integrates directly the charge into the floating diffusion node, when the voltage goes bellow a threshold vmin the comparator toggles and the voltage on the ramp signal vramp is stored on a sampling capacitor. Then the saturation time and voltage on the photodiode are readout, and the two values should be combined digitally to create the HDR output data. The time to saturation data can be collected in global shutter mode, but the residue readout should be done in rolling shutter mode. The vramp signal is rising from the beginning of the exposure time and reaches the maximum value at the end of the exposure time. TIME TO SATURATION PIXEL WITH RESIDUE READOUT The dynamic range is increased by the ratio between the integration time, Tint, and the uncertainty in the saturation time, σsat. σsat is the standard deviation of the time introduce by the noise introduced by the comparator, the ramp generator and the rest of the readout circuitry. One pro of this architecture is the very high dynamic range, greater than 150 dB. Counters include: • high power dissipation, • large pixel and low fill-factor, • the SNR falls at high illumination levels, and • not good low light performances. 4.1 High Dynamic Range state-of-the-art review _ 103 Table 9 overviews main features of this HDR technique Table 9. MAIN PERFORMANCES IN TIME TO SATURATION PIXEL HDR TECHNIQUE Dark Noise Dynamica range, DR Signal to Noise ratio, SNR Dark Noise performances may be poor since reset noise (kTC) is included. The increament in the dynamic range is given by ratio between the integration time and the uncertainty in the saturation time. ∆𝐷𝑅=𝑇𝑖𝑛𝑡 𝜎𝑠𝑎𝑡 The SNR maximum will come from the maximum FWC of the photodiode, considering defined by vmin voltage. After that, the SNR starts slowly decaying due to the uncertainty in the saturation time Fig. 102 shows the SNR of time to saturation pixel technique. In this technique, there are two differentiated parts: one where the data is coming from the source follower M3, and the second where the data is coming from the saturation comparator circuitry. The first part the SNR is equivalent to standard 3T pixel. In the second part, the SNR does not increase since the number of electrons in the pixel is always the same and the related shot noise, however the SNR starts decaying due to the uncertainty in the saturation time that, when it is translated in electrons, the noise increase with the light intensity. SNR CURVE FOR TIME TO SATURATION PIXEL 4.1.6 HDR techniques comparative Table 10 shows the summary of all HDR techniques commented in this section, where it is shown the increment of dynamic range along with the main limitation in the signal to noise ratio. Table 10. HDR TECHNIQUES COMPARATIVE TABLE HDR technique ∆𝑫𝑹 SNR Comments Multiple exposure 𝑇𝑖𝑛𝑡𝑙𝑜𝑛𝑔 𝑇𝑖𝑛𝑡𝑠ℎ𝑜𝑟𝑡 Limited by pixel FWC Complexity when objects are moving in the scene Multiple gain Dual gain column amplifier 𝜎𝑑𝑎𝑟𝑘_𝑙𝑜𝑤𝑔𝑎𝑖𝑛 𝜎𝑑𝑎𝑟𝑘_ℎ𝑖𝑔ℎ𝑔𝑎𝑖𝑛 Limited by pixel FWC Dynamic range increased by reducing the dark noise with high gain Chapter 4 Two stages ADC extension for dual conversion gain HDR 104 Multiple gain Dual conversion gain 𝐶𝐺𝑙𝑜𝑤𝑔𝑎𝑖𝑛 𝐶𝐺ℎ𝑖𝑔ℎ𝑔𝑎𝑖𝑛 Limited by pixel photodiode FWC Dynamic range increased by reducing the dark noise with high gain and increasing FWC limited by voltage range in the sense node Multiple gain Dual conversion gain with LOFIC 𝐹𝑊𝐶𝐶𝑆𝑙𝑜𝑤_𝑔𝑎𝑖𝑛 𝐹𝑊𝐶ℎ𝑖𝑔ℎ_𝑔𝑎𝑖𝑛 Limited by range in sense node in low gain. Dynamic range is not limiting by the photodiode, it is limited by range in sense node in low conversion gain Multiple gain Split photodiode 𝑠𝑒𝑛𝑠𝑖𝑡𝑖𝑣𝑖𝑡𝑦𝑙𝑎𝑟𝑔𝑒 𝑠𝑒𝑛𝑠𝑖𝑡𝑖𝑣𝑖𝑡𝑦𝑠𝑚𝑎𝑙𝑙 Limited by pixel FWC from larger photodiode Dynamic range is increased by the ratio between small and large photodiode Logarithmic pixel 𝑖𝑚𝑎𝑥 𝑖𝑚𝑖𝑙 =𝑒(𝑣𝑑𝑑−𝑣𝑡ℎ)𝐾/𝑣𝑡ℎ 𝑒(𝑣𝑑𝑑−𝑣𝑛)𝐾/𝑣𝑡ℎ Limited by threshold voltage in diode transistor Dynamic range is limited by the threshold voltage in diode transistor. Non linear function in the response. Well capacity adjustment 𝐼𝐿max(𝑤𝑎) 𝐼𝐿max(𝑙𝑖𝑛) Limited by pixel FWC Full well is changed during integration time . Multiple sampled pixel level ADC 2𝐾 Limited by pixel FWC Multiple sampled pixel allows to have several integrations values. Pixel level sigma delta ADC 2𝐾 Limited by pixel FWC Multiple sampled pixel allows to have several integrations values. Time to saturation pixel 𝑇𝑖𝑛𝑡 𝜎𝑠𝑎𝑡 Limited by pixel FWC The time to saturation is converted along with the nominal output. Based on this comparative analysis, the dual conversion gain technique was selected for implementation because: • the target dynamic range is between 95 dB and 100 dB and for this level there is not limitation in the photodiode, considering the pixel pitch 10um. • the dual conversion gain allows achieving high level of SNR which is also important for scientific and astronomy applications. 4.2 PIXEL ARCHITECTURE As said above, the pixel photodiode will not represent an obstacle to achieve 100 KeFWC and a dynamic range of 100 dB when the readout channel is presenting 1 electron noise. A test chip has been designed to validate the design methods, test and optimize the several flavors of the pixel and then obtain the optimum sizzing for the devices inside the pixel along with the optimization of the process in order to minimize the noise and extend the maximum capacity over the 100 Ke-. 4.2.1 Pixel schematics and waveforms Fig. 103 shows the pixel and Fig. 104 shows the corresponding waveforms. Operation is according to the sequence listed in the numbered points below. 1) First, the signals RST, TX and GAIN are activated to remove all the charge from the photodiode (photodiode reset) and to set the reset level in A and B node, it is in CFD and CS capacitors. 2) After that, the exposure starts with the falling edge of the TX signal. From that moment on, all the photons that are collected in the photodiode are stored as electron charges. 4.2 Pixel architecture _ 105 3) Just before the readout operation, the RST and GAIN signals are activated in order to sample the reset voltage in CFD and CS capacitors. DUAL CONVERSION GAIN PIXEL IN THIS WORK DUAL CONVERSION PIXEL WAVEFORMS 4) The readout operation starts activating the SEL transistor that connect the pixel output to the column readout. The readout operation is at follows: a. The reset stored in the node A+B, CFD + CS. This is the reset level related to the low conversion gain (LGC RST) b. After that, the RST signal goes down and the reset level stored in the floating diffusion is read. This level of reset is related to the high conversion gain (HCG RST). c. Once the two levels of reset have been read, the transfer pulse (TX) is applied and the photoelectron charge is stored in the CFD. Now, the signal level related to the high gain is stored (HCG SIG). When applying correlated double sampled technique, the reset noise sampled in the floating diffusion is subtracted and the concerned noise is totally eliminated. In this way, the pixel signal readout of high gain is also low noise as a typical 4T approach. IN GAIN RST TG SEL RST_LG RST_HG SIG_HG SIG_LG Baja iluminación Alta iluminación ReadOut Exposure RST GAIN CS CFD 112 113 CHAPTER 5 5. LOW NOISE CISS WITH OPTIMIZED PIXELS,,DUAL GAIN AND OVERSAMPLED ADCS ABSTRACT This chapter describes two CMOS image sensor chips that demonstrate the architectures and methods described in previous Thesis´s chapters. Besides, these chips have reached industrial maturity up to TRL 9 following several prototype fabrication re-spins. The first of these chips embeds two primary contributions of the Thesis, namely • A low noise pixel; • A two-stage oversampled ADC. Pixels and ADCs fit the architectures and methods described in Chapter 2 and Chapter 3, respectively. As explained in the former of these chapters, the pixel includes two supplies for enhanced noise response. Associated voltage drivers of these voltages are compatible with the procedures described in that chapter regarding linearity and noise optimization. Of course, the design of the complete sensor chip raises problems that go far beyond the reach of these previous chapter materials. Indeed, several challenges have been faced during sensor implementation, like the glow effect that limits the dark current at low temperatures and the row temporal noise that should remain much lower than the bidimensional temporal noise to avoid being visible, among others described in this chapter. The second of these chips is a large-format low-noise device that employs the dual conversion gain pixel optimization presented in Chapter 4. This image sensor incorporated the ADC described in Chapter 3 plus the modification described in Chapter 4 to feature a high dynamic range while keeping area and power demands contained. Implementation of this sensor chip faced several challenges related to yield and wafer-scale integration. This chapter is organized as follows. Section 5.1 describes the sensor specifications and main features. Section 5.1.2 shows the sensor architecture with all the main building blocks that allows to obtain the data from the pixel to the output image interface. Section 5.1.3 describes the sensor operation modes where the internal and external correlated double sampled is described along with multisampling operation, along with additional functionalities like windowing. The sensor performances and characterization are described in sections from 5.1.4 to 5.1.8 . The glow effect and how to optimize image sensor against this effect is described in section 5.1.9 . Section 1.1 is presenting the other development consisting of large format low noise and high dynamic range image sensor. Section Fig. 142 describes the sensor architecture with the basic blocks and the techniques used in large die implementation. Section 5.2.2 shows the operation modes available in this large image sensor followed by the functions in section 5.2.3 . Yield special techniques used in this large die are described in section 5.2.4 . Optical performances of the sensor are given in section 5.2.5 . The sensor has been incorporated in active cooling camera described in section 0. Finally, a low noise image sensor bench mark comparison is showed in section 0. Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 114 5.1 LOW NOISE SENSOR WITH 5.3 MPIXEL AND 0.7ERMS DARK NOISE 5.1.1 General description From now on, we will refer to this CIS by the acronym: ULN5.3: Ultra Low Noise CIS - version 5.3 Table 14 shows the primary features of ULNS5.3. It is fabricated in Tower-Semi 180 nm CIS technology [Tower], where the pixel has been optimized for noise and linearity following the semi-empirical approach in Chapter 2. This technology is well suited for machine vision, instrumentation, and scientific applications. Table 14. ULN5.3 SENSOR PERFORMANCES Parameter Value Pixel number [pixels2] 2,304 x 2,304 Pixel size [µm2] 6.5 x 6.5 Pixel structure 4T Shutter types Rolling and Global Row conversion time (TROW) [µsec.] ≥ 4.9 Multi ROI readout function Yes ADC resolution [bits] 14,15 and 16. Output interface 32 + 4 LVDS ports @ 544Mbps Full well capacity [103 x electrons] Standard mode 15 Extended full-well mode ≥ 30 Max. frame-rate [fps] (corresponds to TROW = 5µsec) At full-res. (2,304x 2,304) 88 At ROI of 2,304 x 2,048 100 Dark fixed pattern noise [%FS] VFPN 0.001 HFPN 0.001 Bright field pattern noise [%] VFPN < 0.2 HFPN < 0.2 Temporal Readout noise in rolling shutter mode. [erms] 14 bits TROW ≥ 4.9µsec ≤ 1.3 16 bits TROW ≥ 20µsec ≤ 0.9 14bits M=16 TROW ≥ 80µsec ≤ 0.7 Temporal Readout noise in global shutter mode with external true-CDS [erms. @ TROW ≥ 5µsec] < 3.0 Dynamic Range (14b/16b/ 14b M=16) [dB] 81.24/84.44/86.6 Dark current [e-/pixel/sec @ 25 degree C] 15 Linearity [%] < ±1 PRNU [% rms.] < 1 Quantum Efficiency [%] for frontside illuminated (FSI) process @400nm > 65 @500nm - 600nm ≥ 75 Peak @550nm 79 @700nm ≥ 65 @800nm ≥ 44 Operating Consumption [W] < 3.4 Image lag [%] < 0.01 5.1 Low noise sensor with 5.3 Mpixel and 0.7erms dark noise _ 115 ULN5.3 is a single-chip, fully digital image sensor with: 5.3M pixels working at a maximum speed of 88 frames per second at full resolution ULN5.3 incorporates several functions on-chip, such as: • programmable exposure time, • rolling and global shutter operation, • windowing and flipping. All these functions are programmable via a four-wire Serial Peripheral Interface (SPI) standard interface. ULN5.3´s readout channel incorporates the column-parallel two stages ADC architecture with multiple resolutions described in Chapter 3. The sensor is optimized for applications requiring very low noise; it can provide sub-electron temporal noise at full speed in rolling shutter modes and 2.5-electron temporal noise working in global shutter mode. The noise data in Table 14 correspond to the readout noise performance based on the programming readout mode. ULN5.3 output interface is based on 32 Low Voltage Differential Signal (LVDS) data ports. Four extra LVDS ports are used for outputting recovery clock and synchronization data in parallel. Architectural and physical design is made for compatibility with: • Front Side Illumination (FSI) sensor implementation. • Back Side Illumination (BSI). Fig. 108 shows the main differences between the illumination options at the conceptual level. In the FSI device the incoming light go throw the metals up to reach the silicon surface and enters into the photodiode sensitive area, while in the BSI device the light is coming directly to the silicon surface to enter in the photodiode. The back side illuminated version is obtained from the same wafer where the FSI device is fabricated. The first step to obtain the BSI sensor is to bond the device wafer to a support wafer that can be made by glass or silicon onto the top surface of the sensor wafer. Then, a back thinning process is realized to reduce wafer thickness to a value that ranges in the [4m, 10m] interval. After that, the PADs are created onto the original bond pads and they are interconnected using through silicon vias. To do the throw silicon vias, the remaining [4m, 10m] are etched in the via region and then covered with metal. Finally, additional process like metal grid deposition, color filters array and micro-lens deposition should be done. To make a design compatible FSI and BSI there should be some rules to be met as for example the distance between PADs should be larger than 150 m in the current technology. FSI AND BSI IMAGE SENSOR CONCEPTS Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 116 Fig. 109 shows the micro-photographs of ULN5.3 FSI and ULN5.3 BSI, respectively. (a) (b) PHOTO OF ULN5.3 FSI (A) AND ULN5.3 BSI (B) BSI technology has the advantage of providing better quantum efficiency and fill factor, since there are no metals blocking the light. Additionally other advantages of BSI is the sensitivity to UV waveforms can be much more higher since these energetic waveforms are recombined very close to the surface and then out of the silicon region in FSI devices. Fig. 110 shows the quantum efficiency of the ULN5.3 device, considering the fill factor of the pixel and the quantum efficiency of silicon. It is observed a much better QE for BSI sensor and how for the UV waveforms, from 10 nm to 40 0nm, the version BSI without glass lid has a good sensitivity. When using glass lid the crystal glass lid is absorbing bellow 350nm wavelength. QUANTUM EFFICIENCY OF ULN5.3 IMAGE SENSOR FSI, BSI AND BSI WITHOUT GLASS LID 5.1 Low noise sensor with 5.3 Mpixel and 0.7erms dark noise _ 117 ULN5.3 CIS is totally programmable using SPI interface. The device is designed to support different trigger modes by programming. • Continuous Frame (CF) mode started either internally (by a START command) or with external trigger, • Single-edged type Single Frame mode started with external trigger, and • PWC type Single Frame mode started with external trigger • External synchronous readout trigger mode. • Global reset single edged type Single Frame mode with external trigger, and • Global reset PWC type Single Frame mode with external trigger Other features is configurable Region of Interest (RoI). In the sensor can be configured up to 4 RoIs. The vertical row direction can be programmed. Additionally, the row time, also known as interval time can be programmed as well increasing the minimum one given in previous table. 5.1.2 Sensor Architecture Fig. 111-top shows the ULN5.3 block diagram and highlights the on-chip integration of multiple functions to support system autonomy and reduce the hardware needed for camera implementation, according to the very concept of camera-on-chip [Fossu97]. Particularly, functions needed to acquire images, read and digitize them, correct errors and transmit digital images are all on-chip. The schematics at the bottom in Fig. 111 shows the concept of the Active Pixel Sensor (APS) used in this CIS chip. The ULN5.3 circuitry divides into five sections: Pixel array, Readout and conversion channel, Digital control circuitry, Communication interface, and Auxiliary on-chip blocks. Pixel Array and Readout Path As Fig. 111-bottom shows, the APS is a 4-T one and employs a Pinned-PhotoDiode (PPD) for sensing [Fossu14].The Pixel Array contains 2304 x 2304 active pixels (5.3M px effective resolution), and the pixel pitch is 6.5 m. The optimum optical format is therefore 1 1/6 inch. In addition, the pixel array contains a number of Optically-Black (OB) columns and rows as well as a number of dummy columns and rows used for doing HFPN and VFPN corrections, by averaging the OB pixels and subtracting to the whole row and column respectively. The sensor Readout Path follows a per-column parallel approach. It contains one two-stages ADC readout channel per pixel column that operates in parallel, conditioning and digitizing the analog data from 1 entire row of pixels simultaneously. It also contains additional per-column channels to read OpticalBlack (OB) columns and dummy columns. The readout path has been optimized for low-noise operation. On-chip digital circuitry and communication interface The on-chip Digital Circuitry is responsible for the overall control of the system and the generation of the frames for the high-speed LVDS outputs. The on-chip Digital circuitry is composed of: • Sensor control block, which executes the overall control of the system, including waveform generations for pixel array and readout. The pixel control signal (Trf, Rst and Sel) are driven by on-chip programmable buffers. • Serialization block (PSER). Once digitized by the Readout, pixel data are serialized out to the Framing blocks. Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 118 (TOP) ULN5.3 CIS BLOCK DIAGRAM (BOTTOM) SCHEMATICS OF THE 4T APS IN ULN5.3 Figure is in blank because it is containing confidential information. 5.1 Low noise sensor with 5.3 Mpixel and 0.7erms dark noise _ 119 • The LVDS Framing block receives data from Serialization block, generates the LVDS frame, and serializes it out. • Communication interface blocks. This part comprises all blocks related to input/output signals, such as SPI, external control signals (TRIGGER, RESETN, etc.) and data output. The data are outputted through LVDS ports. The LVDS output is formed of 32 LVDS ports for image data (PDO[0:31]/NDO[0:31]), two more for clock-recovering purpose (PCLK0/NCLK0 and PCLK1/NCLK1), and additional two for synchronization data (PSYN0/NSYN0 and PSYN1/NSYN1). The clock and synchronization information is copied into two LVDS ports in order to give flexibility to the receiver to route either one clock and synchronization port along with the 32 data ports or group one clock and synchronization port with 16 data ports and have another group with the remaining clock and synchronization port with the rest of data ports. Auxiliary on-chip blocks The Auxiliary On-Chip Blocks are auxiliary on-chip IPs, which reduce the number of external components required for the operation of the ULN5.3 device. They include the Power-on-Reset (PoR), the temperature eensor (TempS), a Clock Generation Block with a low-jitter low-power Phase Locked Loop (PLL), and the Reference Voltage Generator with a high-accuracy band-gap. The ULN device is controlled by a number of internal clocks, which are generated from a single external crystal reference (or clock source) whose frequency is scaled by using the PLL. The nominal reference external frequency is 8MHz. 5.1.3 Operation modes The pixel (see Fig. 111-bottom) is driven by the control signals Trf, and Rst. Once the photo-generated charge is converted to voltage at the Floating Diffusion (FD) capacitance, it is read out via the in-pixel source-follower (SF) and the selection switch (Sel) that connects it to the data column and current source. The waveforms applied to the control signals above are generated via a highly flexible state machine that permits programming a large number of combinations involving the control sequence as well as the duration of each pulse. The exposition (or procedure for light sensing and photo-generated charge transference and storage at the FD node), requires passing through a number of states that can be grouped as follows: • States B: Required to prepare the exposition. During those states, Rst and Trf signal are actived simultaneously to clean the FD node and the photodiode. It can also be referred to as the “Reset” phase. • States E: Light sensing or Exposure phase. Actually, light sensing begins at the falling edge of Trf when Rst still remains at high level, it occurs within States B. The end of exposure phase occurs at the following falling edge of Trf when the charge accumulated in the photodiode is transferred to the FD node , which may happen during the readout in rolling shutter or during States F in global shutter. • States F: Required to finish the exposition. In global shutter, the transference of the photo-charge to FD node is performed during those states, which requires a previous activation of the Rst signal for refreshing the FD, followed by an activation of the Trf signal to actually transfer the charge from the photodiode to the FD node. In rolling shutter, only the refreshing Rst is activated within States F, as the charge transference takes place during the readout. The duration of the complete exposition procedure is in fact the sum of the duration of states B, E, and F, which are programmable. ULN5.3 is designed to operate in two different shutter modes: • rolling shutter and • global shutter. Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 120 5.1.3.1. ROLLING SHUTTER This mode yields low noise due to the cancellation of the reset noise thanks to on-chip “true” Correlated Double Sampling (on-chip CDS). As it is shown in 0-top both the image acquisition (exposure) and readout are performed in a row-by-row basis in rolling-shutter mode. the pixel array in an "idle state". First, during the B states of each row, the photodiode and the FD node must be cleaned and re-set, by activating the transfer (Trf) and reset signal (Rst) simultaneously. The image acquisition actually starts when the transfer control signal (Trf) is deactivated. From this state on, the photogenerated charge starts to accumulate electrons from photons recombination in the pinned diode. (TOP) ILLUSTRATING ROLLING SHUTTER ROW-BY-ROW EXPOSITION AND READOUT (BOTTOM) EXAMPLE OF ROLLING-SHUTTER PIXEL CONTROL WAVEFORMS For each row, the readout phase starts reading the reset value, resulting from lowering the Rst control signal. This signal has been kept high during the whole exposure or pulsed right before the readout (as exemplified in 0-bottom. Then, the photo-generated charge is transferred from photodiode to the FD and read out. At this point, the actual exposition finishes and all the pixel information is transferred to the first stage of the Readout channel. Note that readout of a row of pixels can be made concurrently to any other operation in other rows, including the F states, except the Readout state (R). 5.1.3.2. GLOBAL SHUTTER In global-shutter mode, image acquisition and photo-generated charge transference to FD node is performed by all pixels simultaneously. The timing diagram shown in Fig. 113 is an example of global shutter pixel control. Note that global shutter requires global control of the reset (Rst) and transfer (Trf) signals. The 5.1 Low noise sensor with 5.3 Mpixel and 0.7erms dark noise _ 121 sensing starts with the pixel array in the "idle state". The Rst and Trf pulses are activated globally within B states to clean the photodiode. Then Rst pulse is applied at the beginning of F states to clean the FD node. Finally, the charge transference from the photodiode to the FD is carried out with a global transfer pulse (Trf). ULN5.3 can combine global shutter image acquisition with two types of readout procedures, enabling onchip (false) CDS, or off-chip (true) CDS, respectively. These two readout modes are explained in the next sections. ILLUSTRATING ROW-BY-ROW READOUT AFTER GLOBAL F STATES IN GLOBAL SHUTTER 5.1.3.3. ON-CHIP (FALSE) CDS When on-chip CDS is used, once the F states have finished, the readout process is performed row-by-row, like in rolling shutter mode (see Fig. 114). First, the data corresponding to the transferred charge is read out, then, after a pulse of the Rst signal applied to the active row, the reset level is read out. Fig. 114 shows typical global-shutter pixel control waveforms for on-chip CDS. Once the photo-charge has been transferred to the FD, at the end of F states, it remains there till the readout of the pixel is activated. However, as a general remark, it should be noticed that no readout is allowed for a pixel during its F states, because at that time the FD of such a pixel is being re-written with the new image data coming from the PPD. Note that, since this global shutter on-chip CDS actually requires two reset pulses (one global pulse before the charge transference, and one per-row pulse during the readout), the errors accompanying the reset and signal levels are not fully correlated. Thus, they cannot be fully removed by double sampling like in rolling shutter. This is why this operation it is often referred to as “false CDS”. In fact, only fixed-pattern noises are efficiently removed, whereas temporal reset noise (KTC noise) associated to the FD sampling mechanism is actually doubled in power by this procedure. Some low-frequencies temporal noises are attenuated, though, provided that the time elapsed between the two readings is not too long. False CDS is the only way to perform on-chip CDS in global shutter operation. Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 128 SPATIAL NON-UNIFORMITY (LEFT) AND TEMPORAL NOISE (RIGHT) AS A FUNCTION OF THE OUTPUT LEVEL USING THE TWO METHODS ABOVE 5.1.4.2. OVERALL SYSTEM GAIN (CONVERSION GAIN) Measurement of the overall system gain (Conversion Gain (CG), called also Charge to Voltage Factor (CVF)), is based on the linear dependence of the shot noise RMS with the signal level. In general, the temporal noise of the sensor can be approximated by the summation (in power) of a signal-independent terms, like readout noise, quantization noise, source follower noise etc… and the shot noise, shot, contribution whose variance is proportional to the electro average: )()( . 2 0 . 22 0 22 0 2, 22 0 2darkyy darkyy eeshoty K K KKK    −+= − +=+=+= (5. 6) It is possible to accurately measure CG by plotting the temporal variance as a function of the signal average and calculating the slope of the best-fitting straight line. Fig. 121 illustrates this method and shows the extracted value the conversion gain for ULN5.3 when operating with 14 bit resolution. CONVERSION GAIN EXTRACTION: TEMPORAL VARIANCE AS A FUNCTION OF THE OUTPUT LEVEL 5.1 Low noise sensor with 5.3 Mpixel and 0.7erms dark noise _ 129 5.1.4.3. SIGNAL-TO-NOISE RATIO (SNR) For given illumination, the Signal-to-Noise Ratio (SNR) is defined as the ratio of the signal increment (with respect to dark conditions) to the total temporal noise at the reached output level: y darkyy SNR   . − = (5. 7) which amounts to saying e e SNR   = (5. 8) where e and e are the signal and the total temporal noise, respectively, expressed in electrons. When plotted vs. the averaged digital output, see Fig. 122, SNR reaches its meaningful maximum value at the so-called “saturation capacity 7 ”, which corresponds to the maximum of the temporal noise. Beyond that point, SNR largely increases as a consequence of the sudden drop of the temporal noise caused by saturation. The SNR at the saturation capacity is reported as SNRmax. y darkysaty e sate SNR     .. . max − == (5. 9) SNR VS. OUTPUT LEVEL (TOP) AND THE CORRESPONDING TEMPORAL NOISE (BOTTOM) 5.1.4.4. DYNAMIC RANGE The Dynamic Range (DR) is defined as the ratio of the saturation capacity to the absolute sensitivity threshold, corresponding to the level at which SNR equals unity. When expressed in electrons, it becomes: 7 The saturation capacity must not be confused with the full-well capacity. The saturation capacity must not be confused with the full-well capacity. It is normally lower than the full-well capacity, because the signal is clipped to the maximum digital value, 214-1, before the physical saturation of the pixel is reached. Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 130 2 . .. min. . 1288 K DR darky darkysaty e sate + − ==     (5. 10) In EMVA Standard 1288 it is shown that the factor K/2 comes from the fact that at the “SNR=1” point there may be a non-negligible fraction of light-induced shot noise, apart from the noise in dark conditions. However, the K/2 term is often overlooked. In ULN5.3, DR is specified in reference to the pixel full-scale voltage range and temporal dark noise as follows: 𝐷𝑅=𝑉𝐹𝑆 𝜎𝑣.𝑑𝑎𝑟𝑘=𝑦𝐹𝑆−𝜇𝑦.𝑑𝑎𝑟𝑘 𝜎𝑦.𝑑𝑎𝑟𝑘 (5. 11) 5.1.4.5. SPATIAL NON-UNIFORMITY (DSNU, PRNU, AND FPN) Spatial non-uniformity is characterized by the following parameters: • The dark-signal non-uniformity defined as 𝐷𝑆𝑁𝑈1288=𝑠𝑦.𝑑𝑎𝑟𝑘 𝐾[𝑒−] (5. 12) where sy.dark is the spatial noise in dark conditions (in DN) and K is the system gain (in DN/e-). • The photo-response non-uniformity, defined as: 𝑃𝑅𝑁𝑈1288=√ 𝑠𝑦.50 2−𝑠𝑦.𝑑𝑎𝑟𝑘 2 𝑢𝑦.50−𝑢𝑦.𝑑𝑎𝑟𝑘 ∙100% (5. 13) with 𝑠𝑦.50 and 𝑢𝑦.50 being the respective spatial noise and average level around 50% of saturation. 5.1.4.6. RESPONSIVITY AND FF X QE The responsivity is the slope of the light-to-digital curve. It is a function of the light wavelength due to the spectral dependence of several factors like for example the photon energy, the transmittance of the optics and glass lid, the presence or not of antireflective coatings or filters, and the pixel quantum efficiency. Among those, the quantum efficiency (or better, the product of the fill-factor x quantum efficiency, since the two factors cannot be dissociated), dominates the spectral response of the sensor according to the linear law: exp. ··)(· tE hc A FFQEK pix darkyy   += (5. 14) The quantum efficiency was previously depicted in Fig. 110. 5.1.4.7. NON-LINEARITY Non-linearity of the light-to-digital response is measured by fitting data points between 5% and 95% of saturation capacity to a straight line and computing the fitting error or deviation y. The Linearity Error (LE) then defined as the mean of the difference of the maximal deviation to the minimal deviation: 2 )min()max( yy LE  − = (5. 15) It is expressed in %FS. 5.1 Low noise sensor with 5.3 Mpixel and 0.7erms dark noise _ 131 5.1.4.8. DARK CURRENT The dark output is not constant but it increases with exposure time as a consequence of the thermal generation of electrons within the photodiode. Using the EMVA Standard 1288 notation, we can write exp0.0. ·t Idthermdd  +=+= (5. 16) where μd.0 is the dark level corresponding to virtually zero exposure and μI is the dark current expressed either in DN/s or, preferably, in e-/s. exp 20. 22 0. 2·t Idthermdd  +=+= (5. 17) This equation is valid only if images are not dark-level compensated. If such compensation could not be disabled to measure the dark current, the equality given in (5. 18) would be used instead, because thermally induced electrons follow a Poisson distribution similar to the shot noise. 𝜎𝑡ℎ𝑒𝑟𝑚 2=𝜇𝑡ℎ𝑒𝑟𝑚 (5. 18) 5.1.5 Optical performances in 14 bits rolling-shutter mode The optical performances of ULN5.3 operation in the rolling shutter mode and 14 bits resolution are depicted in Fig. 123, along with the Photo Transfer Curve (PTC) graph. OPTICAL PERFORMANCES AND PTC IN 14 BITS ROLLING SHUTTER MODE Fig. 124 shows the responsivity and the linearity error, kept below 1% according to the specification. Linearity under low level accumulated light conditions is relevant for low-noise image sensors because a response compression on the low side would require applying a linearization gain, thus increasing the noise. The linear response featured by ULN5.3 makes such linearization unnecessary. Fig. 125 is a normalized histogram of the dark temporal noise displaying the dark noise distribution of ULN5.3 in 14 bits mode. Note that all pixels have a dark noise smaller than 6 e-RMS - much better than other sensors in the art [Ma17] [Xinya15] as Fig. 125 illustrates. This performance is very important in low-noise applications since large tails in dark noise distribution generate images with low noise but with salt and pepper effect yielding image with non-good sense of quality [Nakam06]. UNITS ºC dB dB e- % DN/edB DN erms FWC 15568 Dark noise, NEE 1.38 1.31 OPTICAL PERFORMANCES Tjunction -5.55 DR 80.03 SNRmax 41.42 DSNU 1.71 PRNU 0.24 CG 1.05 Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 132 RESPONSIVITY AND LINEARITY RESPONSE IN 14 BITS ROLLING SHUTTER OPERATION MODE (LEFT) DARK TEMPORAL NOISE DISTRIBUTION IN 14 BITS ROLLING-SHUTTER OPERATION MODE; (RIGHT) RESULTS FOR THE SENSOR IN [MA17] 5.1.6 Optical performances in 16 bits rolling-shutter mode Fig. 126 shows the optical performances the photo transfer curve in this mode. Sub-electron readout noise is achieved without external multisampling. Fig. 127 shows the responsivity and the linearity error; the latter remains below 1% and does not require linearization to correct low-light response. OPTICAL PERFORMANCES AND PTC IN 16 BITS ROLLING-SHUTTER MODE UNITS ºC dB dB e- % DN/edB DN erms OPTICAL PERFORMANCES Tjunction -6.19 DR 83.19 SNRmax 41.77 DSNU 0.67 PRNU 0.24 CG 4.27 FWC 14573 Dark noise, NEE 3.96 0.93 Normalized Pixel Count 5.1 Low noise sensor with 5.3 Mpixel and 0.7erms dark noise _ 133 RESPONSIVITY AND LINEARITY RESPONSE IN 14 BITS ROLLING-SHUTTER OPERATION MODE Finally, Fig. 128 depicts the dark noise distribution for 16 bits mode. All pixels remain below 5.25 e-RMS − better than for the 14 bits mode. DARK TEMPORAL NOISE DISTRIBUTION IN 16 BITS ROLLING-SHUTTER OPERATION MODE 5.1.7 Performances in 14 bits multisampling (M = 16) rolling-shutter mode Corresponding optical performances, responsivity/linearity error and dark noise distribution are depicted in Fig. 129, Fig. 130 and Fig. 131, respectively. Note the following: i) linearity error is below 1% according to the specification and does not require low-light correction; ii) the dark noise distribution is even better than for the 16bits mode, with all pixels below 4 e-RMS. OPTICAL PERFORMANCES AND PTC IN 14BITS MULTISAMPLING M =16 ROLLING-SHUTTER MODE UNITS ºC dB dB e- % DN/edB DN erms OPTICAL PERFORMANCES Tjunction -4.08 DR 85.85 SNRmax 41.59 DSNU 0.27 PRNU 0.22 CG 1.09 FWC 14739 Dark noise, NEE 0.77 0.71 Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 134 RESPONSIVITY AND LINEARITY RESPONSE IN 14 BITS ROLLING SHUTTER OPERATION MODE DARK TEMPORAL NOISE DISTRIBUTION IN 14 BITS MJLTISAMPLING M = 16 ROLLING-SHUTTER OPERATION 5.1.8 Dark current Dark current measurement has been done using 14 bits rolling-shutter operation method. To obtain the dark current the ULN5.3 device is measured inside a climate chamber, and dark images have been obtained sweeping the exposure time, this measurement is repeated in the range of temperature from -40⁰C to 50⁰C. Table 15 shows the data of every measurement, where Troom is the temperature inside the climate chamber, Tjunction is the temperatures in the die, μ(DN/s) is the slope of the mean value or temporal standard deviation of the pixels output vs the exposure time, and σ(DN/s) is the slope of the spatial standard deviation of the pixel output vs the exposure time. The table also shows two parameters are extracted for the temporal(μ) and spatial(σ) components, namely: • the doubling coefficient (Kd), and • the value of each parameter at 25⁰ C(Nd0). The doubling coefficient is defined as the temperature shift the device should experience in order to increase (or decrease) the dark current by a factor of 2. The dark current at an temperature To is given as: 𝜇𝑑𝑎𝑟𝑘=𝑁𝑑0∙2(𝑇𝑜−25) 𝐾𝑑 (5. 19) Fig. 132 shows the dark current measurement on a semi-logarithmic scale where such that the doubling coefficient (Kd) is the slope of the curve. 5.1 Low noise sensor with 5.3 Mpixel and 0.7erms dark noise _ 135 Table 15. DARK CURRENT MEASUREMENT DATA Dark Current measurement Troom (ºC) Tjunction(ºC) μ (DN/s) σ(DN/s) -40 -11.1 0.4 0.1 -30 -1.9 1.1 0.6 -20 6.4 2.5 1.9 -10 16.6 6.5 5.5 0 25.6 16.8 13.7 10 35.1 45.0 32.2 20 44.2 125.7 72.6 30 54.1 340.5 152.0 40 62.7 916.2 306.5 50 68.4 1819.0 447.6 Extracted parameters CG(DN/e) Kd (ºC) (doubling coeff) μ σ 6.6 7.9 1.0670 Nd0 (e/s) (value at 25ºC) μ σ 15.8 11.0 (a) (b) DARK CURRENT MEASUREMENT: (A) TEMPORAL DEVIATION (B) SPATIAL DEVIATION 5.1.9 Glow effect and mitigation techniques This section is in blank because it is containing confidential information. 5.1.10 Low light benchmark comparison Low light testbench A low light testbench has been used to develop specific characterization for low-noise image sensors under controlled low light conditions. Fig. 133 depicts the low light bench, which consists of a black box, an integrating sphere with shutter, a detector or camera, a filter holder and a calibrated photodiode to measure the light intensity. The low light bench has been designed to allow: • Controled and reproducible light conditions: irradiance, input MTF and transmittance test chart. • Low light measurements, image and comparisons of devices, including from different technologies EMCMOS, EMCCD, EBCMOS and low noise CMOS image sensor Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 136 • Measurements or extrapolations of variable application conditions: light conditions, optics, atmosphere model, target contrasts. • Providing measurements and merit figures (MTF, Noise, Contrast threshold [Bisog07]) • Providing Defense and Surveillance specific metrics (Johnson criteria [Johns58]). Fig. 134 shows the measurement setup consisting of KOWA lens optic, light intensity variation thanks to the shutter aperture, integration time 1/60s, Gain x4 in ONYX MAX and CIS 2521 sensors and USAF test chart at 20cm from the sphere output. LOW LIGHT TESTBENCH MEASUREMENT SETUP Sensor performance comparison Night levels images comparison has been done using ULN5.6 and two additional sensor: • ONYX is a 1.3 Megapixel sensor for low light applications [Te2v21] • CIS2521 sensor [BAE] Table 16 collects data regarding sensor comparison. Furthermore, Fig. 135 to Fig. 139 include images captured by the three sensors for illuminance levels from 10mlux to 0.69 mlux. Table 16. IMAGE SENSOR PERFORMANCES COMPARATIVE Features Units ULN5.3 ONYX1.3M CIS2521 Resolution 2304 (H) x2304 (V) 1280 (H) x 1024 (V) 2560 (H) x 2160 (V) 5.1 Low noise sensor with 5.3 Mpixel and 0.7erms dark noise _ 137 Pixel size m 6.5 10 6.5 Frame Rate fps 87 95 100 Dynamic range dB 84.4 73 83.5 Read Noise eRMS 1.3 3 2 Full Well Capacity Ke15 14 30000 IMAGES AT NIGHT LEVEL 2 WITH 10 MLUX AT F#1 IMAGES AT NIGHT LEVEL 3 WITH 5 MLUX AT F#1 Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 144 ULN66 READOUT CHANNEL 5.2.2.1. DIGITAL CDS The ULN66 sensor can operate in digital CDS. When this mode is selected, the 1st stage of the ADC converts the data coming from the pixel referred to a voltage reference and generates the analog residue after the conversion. The residue is converted by the 2nd ADC stage. When only the one gain level is selected (either high or low gain), the ADC converts two samples per row time, one related to the pixel RESET voltage and the other related to the pixel SIGNAL voltage. The digitized samples are subtracted in the digital domain, which must be done externally (in the receiver system). Fig. 147 shows the digital CDS operation. ULN66 DIGITAL CDS OPERATION When dual conversion gain is selected the ADC converts four samples per row time, one related to the RESET low gain voltage, the second to the RESET high gain, the third to the SIGNAL high gain and the fourth data column line Pixel SF sel Prog. Current Source + Prog. Offset 1st stage ADC 2nd stage ADC 4, 5, 6 10 MSBs LSBs CDS Analog Buffer Residue D1D2 21 2 2DDD N out += 5.2 Large scale 66 Mpixel 10 mm pixel low noise and high _ 145 related to the SIGNAL low gain. The digitized samples are subtracted and processed in the digital domain, which must be done externally. Fig. 148 shows the digital CDS operation with dual gain. ULN66 DIGITAL CDS OPERATION WITH DUAL CONVERSION GAIN 5.2.2.2. ANALOG CDS The image sensor can operate in analog CDS. When only one gain is selected, low or high gain, the ADC starts integrating the RESET level, once the charge is transferred and the SIGNAL level is ready, the ADC integrates the pixel output with sign inversion, thus performing the CDS operation in analog domain and generating the analog residue to the second stage of the ADC. The ADC delivers only one word output in one row time, since CDS is done internally in analog domain. Fig. 149 shows the analog CDS operation. In this mode the circuitry and architecture of readout channel is the same, but it is operated differently ULN66 ANALOG CDS OPERATION The analog CDS with dual high gain is available as well. In this case, the ADC is converting the high gain in the same way it is done when only one gain is selected, however the low gain component is only sampled by the first stage of the ADC and then the CDS operation is performed prior to sent to the second stage of the ADC, as described in Chapter 4. This operation optimized the trade-off between precision, power consumption and time, since the low gain signals does not require ultra-low level of noise because shot noise Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 146 is supposed to be dominating when low gain is used. Fig. 150 shows the analog CDS with dual conversion gain operation mode. ULN66 ANALOG CDS OPERATION WITH DUAL CONVERSION GAIN 5.2.2.3. ROLLING AND GLOBAL SHUTTER MODE Rolling-shutter mode Like ULN5.3, the image sensor ULN66 incorporates rolling and global shutter mode. The rolling mode yields low noise due to the cancelation of reset noise by the correlated double sampling operation. Fig. 151 shows the rolling shouter operation where every row is exposed in a row time shift, with exposure and readout is done in a row-by-row basis. ROLLING-SHUTTER ROW-BY-ROW EXPOSURE AND READOUT Global-shutter mode In global shutter mode, image acquisition and photo-generated charge transference to FD node is performed by all pixels simultaneously. Typical global shutter with false CDS (explained in Section 5.1.3.2) is available in ULN66 as well, however this mode introduces the reset noise and it is not interesting from the point of view of delivering low noise dark images. Instead, ULN66 provides global shutter operation with external CDS delivering the reset image, which is readout prior to the global transfer pulse, and then the signal image is readout. Since the signal is accumulated over the reset, the pixel reset noise is totally cancelled rendering a low noise image. This operation mode is call off-chip global shutter true CDS. The low noise performance can be not so good as rolling shutter operation, because some readout contribution like quantization noise is added twice, the low frequency noise contributor of source follower is not so effectively cancelled because the time between the two samples is much higher, and finally there is an additional contribution coming from the dark current that is integrated in the floating diffusion node between the reset of the floating diffusion and the signal readout. This contribution is not negligible since the dark current generated in the floating diffusion can be at least one order of magnitude larger than photodiode dark current. To mitigate dark current contribution in the floating diffusion active colling system can be added in the final system. row B 0E F R B 1E F R 2 3 4 5 ... n-2 n-1 BE F R BE F R BE F R BE F R ... BE F R BE F R Tframe ... 5.2 Large scale 66 Mpixel 10 mm pixel low noise and high _ 147 GLOBAL SHUTTER OPERATION OFF-CHIP TRUE CDS MODE When dual gain operation is selected, four frames must be readout, one related to the reset low gain, another with the reset high gain, the third to the signal high gain and finally the fourth with the signal low gain. The digitized images are subtracted and processed in the digital domain, that can be done in the receiver system. 5.2.2.4. MULTISAMPLING Multisampling operation mode is also available in rolling shutter and global shutter, Fig. 153 and Fig. 154 respectively. In this mode, external readout with non-destructive-readout is used. External processing averaging every sample can be used to lowering part of the readout noise. The wide-band noise contributors like thermal noise are reduced by the square root of M, being M the number of samples of reset and signal levels. However, the low frequency noise components, like the flicker noise 1/f, are increased because the CDS time is increased with the number of samples, M. In fact, there is a trade-off to obtain the optimum value for M, where increasing the number of samples does not decrease the total dark noise. ROLLING SHUTTER OPERATION CORRELATED MULTISAMPLING (CMS) MODE GLOBAL SHUTTER OPERATION CORRELATED MULTISAMPLING (CMS) MODE Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 148 5.2.3 Sensor functions 5.2.3.1. WINDOWING ULN66 can be configured for reading the whole pixel array or a set of region of interest. Up to 4 different ROIs can be programmed. Every ROI is defined with the initial row and the width, being read all columns. An example of ROI selection is shown in Fig. 155. Additional to the 4 ROIs the special rows, consisting of dummy rows, OB rows and 2 test rows can be selected. The two test rows can be selected for calibration and to test the readout path. The windowing affects the maximum frame rate because the readout time is proportional to the number of rows defined to be readout. REGION OF INTEREST DEFINITIONS 5.2.3.2. BINNING ULN66 also incorporates binning function. The binning consists of averaging or accumulating the pixel signal for neighbour pixels. In this case, the sensor can provide row binning in the analog domain. To do that, two rows are enable at the same time, activating the pixel control signals of two consecutive rows to activate the pixel source followers and short-circuit the source follower output. This operation reduces the pixel array resolution by two in the row direction. This operation increases SNR and DR, as well as frame rate. 5.2.3.3. LOW POWER MODE ULN66 includes low power mode to reduce the “glow effect”. Internal blocks can be independently selected through configuration register to be power off during exposure or idle state, as shown in Fig. 156. The sensor automatically can enter in low power mode, disabling all blocks configured in low power configuration register. Before entering the low power mode (idle or exposure), the readout pipeline must finish the current readout operation. It means that enable the low power mode must wait until the data is output through the LVDS. A programmable delay can be programmed to adjust entering in low power mode. LOW POWER MODE IN ROLLING SHUTTER 5.2.4 Sensor yield improvement This section is in blank because it is containing confidential information. 5.2 Large scale 66 Mpixel 10 mm pixel low noise and high _ 149 5.2.5 Optical performances measurements The optical characterization of ULN66 is done using similar setup and procedure as described in Section 5.1.4 , following the EMVA standard 1288 [EMVA21]. In the next section the optical performances of ULN66 sensor in different operation modes are given at: i) low temperature, −40⁰ C, and ii) room temperature, 20⁰ C, with the exception of multisampling modes where only low temperature data is shown. The ULN66 sensor will be incorporated in a scientific camera with active cooling working at −40⁰ C that provides junction temperatures in the range 31⁰ C and 28⁰ C depending in sensor power consumption. The optical sensor performances have been optimized at low temperature and then measured at room temperature to obtain the performances deviations if any. Besides optical performance metrics, responsivity, linearity, spatial noise and PTC curves are showed in order to check the main performances along the sensor response. 5.2.5.1. ROLLING SHUTTER 14 BITS INTERNAL CDS HIGH GAIN OPTICAL PERFORMANCES 14BITS INTERNAL CDS HIGH GAIN RESPONSIVITY, LINEARITY, SPATIAL NOISE AND PTC IN RS 14BITS INTERNAL CDS HIGH GAIN Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 150 5.2.5.2. ROLLING SHUTTER 14 BITS INTERNAL CDS LOW GAIN OPTICAL PERFORMANCES 14BITS INTERNAL CDS LOW GAIN RESPONSIVITY, LINEARITY, SPATIAL NOISE AND PTC IN RS 14BITS INTERNAL CDS LOW GAIN 5.2 Large scale 66 Mpixel 10 mm pixel low noise and high _ 151 5.2.5.3. GLOBAL SHUTTER 14 BITS EXTERNAL CDS HIGH GAIN OPTICAL PERFORMANCES 14BITS IN GLOBAL SHUTTER EXTERNAL CDS HIGH GAIN RESPONSIVITY, LINEARITY, SPATIAL NOISE AND PTC IN GLOBAL SHUTTER 14BITS INTERNAL CDS HIGH GAIN Chapter 5 Low Noise CISs with Optimized Pixels, Dual Gain and Oversampled ADCs 152 5.2.5.4. GLOBAL SHUTTER 14 BITS EXTERNAL CDS LOW GAIN OPTICAL PERFORMANCES 14BITS IN GLOBAL SHUTTER EXTERNAL CDS LOW GAIN RESPONSIVITY, LINEARITY, SPATIAL NOISE AND PTC IN GLOBAL SHUTTER 14BITS INTERNAL CDS LOW GAIN 5.2 Large scale 66 Mpixel 10 mm pixel low noise and high _ 153 5.2.5.5. ROLLING SHUTTER 14 BITS EXTERNAL CDS HDR OPTICAL PERFORMANCES 14BITS IN ROLLING SHUTTER EXTERNAL CDS HDR RESPONSIVITY, LINEARITY, SPATIAL NOISE AND PTC IN ROLLING SHUTTER 14BITS EXTERNAL CDS HDR