Discontinuous PWM Technique with Reduced Low-order Harmonic Distortion for High-Power Applications

1 Discontinuous PWM Technique with Reduced Low-order Harmonic Distortion for High-Power Applications Jon X. Balenciaga, Abraham M. Alcaide, Member,IEEE, Jose I. Leon, Fellow Member,IEEE, Eritz Aldazabal, Danel Madariaga, Iraitz Legarra and Leopoldo G. Franquelo Life Fellow,IEEE Abstract—The modulation techniques used in high power applications have to generate high quality waveforms with reduced switching losses. As an attractive alternative, Discontinuous PWM (DPWM) techniques present lower device switching frequencies than conventional continuous PWM methods lowering the converter switching loss. Considering the same cooling system, this allows to increase the carrier frequency of DPWM methods displacing the main switching harmonics to higher frequencies. As a main drawback, when low carrier to fundamental ratios are used, DPWM methods present some undesired low-order harmonics that are required to be filtered. This paper presents a low-order harmonic minimization method for synchronous DPWM methods by modifying the conventional modulating reference to limit low order harmonics amplitude, while keeping the same effective switching frequency and thus limited switching losses. Index Terms—Discontinuous Pulse Width Modulation, Metaheuristics, multilevel inverter, high voltage devices I. INTRODUCTION HAnd by hand with the increasing power demand, the role of power electronics with the need for a more efficient and cost-effective power conversion systems is becoming fundamental. In conventional high-power three-phase converters, power range of several tens of megawatts is required. This leads to the use of multilevel inverter topologies such as the neutral-point clamped converter (NPC) which is illustrated in Fig. 1. Multilevel converters achieve a high output voltage with power semiconductors with low maximum voltage rating at the expense of developing more complex control and modulation methods [1]–[3]. An important feature to be optimized in high-power systems is the converter efficiency, where the modulation algorithm to synthesize the voltage has a direct influence [4], [5]. One The authors gratefully acknowledge financial support provided Ministerio de Ciencia e Innovaci´ on under the project PID2020-115561RB-C31, Junta de Andaluc´ ıa under the project P18-RT-1340 and Contrataci´ on de Personal Investigador Doctor Paidi 2020, supported by the European Social Fund and Junta de Andaluc´ ıa. Jon Xabier Balenciaga, Eritz Aldazabal and Iraitz Legarra are with Ingeteam Power Technology, Marine and Industry department, Zamudio, 48170 Spain Abraham M. Alcaide is with the Electronic Engineering Department, Universidad de Sevilla, Seville, 41092 Spain (e-mail: [email protected]g). Jose I. Leon and Leopoldo G. Franquelo are with ENGREEN Laboratory of Engineering for Energy and Environmental Sustainability, Universidad de Sevilla, Seville, 41092 Spain and also are chair professor with the School of Astronautics, Harbin Institute of Technology, Harbin (China). suitable method to reduce losses while keeping high quality waveforms is to apply a pre-programmed pulse-width modulation (PWM) technique. These methods, that usually are called selective harmonic elimination PWM (SHE-PWM) or selective harmonic mitigation PWM (SHM-PWM), remove or reduce the low-order harmonic distortion, and thus harmonic filtering by means of an LC network becomes easier [6], [7]. As a main drawback, the power converter dynamic performance is worse compared to the conventional performance of those converters applying the traditional carrier-based PWM techniques (CBPWM) [8], [9]. CB-PWM methods generate the power semiconductors switching signals based on the comparison between triangular carrier and modulating waveforms. The resulting harmonic spectrum of the output waveform is characterized by sidebands around multiples of the carrier frequency (fc) [10]. This represents a high limitation of the CB-PWM methods for high-power applications because the carrier frequency requires to be very reduced because of limitations in the allowed maximum power loss. In order to face this challenge, applying discontinuous PWM methods (DPWM) the effective switching frequency (fsw) and the corresponding switching losses are reduced by an approximate 1 /3factor compared with the conventional continuous CB-PWM methods [10]– [12]. In DPWM methods, the reduction of the switching losses is obtained by clamping the modulating references to specific fixed voltage levels avoiding the power devices switching. As a consequence, considering the same switching losses than those obtained applying continuous CB-PWM methods, the carrier frequency can be increased, shifting the main switching harmonics to higher frequencies [10], [11]. As a main drawback of DPWM methods, for low ratios between the carrier and the fundamental output frequency (mf), low-order harmonic magnitudes of the output waveform become significant. This may represent a major drawback for filtering by means of a LC network, since resonance issues may be arisen, requiring a higher damping resistor and thus increasing the power losses. A DPWM technique with modified offset with the aim to minimize low order harmonics amplitudes is proposed in [13], but conventional DPWM clamping periods are not guaranteed, leading to increased semiconductor switching losses. In [14], switching sequences for symmetrical current ripple were investigated to minimize low-order harmonics, but the method also presents This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3219120 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. 2 Vdc,1 Cdc Cdc N P O T1 D1 D2 T2 T3 T4 L R ix V ab Vdc,2 io Fig. 1. Three-phase three-level neutral-point clamped inverter higher losses since additional switching transitions are inserted. On the other hand, technical literature shows that when synchronized output voltages applying half-wave and quarter wave symmetry properties are used, the harmonic distortion of CB-PWM methods can be minimized [15], [16]. In this sense, synchronized space vector modulation (SVM) switching sequences that minimize output current ripples were investigated in [17]. As the main contribution of this work, a DPWM method with reduced low-order harmonic distortion is developed by considering a synchronized output voltage waveform that is optimized by means of pre-programmed PWM techniques basic concepts. In the proposed method, an optimization problem based on pre-programmed PWM methods formulation is carried out leading to modify the original DPWM switching pattern but taking into account the switching angles restrictions that are given in a DPWM method. II. PROPOSED ENHANCED HARMONIC PERFORMANCE DPWM METHOD When a DPWM method is applied, a zero-sequence waveform is added to the phase voltage references in order to force the clamping of the phase states to specific voltages [10]. In the case of the NPC converter topology, by applying the DPWM method, Y∗ x(x=a, b, c)modulating signals that clamp phase voltages to P, O or N are determined. Normally, the DPWM methods avoid power semiconductor commutations at the instants where the phase currents (ix) present maximum values leading to an important switching losses reduction. Some DPWM method alternatives are presented in Fig. 2. DPWM1 method is well-suited for active power loads, whereas DPWM3 is mostly recommended for reactive loads [10], [11]. In this way, in power conversion systems such as a grid-connected or inverter fed drives, the power factor is close to the unity making DPWM1 method an appropriate choice. This work will be focused on developing an enhanced DPWM1 method, but other DPWM techniques could be also considered. Switching loss reduction achieved by the DPWM1 method is given by the 60° clamping periods defined for positive and negative half-cycles respectively. Taking this into account, for Y x * i x a b Fig. 2. Review of DPWM techniques a) DPWM1 b) DPWM3 0 5 10 15 20 25 30 35 40 45 50 0.0 0.2 0.4 0.6 0.8 1.0 Harmonic order (n) Amplitude v i Fig. 3. Load voltage and current harmonic spectrum applying the DPWM1 method (ma= 0.85 and mf= 27) the same effective switching frequency (fsw) compared with conventional PWM methods, a carrier frequency increase by a 3 /2factor is permissible. In this situation, and due to the fact of having the most dominant harmonics grouped around the first carrier group, they will be shifted to a higher frequency band. However, considering a low carrier to fundamental ratio (mf) to enhance the system efficiency, when the DPWM1 method is applied, the presence of non negligible low-order harmonics (located at harmonic orders 5,7,11,13..) are found. As an example, considering a modulation index Ma= 0.85 and a carrier ratio mf= 27, the NPC converter output voltage and current harmonic amplitudes are represented in Fig. 3. The presence of these harmonics might be critical for grid connected applications since grid codes limit voltage and current magnitudes in the Point of Common Coupling (PCC), while low-order current harmonics might be also sensible for motor drive applications leading to torque ripple and undesired mechanical vibrations [17]. In order to overcome the challenges of DPWM methods with low mfvalue, the harmonic content of such modulation strategies can be studied. In particular, in a similar manner as pre-programmed PWM techniques, an optimization problem to minimize low-order harmonics of a synchronous DPWM1 technique can be defined. This work proposes to define DPWM methods as a particular case of the pre-programmed PWM strategies but forcing the switching angles to follow a fixed switching frequency PWM pattern keeping the CB-PWM structure. In this section, the procedure for the proposed enhanced DPWM1 method (eDPWM1) implementation, including problem formulation to minimize low order harmonics as well as corresponding switching angles calculation, followed by a modified block-diagram of conventional CB-PWM implementation is detailed. A. Harmonic analysis and problem formulation The output voltage waveform obtained by a generic CBPWM method is defined by αkswitching angles that are This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3219120 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. 3 Yx* Vx Yx* Vx a b ®k,min ®k,max ®k®k,min ®k,max ®k Fig. 4. Typical voltage waveform applying a CB-PWM scheme a) bottomupdate b) top-update Yx* Vx ®1 ® are flexible ® are fixed ®2®3®4®5®6®7®8 Clamped to P Unclampled a ) b ) Fig. 5. Phase voltage waveform applying a DPWM1 strategy with fixed and variable switching angles a) Modulating references Y∗ xb) Voltage waveform Vx given by the triangle carrier and the modulating reference Y∗ xintersections. In order to illustrate this concept for an asymmetrical sampled reference, a whole carrier cycle is defined in Fig. 4, when the modulating reference is sampled at the lower and upper peaks of the triangle carrier respectively [18]. For each of the k sampling points, αk,min and αk,max in (1) and (2) represent the carrier cycle starting and ending instants, that also depend on the initial sampling point given by initial carrier phase-shift angle θcwhen t= 0. It has to be pointed out that in a generic CB-PWM implementation, the switching angles αkare restricted to be within the carrier bounds defined by αk,min and αk,max. αk,min =θc mf + (k−1) π mf (1) αk,max =θc mf +kπ mf (2) In Fig. 5, the pulsed waveform implementing a DPWM1 strategy considering θc= 0 is shown. Some of these switching instants are determined because of the aforementioned PWM frame and define the average voltage per half carrier cycle, thus leading to generate variable switching angles. However, other switching angles are fixed being related with the DPWM1 strategy frame, where there are instants where the output voltage has to be clamped. In order to keep the DPWM1 frame, the proposed eDPWM1 method will only permit to modify the flexible switching angles values in order to increase the converter harmonic performance. The harmonic optimization process of the proposed eD- PWM1 method requires obtaining a mathematical formulation of the converter output voltage waveform. In this sense, it is possible to use Fourier expansion series to obtain it. Vx 032 Yx* Vx ®1 ®1 ®Nqw ®Nhw b a Fig. 6. Waveform symmetries used in pre-programmed techniques a) SHE with QWS b) DPWM1 with HWS This mathematical tool asserts that periodic signals can be expressed by the infinite sum of trigonometrical terms as: V(t)=a0 2+ ∞ X n=1 ancos(nωt) + bnsin(nωt)(3) Synchronizing output voltage allows to consider one fundamental period of the waveform in order to simplify the formulation. For conventional pre-programmed PWM techniques, as it is shown in Fig. 6a, quarter wave symmetrical (QWS) waveforms are preferred leading to a reduction of the number of switching angles considered in the calculations [19]. However, for conventional carrier-based DPWM1 techniques shown in Fig. 6b, the constraint of fulfilling QWS can not be directly met [16]. Instead, for odd mfratios, half-wave symmetry (HWS) can be applied, considering Nhw switching angles comprising 180◦of the fundamental waveform. Taking into account the HWS PWM waveform with Nhw switching transitions, anand bnFourier coefficients can be calculated using [20]: an=−2Vdc nπ Nhw X k=1 pksin {nαk}(4) bn=2Vdc nπ Nhw X k=1 pkcos {nαk}(5) pk=n1 : rising, −1 : fallingo(6) In three-phase systems, each one of these harmonics can be classified as common-mode or differential-mode type, with the latter representing the load current or line-to-line voltages. When the converter output voltages are held so that threephase symmetry (TPS) is guaranteed according to the expression in (7), triplen differential type harmonics become zero since they are common-mode type. On the other hand, with HWS supposing Vdc1=Vdc2, all even harmonics become zero, reducing the analysis to non-even non-triplen harmonics [12], fulfilling that Va(θ) = Vbθ−2π 3=Vcθ+2π 3(7) Cn=an+jbn(8) In addition to minimize the low-order harmonic distortion, fundamental voltage constraints of the proposed eDPWM1 This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3219120 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. 4 method must be kept the same as the original DPWM strategy. Taking into account that with HWS waveforms, harmonic phase angle is not predefined as for QWS, both fundamental waveform amplitude and phase angle constraints need to be controlled [20]. Defining αkas the conventional DPWM1 strategy switching angles and βkas the eDPWM1 switching angles looking to enhance the converter harmonic performance, the fundamental component amplitude error ϵ|C1|and phase error ϵC1 can be determined as: ϵ|C1|=|C1|βk− |C1|αk(9) ϵC1=C1βk−C1αk(10) When the converter harmonic performance is evaluated, two of the most common indicators are the voltage Total Harmonic Distortion (THD) and the Weighted Total Harmonic Distortion (WTHD) that also represents the current ripple for pure inductive loads [18]. From the complex harmonic coefficients defined in (8), and given the simplifications related to TPS and HWS, non-even non-triplen harmonics considering up to a maximum Nmax harmonic order are defined in the voltage and current distortion factors given in: T HD(Nmax) = v u u t Nmax X n=5 |Cn|2(11) W T HD(Nmax) = v u u t Nmax X n=5 |Cn| n!2 (12) In order to reduce the low-order harmonic content, voltage and current distortion representing factors up to a NLF harmonic order given by THDLF and W T HDLF are considered (where Nmax =NLF ). These are weighted by total harmonic distortion factors, normally defined considering the first 50 harmonics (Nmax = 50) leading to the normalized factors THDpu LF and WTHDpu LF that represent the amount of the total distortion factors keeping within the low frequency range. Taking into account that load impedance for inductive loads is small for low frequency and thus current harmonics becomes sensitive to small voltage amplitudes, the minimization of WTHDpu LF that also contributes to low frequency voltage distortion factor is prioritized. T HDpu LF =T HDNLF T HD50 (13) W T HDpu LF =W T HDNLF W T HD50 (14) Finally, in order to discard eDPWM1 method switching angles values that do not fulfill the fundamental waveform constraints, a discontinuous switching function declared as λis defined. When the constraints ϵ|C1|and ϵC1 are not within intended tolerances, the obtained switching angles of the eDPWM1 method are set as non valid solutions by forcing λ=∞, leading to maximize the cost function defined in (15). On the other hand, if these tolerances are not overcome, λ becomes zero and the cost function is directly related with [¯10 ¯11 ¯1k -1]eDPWM1 angles Shareholders Ranking (according their Fi ) Evaluate Cost Function F (15) InitEMA() Shareholders Init. Solution = DPWM1 angles Stock ®10 ®11 ®1k-1 F1 F2 Fp ®20 ®21 ®2k-1 ®p0 ®p1 ®pk-1 Balanced Market Evolution Trading Market Evolution DPWM1 switching angles restriction M=0? Shareholder evolution Evaluate Market Rank Sharedholder M =1 M =0 YES NO Fig. 7. Exchange Market Algorithm flowchart to find an eDPWM1 solution determining the most proper switching angles to reduce the cost function F low frequency distortion factor WTHDpu LF . Taking this into account, the cost function Fconsidered by the eDPWM1 method can be finally defined as follows: F=W T HDpu LF +λ(15) where the parameter λis defined as: λ=     ∞, if (ϵ|C1|>10−3)or (ϵC1 >0.01◦) 0, if (ϵ|C1|<10−3)and (ϵC1 <0.01◦) (16) B. Variable switching angles determination of the eDPWM1 method The objective of pre-programmed PWM techniques is to calculate switching patterns that manage the harmonic distortion at specific frequencies. Using proper optimization techniques, the switching angles that minimize an objective function can be calculated [21]. The expression defined in eq. (15) is a highly complex non-linear cost-function, which requires a mathematical search algorithm to look for the most proper variable switching angles to minimize F. From the metaheuristics and evolutionary algorithms used to solve complex mathematical problems, a recent continuous non-linear optimization method named Exchange Market Algorithm (EMA), initially designed to optimize financial transactions between shareholders, has been adopted in this work [22]. This method combines advantages of different meta-heuristic algorithms in order to achieve good solutions in a few iterations also avoiding stacking in a local minima. A modified version of the EMA in order to deal with the objectives of this work in terms of determining a proper switching angles set to minimize a cost function Fis shown in Fig. 7. However, it is important to highlight that despite of using the EMA due to reduced computational cost and increased convergence ratio, other optimization methods can be used such as Particle This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3219120 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. 5 Modulation index (Ma) 0.2 0.4 0.6 0.8 1.0 1.2 /2 2 /3 5 /3 /6 /6 ®k¯k Fig. 8. DPWM1 method and proposed eDPWM1 method switching angles Swarm Optimization (PSO), Genetic Algorithms (GA) or Exhaustive Search Algorithm. The choosing of the most proper mathematical method to look for the minimum value of the cost function Fdefined in eq. (15) is out of the scope of this work. The starting solutions of the EMA to minimize the cost function Fare based on conventional DPWM1 implementation switching angles (αk), randomly combined to build an initial population that feed the algorithm. EMA modifies the variable switching angles following market exchange operations and gets a new set of angles (named βk) that are ranked according to cost function Fvalue. It is important to notice that extra layers are introduced in the EMA algorithm from Fig. 7 to assure that, after any iteration, the set of obtained switching angles meets the restrictions of the DPWM frame. Also it is introduced a restriction about the power semiconductor minimum on-time (tonmin ) considering the dead-time to prevent cross-conduction as well as the driver response to detect a short-circuit, so that narrow pulses [23]. The final switching angles that are obtained from the EMA are shown in Fig. 8, showing that some slight switching angle variations are required to minimize the cost function F. The obtained values of the WTHDpu LF factor are represented in Fig. 9, demonstrating that the enhanced set of variable switching angles obtained by the proposed eDPWM1 method greatly reduces the content of low-order weighted voltage harmonics. As an exception, values at the boundary modulation index (Ma=2 /2√3) become similar, since the loworder harmonics of the conventional DPWM1 are already low at that modulation index range. In any case, it is also important to point out that this low-order harmonic distortion reduction is achieved without additional losses, since the switching angles modifications are carried out keeping the DPWM frame and therefore maintaining the number of switching transitions. TABLE I OPERATIONAL CONDITIONS Parameter Value Carrier frequency fsw 1350 Hz Fundamental frequency fo50 Hz mf27 tonmin 20 us LF harmonics included in F5,7,11,13,17,19 0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 F Modulation index (Ma) DPWM1 eDPWM1 Fig. 9. Fcost function magnitudes Y x ¢Y DPWM1 offset ++ - + Look-up table ++ ZSS eDPWM1 Yxe* Yxe Vx ++ Yvo DC-link balance Yxe vo* Fig. 10. Implementation of the proposed eDPWM method C. Implementation of the eDPWM1 method as a CB-PWM technique by modifying the modulating references When the conventional CB-PWM implementation is considered, Y∗ xmodulating references used to synthesize output voltage waveforms are obtained after adding a zero-sequence signal (ZSS) to three-phase sinusoidal references (Yx). In order to consider a CB-PWM implementation of the eDPWM1 method, modulator references that produce the same output voltage as the obtained βkangles are required. The translation from the βkangles to eDPWM1 method modulating references (Y∗ xe) can be done by averaging the pulsed waveform over each half carrier cycle (Ts). In addition, since ZSS offset is predefined to clamp phase states to specific DC- link levels, only the information regarding differential mode reference signals (Yxe) becomes relevant for the modified CBPWM implementation. A synchronous CB-PWM method that uses an odd triplen ratio guarantees HWS and TPS symmetries and therefore evenly shifted phase modulating references can be considered in eq. (17) for ZSS offset calculation. With this expression, differential references are obtained by removing ZSS to precalculated modulating references as defined by eq. (18). In comparison with the conventional DPWM1 method, Yxe is not a pure sinusoidal waveform, instead a modified reference that achieves the intended low-order harmonic minimization. This reference has been introduced as a modified input to a conventional CB-PWM scheme in Fig. 10, with ∆Yvariations being precalculated in eq. (19) for each modulation index. The original sinusoidal reference (Yx) used for the conventional DPWM1 method is modified by the information stored in a look-up table to achieve voltage waveform that reduces the low-order harmonics. ZSS =1 3{Y∗ ae +Y∗ be +Y∗ ce}(17) Yxe = (Y∗ xe −ZSS)(18) This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3219120 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. 6 100 20 30 40 50 DPWM1 eDPWM1 Ma= 0.85Ma= 0.35 Harmonic (n) Current ( C n = n) Yxe 0 5 10 15 200 5 10 15 20 100 20 30 40 50 Time (ms)Time (ms) Harmonic (n) a b c d 0 1 -1 0 0 0.2 0.4 0.6 0.8 1.0 1 -1 Yxe * e f Fig. 11. Theoretical CB-PWM references and current harmonics for Ma= 0.35 and Ma= 0.85 a-b) Yxe c-d) Y∗ xe e-f) Current harmonics Cn/n ∆Y=Yxe −Yx(19) For some representative operating points corresponding to Ma= 0.35 and Ma= 0.85, Yxe and Y∗ xe modulator references are represented in Fig. 11, showing that in comparison with the conventional DPWM1 strategy, the reference signal Yxe for the eDPWM1 method is not anymore a pure sinusoidal waveform, but it is a reference that keeps the same fundamental phase and amplitude while reducing the low-order harmonics. The harmonic spectrum applying the proposed eDPWM1 and the original DPWM1 are also compared in Fig. 11 in terms of output current quality by weighting Cndifferential voltage harmonics by the harmonic order as Cn /n. The results show that the eDPWM1 method is able to effectively reduce those low-order harmonics that were included in the cost function F. III. NPC MIDDLE-POINT VOLTAGE REGULATION FOR THE EDPWM1 METHOD One of the main challenges for the stable operation of threelevel NPC inverters is to keep balanced the voltage across the two dc-split capacitors Vdc,1and Vdc,2. When the modulation is synchronized with its fundamental frequency, even harmonics are cancelled and the average DC-link midpoint current (Io) becomes zero, leading to a theoretical natural balance of the middle point voltage [15]. However the presence of any unexpected dc-link unbalance caused by devices mismatching or load transients, requires to design a middle-point voltage control strategy. In this way, DC-link mid-point current waveform (io) is defined by the sum of the the instantaneous phase currents (ix) of the phases that are generating a phase voltage equal to zero. io= 3 X x=1 ix⌋∀x/Vx=0 (20) In order to get the dc-link voltage balance, the main idea is to modify the original eDPWM1 waveform with the aim of injecting an average middle point current Ioas it was introduced in [24], [25]. In this way, the DC-link balance control can be achieved by modifying the theoretical modulating references taking into account the instantaneous output current, so that an average value of the middle-point current Iodifferent to zero is established within one fundamental period. The proposed middle point voltage regulation diagram is represented in Fig. 13, where DC-link unbalance is controlled by means of a PI controller that defines the amplitude (Mvo) of the offset signal (Yvo) to be added to the modulating reference. In this way, the modified modulating references can be calculated as: Yvo∗ xe =Y∗ xe +kvo kdpwm Mvo == Yvo (21) where kvo takes values equal to ±1 depending on the criterion summarized on Table II, which takes into account in each phase both the modulating reference sign and the phase current sign [24], [25]. It is also important to note that modulating references are not allowed to be modified within the clamping instants, defining the factor kdpwm that is equal to zero when the phase state is clamped or is equal to one in other instants. As an example of its application to the eDPWM1 method, the resulting modulating references and the middlepoint current waveform are represented in Fig. 12, where it can be observed how the compensated modulating references (Yvo∗ xe ) are slightly modified to achieve an average Iocurrent that enables the DC-link voltage balance control. In the proposed dc-link voltage controller the input error to the regulator (ϵvo) is fed from the DC-link unbalance, after filtering out dominant third order harmonic at middle point voltage (vo) [11]. It is important to note that despite of modifying the converter voltage waveform when middle point regulator is active, this action is negligible at steady state conditions when the dc-link capacitor voltages are balanced. Therefore, in steady state, the NPC inverter will apply the precalculated switching angles βkthat have been obtained by the eDPWM1 method. TABLE II kvo CALCULATION Y∗ xe ixkvo + + +1 + - -1 - + -1 - - +1 This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3219120 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. 7 -1.0 -0.5 0.0 0.5 1.0 -1.0 -0.5 0.0 0.5 1.0 032 b a Compensated No compensated Yxe vo* io Fig. 12. Average middle point current injection a) Modified modulating reference by Yvo offset b) middle point current waveform and mean value Vdc ,1 V dc ,2 + - Mvo v o kvo k dpwm Y vo evo PI Fig. 13. NPC converter middle-point voltage regulation scheme. IV. SIMULATION STUDY The proposed eDPWM1 method with middle-point voltage regulation scheme is verified in a three-level NPC inverter supplying a close to unity power factor RL load, with operational conditions resumed in Table I and Table III. The objective of these simulations is to validate the middle-point voltage control and to check the feasibility of the eDPWM1 method in order to obtain a superior harmonic performance. The middle point voltage regulator has been tested under transient conditions by adding an external perturbance to one of the DC-link capacitors. This perturbance is introduced in Fig. 14 at time instant t= 1s, causing voltage imbalances reaching 500V at the DC-link. It can be seen that, once the capacitor voltages are fully balanced, Yvo reaches ideally zero output, so that modulating references used in the CB-PWM scheme closely correspond to precalculated βkswitching angles. In order to show the performance of the proposed eDPWM1 method in steady state, the obtained differential line-to-line TABLE III SIMULATION SETUP PARAMETERS Parameter Value DC bus Vdc,i 2600 V Capacitance Cdc 8 mF Load Resistance R10 Ω Load Inductance L2mH Fundamental frequency fo50 Hz -0.1 0 0.1 0 1 2 3 4 5 2.2 2.4 2.6 2.8 3.0 Time (s) Voltage (kV)Balance control a bVdc,1 Vdc,2 Mvo evo(x5000) Fig. 14. NPC middle-point voltage regulation a) PI regulator evo and Mvo b) Vdc,1and Vdc,2 Current ( C n = n) Voltage ( C n ) 010 20 30 40 50 0.0 0.5 1.0 0.0 0.5 1.0 010 20 30 40 50 Harmonic order (n)Harmonic order (n) DPWM1 eDPWM1 Ma= 0.85 Ma= 0.35 a b c d Fig. 15. Waveform spectrum for Ma= 0.35 and Ma= 0.85 a-b) voltage c-d) current voltage harmonics have been compared, weighting these by harmonic order as per Cn /nto show the current waveform quality. Considering the same operating points introduced in the theoretical study shown in Fig. 11, both obtained voltage and current harmonics from Fig. 15 show a close correlation with the theoretical results, validating the neglectable contribution to harmonic distortion of middle point voltage regulator, and showing the feasibility of proposed eDPWM1 implementation to minimize the low-order harmonics defined in cost function F. V. EXPERIMENTAL RESULTS The performance of the proposed eDPWM1 method has been experimentally verified in the down scaled laboratory setup represented in Fig. 16, that is a three-level NPC inverter built with Infineon FZ600R17KE3 power devices, and controlled by a 32-bit Digital Signal Processor (DSP) from Analog This article has been accepted for publication in IEEE Transactions on Industrial Electronics. This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3219120 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. 8 DSP Threee-level NPC Inverter DC-Link capacitors Fig. 16. Three-level NPC converter prototype Devices. The system layout in Fig. 1 shows an external 12- pulse rectifier used to feed power to the DC-link, with a close to a unity power factor three-phase RL load connected at the AC output. The modulation algorithm is programmed at the DSP, synchronizing output waveform and combining conventional CB-PWM scheme with previously precalculated tables for low-order harmonic optimization in eDPWM1 method (including in the cost function Fodd non-triplen harmonic orders up to 19th). The control parameters that have been used during the experiments are summarized in table IV, having the same mfratio as the previously reported case for 1350 Hz carrier frequency and 50 Hz fundamental output frequency. In order to compare the conventional DPWM1 method and the proposed eDPWM1 technique, Fig. 17 represents the differential voltage and current harmonic spectra. It can be clearly observed that applying the eDPWM1 method, the loworder harmonics have been minimized. The factor WTHDpu LF considered in the cost function F represents the amount of low-order current harmonics to be minimized. The values obtained during the experimental tests are represented in Fig. 18-a, showing that the obtained performance is similar to the theoretical one, leading to distortion TABLE IV SETUP PARAMETERS Parameter Value DC bus Vdc,i 220 V Capacitance Cdc 4.95 mF Load Resistance R22 Ω Load Inductance L2.5mH Carrier frequency fc1350 Hz Fundamental frequency fo50 Hz mf27 NLF 19 factors below 10% for a wide modulation index range. In the same way, the low-order distortion factor THDpu LF has been also minimized by applying the eDPWM1 method, as it can be seen in Fig. 18-c, achieving values below 5% for a wide modulation index range. On the other hand, total weighted harmonic distortion factor WTHD50, represented in Fig. 18-b, keeps similar values for both methods, but slight reductions for the eDPWM1 method are observed for the higher modulation index range. Finally, in Fig. 18-d the obtained values of the THD50 factor are represented. In this case, it is clear that the definition of the cost function Fforces the eDPWM1 method to move the loworder harmonics to higher frequency orders contributing to a slight increase in the THD50 factor. VI. CONCLUSIONS This paper proposes a new approach to develop an enhanced DPWM method reducing the low-order harmonics when low carrier to fundamental ratios are used. By using the preprogrammed PWM techniques basic concepts, the flexible switching angles allowed to vary within the DPWM frame are modified, so that harmonic profile of the output voltage is modified. In order to perform the optimization, a cost function to be minimized is defined considering low-order current harmonics distortion, while keeping fixed switching frequency, and generating the desired fundamental voltage amplitude and phase. The obtained switching angles are translated to generate the corresponding modified references, so a conventional CBPWM scheme can be used to generate the gate pulses. From the theoretical and experimental tests, the superior ability of the proposed eDPWM1 to reduce low-order voltage and current harmonic compared with the conventional DPWM1 method is demonstrated. It has to be pointed out that same methodology might be used to reduce low-order harmonic content of other DPWM methods by considering their specific clamping periods to define the switching pattern (including fixed and flexible switching angles). REFERENCES [1] H. Akagi, “Multilevel converters: Fundamental circuits and systems,” Proceedings of the IEEE, vol. 105, no. 11, pp. 2048–2065, 2017. [2] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. 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Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information. 9 Minimized harmonic components (n) with eDPWM1: [5, 7, 11, 13, 17, 19]DPWM1 eDPWM1 Ma= 0.20 Ma= 0.35 Ma= 0.75 Ma= 0.85 Ma= 0.95 0.0 0.4 0.8 1.2 0.0 0.4 0.8 1.2 100 20 30 40 50 Harmonic order (n) 100 20 30 40 50 Harmonic order (n) 100 20 30 40 50 Harmonic order (n) 100 20 30 40 50 Harmonic order (n) 100 20 30 40 50 Harmonic order (n) Current (C n = n) Voltage (C n ) a b c d e fgh i j Fig. 17. Comparison of experimental voltage waveforms harmonic spectra for different modulation indexes. From a) to e) Voltages (Cn). From f) to j) Currents (Cn) /n WTHD LF pu WTHD50 THD50 THD LF pu DPWM1 eDPWM1 0.2 0.4 0.6 0.8 1.0 Modulation index (Ma) 0.2 0.4 0.6 0.8 1.0 Modulation index (Ma) 0 0.1 0.2 0.3 0.4 65 75 85 95 105 115 0 0.2 0.4 0.6 2.0 2.4 2.8 3.2 3.6 4.0 d a c b Fig. 18. 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This is the author's version which has not been fully edited and content may change prior to final publication. Citation information: DOI 10.1109/TIE.2022.3219120 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See https://www.ieee.org/publications/rights/index.html for more information.