A thermal analysis for two modulation and control approaches for five-level diode-clamped rectifiers

1 A thermal analysis for two modulation and control approaches for five-level diode-clamped rectifiers Pablo Montero-Robina, Francisco Gordillo Abstract—This paper compares two recently published modulation and control approaches for a grid-connected five-level diode-clamped rectifier in terms of conducting losses. In this way, a prior analysis of the conducting time at steady state is presented for both approaches, and the usage of the most stressed switching device is calculated. The usage for this switching device is then compared with a typical nearest-two-level modulation strategy to show the efficiency of the studied approaches. Some simulations are also carried out to validate this comparison. Index Terms—Multilevel converters, Thermal analysis, Diode-clamped converter, Power control and modulation I. INTRODUCTION The increasingly demand of cleaner, more flexible and more reliable electric energy is making a revolution in the power electronic scenario as new devices, topologies and algorithms are arising as a response to this demand [1]–[3]. In this context, device temperature concern is leading a new concept of power converter designing known as thermal management [4]. This is due to the undesired effects that high temperature or temperature changes may have on power device reliability and durability [5]. Consequently, temperature is a key point that has to be taken into account in order to extend power device lifetime [6]. The current going through each power device creates a power flow that yields cyclic heating and cooling intervals. Considering the different thermal expansions coefficients of the components inside the power device, these intervals create mechanical stress that are translated to aging and, consequently, reduced lifetime expectancy [5], [7]. Therefore, it is critical to reduce its magnitude such as to reduce long-term expenses [8]. In this sense, active thermal control (ATC) takes into account these effects to modify the overall performance such as to reduce the amplitude of these cycles or the averaged temperature level [9]. At the same time, the device temperature monitoring and the junction temperature estimation have become of great importance to estimate the power device health state and also to allow the active thermal control to act accordingly [10]. On the other hand, an appealing topology of converters, referred as multilevel ones, offers several advantages regarding grid current distortion and power device voltage limits, although the use of them entails more semiconductors devices in the system [11]. Depending on the topology, some semiconductors might be closed longer than others which entails more conducting losses and therefore bigger thermal aging effects. As a consequence, these devices are more likely to reach its lifetime end than the others which highly increase the cost of maintenance. As a result, several studies have been carried out to consider the thermal management into the control of multilevel converter [12]–[14]. One of the most common multilevel converter topologies used in the industry is the diode-clamped converter (DCC) [15]. In this regard, the three-level kind has been well accepted and spread along plenty of industrial applications [16]. However, the actual research on the five-level one has still room for improvements. That is why this paper focuses on the five-level diode-clamped converter topology and analyzes two of the modulation and control approaches previously published [17] that tackles the capacitor voltage unbalance issue. In the cited publication, the approaches are based on considering the duty ratios of each voltage level for each phase and modelling the current control and capacitor voltage unbalance with these variables. As a result, they consider all possible levels within a switching period. This fact could yield higher switching losses than other ones, although it could make the dissipated power to be more equally distributed among the semiconductors, reducing the thermal cycles and aging. Therefore, this paper revisits the two proposed approaches and compares them in terms of thermal effects. The outline of the paper is as follows: Sect. II summarizes the used model, control and modulation 2 Fig. 1. Schematic of 5-level DCC approaches; Sect. III presents a thermal analysis of this topology with the cited approaches; Sect. IV presents several simulations and its main comparisons; and, finally, Sect. V draws some conclusions about the contribution. II. MODEL, CONTROL AND MODULATION APPROACHES This paper focuses on a five-level DCC shown in Fig.1 . The modelling, control and modulation approaches used in this paper are retrieved from [17] and summarized in the next subsections. A. Five-level DCC Model The dynamics of the system are modelled using variables averaged over a switching period Treferred as duty ratios. These duty ratios dij P r0,1s are labelled for each phase i“ ta, b, cuand each level j“ t1,2,3,4,5uand reflects the part of a period Tthat phase ioutput is connected to level j, therefore ř5 jdij “1which is a restriction for each phase. By performing a Clarke transformation using the power invariant form, the duty ratios can be expressed in αβγ frame instead of the abc one. The main advantage of doing so in a three-phase system is that variables dγj are related to the zero-sequence component of the voltage output and therefore, they do not appear in the current dynamic. In this way, their value do not affect the current controller as long as saturation is avoided—i.e. 0ďdij ď1— and they will be considered as degrees of freedom. Defining the desired normalized output voltage of each phase as ukfor k“ tα, βu, its value can be achieved in averaged terms by fulfilling uk“ ´2dk1´dk2`dk4`2dk5, (1) where duty ratios dk3do not appear and therefore they will be obtained in abc frame by applying the ř5 jdij “1restrictions. As a consequence, there are still 8 duty ratio values to obtain. Notice that component γhas been omitted due to the reason stated previously. Regarding the capacitor voltage unbalance, there are four signals to balance which yield three unbalancing signals referred as tvd1“vc4´vc1, vd2“vc3´vc2, vd3“vc2´vc1u. Considering the previous definition of duty ratio in αβ frame, the dynamics of these signals can be expressed accordingly, Cdvd1 dt “ ´iαpdα5`dα1q´iβpdβ5`dβ1q(2) Cdvd2 dt “ ´iαÿ j“t1,2,4,5u dαj ´iβÿ j“t1,2,4,5u dβj (3) Cdvd3 dt “ ´iαdα4´iβdβ4(4) B. Control Algorithm Usually, in grid-connected rectifier applications, variables uα, uβcome from the application of the current controller such as to achieve current and dc-link voltage regulation. Accordingly, it is assumed that a PI Controller, for the dc-link voltage regulation, is set in cascade with a proportionalresonant current controller [18] that results in the values of uα, uβ. In summary, once that variables uα, uβare known, two restrictions are obtained from (1). The remaining six conditions comes from the balancing control. Inspired by (2)–(4), control signals tu3, u4, u5, u6, u7, u8uand their corresponding control laws are defined such that u3“ pdα5`dα1q “ kbal iαvd1(5) u4“ pdβ5`dβ1q “ kbal iβvd1(6) u5“ÿ j“t1,2,4,5u dαj “kbal iαvd2(7) u5“ÿ j“t1,2,4,5u dβj “kbal iβvd2(8) u7“dα4“kbal iαvd3(9) u8“dβ4“kbal iβvd3,(10) where kbal is the balancing control parameter. In this way, the balancing is achieved at the same time that the 8 duty ratios are fully determined. 3 C. Modulation Stage The duty ratios computation is straightforward but for the value of dγj left as a degree of freedom until this stage. Considering the previous steps, duty ratios dαj, dβj for j“ t1,2,4,5uare known so it can be returned to abc frame once the corresponding dγj is also known. In this sense, two approaches are presented: the first one considers fixed values of dγj, whereas the second one selects the values of dγj that makes one duty ratio dij equal to zero. By doing so, the phase iwith a duty ratio dij “0 does not commute at level j, avoiding additional commutations. ‚Approach 1: dγj “kγj ‚Approach 2: dγj “max ˜ ´?2dαj,dαj ?2´dβjc3 2,dαj ?2`dβjc3 2¸, for j“ t1,2,4,5u, where kγj are constant values and max is the function that retrieves the maximum value. However, in [17], approach 2 for j“ t2,4u is not always applied as it could introduce ”large jumps” within one switching period. Thus, duty ratio di2or di4could be equal to zero only in case di1or di5turned out to be also zero respectively, otherwise it applies the same law than approach 1 for the corresponding level. For the theoretical comparison, this latter restriction is skipped such as to emphasize the differences in both approaches. In this way, the values of dij for each phase iand j“ t1,2,4,5uare obtained by using the inverse Clarke transformation. The remaining duty ratios di3 are obtained from the řj“1Ñ5dij “1restriction. Finally, once all duty ratios are known, the levels they generate can be sequenced in a saw-tooth or stair-shaped waveform within a switching period to generate the voltage output of each phase. III. CONDUCTING LOSSES OF THE STUDIED APPROACHES It can be noted that the previous modulations will yield different losses profiles as the conducting time and turning-on/off cycles of the power devices differ depending on the levels used. The higher the duty ratio, the higher the conducting time of the power devices. Regarding the switching losses, they highly depends on the switching frequency, the point of operation and how the levels are sequenced, however in multilevel converter, as the device blocking voltage is reduced by the introduction of several levels, its effect is considerably reduced in comparison with two level topologies. Nevertheless, a tradeoff comparison dependant of the operating point has to be made to determine which is the most suitable approach. Because of this, the switching losses has not been considered in this analysis as it would not yield any straight conclusion. Thus, the analysis will focus on a generic phase iand the conducting losses of the four upper semiconductors tSi 1, Si 2, Si 3, Si 4uconsidering that the lower ones will have a symmetrical behaviour. Also, no dead time is considered as it can be emulated as an extension of the duty ratios [19]. Notice that whenever a switching device Si nis open, its complementary lower-side one Si nis closed. Hence, it is straightforward that four switching devices will be always connected. It is also worth to mention that the current will not always go through the switching device but through the anti-parallel diode depending on its direction, changing the losses profile. However, considering the periodical behaviour of the phase current and that this paper aims for a comparative analysis, it can be made assuming the worst-case conducting losses, usually the ones that are generated by the switching devices (iiď0). In this way, a variable called switching device usage Si n ucan be modelled as Si 1 u9“#di5|ii|if iiď0 0if iiě0 Si 2 u9“#pdi5`di4q|ii|if iiď0 0if iiě0 Si 3 u9“#pdi5`di4`di3q|ii|if iiď0 0if iiě0 Si 4 u9“#pdi5`di4`di3`di2q|ii|if iiď0 0if iiě0, (11) which represents the averaged current that goes through the device Si nover a switching period. The greater this value, the greater the conducting losses. A well-known approach to estimate the module’s lifetime is the Coffin–Manson–Arrhenius model [20] that provides the number of cycles to fail (N). This model highlights the importance of 4 the cycling effect on the lifetime expectancy: the greater the temperature range of the cycle or the maximum reached temperature the smaller the value of N. Consequently, these two parameters would have to be managed to provide thermal management of the devices. To retrieve how dγj affect them, let us consider that the value of dγj increases monotonically the value of all duty ratios of level j. Notice that at steady state, uα“c3 2Ucospωtq, iα“c3 2Icospωt `σq uβ“c3 2Usinpωtq, iβ“c3 2Isinpωt `σq u3,...,8«0(12) where U, I are the amplitude of the normalized output voltage and the phase currents in abc respectively; σis the phase-shift of the currents; and ωt is the grid angle. Also, consider that from (12) and (5)–(10), variables dαj and dβj for j“ t2,3,4uare equal to zero. Therefore, from (1) and (11) Si n u“¨ ˝TαβÑirdα5dβ5sT`ÿ j“t5,...,6´nu dγj{?3˛ ‚|ii|(13) dα5“uα 4;dα1“ ´uα 4(14) dβ5“uβ 4;dβ1“ ´uβ 4,(15) for n“ t1,2,3,4u,iiď0and being TαβÑi the transformation vector from αβ to phase i. Hence, the differences in the switching devices usage among phases is highly dependant on the values of the product řdγj|ii|. On the other hand, the differences in the device usage within the same phase at steady state relies mainly in the dγj value. The lower its value for level j, the more similar the usage for devices inside range nă6´jand range ně6´j. According to the studied approaches and the steady state conditions, the value of řdγj|ii|are: - Approach 1: ÿ j“t5,...,6´nu pdγjq|ii| “ÿ j“t5,...,6´nu pkγjq|ii|(16) - Approach 2: ÿ j“t5,...,6´nu pdγjq|ii|“#dApp2 γ5|ii|nď2 pdApp2 γ5`dApp2 γ3q|ii|ną2(17) where dApp2 γj is the value of dγj according to the second approach. Notice that dApp2 γ2“dApp2 γ4“0 because of the steady state condition . The values of the first approach depends on the user, but the second ones are retrieved from the approach algorithm. Besides, notice that dγ3for any approach can be obtained from applying the Clarke transformation to the restriction of ř5 j“1dij “1which results in the condition ř5 j“1dγj “?3. Therefore, the second approach can be applied at steady state in (17) and, in addition to (16), replaced into (13) to retrieve the general usage for the switching device Si n u. For the sake of comparison, the usage of Si 4 u—the most used switching device among the upper ones—will be depicted. Figure 2 shows the value of the usage Si 4 uwhen U“1.60 and normalized current along a grid period and different values of σ. The first approach is depicted as a mesh, while the second one is depicted as a surface. On the other hand, Fig. 3 depicts the results of integrating Si 4 uover a grid period as a function of σfor different values of Ufor the first and second approach and also for the two nearest level modulation. Notice that σis directly related to the power factor as PF “cospσq. Such as to picture the different performance of the approaches and the two nearest level modulation, Fig. 4 depicts the duty ratios of each switching device Si 1,...,4. It can be seen that the PF barely changes the overall usage and that the first approach offers a lower usage compared to the 2nd approach and twolevel modulation. The first being better than the second is due to the minimization of the dγ5and dγ1 values that reduces the commutations, but increases considerably the value of dγ3which yields to more conducting time of the devices Si 3and Si 4. Besides, the bigger the duty ratios of levels 2,3,4, the greater the usage for Si jwith j“ t2,3,4uin comparison with Si 1which yields in different number of cycles to fail. IV. SIMULATION RESULTS This section will present some results from applying the mentioned approaches into a model. The modulation algorithm is directly extracted from [17] and straightly applied to the model. The simulation parameters and circuit parameters are presented in Table I. To simulate different values of σ, three tests for each approach have been carried out where 5 Fig. 2. Usage Si 4 ufor U“1.60 and normalized current along a grid period and different values of σ. Approach 1 is depicted as a mesh (red) while approach 2 is depicted as a surface (blue). Fig. 3. Integral of the usage over a grid period considering different values of σand Ufor the first approach, the second approach and the two nearest level modulation. Fig. 4. Duty ratios of switching devices tSi 1, Si 2, Si 3, Si 4ufor the first approach (App1), the second approach (App1) and the nearest two level modulation (2L). the reactive power reference (Qr) and the dc-link resistor value (R) change as shown in Table I. TABLE I SIMULATION AND CIRCUIT PARAMETERS Parameter Value Parameter Value L2 mH C3300 µF vdc 800 V vgrid 220 Vrms kbal 2¨10´4kγ2,40.1 kγ1,5p?3´0.25q{2Rrinf,43,infsΩ Qr[-25,-10,5] kVA fsw 10 kHz Similarly, these applied conditions resulted in the values of U“ t1.4,1.47,1.6uat steady state. Figure 5 summarizes the results of the simulations where the main differences in the two approaches and the nearest two level modulation can be seen. The switching states are depicted in the first graph where it can be seen that, whereas the Approach 1 (App1) use all level every switching period, Approach 2 (App2) skip some of them. Similarly, the second graph shows the current through Sa 4 including the anti-parallel diode. Notice again that Approach 1 conducts every period, in contrast to Approach 2. However, by looking at the third graph where the conducting losses are depicted according to the integrated IGBT model 5SNA1600N170100, it can be seen that the overall conducting losses are worse for Approach 2 when the current goes through the device (iaď0). Considering this, it can be said that Approach 1 offers a better profile for the conducting losses that, in global terms, will yield less thermal stress for the device. On the other hand, the conducting losses when the current goes through the diode is worse for the Approach 1 than the Approach 2, although diodes has usually 6 Fig. 5. Simulation results for the two approaches and the two level modulation approach for the three test considered in phase a. Upper graphs show the switching states; upper-mid graphs show the current thorugh the device Sa 4; lower-mid graphs show the conducting losses computed in simulation; and lower graphs show the normalized current and output voltage for phase a. Fig. 6. Switching losses (W) of the approaches considered with a switching frequency of 10 kHz. The turn-on and turn-off energy has been retrieved from the datasheet of model 5SNA1600N170100 at 25 oC. longer life expectancy and less voltage drop than the switching devices. Therefore, its impact on the equipment life expectancy is less strident. In any case, both approaches offer a better profile for the conducting losses than the two level modulation approach. Not only its integral is smaller but also the conducting losses are more ”spread” over a grid period, reducing the thermal cycling effect. In spite of not considering the switching losses in the analysis, for the approaches considered here, the first one yields a large number of commutations: 4 transitions per switching period; the second one yields less commutations: between 2 and 4 transitions per period; whereas the nearest two level modulation offers the best performance in this regard: 1 transition per period. Nevertheless, for the sake of comparison, Fig. 6 shows the switching losses of device Sa 4using the same IGBT model for these approaches under the three tests carried out. It can be seen that two nearest level modulation could cut down the switching losses to a 25% of those of the Approach 1, whereas the second could do so down to 67% depending on the test considered. It is also worth to mention that the two nearest level modulation offers the lowest switching losses but it could not be applied with no modification as it does no tackle the capacitor voltage balance issue. Any other approach which does so will increase the switching losses as more transitions will be inserted. Consequently, once the operating conditions are known, a trade-off comparison between conducting losses and switching losses has to be considered such as to select the more appropriate algorithm. V. CONCLUSIONS A brief conducting losses analysis of two modulations approaches for grid-connected five-level DCC has been presented in this paper. The results are also 7 compared with the well-known two nearest level modulation approach resulting in one modulation offering the better profile in terms of conducting losses. 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