A 4.2–13.2 V, on-chip, regulated, DC–DC converter in a standard 1.8V/3.3V CMOS process

Int. J. Electron. Commun. (AEÜ) 161 (2023) 154527 Available online 7 January 2023 1434-8411/© 2023 The Author(s). Published by Elsevier GmbH. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/). Contents lists available at ScienceDirect Int. J. Electron. Commun. (AEÜ) journal homepage: www.elsevier.com/locate/aeue Regular paper A 4.2–13.2 V, on-chip, regulated, DC–DC converter in a standard 1.8V/3.3V CMOS process✩ David Palomeque-Mangut∗, Ángel Rodríguez-Vázquez, Manuel Delgado-Restituto∗ Instituto de Microelectrónica de Sevilla (CSIC - Universidad de Sevilla), Sevilla, Spain ARTICLE INFO Keywords: Charge pump High voltage compliance DC–DC converter Neural stimulation CMOS Power management Switched-capacitor ABSTRACT This paper presents a fully on-chip HV-regulated DC–DC boost converter for the power management unit of an electrical neural stimulator. The core of the DC–DC converter consists of a 4x4 array of individuallyconfigurable charge pumps. The rows and columns of the array can be dynamically enabled or disabled, thus extending the range of suitable output voltages and load currents. Additionally, the converter includes a feedback loop for output voltage regulation which allows responding to abrupt changes in the load current within a few microseconds. The circuit has been designed in a standard 180 nm 1.8V/3.3V CMOS process and occupies an active area of 2.1mm2. An exhaustive experimental characterization of the proposed circuit was carried out. Experimental results demonstrate that, for an input voltage of 3V, the DC–DC converter’s regulated output ranges from 4.2V to 13.2V under load currents of 0.1–4 mA. Maximum delivered power is around 48mW. The power efficiency of the converter at the highest achievable output voltage under a 4 mA load current is higher than 65% for input voltages above 2.4V. 1. Introduction Electrical modulation using implantable devices with arrays of stimulating electrodes is an emerging therapy for neurological diseases. Some examples of neuromodulation devices include prostheses for spinal cord injury; cochlear auditory implants; retinal and cortical visual prostheses; vagus nerve stimulators for epilepsy and depression; or deep brain stimulators for essential tremors and Parkinson’s disease. These devices are often combined with a neural recording section for evaluating, and eventually adapting, the stimulation on the tissue, thus resulting in a closed-loop architecture, as shown in Fig. 1. Further, neural implants are often supplied by a wireless power transmission (WPT) mechanism to avoid the use of bulky batteries [1–4]. The efficacy of these implants ultimately depends on their ability to trigger a functional response in the target tissue by inducing a flow of current between two or more electrodes. This is typically done by applying a series of biphasic current pulses with cathodic and anodic phases whose amplitudes and durations are adjusted to result in an overall zero net charge in the tissue [5,6]. A major concern in the implementation of stimulators is the impedance at the Electrode- Tissue Interface (ETI). Such impedance depends on the geometry and materials of the electrodes; the physiological parameters of the tissue; ✩This work was supported by grant PID2019-110410RB-I00, funded by MCIN/AEI; and by grant 310 N00014-19-12156, funded by US Office of Naval Research. David Palomeque-Mangut’s work has been supported by the Spanish Government (FPU18/00247). ∗Corresponding authors. E-mail addresses: [email protected] (D. Palomeque-Mangut), [email protected] (Á. Rodríguez-Vázquez), [email protected] (M. Delgado-Restituto). and the degree of electrical contact at the stimulation zone [5]. Further, the interface is not stationary in nature, and the impedance changes throughout the life cycle of the implant. These factors make that the stimulation currents practically range from some tens of μA up to some mA and that the voltage compliance of the current drivers varies from a few volts up to over 10V [7–10]. To withstand such a broad range of current/voltage values, it is fundamental that the power management unit of the implant, on which this work focuses, includes a programmable DC–DC converter with adjustable Voltage Conversion Ratio (VCR) to guarantee that the stimulator operates under safety limits without excessive power dissipation [11], particularly, when the ETI equivalent impedance and/or the stimulation currents are large. Additionally, to relax the power transfer specifications of the WPT mechanism, the efficiency of the DC–DC converter should reach its peak for large stimulation currents for which the availability of electrical power is more demanding. According to our simulations, the WPT link, currently under design [4], is capable of providing supply voltages around 2.7V, therefore, the DC–DC converter should operate correctly at those input voltage levels. Last but not least, the DC–DC converter should react rapidly under variations of the load current as occurs in electrical neurostimulation, and use no external component to reduce the form factor of the implant. https://doi.org/10.1016/j.aeue.2023.154527 Received 17 October 2022; Accepted 1 January 2023 AEUE - International Journal of Electronics and Communications 161 (2023) 154527 2 D. Palomeque-Mangut et al. Fig. 1. Block diagram of a neural implant. Fig. 2. Simplified schematic of the proposed HV regulated DC–DC boost converter. These aspects are addressed in this work, where a versatile fully onchip High-Voltage (HV) DC–DC boost converter for neuromodulation applications is proposed. Instead of using an HV CMOS node, the converter is implemented in a standard 1.8V/3.3 V 0.18μm CMOS process to allow for a single-chip neural implant integration, along with other elements already designed in this technology [12]. The use of standard processes for the generation of voltages above the nominal supply of the technology demand for circuit solutions that guarantee that voltage drops across devices are safely below the breakdown limits. The approach has been also followed in previous contributions [9,13– 18]. However, these solutions present some drawbacks such as the lack of output voltage regulation [14], usage of off-chip capacitors [14,18], generation of a fixed output voltage [9,18], low load current driving capability [14,15,17,18], or low VCR [16]. Fig. 3. Block diagram of the charge-pump array. Signals 𝑉𝑐,𝑗 are voltage-shifted versions of 𝐶𝑗which are distributed per column in the array. The architecture, components, and operation modes of the proposed DC–DC converter, described in Section 2, have been specifically designed to overcome these shortcomings. This is illustrated in Section 3, where experimental results are presented and discussed. The paper concludes with some remarks in Section 4. 2. System architecture and circuit design Fig. 2 shows the proposed HV-regulated DC–DC converter. It consists of three main blocks: (1) an 𝑀×𝑁array of charge-pumps (CP) driven by the input voltage 𝑉𝑖𝑛, (2) a Voltage-Controlled Oscillator (VCO) based feedback loop which regulates the output voltage of the CP array 𝑉𝑜𝑢𝑡 against variations of the load current 𝐼𝐿by adjusting the pumping clock frequency 𝑐𝑙𝑘, and (3) a programming interface for enabling/disabling rows or columns in the array and for generating a set of clock phases from 𝑐𝑙𝑘. The output of the array is loaded with a 125pF Metal-Oxide-Metal (MOM) capacitor 𝐶𝑜𝑢𝑡 to attenuate voltage ripples. The feedback loop and the programming interface are supplied at 𝑉𝐷𝐷 = 1.8𝑉. The logic high of the clocks driven the CP array, Φ𝑗 and Ψ, and the row/column cell selection variables, 𝐑and 𝐂, are boosted from 𝑉𝐷𝐷 to 𝑉𝑖𝑛 by means of conventional level shifters based on differential cascode voltage switch logic [19]. 2.1. Charge-pumps array and programming interface In the proposed implementation, the array comprises 16 structurally identical CPs distributed in a 4 ×4 architecture (𝑀= 4,𝑁= 4), as shown in Fig. 3. The outputs of all the CPs in the same column are connected together. Active rows and columns are enabled using the 𝐑= {𝑅𝑖}, 𝑖 = 1,…,4, and 𝐂= {𝐶𝑗}, 𝑗 = 1,…,4, configuration bits, respectively (see Fig. 2). All possible row combinations, 16 in total, are possible. However, a column can only be activated if the previous one is enabled and, therefore, only 4 combinations are possible. Extensions for different numbers of rows, 𝑀, or columns, 𝑁, is straightforward, whenever the breakdown voltages of the CMOS process are not exceeded. In the selected process, the parasitic pn-junctions of PMOS and DNW-NMOS transistors have breakdown voltages above 14V, and transistors can withstand voltage differences of up to 3.3V. Consequently, the number of columns in the presented design has been set to 𝑀= 4 and the maximum input voltage has been set to 3V, to give some margin against transient spikes during switching. AEUE - International Journal of Electronics and Communications 161 (2023) 154527 3 D. Palomeque-Mangut et al. Fig. 4. Schematic and symbol of the floating level-shifter for sliding configuration bits. The voltage levels of 𝐑and 𝐂have to be adjusted according to the cell position in the array. Namely, it has to be guaranteed that the transformed variables are comprised between the input 𝑉𝐶𝑃 ,𝑗−1, and the output, 𝑉𝐶𝑃 ,𝑗 of the cell (by construction, 𝑉𝐶𝑃 ,0=𝑉𝑖𝑛, i.e., the input voltage of the array). This is done by means of High-Voltage Floating Level Shifters (HV-FLS) [20,21]. The schematic and symbol of an HV-FLS are shown in Fig. 4. Assuming the control signal IN is comprised between ground and 𝑉𝐷𝐷, the circuit generates a voltageshifted version, 𝑂𝑈𝑇 , which swings from 𝑉𝑆𝑆𝐻 to 𝑉𝐷𝐷 +𝑉𝑆𝑆𝐻. As capacitors 𝐶1𝑥−𝐶2𝑥(𝑥stands for 𝑎or 𝑏) are periodically refreshed with Ψ= {𝜓𝑘}, 𝑘 = 1,…,4, the circuit can tolerate non-periodical IN signals or variations of the shifting voltage, 𝑉𝑆𝑆𝐻 – see [21] for more details. Fig. 5(a) shows the timing diagram of clock Ψ, which is generated at the programming interface from the 𝑐𝑙𝑘 output of the regulation loop (see Fig. 2). Clock Ψis made 8×slower than Φby means of a clock divider to save power consumption. Fig. 6 shows the schematics of the CP core. It follows a crosscoupling architecture [22,23]. Besides the main charge pumping stage (𝑀1𝑥−𝑀2𝑥and 𝐶1𝑥), it includes two auxiliary charge-pump circuits (𝑀3𝑥−𝑀4𝑥and 𝐶2𝑥−𝐶3𝑥) for boosting the conductivity of the core transistors; one HV-FLS integrated within the CP cell for level-shifting the selection bits 𝑅𝑖and 𝐶𝑗to 𝑉𝑐𝑒𝑙𝑙,𝑖𝑗 ; and switches (𝑀5𝑥−𝑀6𝑥). The flying capacitors (𝐶1𝑥−𝐶3𝑥) nominally have a capacitance of 𝐶𝑓𝑙𝑦 = 12.5pF. They are implemented with a single metal–insulator–metal (MIM) structure in the cells located in the first and second columns of the array; however, the CPs in the third and fourth columns use two series-connected MIM capacitances to support higher voltages. Deep n-well NMOS transistors were employed in the CPs. Fig. 7 shows the cascade circuit used for implementing the voltageshifted column selection signals 𝑉𝑐,𝑗 from the configuration bit 𝐶𝑗, 𝑗 = 1,…,4. The circuit is implemented outside the CP array and, similar to the clocks in Fig. 5, a level shifter is placed at the output. The clock signals Φ𝑗= {𝜙𝑗,𝑘}, 𝑘 = 1,…,4employed by the CPs are shared by columns. They are derived from the non-frequency-divided clock Φrepresented Fig. 5(a) using the circuit shown in Fig. 5(b). Note that the phases 𝜙𝑗,𝑘 depend on the configuration bits 𝐶𝑗. Using the Delta blocks shown in Fig. 5(b), the phases 𝜙𝑗,𝑘 are defined as: Φ𝑗={{𝜙1, 𝜙2, 𝜙3, 𝜙4}, 𝐶𝑗= 1 {0 ,0, 𝜙1, 𝜙2}, 𝐶𝑗= 0 (1) Also note that because of the cascaded synthesis of the clocks Φ𝑗, 𝑗 = 1,…,4, they are slightly time delayed each other, regardless of the 𝐶𝑗 values. This avoids flying capacitors being charged at the same time, thus smoothing the current demand of the DC–DC converter [24]. Depending on whether the row and column of the CP cell are enabled or disabled, three different operation modes, denoted as PUMP, BYPASS, or DISABLED, can be defined. They are illustrated in Fig. 8 (only core transistors 𝑀1𝑥−𝑀2𝑥are shown for clarity). •PUMP. In this mode (Fig. 8(a)), the row and column of the cell are enabled, 𝑉𝑐𝑒𝑙𝑙,𝑖𝑗 =𝑉𝐶𝑃 ,𝑗−1 and 𝑉𝑐,𝑗 =𝑉𝐶𝑃 ,𝑗−1. Hence, the cell operates as a cross-coupled CP in which core transistors (𝑀1𝑥−𝑀2𝑥) are switched on and off as illustrated in the figure, and switches (𝑀5𝑥−𝑀6𝑥) are off. The voltage 𝑉𝑝𝑢𝑚𝑝,𝑗 pumped to the following j-th column of the array is given by 𝑉𝑝𝑢𝑚𝑝,𝑗 =𝑉𝐶𝑃 ,𝑗 −𝑉𝐶𝑃 ,𝑗−1 =𝑉𝑖𝑛 −𝐼𝐿 2𝑀𝑎𝑓𝑐𝑙𝑘𝐶𝑓 𝑙𝑦 (2) where 𝐶𝑓𝑙𝑦,𝑀𝑎,𝑉𝐶𝑃 ,𝑖−1,𝑉𝑖𝑛,𝑓𝑐𝑙𝑘, and 𝐼𝐿are, respectively, the value of the flying capacitor 𝐶1𝑥, the number of active rows, the cell’s input voltage, the input voltage of the DC–DC converter, the pumping frequency, and the load current. Since the cells of the CP array are equally sized, the charge pumped from the input voltage source to the load is equally distributed among the flying capacitors, thus resulting in a constant pumping voltage, 𝑉𝑝𝑢𝑚𝑝, across all cells. As 𝑉𝑝𝑢𝑚𝑝 decreases, the conduction resistance of 𝑀2𝑥increases, thus increasing the charge transfer time constant formed with the flying capacitors. When this time constant is comparable to the pumping clock period, the charge is not fully transferred to the next stage, and the output voltage cannot be properly regulated. In the proposed design, this performance limit is observable when 𝑉𝑝𝑢𝑚𝑝,𝑗 drops below roughly 1V. •BYPASS. In this mode (Fig. 8(b)), the row of the cell is enabled but the column is disabled. This is done by permanently setting 𝑀2𝑥on and by alternatively switching 𝑀1𝑥on and off. In this case, 𝑉𝑐𝑒𝑙𝑙,𝑖𝑗 =𝑉𝐶𝑃 ,𝑗−1 and 𝑉𝑐,𝑗 =𝑉𝑐,𝑗−1. If the previous stage is in PUMP mode, 𝑉𝑐,𝑗 =𝑉𝐶𝑃 ,𝑗−2, otherwise, if it is in BYPASS mode, 𝑉𝑐,𝑗 =𝑉𝑐,𝑗−2. Note that the flying capacitors are tied to the cell output node to reduce voltage ripples. •DISABLED. In this mode (Fig. 8(c)), the row of the cell is disabled, and, regardless of the 𝐶𝑗value, the cell’s input and output voltages are isolated, and flying capacitors contribute to reducing the ripple. In this case, 𝑉𝑐𝑒𝑙𝑙,𝑖𝑗 =𝑉𝐶𝑃 ,𝑗−1 +𝑉𝑖𝑛, and if the column is enabled, 𝑉𝑐,𝑗 =𝑉𝐶𝑃 ,𝑗−1, otherwise 𝑉𝑐,𝑗 =𝑉𝑐,𝑗−1. Assuming a general 𝑀×𝑁array architecture and neglecting conduction and switching losses in the CPs, the output voltage 𝑉𝑜𝑢𝑡 of the DC–DC converter follows a saw-tooth waveform with period 𝑇ℎ=𝑇𝑐𝑙𝑘∕2 given by 𝑉𝑜𝑢𝑡(𝑡) = 𝑉0−𝑅𝑒𝑞𝐼𝐿+[1 − (𝑡 𝑇ℎ −⌊𝑡 𝑇ℎ − 1⌋)]𝐼𝐿 𝐶𝑒𝑞 (3) where ⌊⋅⌋represents the floor function, 𝑉0= (𝑁𝑎+ 1)𝑉𝑖𝑛,𝑁𝑎is the number of active columns in the array, and 𝑅𝑒𝑞 =𝑁𝑎 2𝑀𝑎𝑓𝑐𝑙𝑘𝐶𝑓 𝑙𝑦 (4) 𝐶𝑒𝑞 =[2𝑀(𝑁−𝑁𝑎+ 1) − 𝑀𝑎]𝐶𝑓𝑙𝑦 +𝐶𝑜𝑢𝑡 (5) Note that during the time interval [0, 𝑇ℎ],𝑉𝑜𝑢𝑡(𝑡)can be interpreted as the voltage drop across an equivalent 𝑅𝑒𝑞 −𝐶𝑒𝑞 series circuit, with the capacitor having an initial voltage 𝑉0, which is discharged by a current load 𝐼𝐿. From (3), the average output voltage, 𝑉𝑜𝑢𝑡,𝑎𝑣𝑔, and the output ripple, 𝛥𝑉𝑜𝑢𝑡, of the converter are, respectively, given by 𝑉𝑜𝑢𝑡,𝑎𝑣𝑔 =𝑉0−(𝑅𝑒𝑞 +1 4𝑓𝑐𝑙𝑘𝐶𝑒𝑞 )𝐼𝐿(6) 𝛥𝑉𝑜𝑢𝑡 =𝐼𝐿 2𝑓𝑐𝑙𝑘𝐶𝑒𝑞 (7) AEUE - International Journal of Electronics and Communications 161 (2023) 154527 4 D. Palomeque-Mangut et al. Fig. 5. Timing diagram of the 4-phase clock signals Φ,Φ𝑗and Ψ. All the circuit elements are supplied at 𝑉𝐷𝐷 , excepting the clock drivers that are biased at 𝑉𝑖𝑛 . For a given flying capacitance 𝐶𝑓𝑙𝑦 and output capacitor 𝐶𝑜𝑢𝑡,(6) shows that the voltage conversion ratio 𝑉 𝐶𝑅 =𝑉𝑜𝑢𝑡∕𝑉𝑖𝑛 is mainly determined by 𝑁𝑎, however, it also depends on 𝑀𝑎and 𝑓𝑐𝑙𝑘. Similarly, the output voltage ripple also depends on 𝑁𝑎,𝑀𝑎and 𝑓𝑐𝑙𝑘, according to (7). This reliance on multiple parameters is key to expanding the operating range of the DC–DC converter, as well as allowing different configurations for a given target. This is illustrated in Fig. 9 which shows the operation range segments (thick lines) for four different 𝑀𝑎 and 𝑁𝑎combinations in the 𝑉𝑝𝑢𝑚𝑝 vs. 𝑉𝑜𝑢𝑡(0) plane for an arbitrary case where 𝑉𝑖𝑛 = 3.0V and 𝐼𝐿= 0.5mA. The combinations are 𝑀𝑎=𝑁𝑎= {1,2,3,4}. From (2) and (3), the segments follow the expression 𝑉𝑝𝑢𝑚𝑝 =𝑉𝑜𝑢𝑡(0) − 𝑉𝑖𝑛 𝑁𝑎 (8) and the upper and bottom boundaries of each are obtained from (2) for the maximum and minimum values of the pumping clock frequency 𝑓𝑐𝑙𝑘 generated by the regulation loop. As mentioned, the lower boundaries cannot be decreased below approximately 1V. Note from Fig. 9 that the segments cover different operation ranges, and there are output voltages that can only be accessed with one configuration. For instance, an output voltage of 4.3V is only achievable if 𝑀𝑎=𝑁𝑎= 1, as shown in the plot. It can also be observed that the segments overlap for given output voltages. For instance, an output voltage of 𝑉𝑜𝑢𝑡 = 11.3V can be generated both with 𝑀𝑎=𝑁𝑎= 3 and 𝑀𝑎=𝑁𝑎= 4. This paves the way to select one configuration or another for a target output voltage based on considerations like power efficiency or voltage ripple. This is further illustrated in Fig. 10 which shows the accessible output voltage regions of the converter in terms of the load current and the number of activated rows 𝑀𝑎= {1,2,3,4}, assuming 𝑁𝑎= 4 and 𝑉𝑖𝑛 = 3 V. The overlaps between the different regions are clearly observable and it can also be seen that some operation points are only accessible from a single configuration. For instance, 𝑀𝑎= 1 is the only possibility for generating a target output voltage 𝑉(0) = 10.5V for load currents down to 0.1 mA. This illustrates the advantages that row programming offers for extending the operating range of the converter – a non-programmable 𝑀𝑎= 4 implementation would have required a load current of 0.5 mA for the same output voltage–. The power losses of the array, not considered in (3), depend on the number of active cells and the 𝑓𝑐𝑙𝑘⋅𝐶𝑓𝑙𝑦 product as [25], 𝑃𝑙𝑜𝑠𝑠,𝑡𝑜𝑡 =𝑓𝑐𝑙𝑘⋅𝐶𝑓𝑙𝑦⋅(2⋅𝛽⋅𝑉2 𝑖𝑛 +𝐾𝑖𝑛𝑣)⋅𝑀𝑎⋅𝑁𝑎.(9) where the first sum term accounts for the switching losses due to the parasitic capacitances of the flying capacitors (they are estimated as a fraction 𝛽of the 𝐶𝑓𝑙𝑦 nominal value), and the second term represents the short-circuit losses of the flying capacitor drivers. This loss is modeled by the parameter 𝐾𝑖𝑛𝑣 which depends on circuit dimensions and increases with the square of the input voltage, 𝑉𝑖𝑛. Eq. (9) reveals that power losses increase with the pumping frequency. However, from (4) and (7), the equivalent output resistance and the output voltage ripple are both inversely proportional to 𝑓𝑐𝑙𝑘. Hence, there is a trade-off between power efficiency, achievable output voltage, and voltage ripple. A similar trade-off also holds if the number of active rows increases, i.e., power efficiency lowers but the converter output is smoother. Referring back to the graphical representation in Fig. 9, if a given target output voltage can be generated from two or more configurations, the one for which the operating point is closer to the lower limit of its feasibility segment gets a better energy efficiency. On the contrary, the configuration with an operating point closer to the upper limit obtains a better ripple behavior. These trade-offs will be further illustrated in Section 3. 2.2. Regulation circuit It consists of a negative feedback loop that generates a clock signal that locks when the difference between a 1/10 scaled version of the DC–DC converter output and an internal voltage reference cancels out. Voltage scaling is implemented using a string of diode-connected PMOS transistors from the converter output to ground, and the voltage reference is obtained from a 4-b NMOS-based thermometer DAC. The AEUE - International Journal of Electronics and Communications 161 (2023) 154527 5 D. Palomeque-Mangut et al. Fig. 6. Proposed cross-coupling charge-pump (CP) cell with enhanced conduction main transistors. The dimensions of the transistors and capacitors are given in μm and pF, respectively. All the transistors have a length of 0.35μm. Fig. 7. HV-FLS based generation of voltage-shifted column selection signals 𝑉𝑐,𝑗 from the configuration bit 𝐶𝑗, 𝑗 = 1,…,4. Fig. 8. Simplified schematic of the proposed CP cell in its different states: (a) PUMP, (b) BYPASS, (c) and DISABLED. Clock phases are also shown. Fig. 9. Graphical representation of the converter operation range for different row/column configurations, assuming 𝐼𝐿= 0.5mA, 𝑉𝑖𝑛 = 3.0V. Top (alt. bottom) horizontal colored lines represent the achievable pumping voltage at maximum (alt. minimum) 𝑓𝑐𝑙𝑘 for 𝑀𝑎= 1,2,3,4. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.) Fig. 10. Graphical representation of the converter operation range in terms of the load current and the number of activated rows for 𝑁𝑎=4, 𝑉𝑖𝑛=3V. DAC output is comprised within the range from 0.42 mV to 1.32V at 60 mV steps, and can be selected using the input word 𝑉𝑟𝑒𝑓 (see Fig. 2). A resistor-less bandgap provides the DAC Ref. [26]. AEUE - International Journal of Electronics and Communications 161 (2023) 154527 6 D. Palomeque-Mangut et al. Fig. 11. Regulation loop circuit. (a) 𝐺𝑚-C integrator with a current auto-zeroing circuit for offset compensation. (b) VCO. Additionally, the feedback loop comprises a 𝐺𝑚-C integrator, and a VCO. Both are powered at 1.8V, and biasing currents are obtained from an integrated self-biased 25nA current Ref. [27]. The 𝐺𝑚-C integrator is shown in Fig. 11(a). It consists of a singleended current-mirror transconductor with input source-degeneration for enhancing linearity, and a 110fF MIM integration capacitor, 𝐶𝑖. The integration time constant is about 160μs. A current auto-zeroing circuit is used for offset-compensation [28]. During auto-zero (AZ =‘1’), the feedback loop is opened, the inputs of the transconductor are shorted together to the DAC output, and the offset current is sampled in a 780fF MIM capacitor, 𝐶𝑎𝑧. In this phase, which lasts 15 μs, the integration capacitor 𝐶𝑖is disconnected from the transconductor and drifts at a rate of roughly 2mV/ms. This, however, has a negligible impact on the pumping frequency 𝑓𝑐𝑙𝑘 and, hence, on the converter output. When the transconductor is enabled (AZ =‘0’), 𝐶𝑎𝑧 is disconnected from the transconductor output, and the stored offset current is subtracted from the output current. Montecarlo simulations with PVT variations on extracted layout showed that the standard deviation of the transconductor input-referred offset decreased from 38.2 mV down to 61μV through auto-zero. The storage capacitor 𝐶𝑎𝑧 discharges during the hold phase (AZ =‘0’) at about 0.2 mV/m and has to be refreshed through auto-zeroing at a minimum frequency of 200Hz to maintain the transconductor offset below 1 mV. This deviation carries a converter’s output decrease of 10 mV, which is deemed acceptable for the intended application. Fig. 11(b) shows the VCO. It uses a source-degenerated OTA for voltage-to-current conversion and a current-starved ring oscillator for current-to-frequency conversion. The negative input of the OTA is set to Fig. 12. Simulation of the startup of the DC–DC converter. The output settles at a 11.5V output voltage in roughly 12μs. Fig. 13. Microphotograph of the fabricated chip. The DC–DC converter occupies an active area of 2.1mm2. mid-rail, and the output current range is shifted from [−𝐼𝑜𝑢𝑡,𝑚𝑎𝑥, 𝐼𝑜𝑢𝑡,𝑚𝑎𝑥] to [0,2⋅𝐼𝑜𝑢𝑡,𝑚𝑎𝑥]. In this range, the frequency of the VCO output, 𝑐𝑙𝑘, approximately sweeps from 5MHz up to 60 MHz. The regulation loop allows a fast settling of the output voltage even at startup. Fig. 12 illustrates the operation of the DC–DC converter at startup for a target operating point with 𝑉𝑜𝑢𝑡 = 11.5V, 𝐼𝐿= 1 mA, 𝑀𝑎 = 3, and 𝑁𝑎= 4. As can be seen, the desired output voltage is reached after about 12μs. 3. Experimental results Fig. 13 shows a micro-photograph of the proposed regulated DC–DC converter, fabricated in a standard 0.18μm 1.8V/3.3 V CMOS process. The circuit occupies an active area of 2.1mm2and can be programmed through an internal SPI module. No external components are needed. Depending on the experiment, the load current is generated either with an off-chip voltage-controlled current source (for the static characterization of the circuit) or with the on-chip neural stimulator (for evaluating the dynamic behavior of the converter). The on-chip neural stimulator delivers current pulses with amplitudes up to 2 mA, pulse widths as low as 50μs, and frequencies up to 1 kHz. In this case, a micro-controller is used for implementing a look-up table (LUT) which automatically maps the 128 combinations of the 16 target output voltages and 8 target load currents −0–2 mA range divided into 8 intervals– to the number of active rows and columns. This LUT was generated from the insights given by Fig. 9,Fig. 10, and (3). Given that the microcontroller also shapes the current stimulation pulses, the DC–DC converter can be precisely programmed to adapt the number of active rows and columns to the stimulation current. AEUE - International Journal of Electronics and Communications 161 (2023) 154527 7 D. Palomeque-Mangut et al. Fig. 14. Open loop measurements. Parameters: (a) 𝑀𝑎= 4,𝑁𝑎= 1,𝑉𝑖𝑛 = 3 V; (b) 𝑀𝑎= 4,𝐼𝑙𝑜𝑎𝑑 = 0.5mA, 𝑉𝑖𝑛 = 3 V; (c) 𝑓𝑐𝑙𝑘 = 50 MHz, 𝐼𝑙𝑜𝑎𝑑 = 0.5mA, 𝑉𝑖𝑛 = 3 V; and (d) 𝑀𝑎= 4, 𝑁𝑎= 4,𝐼𝑙𝑜𝑎𝑑 = 3.5mA. Fig. 15. Closed loop measurements. Power efficiency for (a) 𝑉𝑖𝑛 = 3.0V, (b) 𝑉𝑖𝑛 = 2.7V, and (c) 𝑉𝑖𝑛 = 2.4V. 3.1. Open loop characterization In this setup, the output of the regulation circuit is disconnected from the programming interface, the pumping clock 𝑐𝑙𝑘 is provided externally, and the average output voltage and efficiency of the DC–DC converter are measured under different conditions. Fig. 14(a) shows the effect when the load current is swept from 0 to 4 mA for pumping frequencies of 12.5, 25, and 50MHz. The number of activated rows and columns, 𝑀𝑎and 𝑁𝑎, are 4 and 1, respectively. As described in (6), the average output voltage decreases linearly with the load current, and the slope becomes steeper as the clock frequency decreases. Also, the load current for which the power efficiency is maximum increases with the clock frequency. Note that when the output voltage drops below roughly 4V –i.e. the pumping voltage is below 1V–, the charge is not fully transferred by the CP-cell and the output voltage exhibits a more pronounced decrease with the load current. Fig. 14(b) illustrates the converter behavior when the pumping frequency 𝑓𝑐𝑙𝑘 is swept from 2.5 to 50MHz for different numbers of activated columns 𝑁𝑎. In these plots, the number of activated rows is 4 and the load current 𝐼𝐿is 0.5 mA. Note that the output voltage tends asymptotically to 𝑉0as the pumping frequency increases, reaching 14.45V for 𝑓𝑐𝑙𝑘=50MHz. Also, in agreement with (9), for a given load current, the power efficiency decreases with the pumping frequency from nearly 60% to 15%. Fig. 14(c) shows the converter performance for different numbers of activated rows and columns, 𝑀𝑎and 𝑁𝑎. Load current and pumping frequency are 0.5 mA and 50MHz, respectively. The output voltage increases with the number of activated rows as a result of the decrease in the equivalent output impedance of the DC–DC converter, as shown in (4). However, the power efficiency decreases due to the higher number of switching elements, as stated in (9). Finally, Fig. 14(d) shows the output voltage and efficiency in terms of the input voltage. As shown in (6), the output voltage linearly increases with the input voltage; however, the measured efficiency decreases due to the increasing power losses, as stated in (9). 3.2. Closed loop characterization In this setup, the pumping frequency of the CP array is internally controlled by the regulation loop; and the average output voltage, power efficiency, and output voltage ripple of the DC–DC converter are evaluated for all 16 possible values of 𝑉𝑟𝑒𝑓 . Measurements are repeated for every combination of load currents (assuming discrete values of 0.5, 1.5, 3.5, and 4 mA) and input voltages (assuming discrete values of 3.0, 2.7, and 2.4V). The surface plot of Fig. 15(a) illustrates the circuit behavior for a 3.0V input voltage. Row/column configurations have been selected for improving power efficiency. The DC–DC converter can deliver output voltages from 4.2V up to 13.2 V depending on the load current. For a 4 mA load, the output voltage is 12.1V and the power efficiency is 65%. For loads larger than 1.5 mA, the efficiency is above 50%. At lower values, the efficiency decreases to 35%. Fig. 15(b) illustrates the case for 𝑉𝑖𝑛 = 2.7V. The output voltage can be adjusted from 4.2V up to 13V and, hence, the VCR is comprised in the range 1.6–4.8 V/V. The peak power efficiency is 66%, obtained when the circuit delivers around 40mW. Finally, Fig. 15(c) shows the operation for 𝑉𝑖𝑛 = 2.4V. The DC–DC converter outputs voltages from 4.2V up to 11.7 V, and the efficiency stays above 40% in most of the operation points, reaching a local maximum of 67%, when driving a 4 mA load current at 8.6V. Using the same setup, output voltage ripple, rather than power efficiency, is measured and the corresponding surface plots are shown in Fig. 16. In the case 𝑉𝑖𝑛 = 3.0V, illustrated in Fig. 16(a), the peak voltage ripple is measured at 3.5 mA load current and 11.4V output voltage, where a ratio 𝛥𝑉𝑜𝑢𝑡∕𝑉𝑜𝑢𝑡,𝑎𝑣𝑔 of 2.4% is obtained. In the case 𝑉𝑖𝑛 = 2.7V, shown in Fig. 16(b), the peak ratio decreases to 1.4%, obtained at 4 mA load current and 10.4V output voltage. Finally, when 𝑉𝑖𝑛=2.4V (case shown in Fig. 16(c)), the peak 𝛥𝑉𝑜𝑢𝑡∕𝑉𝑜𝑢𝑡,𝑎𝑣𝑔 ratio AEUE - International Journal of Electronics and Communications 161 (2023) 154527 8 D. Palomeque-Mangut et al. Fig. 16. Closed loop measurements. Output voltage ripple for (a) 𝑉𝑖𝑛 = 3.0V, (b) 𝑉𝑖𝑛 = 2.7V, and (c) 𝑉𝑖𝑛 = 2.4V. Fig. 17. Closed loop measurements. The orange line represents the output voltage for 𝑀𝑎=4. The blue line represents the output voltage when 𝑀𝑎is adapted to the load current. 𝑉𝑖𝑛 = 3.0V, 𝑉𝑟𝑒𝑓 = 1010,𝑁𝑎= 4. (For interpretation of the references to color in this figure legend, the reader is referred to the web version of this article.) further decreases to 0.9%, measured for 𝑉𝑜𝑢𝑡=8.6V and 𝐼𝐿=4 mA. This decrease of the output voltage ripple with the input voltage can be explained through (2) and (7). Decreasing 𝑉𝑖𝑛 increases the pumping clock frequency needed for reaching the target output voltage and, thus, ripples are smaller. As discussed in Fig. 10, the programmability of the charge-pump array extends the low side of the load current operation range. This is experimentally confirmed in Fig. 17, which shows the output voltage, 𝑉𝑜𝑢𝑡, for different load currents ranging from 0.1 mA to 4 mA at 𝑉𝑟𝑒𝑓 =‘1010’. The plot compares a case in which 𝑀𝑎= 4 to a case in which the number of activated rows is programmed according to the current load. Note that for currents below 0.5 mA the converter with 𝑀𝑎= 4 is not able to regulate the targeted output voltage and large deviations occur. Contrarily, when 𝑀𝑎is programmable, the circuit tolerates load currents as low as 0.1 mA with an average voltage deviation of 36 mV. This is in agreement with Fig. 10. Furthermore, as discussed in Section 2and captured by (7), flying capacitors of disabled rows contribute to reducing the voltage ripple by increasing the equivalent capacitance, 𝐶𝑒𝑞. Fig. 18(a) illustrates the use of the DC–DC converter together with the on-chip neural stimulator. It shows the output voltage response to a load current 𝐼𝐿that switches from 0.2 mA to 2 mA at a rate of 1kHz. During the transitions, the configuration of the CP array changes from 𝑀𝑎= 1,𝑁𝑎= 4 (for the low current level), to 𝑀𝑎= 4,𝑁𝑎= 3 (for the high current level). Note that despite the large load change and the structural reconfiguration of the array, 𝑉𝑜𝑢𝑡 variations remain below 0.3V. Additionally, it can be observed that the regulation loop successfully stabilized the output voltage after around 6μs. Finally, Fig. 18(b) shows the output voltage transient response to a change in the target output voltage, 𝑉𝑟𝑒𝑓 for a load current of 1.5 mA. Each 40μs, the target voltage is changed from ‘0000’ to ‘1111’. The output voltage can reach the target within 5μs. Fig. 18. (a) Response of 𝑉𝑜𝑢𝑡 to a switching load current. (𝑀𝑎,𝑁𝑎) is set to (1, 4) under 𝐼𝐿=0.2 mA and to (4, 3) under 𝐼𝐿=2 mA. 𝑉𝑖𝑛=3V, 𝑉𝑟𝑒𝑓 =‘1111’. (b) Response of 𝑉𝑜𝑢𝑡 to a change in 𝑉𝑟𝑒𝑓 . (𝑀𝑎,𝑁𝑎) is set to (2, 1) for 𝑉𝑟𝑒𝑓 =‘0000’ and to (2, 4) for 𝑉𝑟𝑒𝑓 =‘1111’. 𝑉𝑖𝑛=3V, 𝐼𝐿=1.5 mA. 3.3. State-of-the-art comparison Table 1 summarizes the performance of the proposed HV-regulated DC–DC converter, together with other solutions proposed in the literature. Only a few reported HV DC–DC converters implemented LV CMOS processes are fully implemented on-chip [9,15–17]. Compared to them, the proposed circuit obtains higher output power and the occupied area is smaller than the work achieving similar delivered power [16]. Our proposal works for input voltages 𝑉𝑖𝑛 ∈ [2.4,3.0] V what makes it suitable to operate with WPT systems such as the one presented in [4]. Moreover, the efficiency when delivering maximum power is among the highest of the fully-on-chip solutions. Finally, the output voltage gets regulated under a wide range of load currents and the regulation loop is able to stabilize the output voltage within a few microseconds when the load current switches abruptly. AEUE - International Journal of Electronics and Communications 161 (2023) 154527 9 D. Palomeque-Mangut et al. Table 1 Performance comparison with previously reported HV DC–DC boost converters in LV CMOS process. [14] [15] [17] [16] [18] [9] This work CMOS Process 0.18 μm LV 0.35 μm LV 0.18 μm LV 0.18 μm LV 0.18 μm LV 65 nm LV 0.18 μm LV 𝑉𝑖𝑛 1.8V 2.5V 3.3V 3.3V 2.8V 0.5V 2.4-3 V 𝑉𝑜𝑢𝑡 1.7-11.4V 7.5-16V 5-19.6V 3.3-12.6V 12.8V 11V 4.2-13.2 V 4.2-13.0 V 4.2-11.7 V Load current 0.1-1 mA 0.1-25μA Up to 150 μA 0.5-3.5 mA 0.01-2 mA Up to mA 0.1-4 mA Max. op. point 9.8V@1 mA 11.5V@25μA 17V@150 μA 10.8[email protected]mA 12.8 V@1mA 11 V@2mA 12.1 V@4 mA 10.2 V@4 mA 8.6 V@4 mA Max. power (mW) 9.8 0.3 2.6 37.9 12.8 22 48.4 (3.0V) 40.8 (2.7V) 34.4 (2.4V) Efficiency at max. op. point 77% 32% 34% 60% 82% 31% 65% (3.0V) 66% (2.7V) 67% (2.4V) Area (mm2) – 0.07 0.06 2.87 – 0.04 2.10 Capacitors 1.2μF 18pF 26.4pF 400pF 9 μF – 400+125 pF Fully on-chip No Yes Yes Yes No Yes Yes Regulated No Yes Yes Yes Yes Yes Yes 4. Conclusion This paper reports a fully on-chip HV-regulated DC–DC converter for implanted neural stimulation applications, implemented in a standard 1.8V/3.3 V CMOS process. It can generate output voltages four times higher than the nominal process supply while keeping device terminal voltages below safe limits, thus ensuring long-term reliability. Furthermore, the converter can tolerate a wide range of output current loads, from 0.1 mA up to 4 mA, making it suitable for quite diverse stimulation scenarios, both in rodents and mammals. The circuit features an array of individually configurable chargepumps which maximize its power efficiency, up to approximately 65% with 𝑉𝑖𝑛=3V, as the load current increases, thus allowing to relax the power demand of the neuromodulator when more current consumption is needed, i.e., during the stimulation cycles. This is particularly relevant if the implanted device is supplied with wireless powering techniques. Additionally, the on-chip regulation loop allows fast recovery of the converter output under abrupt changes in the load current. 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