Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions

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Access to the published version may require subscription. “This is the peer reviewed version of the following article: Brox, Piedad ; Martínez-Rodríguez, Macarena C. ; Tena-Sánchez, Erica ; Baturone, Iluminada ; Acosta, Antonio J.: Application specific integrated circuit solution for multi-input multi-output piecewise-affine functions: from INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, vol. 44 n.1 which has been published in final form at https://doi.org/10.1002/cta.2058 This article may be used for non-commercial purposes in accordance with Wiley Terms and Conditions for Use of Self-Archived Versions. This article may not be enhanced, enriched or otherwise transformed into a derivative work, without express permission from Wiley or by statutory rights under applicable legislation. Copyright notices must not be removed, obscured or modified. The article must be linked to Wiley’s version of record on Wiley Online Library and any embedding, framing or otherwise making available the article or pages thereof by third parties from platforms, services and websites other than Wiley Online Library must be prohibited." 1 ASIC Solution for MIMO Piecewise-Affine Functions Piedad Brox*, Macarena C. Mart´ ınez-Rodr´ ıguez, Erica Tena-S´ anchez, Iluminada Baturone, and Antonio J. Acosta Instituto de Microelectr´ onica de Sevilla (IMSE-CNM), CSIC-University of Seville *Corresponding author. E-mail: [email protected] Abstract This paper presents a fully-digital architecture and its ASIC implementation for computing Multi- Input Multi-Output (MIMO) Piecewise-Affine (PWA) functions. The work considers both PWA functions defined over regular hyper-rectangular and simplicial partitions of the input domains and also lattice piecewise-affine representations. The proposed architecture is able to implement PWA functions following different realization strategies, using a common structure with a minimized number of blocks, thus reducing power consumption and hardware resources. Experimental results obtained with an ASIC integrated in a 90-nm CMOS standard technology are provided. The proposed architecture is compared with other digital architectures in the state-of-the-art habitually used to implement model predictive control applications. The proposal is superior in power consumption (saving up to 86%) and economy of hardware resources (saving up to 40% in comparison with a mere replication of the three representations) to other proposals described in literature, being ready to be used in applications where high-performance and minimum unitary cost are required. Keywords Piecewise-affine (PWA) functions, VLSI digital circuits, resource optimization, embedded model predictive controllers. This work was partially supported by MOBY-DIC project FP7-INFSO-ICT-248858 (www.mobydic-project.eu) from European Commission, TEC2013-45534-R and TEC2011-24319 projects from the Spanish Government (both projects with support from FEDER), and 201450E034 project funded by CSIC. November 30, 2017 DRAFT 2 I. INTRODUCTION Piecewise-affine (PWA) functions are affine over limited regions of the domain where they are defined. Due to their capability of approximation or identification [1], they have been widely employed in many engineering applications. Examples of PWA function applications include Model Predictive Control (MPC) [2]-[4], fuzzy control [5], virtual sensors [6], approximation of dynamical systems [7]-[9], and neural networks [10]. PWA functions have been studied in circuit theory for a long time [11]-[12]. The literature enumerates many pieces of work concerning circuit implementations of PWA multivariate functions. Among the many proposed circuits, there are analog [13]-[15], mixed-signal [16], and digital implementations [20]-[37]. Although primitive efforts were directed towards developing analog and mixed-signal implementations, such solutions are not sufficiently robust for most applications, thus recent contributions have been addressed to digital architectures, oriented either to Field Programmable Gate Arrays (FPGAs) or to dedicated Application Specific Integrated Circuits (ASICs). Usually, although FPGA implementations are feasible, ASIC solutions provide better performances and are more suited for embedded system design. Increasingly, the tendency is to handle applications that require embedded control solutions in the digital domain (automotive, robotics, aviation, automation systems, etc.), where ASIC solutions are of immediate applications [17]-[19]. Any circuit implementation calculates the value of a PWA function defined over different polytopic partitions of the input domain. The most widespread form of generating a PWA function is to allow any kind of polytopic partition (Figure 1(a)). Such generic PWA functions are referred to as PWAG functions. A way to evaluate PWAG functions requires the exploration of a binary search tree in order to find the polytope that the input belongs to, but this can be a slow solution if the tree depth is high [20]. This realization strategy has recently been implemented digitally in both FPGAs and ASICs [21]-[23]. The ASIC solution described in [23] provides flexibility for the exploration of different binary search trees by means of efficient run-time reprogramming. Another way to evaluate PWAG functions is the lattice representation, which does not need to find the polytope where the input is located and therefore, requires many fewer parameters to define the PWA function over any kind of polytopic partition [24], [25]. Lattice representation (PWAL) is mainly used to address continuous PWA functions. One of its main attractions is that November 30, 2017 DRAFT 3 the hardware implementation for a given PWA function can be easily obtained using the design methodology described in [28]. Other implementations generate PWA functions defined over particular partitions of the input domain [29]-[37]. Simplicial PWA (PWAS) functions are defined over non-overlapping hypertriangular regions called simplices (Figure 1(b)). One great advantage of PWAS functions is that, given the simplicial partition, they can easily be designed to approximate any non-linear function by applying least-square minimization. Several digital architectures for implementing PWAS functions have been reported in literature [32]-[36]. A solution based on Digital Signal Processors (DSPs) is reported in [34], and a mixed-signal ASIC is described in [35]. More recently, an architecture has been developed to implement PWAS functions with FPGAs. Two versions of this architecture, one parallel and one serial, are described in [36]. A simpler partition of the input domain is a hyperrectangular partition (Figure 1(c)). PWA functions defined over this type of partition are known as PWAR functions, and they are very suitable to be implemented by digital circuits. Architectures implemented in FPGAs to generate PWAR functions are presented in [37]. From a hardware point of view, the PWAR implementation is the simplest and fastest way to compute a PWA function. Implementation of PWAS functions, although also fast, is not so simple. The drawback of PWAR and PWAS functions is that they suffer from the curse of dimensionality when they have to approximate a non-linear function with arbitrarily low error; that is to say, the number of hyperrectangular or hypertriangular regions grows exponentially with the number of input variables. On the other hand, the implementation of PWAL functions is not as simple or as fast, but their capability of approximation is higher and they do not suffer from the curse of dimensionality. One PWA realization strategy is therefore better than another depending on the accuracy and performances required by the application. The choice of a specific strategy to evaluate a PWA function is not a trivial task, being necessary in most of cases a fully implementation to be sure that the selected form is the suited one. As far as we know, no versatile architecture exists that is capable of implementing different PWA forms in a single circuit. The main contribution of this paper is to provide a unified architecture covering different realization strategies (PWAR, PWAS, and PWAL) in a single, programmable, configurable ASIC. This approach offers to the user the possibility of choosing the PWA form that best matches the specifications of a particular application. The basic architecture November 30, 2017 DRAFT 4 and functional blocks required to generate PWAR, PWAS, and PWAL functions have been analyzed so as to share circuitry as much as possible, thus obtaining an optimized solution in terms of hardware resources, operation frequency and power consumption. It also allows implementations of the three forms to be easily configured and programmed. The inclusion of such forms in a single ASIC offers two additional advantages, well-known characteristics of such customized solutions: saving in unitary cost for massive manufacturing and huge improvement in performances, space and resources. As a significant added value regarding embedded MPC applications, this ASIC provides a circuit solution able to close a complete embedded control design flow, as the one included in Moby-Dic Toolbox [38]. Many applications require PWA functions with multiple outputs. Most of the digital architectures proposed in literature work with a single output [22]-[23], requiring dedicated circuitry per output and also additional glue logic for smooth operation when implementing multiple output PWA functions. As a valuable additional contribution, the approach presented here also allows for multiple output PWA functions and offers an optimized architecture with minimal need for additional hardware resources. As a matter of fact, the architecture offered is itself a high-performance implementation of MIMO PWA functions. The proposed architecture can be adapted without a preliminary limitation in the number of inputs and outputs. However, an architecture with four inputs and two outputs was integrated into the ASIC since this particular implementation could cover a wide range of embedded control applications [17]-[19]. This ASIC solution is very suitable for low-power and highspeed embedded control systems based on MPC, providing a high-performance digital circuit that can be used in many domains (DC-DC power converters [17], automotive applications [18], and biomedical engineering [19]). The paper is organized as follows. Some necessary preliminaries are introduced in Section II. The architecture for implementing PWAR, PWAS, and PWAL in one single circuit is detailed in Section III. Section IV provides implementation details of an ASIC integration in a 90-nm CMOS standard-cell technology. The experimental results obtained after programming the ASIC to work in MPC applications are shown in Section V, and final conclusions are presented in Section VI. November 30, 2017 DRAFT 5 II. PRELIMINARIES A generic PWA function with multiple inputs and multiple outputs, FP W A(x):Rn→Rm, can be represented by: FP W A(x) = Fi·x+Gi, if x∈Ωi(1) where x∈S⊂Rn,Fiis a matrix of dimensions m×n,Giis a matrix of dimensions m×1, and the Sdomain is divided into Θpolytopes: S= Θ [ i=1 Ωi(2) Figure 1(a) shows a two-dimensional input domain that is divided into 5 polytopes. The PWA function is defined over a n-dimensional compact Sdomain as follows: S={x∈Rn:ai≤x≤bi, i = 1, . . . , n}(3) For a single output, the expression in (1) is as follows: fP W A(x) = n X j=1 fij ·xj+gi, if x∈Ωi(4) For the sake of simplicity, different strategies to implement PWA functions with a single output are summarized in the following. A. PWAR functions A subclass of PWA functions, called PWAR functions, is characterized by a regular partition of the Sdomain. Each axis of the Sdomain can be subdivided into mRisubintervals of the same amplitude: αi=bi−ai mRi (5) and mRi= 2ti, with ti∈N(6) yielding many possible partitions. Consequently, the domain is divided into n Q i=1 mRi= 2 n P i=1 tiidentical hyperrectangles. This kind of partition is called a ‘single-resolution hyperrectangular partition’ [37]. Figure 1(c) shows a November 30, 2017 DRAFT 6 two-dimensional Sdomain partitioned into single-resolution hyperrectangles with mR1=22=4, and mR2=23=8. The value of fP W AR(x)is evaluated following the steps: (i) find the hyperrectangle that the input (x) belongs to, (ii) retrieve fij and gifrom a memory, and (iii) evaluate the affine expression P j fij ·xj+gi. For a multiple-output PWAR function, this process is repeated for each output variable using different parameters (fij,gi) for each one. B. PWAS functions Another subclass of continuous PWA functions, characterized by a regular partition, is called PWAS functions. The generic instance in (1) can always be reported to this particular instance: S={z∈Rn: 0 ≤zi≤mi, i = 1, . . . , n}(7) The equation in (7) is obtained by applying a proper affine transformation [39]: z=T(x)(8) We also assume that every dimensional component ziof the Sdomain is partitioned into mi subintervals of unitary length. Consequently, the Sdomain is partitioned into n Q i=1 miregions and contains N= n Q i=1 (mi+1) vertices [35]. Each one of these regions can be further partitioned into n!non-overlapping regions called simplices. The PWAS function is affine over each simplex of the partitioned Sdomain. The value of the PWAS function can be evaluated as a linear interpolation of a subset of n+1 coefficients cj(for an n-dimensional function): fP W AS(z) = n X j=0 µjcj(9) where the interpolation weights µjdepend on z, the vertices surrounding zare n+ 1 [35], and the values of the function at the vertices vjof the simplex containing zare cj. The value of fP W AS (z)is evaluated following the steps: (i) find the vertices of the simplex that the input zbelongs to, (ii) retrieve cjfrom a memory, (iii) calculate the coefficients µjfor the given input z, and (iv) evaluate the affine expression n P j=0 µjcj. For a multiple-output PWAS function, this process is repeated for each output variable using different coefficients (cj) for each one. November 30, 2017 DRAFT 7 C. PWAL functions PWAL functions are able to implement any continuous PWA function by using its parameter and structure matrices. Since there are several lattice representations for the same PWA function, the lattice representation used herein is the simplest lattice representation explained in [25]-[27]. The parameter matrix, φ=[φ1,. . .,φW], is a W×(n+ 1) matrix whose the rows, φi, are the parameters (fi, gi)of the affine functions used by the PWA function. The structure matrix, ψ=[ψij] is a V×Wzero-one matrix obtained by applying the methodology described in [25]- [27], which indicates (with ψij = 1) how affine functions are compared, as follows: fP W AL(x) = min1≤i≤V{max(1≤j≤W ψij =1 ){ n X k=1 fjk ·xk+gj}} (10) The main advantage of the PWAL representation is that it can handle generic partitions of the input domain without having to store the polytopes. It simply stores the parameters of the output affine functions as the PWAS and PWAR forms. For a multiple-output PWAL function, different structure and parameter matrices are evaluated for each output. The value of fP W AL(x)is evaluated following the steps: (i) read successively the elements (ψij) of the structure matrix, starting from the first row and first column, and, for each row, i, retrieve fjk and gjif ψij=‘1’, (ii) evaluate the maximum between all the affine expressions for each row, and (iii) calculate the minimum between the maximum results. III. ARCHITECTURE DESCRIPTION The proposed architecture implements a PWA function by selecting one of the following forms: PWAR, PWAS, or PWAL. The three forms are combined in the architecture, sharing blocks with similar functionalities and thereby facilitating a high level of reusability and hardware resource optimization. Those blocks that are not used when a specific PWA form is selected are disabled, saving power consumption. The architecture allows configurability and programmability to implement the three forms. The proposed architecture comprises four main functional blocks, as shown in Figure 2. •Parameter Memory, which stores the parameters needed to compute the affine expressions (hyperplanes). November 30, 2017 DRAFT 8 •Arithmetic Block, containing two arithmetic units: one used by PWAL and PWAR and the other used by PWAS. Both arithmetic units process numbers using the two’s complement binary number representation. •Address Generator Block, which generates the address of the parameter memory to retrieve the parameters involved in the computation of the output hyperplane. A dedicated module is used for PWAL and PWAR forms. The Address Generator for PWAS uses the specific module for PWAR plus a dedicated module for addressing the simplex. •Control & Acquisition is a Finite State Machine (FSM), which exerts global control over the circuitry and implements a local protocol to acquire the values of the inputs. The overall timing of the circuits is also managed by the FSM, which generates all the internal signals needed to synchronize the operations performed by the digital architecture. All the configuration parameters are stored in a register called conf, which is read by the FSM. The values stored in this register address the selected PWA representation and the number of inputs and outputs. The other values stored in the register are interpreted by the FSM because they have a different meaning depending on the form that has been chosen. Intermediate and output multiplexers are needed to select the correct signals depending on the chosen PWA form (see Figure 2). Figure 3 shows a schematic summarizing the blocks used in the architecture. Some blocks are shared by two or three forms. For instance, ‘Control & Acquisition’ is used by all three forms, although its behavior varies depending on the form chosen. Parameter Memory is the same resource used by all three forms. The blocks specific to each representation are detailed in the following subsections. The architectural decisions for each given PWA form are described below, for an instance with ninputs and moutputs. A. Specifications for the PWAR implementation A simplified PWAR architecture scheme is shown in Figure 4. PWAR Hyperplane Address Generator is the block that provides the address to locate a word in the parameter memory. Once the resolution tiis fixed for each input variable, each of the domain axes is partitioned into mRi subintervals, thus leading to a total of 2Pn i=1 tihyperrectangular regions. This means that if xi=ti+sibits are used to code the components of the input variable in the Sdomain, each hyperrectangle can be univocally determined by the tiMost Significant Bits (MSBs) of November 30, 2017 DRAFT 15 In the first example, the capability of the circuit to deal with different forms was analyzed by comparing the results of the ASIC programmed to work with PWAR, PWAS and PWAL forms with the performances of those described in literature. A. MISO controller The double integrator was considered to show the ASIC’s ability to work with different representations. Its discrete-time state-space representation is given by: xt+1 =A·xt+B·ut(19) yt= [1 0] ·xt(20) with A=  1 1 0 1  ;B=  0 1  (21) subject to the constraints −1≤u≤1and −2≤y≤2. The problem of regulating the system to the origin by fulfilling the given constraints can be addressed using the MPC technique. The MPC control function was obtained by solving the following optimization problem: min U      x0 H·C·xH+ H−1 P k=0 [x0 k|0·D·xk|0+u0 k·E·uk]      (22) where x∈Rnand u∈Rmare the state and input vectors, respectively; xkdenotes the predicted state vector at time k, obtained by applying the input sequence U: U= [u0,...,uH−1](23) to the plant to control starting from state x;His the horizon and C,D, and Eare matrices that define the cost function and depend on the specific application. For this example, Cwas the identity matrix, E=0.01, H=4, Dbeing as follows: D=  1 0 0 0  (24) The resulting explicit MPC controller was obtained with the Moby-dic Toolbox [38] from Matlab&Simulink and its interface with the Hybrid and MPT Toolbox [40]-[41], which can solve control problems by applying explicit MPC approaches. The Moby-dic Toolbox provides November 30, 2017 DRAFT 16 a description of the double integrator when one representation (PWAR, PWAS or PWAL) is selected by the user. A Matlab function was developed to provide the parameters required for the hardware realization from the controller description in the Moby-dic Toolbox. The PWAR representation sets the following values for the conf register: form = 00,nout = 0,m= 4,t1=t2= 4, and t3=t4= 0. The Parameter Memory stored 768 parameters in 256 words. All these parameters were directly provided by the Moby-dic Toolbox. For the PWAS representation, the values in the conf register were: form = 01,nout = 0,p1=p2= 4, and p3=p4= 0. The values (cj) of the function at 256 vertices were stored in 64 words of the Parameter Memory. For the PWAL representation, the values in the conf register were: form = 10,nout = 0,m= 5. The value of depth1was 9 whereas depth2remained zero since this was a one-dimensional output example. The saturation values, which correspond to minvalue and maxvalue, were -1 and 1, respectively. A total of 10 words were written in the memory of the PWAL Hyperplane Address Generator and 21 parameters (in 7 words) were stored in the Parameter Memory. The ASIC was programmed and tested with the three PWA forms to control the double integrator system. Figure 10 shows the evolution of the plant state, the control variable, and the plant output when the plant was controlled by the ASIC with the three representations. Blue continuous lines show the evolution of the optimal solution (software results with 64-bits resolution). Note that the ASIC and software evolutions were very close to each other for the PWAL implementation that provides an exact representation. PWAR and PWAS forms represent an approximate MPC controller that also regulated the system to the origin. The NRMSE calculated over Npts = 625 points in the control variable is shown in Table II, where NRMSE is calculated as follows: NRMSE = Npts Σ i=1 q1 Npts (ˆu(i)−u(i))2 umax −umin (25) being ˆuthe output of the PWAR, PWAS or PWAL controller in software, uthe control law of the implemented controller using the ASIC and umax and umin the saturation values of the control law. Table III compares different FPGA and ASIC implementations for the double integrator system and the ASIC solution described in this paper. For the PWAL representation, the ASIC November 30, 2017 DRAFT 17 presented in this work achieved the lowest memory requirements. For the PWAR implementation, the proposed ASIC provided the fastest response and the lowest power solution. As it clearly demonstrated, the ASIC performance even surpasses the results obtained from dedicated FPGAs for PWAG, PWAR, and PWAS forms. B. MIMO controller As a demonstrative example of multiple-output capability, let us consider the problem of regulating to the origin the discrete-time unstable multivariable system: xt+1 =A·xt+B·ut(26) yt= [1 0] ·xt(27) with A=  1.3 1 0 1.1  ;B=  0 1 1 1  (28) The PWA controller for the MIMO system is obtained by solving the optimization problem in (22) with: D=  1 0 0 1  ;E=  0.1 0 0 0.1  ;(29) where Cis the identity matrix and H=2. The resulting explicit MPC controller fulfills the constraints −1≤u1≤1,−1≤u2≤1, and −2≤y≤2. The Moby-dic Toolbox provides the description of the MIMO controller. Once again, a Matlab function was developed to provide the parameters needed for the hardware realization. This particular example was taken from [45] for the PWAS representation. For comparative purposes, this application example also used the PWAS representation in the ASIC. The values in the conf register were: form = 01,nout = 1,p1=p2= 4, and p3=p4= 0. The values (cj) of the PWA function at 256 vertices were stored in 64 words of the Parameter Memory. Figure 11 shows the trajectories of the state variables (a) and input and output signals (b)-(d) of the MIMO system, comparing the software results with the ASIC instance using the PWAS implementation. Again the trajectories are quite close and they converge to the origin. For the MIMO, the NRMSE calculated over Npts = 625 points is detailed in Table IV. November 30, 2017 DRAFT 18 Table V compares the response of the ASIC realization presented here with a PWAS MIMO implementation proposed in literature [45]. Our proposal offers the fastest response with a low power consumption (24.53mW). Similar results were obtained for the PWAR and PWAL implementations. The maximum frequency achieved by the proposed ASIC solution widely surpasses the requirements of real embedded control systems [17], [18]. VI. CONCLUSIONS A fully-digital versatile architecture for implementing hyper-rectangular, simplicial, and lattice PWA functions has been presented in this paper. Although intended for similar purposes, the three forms have different backgrounds, resulting in significant variations in building blocks and operating mechanisms. The approach incorporates those operating elements and common units that can be shared into an optimized implementation in a single circuit, in such a way that, when one of the forms is selected, maximum benefits can be obtained in terms of hardware resources and power consumption saving, in an ASIC environment with timing performances that surpass those obtained in other implementations. It is estimated that with the proposed architecture a saving of a 40% is obtained in hardware resources in comparison with a mere replication of the three alternatives in different architectures. One important added value is that the proposal is applicable to multiple-outputs PWA functions, extending the operativity of the circuit to accommodate the most widely used embedded control applications. The ASIC was integrated in a standard 9-metal 1.2V/2.5V 90nm technology, resulting in a versatile, programmable circuit able to work with up to 4-input and 2-output PWAR/PWAS/PWAL functions. The experimental results for the integrated prototypes incorporating typical examples of embedded MPC applications indicate very high performance in terms of operating speed and power consumption. REFERENCES [1] Sontag ED. Nonlinear regulation: The piecewise linear approach. IEEE Trans. on Automatic Control 1981; 26(2) : 346-358. [2] Johansen T., Jackson W., Schreiber R., Tøndel P. Hardware synthesis of explicit model predictive controllers. IEEE Trans. on Control Systems Technology 2007; 15(1) : 191-197. [3] Vouzis PD., Kothare MV., Bleris LG., Arnold MG. A system-on-a-chip implementation for embedded real-time model predictive control. IEEE Trans. Control Systems Technology 2009; 17(5) : 1006-1017. November 30, 2017 DRAFT 19 [4] Bemporad A., Oliveri A., Poggi T., Storace M. Ultra-fast stabilizing model predictive control via canonical piecewise affine approximations. IEEE Trans. on Automatic Control 2011; 56(12) : 2883-2897. [5] Echevarr´ ıa P., Mart´ ınez M., Echanobe J., del Campo I., Tarela J. Digital hardware implementation of high dimensional fuzzy systems. Lecture Notes in Computer Science in Applications of Fuzzy Sets Theory, ser. Springer : Berlin, 2007; 245-252. [6] Poggi T., Rubagotti M., Bemporad A., Storace M. High-speed piecewise affine virtual sensors. IEEE Trans. on Industrial Electronics 2012; 59(2) : 1228-1237. [7] Storace M., De Feo O. Piecewise-linear approximation of nonlinear dynamical systems. IEEE Trans. on Circuits and Systems I 2004; 51(4) : 830-842. [8] Storace M., Bizarri F., Parodi M. Cellular non-linear networks for minimization of functionals. Part 1: Theoretical aspects. International Journal of Circuit Theory and Applications 2001; 29(2) : 151-167. [9] Bizarri F., Storace M., Parodi M. Cellular non-linear networks for minimization of functionals. Part 2: Examples. International Journal of Circuit Theory and Applications 2001; 29 (2) : 168-184. [10] Groff RE., Koditschek DE., Khargonekar PP. Piecewise linear homeomorphisms: The scalar case. Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks (IJCNN) 2000; 3. [11] Chua LO., Deng A. Canonical piecewise-linear analysis: Generalized breakpoint hopping algorithm. International Journal of Circuit Theory and Applications 1986; 14(1) : 35-52. [12] Leenaerts D. Further extensions to Chua’s explicit piecewise-linear function descriptions. International Journal of Circuit Theory and Applications 1997; 24(6) : 621-633. [13] Kettner T., Heite C., Schumacher K. Analog CMOS realization of fuzzy logic membership functions. IEEE Journal of Solid-State Circuits 1993; 28 : 857-861. [14] Delgado-Restituto M., Rodr´ ıguez-V´ azquez A., Vidal F. Nonlinear synthesis using ICs. Wiley Encyclopedia of Electrical and Electronics Engineering (edited by J. G, Webster) 1999; 14 : 472-502. [15] Rodr´ ıguez-V´ azquez A., Navas R., Delgado-Restituto M., Vidal F. A modular programmable CMOS analog fuzzy controller chip. IEEE Trans. on Circuits and Systems - II 1999; 46 : 251-265. [16] Baturone I., S´ anchez-Solano S., Barriga A., Huertas J.L. Implementation of CMOS fuzzy controllers as mixed-signal integrated circuits. IEEE Transactions on Fuzzy Systems 1997; 5(1) : 1-19. [17] Spinu V., Oliveri A., Lazar M., Storace M. FPGA implementation of optimal and approximate model predictive control for a buck-boost DC-DC converter. Proc. IEEE Int. Conference on Control Applications (CCA) 2012; Dubrovnik (Croatia) : 1417-1423. [18] Naus G., Ploeg J., De Molengraft MV., Heemels W., Steinbuch M. Design and implementation of parametrized adaptive cruise control: An explicit model predictive control approach. Control Engineering Practice 2010; 18(8) : 882 - 892. [19] Chui CK., Nguyen BP., Ho Y., Wu Z., Nguyen M., Hong GS., Mok D., Sun S., Chang S. Embedded real-time model predictive control for glucose regulation. Proc. World Congress on Medical Physics and Biomedical Engineering 2013; Beijing (China), 39 : 1437-1440. [20] Tøndel P., Johansen T., Bemporad A. Evaluation of piecewise affine control via binary search tree. Automatica 2003; 39(5) : 945-950. November 30, 2017 DRAFT 20 [21] Johansen T., Jackson W., Schreiber R., Tøndel P. Hardware synthesis of explicit model predictive controllers. IEEE Trans. on Control Systems Technology 2007; 15(1) : 191-197. [22] Oliveri A., Poggi T., Storace M. Circuit implementation of piecewise-affine functions based on a binary search tree. Proc. European Conference on Circuit Theory and Design (ECCTD) 2009; Antalya (Turkey) : 145-148. [23] Brox P., Castro-Ram´ ırez J., Mart´ ınez-Rodr´ ıguez MC., Tena E., Jim´ enez CJ., Baturone I., Acosta AJ. A programmable and configurable ASIC to generate piecewise-affine functions defined over general partitions. IEEE Trans. on Circuits and Systems I 2013; 60(12) : 3182-3194. [24] Tarela J., Mart´ ınez M. Region configurations for realizability of lattice piecewise-linear models. Mathematical & Computer Modelling 1999; 30(11-12) : 75-83. [25] Wen C., Ma X., Ydstie BE. Analytical expression of explicit MPC solution via lattice piecewise-affine function. Automatica 2009; 45(4) : 910-917. [26] Bayat F. Comments on ‘Analytical expression of explicit MPC solution via lattice piecewise-affine function’. Automatica 2012; 48(11) : 2993-2994. [27] Wen C., Ma X., Ydstie BE. Reply to ‘Comments on ‘Analytical expression of explicit MPC solution via lattice piecewiseaffine function”. Automatica 2012; 48(11) : 2995-2996. [28] Mart´ ınez-Rodr´ ıguez MC., Baturone I., Brox P. Design Methodology for FPGA Implementation of Lattice Piecewise-Affine Functions. Proc. Int. Conf. on Field-Programmable Technology (FPT) 2011; New Delhi (India) : 1-4. [29] Juli´ an P., Desages A., Agamennoni O. High-level canonical piecewise linear representation using a simplicial partition. IEEE Trans. on Circuits and Systems I 1999; 46(4) : 463-480. [30] Di Federico M., Juli´ an P., Poggi T., Storace M. Integrated circuit implementation of multi-dimensional piecewise-linear functions. Digital Signal Processing 2010; 20 : 1723-1732. [31] Bemporad A., Oliveri A., Poggi T., Storace M. Ultra-fast stabilizing model predictive control via canonical piecewise affine approximations. IEEE Trans. on Automatic Control 2011; 56(12) : 2883-2897. [32] Storace M., Repetto ., Parodi M. A method for the approximate synthesis of cellular non-linear networks. Part 1: Circuit definition. International Journal of Circuit Theory and Applications 2003; 31(3) : 277-297. [33] Repetto L., Storace M., Parodi M. A method for the approximate synthesis of cellular non-linear networks. Part 2: Circuit reduction. International Journal of Circuit Theory and Applications 2003; 31(3) : 299-313. [34] Rovatti R., Fantuzzi C., Simani S. High-speed DSP-based implementation of piecewise-affine and piecewise-quadratic fuzzy systems. Signal Processing 2000; 80 : 951-963. [35] Parodi M., Storace M., Juli´ an P. Synthesis of multiport resistors with piecewise-linear characteristics: a mixed-signal architecture. International Journal of Circuit Theory and Applications 2005; 33(4) : 307-319. [36] Storace M., Poggi T. Digital architectures realizing piecewise-linear multi-variate functions: two FPGA implementations. International Journal of Circuit Theory and Applications 2011; 39(1) : 1-15. [37] Comaschi F., Genuitz BAG., Oliveri A., Heemels WPMH., Storace M. FPGA implementations of piecewise affine functions based on multi-resolution hyperrectangular partitions. IEEE Trans. on Circuits and Systems I 2012; 59(12) : 2920-2933. [38] MOBY-DIC Toolbox user manual, June 2012. [Online]. Available: http://ncas.dibe.unige.it/software/MOBYDIC Toolbox/MOBY-DIC Toolbox Documentation/doc/html/index.html November 30, 2017 DRAFT 21 [39] Chien M., Kuh E. Solving nonlinear resistive networks using piecewise-linear analysis and simplicial subdivision. IEEE Trans. on Circuits and Systems 1997; 24 : 305-317. [40] Hybrid Toolbox. Available: http://www.dii.unisi.it/hybrid/toolbox [41] MPT Toolbox. Available: http://control.ee.ethz.ch/∼mpt [42] Bemporad A., Morari M., Dua V., Pistikopoulos EN. The explicit linear quadratic regulator for constrained systems. Automatica 2002; 38(1) : 3-20. [43] www.europractice-ic.com [44] Mart´ ınez-Rodr´ ıguez MC., Brox P., Castro J., Tena E., Acosta AJ., Baturone I. ASIC-in-the-loop methodology for verification of piecewise affine controllers. Proc. 19th IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2012 : 388-39. [45] Poggi T., Baturone I., Storace M. Selection of architectures for PWA functions implementation. Public Deliverable of ‘MOBY-DIC project FP7-INFSO-ICT-248858’, available at: http://www.mobydic-project.eu/communication/deliverables November 30, 2017 DRAFT 22 TABLE I. OCCUPATION AREA OF THE PROTOTYPE IMPLEMENTATION Area µm2(Percentage) Control & Acquisition and Glue Logic 784 (0.095%) PWAR/PWAS Hyperplane Address Generator 22,201 (2.7%) PWAS Simplex Address Generator 12,100 (1.47%) PWAL Address Generator 60,126 (7.32%) Parameter Memory 677,543 (82.58%) PWAR/PWAL Arithmetic Unit 44,100 (5.37%) PWAS Arithmetic Unit 3,600 (0.47%) Total active area 820,454 (100%) TABLE II. NRMSE ERROR FOR THE THREE REPRESENTATIONS (DOUBLE INTEGRATOR) Representation NRMSE PWAR 0.0028 PWAS 0.0002 PWAL 0.0029 TABLE III. COMPARISON OF DIGITAL PWA IMPLEMENTATIONS FOR THE DOUBLE INTEGRATOR Device Occupied Latency Max.Frequency Power Memory (KB) (no.clock cycles / ns) (MHz) @ max.freq. (mW) PWAG [22] FPGA Spartan3 3.35 32 / 477.6 67 37 xc3s200 PWAG [23] ASIC 0.94 18 / 167.4 107.5 38.1 PWAS-A [36] FPGA Spartan3 3.07 6 / 70.5 85 49 xc3s200 PWAS-B [36] FPGA Spartan3 9.22 3 / 145.6 20.6 80.5 xc3s200 PWAR-A [37] FPGA Spartan3 24 4 / 200 FPGA realization 51 (@ 20MHz) xc3s200 @ 20MHz PWAR-B [37] FPGA Spartan3 24 2 / 100 FPGA realization 51 (@ 20MHz) xc3s200 @ 20MHz PWAR in this work ASIC 1.875 2 / 19.2 104 6.74 PWAS in this work ASIC 0.375 6 / 66.2 90.5 13.9 PWAL in this work ASIC 0.065 11 / 76.1 105 13.99 November 30, 2017 DRAFT 23 TABLE IV. NRMSE ERROR FOR THE PWAS REPRESENTATION (MIMO CONTROLLER) Representation NRMSE (output1) NRMSE (output2) PWAS 0.000278 0.000271 TABLE V. COMPARISON OF DIGITAL PWAS IMPLEMENTATIONS FOR THE MIMO CONTROLLER Device Latency (no.clock cycles / ns) PWAS-A [45] FPGA Spartan 3 xc3s200 19 / 266 PWAS in this work ASIC 12 / 136 November 30, 2017 DRAFT