Mismatch distance term compensation in centroid configurations with nonzero-area devices

1997’ IEEE Intemational Symposium on Circuits and Systems, June 9-12,1997, H-Kong -- Mismatch Distance Term Compensation in[ Centroid Configurations with Nonzero-Area Devices E.S. Karhunen, Francisco V. Ferniindez and A,. Rodriguez Viizquez Dept. of Analog and Mixed-Signal Integrated Circuit Design, TMSE-CNM Edif. CICA, Avda. Reina Mercedes s/n, E,-41012 Sevilla, SPAIN Tel.: +34 5 4239923. FAX: +34 5 4231832, E-mail: [email protected] Abstract This paper presents an analytical approach to distance term compensation in mismatch models of integrated devices. Firstly, the conditions that minimize parameter mismatch are examined under the assumption of zero-area devices. The analytical developments are illustrated using centroid configurations. Then, deviations from the previous approach due to the nonzero device areas are studied and evaluated. 1. Introduction The tendency in integrated circuit design towards the use of submicron technologies has motivated improvements in the modeling of the second order effects of the MOS transistor and of the random variations in the fabrication processes, which are critical in the design of high performance analog circuits [ 11-[7]. Variability phenomena of electrical characteristics in integrated circuits can be classified into two groups: inter-die variability and intra-die mismatch. The first one accounts for differences die-to-die or wafer-to-wafer, while the second is due to the existence of parameter fluctuations in the wafer. We will focus on intra-die mismatch as it is the main responsible for the deviations in analog circuit behavior. The mismatch effect on circuit performance has been examined by many authors, and different mismatch models have been proposed recently [3]-[9J. Section 2 will briefly describe the most widely known intra-die mismatch model: the Pelgrom’s model. In section 3 we will focus on the second term of this model, which accounts for the mismatch due to the distance between dlevices. An analytical technique to compensate this mismatch is introduced and applied to several centroid configurations. Finally, section 4 examines the effect of taking into account device areas on the distance term and the magnitude of this perturbation is evaluated. 2. Mismatch modelling In 1988, Pelgrom proposed a model which has become a reference for mismatch effects on analog inte0-7803-3583-X/97 $10.00 01997 IEEE 1644 grated circuits [3]. For two samples of a device with equal W. L and a separation distance Ol2, this model associates a stochastic variable with the difference between the values of the same parameter in each transistor (i. e. threshold voltage). This stochastic variable can be represented by its standard deviation, A aiid S being technology-dependent fitting constants. The first term in (1) includes the influence of transistor sizes and shapes (these do not appear explicitly as rectangular shapes are assumed). It can be assumed that each transistor parameter has a nominal value and a superimposed white noise. Associating Laplace transforms to the transistor configuration, it can be considered as a noise filtering process. Then, this term in (1) appears as a result of noise power not eliminated in the filtering process by the configuration. Therefore, the configuration introduces a set of variables in (l), namely, sizes and shapes. The second term in (1) represents the influence of the distance between transistors DI2, and is a consequence of the existence of gradients in the wafer. The value of any transistor electrical parameter P is represented by a function of distance in the wafer, P=Kd, where: d is the distance from the point where P is evaluated to the point known as perturbation center. This perturbation center is the point in the wafer where the parameter takes its maximudminimum value. Therefore, the radial dependence of a parameter can be modeled as a cone whose vertex is the perturbation center [4]. P P 3. Mismatch Reduction Techniques ‘The physical interpretation of each term in (1) suggests differlent techniques to reduce them. The area term can only be reduced by increasing device areas [8]-[9]. For sinall devices, this is the dominant term and the distance term can be neglected. However, for high-performance design, in which areas are relatively large, distance term plays an important role. In order to reduce this influence, partitioning techniques and centroid configurations are commonly used, although this is only based in heuristic considerations. In the following, reduction techniques are analyzed using an analytical approach which allows to find out configurations with interesting statistical properties. 3.1. Device partitioning Let us assume that the perturbation centre is the reference point for every distance. Therefore, the new set of variables di is the distance from each transistor to the perturbation centre (device separation Ol2 can be easily obtained as the difference vector), as illustrated in Fig. 1. Kurbation centre Figure 1: Distances to perturbacion centre. Given two devices, our technique partitions one or both of them into a set of subdivisions (M and N respectively) and tries to combine them, generating different configurations, to improve the statistical parameters. This is illustrated for the conventional centroid configuration in Fig. 2(b) where one of the devices in Fig. 2(a) has been partitioned into four pieces. The gradient effect compensation due to the four subdivisions seems to make the parameter value more uniform. In this way we could obtain a reduction of the standard deviation compared with the one in the original configuration. nu Figure 2: (a) Basic Structure; (b) Centroid structure. 3.2. Mathematical model A mathematical model must be developed to evaluate the influence on mismatch of the partitions performed on the transistors. Parameter mismatch is an stochastic variable, hence the unique way to obtain this model is using its firstand second-order statistics: mean and standard deviation. We will first assume zero-area transistors placed in their geometric centres. This is reasonable as we are trying to reduce the distance term of Pelgrom's model, and hence in a first approximation we are interested only in the distance between the partitions but not in their areas. Assuming a radial dependence of the parameter P , P= P 0 +K,d (2) and averaging distances from each partition to the perturbation centre, the parameter variation is N M (3) j=l j=] where K is the gradient slope on the wafer, di and d., are the distances from each partition to the perturbation centre, and, M and N are the number of partitions in each device. During the design of a circuit the relative position of the configuration with respect to the perturbation centre is unknown, so we must calculate mismatch as an average of AP for every possible configuration position with respect to the perturbation centre. The mean is, J 27[/ N and the standard deviation is given by, 2 27c N M 0 i=l j=1 IS^ = &I [A di-G 1 dj]'I da-E [AP] (5) a This mathematical model can be used to compare different configurations. It requires the evaluation of (4) and (3, what can be done by expressing distances to the perturbation centre as a function of the symmetrical center of the configuration. 3.3. Evaluation for different centroid structures Fig. 3 shows several centroid configurations and the evaluation of their statistical properties using equations (4) and (5). In each case, distances from transistors to perturbation centre, d, and d, were expressed as a function of the distance R from the configuration center to the perturbation center, as shown in Fig. 4. Assuming zero-area devices, distances can be expressed as: r-, It is impossible to solve (4)-(6) analytically. But, expanding di and dj in Taylor series around R and truncating it appropriately, these integrals can be solved analytically with high accuracy (error is <0.1%). Truncation of Taylor series is a reasonable approximation, since r <( R . 1645 on 2 Kr AP=- 4R _. I do I 'I 0 ilP = 0 32 R' 'xp I 'Vr U. 0 FP = 0 2 o= 32 R 0% TP = 0 2 K2/ (J =- 2 32 R 2 AP=- 4R - Kr Figure 3: Mean and deviation for different structures. yperturbation center Figure 4: Illustrating distances to the perturbation center. The results in Fig. 3 are very interesting for designers. For instance, the detailed analytical study of the conventional centroid structure shows that although it presents quite low standard deviation, the mean is not zero; on the contrary, it is inversely proportional to the distance to perturbation centre. This is disadvantageous compared for instance to circular structures. The price to pay in these is a larger layout area. 4. Area influence on distance term In the model shown in section 3, the distances from each transistor to the perturbation center have been measured from the geometric center of each partition. In this section the influence of considering non-zero area partitions is studied. It must be noticed that we are focusing only on the distance term of Pelgrom's model. This will make clear that there exist a correlation between the mismatch term due to the distance between transistor partitions and their sizes. In order to understand this influence, consider an isolated device, as illustrated in Fig. 5. If the transistor is considered a point located in its geometrical centre, much information is being lost. A more accurate calculation is 10 average out the distance to the perturbation center: D -- -!--.~JA/.X 22 +y dA 1 -- WL (7) A Then, the zero-area model equations can be used substituting d by an average distance. The new mean is, and a corresponding expression can be obtained for the standard deviation. The interpretation of these equations has a clear geometrical meaning as shown in Fig. 6. First, for each angular position of the configuration to the perturbation centre a, an average distance for each partition must be calculated. Then, this previous result must be averaged for each possible initial position of a partition with respect to the Perturbation centre p . L - I. Figure 5: Illustrating area influence. This technique is too complex as an average distance of each partition must be calculated for each angular position a. In the zero-area model, trajectories described by 1646 Figure 6: Geometric interpretation of (8) partition centers are perfectly circular (partition center is constant and equal to the geometrical centre). However, in the nonzero-area model, these trajectories are not circular, because the average distance of each partition depends on the value of a. The resolution complexity of equations in zero-area model was high but, assuming the partition centers dependent on a, the equation resolution is even more difficult. To avoid this problem, an equivalent p-independent point can be considered. With this approach, the area integrals are eliminated and the model complexity is significantly reduced. This point is obtained averaging all the area of each partition for each p value. This gives: 2rr 0A which can be used in the equations for the zero-area models (4)-(5). 5. Perturbation magnitude It is also impossible to solve equation (9) in general, but the displacement of the partition equivalent center with respect to its geometrical center can be avaluated for some simple case, i.e. p = - , shown in Fig. 5. Assum2 ing D>> W, expanding equation (7) in a Taylor series, and integrating over the given area, an approximated analytical result can be obtained. A movement of the partition center with respect to the geometrical center is observed, which for the case in Fig. 5 is&. In the general case, we should average this movement for each value of p. The problem can be solved numerically, using enough p samples to obtain an accurate value of the displacement. The calculated value is around 0.0427 . Taking into account previous results, nonzero-area devices cause a loss of symmetry in the configuration. Assuming that we are working with a wafer diameter of 10 centimeters, that the perturbation center is on the 7t WL wafer, and that we have typical values of device sizes (50ym), the assumption D >> r, W, L can be considered conservative, and hence the approximations in the models are valid. Evaluating the partitition center movement using the previous numerical result, and the values for the different variables involved, the obtained average displacement is around 0.02y.m. Consider the distance values used in section 3, which are the distances from the partition geometrical centers to the configuration center, which are half a transistor size at least (around 25pm). Therefore, the distance error using 25pm instead of values around 25.02 pm is smaller than 0.01%. So, this movement can be neglected. But, it is the influence on the parameter mismatch the really significant information. The evaluation of the mean and standard deviation for each structure using nonzero and zero-area models gives a relative error between the results provided by each model around 0.5% in quite extreme cases (assuming square devices with a 200ym side and rlR=Q. 1). 6. Conclusion. A mismatch evaluation technique for partitioned structures has been developed. Firstly, transistor parameters have been statistically characterized assuming zeroarea devices. Then, the area influence has been examined. These areas cause a transistor center movement, but it is verified that their influence on zero-area results can be neglected, assuming typical distance values. References J. B. Shyu, G. C. Temes, and K. Yao, 'Random Error Effects in Matched MOS Capacitors and Current Sources', IEEE Journal of Solid-State Circuits, Vol. SC-19, pp. 948-955, Dec. 1984. K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, 'Characterization and Modeling of Mismatch in MOS Transistors for Precision Analog Design', IEEE Journal of Solid-State Circuirs, Vol. SC-21, pp. 1057-1066, Dec. 1986. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, 'Matching Properties of MOS Transistor', IEEE Journal of SolidSfufe Circuits, Vol. SC-24, pp. 1433-1440, Oct. 1989. G. Troster and P. Tomaszewski, 'Mismatch Simulation for Layout Sensitive Parameters of IC Components and Devices', IEEE Trans. on Computer-AidedDesign, Vol. 8,pp. 101-107, Feb 1989. C. Michael and M. Ismail, 'Statistical Modeling of Device Mismatch for Analog MOS Integrated Circuits', IEEE Journal of Solid-Sfafe Circuits, Vol, SC-27, pp. 154-166, Feb. 1992. K. N. Ratnakumar and J. D. Meindl, 'Short Channel MOST Threshold Voltage Model', IEEE Journal qfSolid-State Circuits, Vol. SC-17, no. 5. pp. 937-948, Oct. 1982. H. Masuda, M. Nakai, and M. Kubo, 'Characteristics and limitation of scaled-Down MOSFET's due to Two-Dimensional Field Effect', IEEE Transactions on Electron Devices, Vol. ED26, pp. 980-987, June 1979. M. C. Hsu and B. J. Sheu, 'Inverse-Geometry Dependence of MOS Transistor Electrical Parameters', IEEE Transactions on Compurer-Aided Design, Vol. 4, pp, 582-585, July 1987. S. M. Gowda and B. J. Sheu, 'Explicit Geometry Dependence of MOS Transistor Parameters bv the Pseudoboundarv Method'. Analog Integrated Circuits anh Signal Processing, 'Vol. 2, pp. 105-115, Kluwer, 1992. 1647