A Sub-µW Reconfigurable Front-End for Invasive Neural Recording

A Sub-µW Reconfigurable Front-End for Invasive Neural Recording Jose Luis Valtierra, Rafaella Fiorelli, Manuel Delgado-Restituto, Angel Rodriguez-Vazquez Institute of Microelectronics of Seville and University of Seville Avda. Americo Vespucio s/n, 41092-Seville,SPAIN Email: {valtierra,fiorelli,mandel,angel}@imse-cnm.csic.es Abstract—This paper presents a sub-µW ac-coupled reconfigurable front-end for the purpose of neural recording. The proposed topology embeds in it filtering capabilities allowing it to select among different frequency bands inside the neural signal spectrum. Power consumption is optimized by designing for bandwidth-specific noise targets that take into account the spectral characteristics of the input signal as well as the noise bandwidths of the noise generators in the circuit itself. An experimentally verified prototype designed in a 180 nm CMOS process draws a maximum of 815 nW from a 1 V source. The measured input-referred spot-noise at 500 Hz is 75 nV/√Hz while the integrated noise in the 200 Hz - 5 kHz band is 4.1 µVrms. Index Terms—neural front-end, neural recording, ultra-low power, reconfigurable. I. INTRODUCTION Observing brain signals at the cortical level has become a fundamental tool for a number of tasks ranging from basic neuroscience research to brain-machine interfaces. This procedure is normally performed by a multichannel sensing front-end in contact with an array of penetrating electrodes. This scheme offers the highest temporal and spatial resolution out of any other implantable solution [1]. The available extracellular signals at the cortical level are the action potential (AP) and the local field potential (LFP). The AP is a high-frequency (200 Hz - 5 kHz) signal that reflects the dynamics of a single neuron while the low-frequency (1 Hz - 500 Hz) LFP encodes the activity of a group of them. Usually, an offset-rejecting frontend amplifier designed for low-noise and high-gain acquires both signals (i.e. the entire neural bandwidth) per-channel. In addition, many applications necessitate spectral selectivity, which is normally done by subsequent filter stages either in the digital or analog domain. Considering that these specifications have to be met in a context of low-power availability and that the density of recording channels is increasing, it is no surprise that this is an open research problem. Neural front-ends generally consume above 2 µW/channel [2]–[4] while those that implement some form of spectral selectivity consume at least two-times that [5]–[7]. In this work we employ a two-fold strategy for power reduction: first, instead of including additional filters, filtering capabilities are embedded in the frontend. This is made possible by implementing a reconfigurable topology. Second, instead of defining an integrated noise target OTA OTA C1 C2 CL 1 VIN + VOUT - + - CL 2 3 Fig. 1. Proposed reconfigurable front-end. for the entire neural bandwidth, we determine signal-specific noise targets. This eludes any tendency to overdesign and translates directly to power savings. II. PROPOSED RECONFIGURABLE FRONT-END Figure 1 shows the proposed capacitively-coupled neural amplifier with reconfigurable topology. The idea is that four different circuit configurations, each with its own frequency bandwidth, can be accessed through digitallycontrolled switching. Thus, each circuit configuration is tuned to a specific frequency band without heavily impacting the power consumption. The configuration modes are named after the bandwidth they are set to: wideband (WB), LFP, AP and high-frequency oscillations (HFO) [8]. The gain for all modes of operation is C1/C2. The reconfigurable modes are as follows. A. Wideband Mode The circuit enters the WB mode that covers both the local field and action potential frequency bands (Fig. 2(a)) at φ= 1 and θ= 1. The low-frequency corner is given by: fL(W B)≃gm3 2πC2A2 .(1) Here, A2= gm2/gds2while gm2and gds2are the transconductance and conductance of OTA2, respectively. gm3is the978-1-7281-0453-9/19/$31.00 c 2019 European Union 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) 85 transconductance of OTA3. The high-frequency corner is: fH(W B)≃gm1 2πCB1 ,(2) where gm1is the transconductance of OTA1. B. Local Field Potential Mode The LFP mode of operation is accessed at φ= 1 and θ= 0 (Fig. 2(b)). The low-frequency corner is the same as the WB mode. The high-frequency corner is given by: fH(LF P )≃gm1 2πCB2 .(3) Thus, the bandwidth is reduced considering CB2 >CB1. C. Action Potential Mode The AP mode (Fig. 2(c)) reconfigures the feedback of the circuit at φ= 0 and θ= 1 meaning that OTA3connects to the output of OTA2. This has the following effect on the low-frequency corner: fL(AP )≃gm3 2πC2 .(4) Equation (4) shows that by discarding A2,fL(AP )is boosted to a higher frequency. The high-frequency corner is described by (2) as well since CB1 is set as the feedback capacitor. D. High-Frequency Oscillations Mode The amplifier enters HFO mode (Fig. 2(d)) at φ= 0 and θ= 0. The bandwidth is set by a combination of the AP lowfrequency corner and the LFP high-frequency corner. The lowfrequency corner is thus described by (4) while (3) describes the high-frequency corner. III. INPUT SIGNAL AWARE NOISE OPTIMIZATION The conventional design strategy is to set the noise of the amplifier (v2 ni) through the control of the thermal noise of the largest overall contributor (OTA1) by way of gm1as follows, v2 ni,th,OT A1=4kT gm1 ∆f, (5) where k is the Boltzmann constant and T is the temperature. This method leads a fortiori to increased power consumption since gm1has to compensate for other low-frequency noise contributions of which it has no influence on (Fig. 3(a)): v2 ni =v2 ni,th,OT A1+v2 ni,1/f,OT A1+v2 ni,th,OT A3.(6) The proposed noise optimization strategy takes into account the characteristics of the input signal in order to generate power-efficient noise targets. The point is that the amplitude of the wideband neural signal is not uniform [9] [10]: the LFP band shows a 1/fxmagnitude decay while the AP remains flat (Fig. 3(b)). The neural signal at low-frequencies exhibits milivolts-order amplitudes while higher frequency amplitudes are in the microvolt order of magnitude. Thus, the signal to noise ratio (SNR) is larger at lower frequencies. An accurate C1 C2 C3 CB1 OTA1 OTA2 OTA3 (d) (c) C1 C2 C3 CB1 OTA1 OTA2 OTA3 (a) f(Hz) f(Hz) f(Hz) f(Hz) GainGain Gain Gain C1 C2 C3 CB2 OTA1 OTA2 OTA3 CB2 (b) C1 C2 CL OTA1 OTA2 OTA3CB2 CB2 Fig. 2. Reconfigurable Modes. (a) Wideband mode (b) Local field potential mode (c) Action potential mode (d) HFO mode. recording can be guaranteed if we ignore the low-frequency noise contributions and select a spot-noise target at the worstcase SNR (measured around 500 Hz by [11]) for the WB and LFP modes. An input referred spot-noise of 80 nV/√Hz guarantees sufficient SNR for amplitudes as low as 20 µV. The proposed spot-noise target is reached mostly by gm1 since there is less low-frequency noise impact at 500 Hz. This strategy saves significant amounts of power since gm1is set by the largest bias current in the front-end. Meanwhile, the noise target for the AP mode remains the same (i.e. the usual <5µVrms [2]) and is fully controlled by gm1. IV. TRANSISTOR LEVEL IMPLEMENTATION Current reuse amplifiers biased in weak inversion were used for OTA1and OTA2(Fig. 4(a)). These OTAs generate the transconductance of a complementary input pair from half the current as they are biased by the same source. The design starts by biasing OTA1to meet the spot noise target. Flicker noise introduced by OTA1can be minimized by increasing the transistor pair area up to a certain point (i.e. 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) 86 (a) f(Hz) Output Noise f(Hz) Ampl  er Input Referred Noise Input Neural Signal Worst case SNR (b) PSD(V) 10-6 10-3 100102 Fig. 3. (a) Noise bandwidths of the proposed front-end for the WB mode. (b) PSD of a typical front-end noise and input signal. (a) (b) (c) VDD VDD VDD Vss Vss Vss VCM V VCMFB VCMFB VCMFB VIN+ VIN VOUT B VB V B VB V VOUT+ VOUT VIN+ VIN VOUT CMFB Mp Mn Mp MpMp Mn MpMp MpMp IBIAS IBIAS IBIAS IBIAS IBIAS Fig. 4. a) OTA1and OTA2. b) OTA3. c) Common-mode feedback. area specifications). The bandwidth of the amplifier is set by CB1 or CB2 . Total power consumption is kept low by biasing OTA2with the least amount of current possible while keeping stability and high enough open-loop gain. Its impact on (1) should also be considered. Amplifier OTA3(Fig. 4(b)) is biased with an extremely small picoampere current in order to set fL=1 Hz in the WB and LFP modes. The commonmode feedback circuit used for every OTA is shown in Fig. 4(c). The sizing of C1/C2should consider the gain target (40 dB) and its impact on area and input impedance. V. BENCHTOP TESTING Results from experimental verification (Fig 5(a)) are presented in this section. The circuit was designed in a 180 nm process (Fig 5(b)) biased by a 1 V supply. Measured power consumption was 803 nW. An additional current bias tuning in OTA3was included to optimize the high-pass corner. The (a) (b) 600um C1 CB core pad drivers Fig. 5. a) Benchtop setup. b) Physical view. AP WB HFO LFP Fig. 6. Frequency Response. four selectable bandwidths are shown in Fig. 6. The WB mode covers the 1 Hz - 5 kHz band, AP mode covers 200 Hz - 5 kHz, LFP mode 1 Hz - 700 Hz and the HFO 200 Hz - 950 Hz. The AP and HFO modes show a power consumption of 815 nW due to an increase in the current bias of OTA3. The input-referred spot noise at 500 Hz is 75 nV/√Hz (Fig. 7) for the WB and LFP modes while the integrated noise in the AP mode is 4.1 µVrms (Fig. 8). The measured CMRR for 100 mVpp sine inputs at 50 Hz for the LFP and WB modes was 58 dB. This test was repeated at 400 Hz and 1 kHz for the HFO and AP modes respectively yielding >68 dB CMRR in both cases. PSRR was measured by introducing a 100 mVpp sinusoid to the supply input. The measured PSRR was 54 dB for the WB and LFP modes at 50 Hz. This same test found that the PSRR for the AP and HFO modes was 64 dB at 1 kHz and 65 dB at 400 Hz, respectively. The specifications are summarized in Table I and compared with the state of the art. VI. CONCLUSIONS This work presented a neural front-end with a reconfigurable topology that draws a maximum of 815 nW. This power consumption is 50 % less than previously reported works with similar aim and specifications. Unlike other sub-µW neural front-ends, our low power consumption is achieved 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) 87 TABLE I PERFORMANCE SUMMARY [2] [5] [6] [3] [4] This work Process / Year 65 nm / 2017 130 nm / 2017 130 nm / 2017 180 nm / 2018 500 nm /2018 180 nm / 2018 VDD (V) 1.2 1.2 1 1.8 3.3 1 Power (µW) 2 4.7 11 4.5 28 0.803 (LFP,WB) , 0.815 (HFO,AP) High-pass corner 0.2 Hz - 4 Hz 0.5 Hz / 300 Hz 20 Hz 0.7 Hz 13 Hz 1 Hz / 200 Hz / 500 Hz / 1 kHz Low-pass corner 5 kHz 1 kHz / 10 kHz 15 kHz 9.3 kHz 9.8 kHz 700 Hz / 950 Hz / 5 kHz Gain (dB) 26 34-68 44 35 49.5 40.4 Offset rejection - AC-coupled -200 mV ∼100 mV AC-coupled <50 mV AC-coupled Noise AP=7 µVrms56.36 µVrms23.0 µVrms 33.2 µVrms4, 1.88 µVrms5AP Mode = 4.1 µVrms LFP=80 nV/√Hz @ 200Hz 60 nV/√Hz 75 nV/√Hz @ 500 Hz (Wideband) CMRR (dB) ->60dB - 76dB 87dB 58dB (WB,LFP), 68dB(AP,HFO) THD -74 dB @ 20 mVp, 1 kHz 0.4% @ 10 mVpp 0.8% @ 1mVrms, 1 kHz 0.07% @ 1mVpp 1% @ 0.7 mVpp <1% @ 1mVp integrated bandwidth: 1(300Hz-10kHz) 2(10Hz - 17kHz) 3(1 Hz -10kHz) 4(0.03Hz- 25kHz) 75 Fig. 7. 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