ASITRON: ASIC for indirect vector control of induction motors with fuzzy logic based speed regulation

ASITRON: ASIC FOR INDIRECT VECTOR CONTROL OF INDUCTION MOTORS WITH FUZZY LOGIC BASED SPEED REGULATION J.L. Mo a, F. Ba e o, E. Gal án, F. Colod o, J.N. Tombs, M. Ba anco*, A. To alba and L.G. F anquelo. Dp o. de Ingenie ía Elec ónica, Escuela Supe io de Ingenie os, Camino de los Descub imien os s/n, 41092,Se illa (SPAIN) e-mail: m[email p o ec ed] (*) Dp o I+D Mecanismos y Acceso ios, MACPUARSA. Abs ac This pape p esen s ASITRON, an in eg a ed solu ion o he ec o con ol o induc ion mo o s. This ASIC is a mic o-sys em ha in eg a es, in a chip, all he logic equi ed by he indi ec ec o con ol me hod. ASITRON implemen s a PWM based cu en con ol loop, he measu e o speed based on a biphase pulse signal encode , a uzzy logic based speed and posi ion ou e con ol loop and a mic op ocesso ex e nal pa allel in e ace. A buil -in 64- ules uzzy logic con olle can be p og ammed o deal wi h he speed o posi ion ou e con ol loop. This in eg a ed solu ion is he essen ial pa o a compac , high pe o mance, indus ial con ol sys em o ele a o s. 1. In oduc ion In he pas , dc mo o s we e used ex ensi ely in a eas whe e a iable speed ope a ion was equi ed, since he ield and he a ma u e cu en could easily con ol o que and lux. In pa icula he sepa a ely exci ed dc mo o s ha e been used mainly o applica ions ha equi e as esponse and ou -quad an ope a ion wi h high pe o mance nea ze o speed. Howe e , dc mo o s ha e ce ain disad an ages due o he p esence o he commu a o and b ushes. They equi e a pe iodic main enance and canno be used in co osi e o explosi e en i onmen s, and hey ha e limi ed commu a ion capabili y unde high-speed, high- ol age ope a ional condi ions. These p oblems can be o e come by he applica ion o ac mo o s, which ha e a simple and ugged s uc u e, high main ainabili y and hey a e economical, obus and immune o hea y o e loading. Thei small size compa ed wi h dc mo o s allows ac mo o s o be designed wi h subs an ially highe ou pu a ings o low weigh and low o a ing mass. The induc ion mo o is a complex, non-linea sys em, wi h ime- a ying pa ame e s. The dynamic pe o mance o an ac machine is somewha complex because o he coupling e ec be ween he s a o and he o o phases, whe e he coupling coe icien s a y wi h he o o posi ion, [1], [2]. The con en ional ol age/ equency con ol me hods a e being eplaced by mode n ec o con ol. Vec o con ol me hods ha e been p oposed o simpli y he speed con ol o induc ion mo o s so hey can be con olled as a sepa a ely exci ed dc machine. This con ol me hod employs wo se ial con olle s, an inne con ol loop ha egula es he cu en and an ex e nal one o con ol he speed o he d i e. Fu he mo e, his con ol s a egy equi es an exac in o ma ion o he o o lux ec o and ins an aneous and accu a e adjus men o he ac ual s a o cu en s o hei e e ences. Vec o con ol echniques ha e been de eloped conside ably o e he las wen y yea s and ha e become a somewha s anda d in induc ion mo o d i es. Due o i s simplici y, indi ec ec o con ol me hods ha e gained mo e widesp ead applica ion. These con ol s a egies uncouple he mo o cu en componen s by es ima ing he slip speed sl ω , which equi es a p ope knowledge o he o o ime cons an , τ . Di ec ec o con ol me hods equi e lux senso s o a lux model o he sys em. Fo he a ious ec o -con olled d i es i is necessa y o know di e en elec ical pa ame e s o he machine subjec ed o ec o con ol. The ec o con ol is highly dependen on machine pa ame e s and his d awback induces he need o use obus con olle s. Se e al me hods ha e been p oposed, jus as adap i e con olle s, sliding-mode echniques and uzzy con ol. Fuzzy-logic, i s p oposed by L.A. Zadeh, has ecen ly ecei ed a g ea deal o a en ion. The easy way o de ining a uzzy con olle by ules wi h an ob ious physical meaning has helped o expand his con ol echnique. When i is applied o con ol non-linea sys ems, including elec onics d i es, his non-linea con ol s a egy has shown be e esul s han classical con olle s do p o iding obus ness agains changes in he mo o pa ame e s and ex e nal dis u bances. One o he majo p oblems o uzzy- ec o con olle s is he physical implemen a ion. Gene ally, his con ol equi es he use o powe ul compu a ion sys ems, such as DSPs. In ele a o indus y, mo o s a e used in a pa icula way. The mo o is ope a ed om ze o speed o nominal posi i e o nega i e speed and hen pu back o ze o, while posi i e o nega i e o que loads a e applied. His o ically, dc-mo o s we e used ex ensi ely in high pe o mance sys ems o ele a o s, howe e , o all ha has been ou lined, a ele a o sys em based on an ac-mo o is a be e solu ion o i s low cos and low main enance equi emen s. The only d awback is he inc ease in con ol complexi y o he same pe o mance equi emen s. This pape p esen s ASITRON an in eg a ed app oach o uzzy- ec o con ol o induc ion machines ha allows o implemen he high pe o mance con ol sys em equi ed in ele a o ac-d i es applica ions in a compac , non expensi e way. 2. Desc ip ion o he In eg a ed Ci cui ASITRON in eg a es he indi ec ec o con ol algo i hm, a digi al achome e , a uzzy- logic based con olle o speed and posi ion egula ion, a PWM based cu en con olle and a se o ex e nal in e aces, such as A/D con e e s o cu en and ol age measu emen s and a mic op ocesso pa allel in e ace. Figu e 1 depic s a block diag am o a ypical ac-d i e con ol sys em. The basic asks de eloped in ASITRON a e shown in igu e 1. They can be enume a ed as ollows: A. Ex e nal In e ace: Cu en and Vol age measu emen and mic op ocesso in e ace. B. Indi ec ield o ien ed con ol. 1. Inne cu en con ol loop, including a PWM signal gene a o . 2. Speed and posi ion measu emen by means o a buil -in digi al achome e [9] [10]. 3. Ou e speed and posi ion con ol loop wi h a uzzy-logic based con olle . C. In eg a ed ala ms o e alua e no mal unc ion o he sys em. ASITRON can be p og ammed in di e en s ways. Fo he cu en con ol loop i can be p og ammed o unc ion as a 3-phase PWM ol age gene a o o as 3-phase PWM cu en gene a o while o he speed con ol loop h ee op ions exis s: a ol age- equency con olle , a ec o con ol o induc ion mo o and a speed uzzy con olle . A. Ex e nal in e ace. To measu e s a o cu en s and close he inne con ol loop h ee 10-bi A/D con e e s ha e been in eg a ed on he chip. The e o e, o p og am he inne egis e s o he ASIC, i includes a pa allel 8 bi s bus in e ace compa ible wi h he ST9 SGS-Thomson p ocesso . The ASIC has 53 egis e s o a iable numbe o bi s ( om 1 o 16) and 256 egis e s o 12 bi s in an inne RAM. Figu e 1. Block diag am o a ypical ac-d i e con ol sys em. B. Indi ec Field O ien ed Con ol. The ec o con ol block, he coo dina e change and he cu en con ol loop ha e been implemen ed using a da a-pa h s uc u e wi h a 13-bi s mul iplie and a 18-bi s adde . The inpu s o ec o con ol a e he command o que cu en , * q i, lux cu en * d i, and he mechanical speed m ω , de e mined by he speed measu emen block. The ou pu is he elec ical angle e θ , de e mined by equency in eg a ion as ollows: ∫∫ ⋅                ⋅ ⋅+⋅=⋅= d i iPd d qmee * *1 τ ωωθ (1) Being P he poles pai numbe and τ he o o ime cons an . The alue o * q i is he ou pu o he uzzy con olle al hough i can be ex e nally ixed. The ac o s * /1 d i τ and * d i (needed o coo dina e change) a e use p og ammed. The coo dina e change ( o ob ain he h ee phases o he e e ence cu en s * a i, * b iand * c i) is done using he ollowing equa ions: θπθ sinisiniI dqa *** )2/( ++= )3/2()6/( *** πθπθ −+−= sinisiniI dqb (2) () *** bac III +−= These cu en s a e he inpu s o he PWM block. 1. Inne Con ol Loop The implemen ed inne cu en con ol loop consis s o a 3-phase sinusoidal cu en e e ence gene a o d i ing a 3-phase PWM gene a o wi h 10-bi s esolu ion. The PWM iangula ca ie equency can be se om 5kHz up o 43kHz. Keeping his equency abo e he audible band, we can educe noise om he mo o -lamina ion "loudspeake " e ec s. A p og ammable PI con olle closes he loop. The chip ou pu s 6 digi al pulses o d i e he ga es o a h ee-phase in e e wi h p og ammable dead imes (up o 6µs) and na ow pulse dele ion (up o 3µs). The block diag am is depic ed in Figu e 2. 2. Speed and Posi ion Measu emen Se e al me hods o eloci y measu emen can be ound in li e a u e. Digi al achome e s de e mine speed measu emen by calcula ing he equency o a pulse ain coming om he sha encode . Speed measu emen me hods a e ho oughly e iewed in e e ences [4] and [5]. DEAD TIME GENERATOR 6 bi s COUNTER s a end MUX T-/+ REGISTER T+/- REGISTER sel > RAMP GENERATOR Ton LATCH Ton REGISTER load NARROW PULSE DELETION NARROW PULSE DELETION 5 bi s COUNTER end s a 5 bi s COUNTER end s a NARROW PULSE WIDTH REGISTER NARROW PULSE WIDTH REGISTER OUT0 OUT1 Ton FREQ T+/- T-/+ Na ow pukse wid h CLK RESET STOP Figu e 2. Block diag am o he PWM gene a o . In his ASIC, a mul i ange CET me hod is implemen ed [6] o co e a wide speed ange (0 o ±82 Hz) wi h a limi ed absolu e e o depending on he alue o m (numbe o pulses pe e olu ion o he encode ) p og ammed in he ASIC ( igu e 4). The alue o m can be p og ammed om 300 o 2048. A minimum measu ed speed o 0.042Hz and absolu e e o below 0.01 wi h a 1000-pulses pe e olu ion encode is achie ed. The block diag am o he digi al speed achome e design is shown in Figu e 3. Basically his block, calcula es speed as: b clk Cm K ⋅ ⋅ = ω (3) Being clk he clock equency in Hz o he ASIC and b C he numbe o clock pulses coun ed in K pe iods o encode pulses. The speed achome e design is composed o se e al blocks: an in e ace o inpu il e ing and di ec / e e se disc imina ion, a b C coun e o clock pulses (whose bi -numbe can be se om 16 up o 20 in o de o inc ease low speed measu emen capabili y), a K calcula ion block ha de e mines au oma ically K o achie e accu acy in measu e, a successi e app oxima ion di ide o speed calcula ion and a up/down coun e o posi ion es ima ion. 3. Ou e Con ol Loop ASITRON implemen s a uzzy-logic based con olle o he speed and posi ion con ol o an indi ec ec o con olled induc ion mo o , Figu e 5. A uzzy con ol ule, such as “i (x is Ai and y is Bi and z is Ci) hen (w is Ci)” is implemen ed by a uzzy implica ion Ri which is de ined as ollows: [ ] iiiii DCBAR andand µ µ µ µ µ →= (4) whe e i A µ , i B µ and i C µ a e iangula and symme ical membe ship unc ions co esponding o he uzzy se s Ai ,Bi and Ci espec i ely and i D µ is a single on membe ship unc ion associa ed o he uzzy se Di. The ules a e s o ed (up o 63) in a buil -in RAM. In his ASIC, uzzy implica ion uses he p oduc ope a ion ule. The connec i e and is implemen ed by means o he minimum. Fuzzy ules a e combined by means o he sen ence connec i e also which is implemen ed by means o he algeb aic addi ion. Wi h his selec ion o pa ame e s o he uzzy sys em, an exp ession o ule i implica ion (4) is gi en by: ( ) iii iDiDiAsan eceden Dxmin µφµµµ == ' (5) CONTROL UNIT C b COUNTER K COUNTER end C b /K NPPR DIVIDER end enddi INTERFACE sign enddi POSTION UP & DOWN COUNTER SPEED pulses eadpos POSITION SPEED K SELECTOR 14 13 sign sign CLK RESET STOP 16 NPPR READPOS eadnpp WRITENPPR 16 w i enpp READNPPR ENC0 ENC1 SPEED READY Figu e 3. Digi al speed achome e block diag am. igu e 4. Absolu e e o and con e sion ime. De uzzi ica ion is ca ied ou h ough he cen oid me hod, which gene a es he cen e o g a i y o he membe ship unc ion o he ou pu se . As he membe ship unc ions ha de ine he linguis ic e ms o he ou pu a iable a e single ons, he cen e o g a i y o he in e ed uzzy se can be ob ained by means o he ollowing exp ession: ∑ ∑ =m i m ii z w w u 1 1 φ (6) whe e m is he numbe o ules. One ea u e o he implemen ed uzzy con olle is he single on au o-lea ning capabili y. This ea u e is based on he leas means squa e echnique. Fo each i e a ion o he algo i hm, he inpu s a e p ocessed o ob ain he ou pu y. The desi ed ou pu yd is sub ac ed om y and his e o ξ is used o single ons upda ed by means o : ξφη jj w=∆ (7) ∑ − =1 0 m i j j w w φ (8) The uzzy con olle has been designed o p ocess ules sequen ially using simul aneous uzzi ica ion and de uzzi ica ion wi h 10 bi s esolu ion o inpu s and ou pu . MUX INPUTS RAM (32x4x12) bi s Ad ess CT1 CT2 FUZZIFIER & INFERENCE MACHINE α ij C ij INPUT j DEFUZZIFIER w i SGT i OUTPUT + ∆ SGT i o e low RULES COUNTER (5 bi s) CT1 VARIABLES COUNTER (2 bi s) CT2 CONTROL UNIT ... ... desi ed ou pu Figu e 5. Block diag am o he uzzy con olle . C. In eg a ed ala ms. The ASIC has been p og ammed o a oid undesi ed ope a ing condi ions. S a o cu en s a e moni o ed o i e ala ms i one o he ollowing cases is de ec ed: • Maximum phase cu en . • Minimum phase cu en . • Maximum absolu e alue di e ence be ween phase cu en s. Ala m alues a e use p og ammable. In addi ion, a wa chdog ime ci cui y has been included in he ASIC o p e en i o wo k when ou e mic op ocesso has ailu es. 3. Expe imen al Resul s In Figu e 6 he mo o is ope a ed om low speed o nominal speed and, hen, pu back o low speed wi hou load o que. Mechanical speed and mo o cu en s a e shown. No e ha he command speed has an ‘S’ o m, as usually in e ical ope a ion sys ems. The eason o his kind o command speed is ha so accele a ions o decele a ions a oid ab up mo emen s in he ele a o cabin, so he com o le el is inc eased. The esponse o he mo o when a ed speed s ep is applied is showed in Figu e 7. In Figu e 8 a a ed o que s ep is applied when he mo o speed is 25Hz. These esul s ha e been ob ained wi h he 10kW ac-mo o es - ig showed in Figu e 9 connec ed o he ASITRON ac-d i e sys em (Figu e 10). ASITRON has been p og ammed o pe o m a uzzy logic based speed egula ion wi h indi ec ec o con ol. Cu en s has been con olled wi h an PWM a 10kHz. 4. Conclusions In his pape , i is p esen ed ASITRON, a highly p og ammable chip ha implemen s indi ec ec o con ol o 3-phase ac-machines wi h applica ion in ele a o sys em. I can be p og ammed o pe o m 3-phase PWM cu en ( ol age) gene a o , a classical ol age- equency con olle o o implemen a mode n ec o ial con ol o he induc ion mo o wi h a uzzy-logic based speed and posi ion egula ion. ASITRON has been ab ica ed using a 0.7 µm CMOS digi al echnology. Figu e 11 shows a pho og aphy o he inal chip. P esen ly, ASITRON is he co e o a high- pe o mance ac-d i e o ele a o s; he i s indus ial uni s we e scheduled o Decembe 97 and many uni s a e wo king oday wi h excellen esul s. Figu e 6. Speed accele a ion and decele a ion ollowing a ‘S’ e e ence cu e wi hou load o que. Figu e 7. Ra ed speed s ep esponse wi hou load o que. Figu e 8. Ra ed o que s ep a a ed speed esponse. Figu e 9. Ac-mo o es - ig. Figu e 10. ASITRON ac-d i e o ele a o . Figu e 11. Pho og aphy o ASITRON. 5. Re e ences [1] B.K. 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