DC-Link Voltage Regulation of Grid-Connected Converters Using Linear Disturbance Observer

Depósito de investigación de la Universidad de Sevilla https://idus.us.es/ This is an Accepted Manuscript of an papers published IECON 2022 – 48th Annual Conference of the IEEE Industrial Electronics Society available at: 10.1109/IECON49645.2022.9968526 “© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other Works” DC-Link Voltage Regulation of Grid-Connected Converters Using Linear Disturbance Observer Wensheng Luo Sch. of Electr. Engine. and Auto. Harbin Institute of Technology Harbin, China [email protected] Tingyu Shi Sch. of Electr. Engine. and Auto. Harbin Institute of Technology Harbin, China [email protected] Sergio Vazquez Electr. Engine. Depart., Sch. of Engine. Universidad de Sevilla Seville, Spain ser[email protected] Zilin Wang Sch. of Astronautics Harbin Institute of Technology Harbin, China [email protected] Ligang Wu Sch. of Astronautics Harbin Institute of Technology Harbin, China [email protected] Leopoldo G. Franquelo Electr. Engine. Depart., Sch. of Engine. Universidad de Sevilla Seville, Spain [email protected]g Abstract—In this paper, a disturbance observer based control strategy is proposed to regulate the dc-link voltage of three-phase two-level pulse-width-modulation active-front-end rectifiers. In the voltage regulation loop, a linear disturbance observer is designed to improve the system performance. The load connected to the dc-link capacitor is considered as an external disturbance and the observer is used to estimate its value. The estimated disturbance is compensated to the PI controller. Simulations are carried out to verify the effectiveness and advantage of the proposed control strategy. Three different loads have been provided to test the robustness of the control strategy. Simulation results show that the proposed control strategy improves the transient response of the dc-link voltage, meanwhile maintains the steady-state performance in term of the output current total harmonic distortion, and has strong robustness against the external load variation. Index Terms—disturbance observer, voltage regulation, activefront-end I. INTRODUCTION The active-front-end (AFE) converters are intelligent interfaces among utility grid, microgrids, renewable energy sources such as wind turbine system and photo-voltaic system, and energy storage systems. These AFE converters serve as rectifier, inverter, or operate in back-to-back mode. They have favorable characteristics such as bidirectional power flow, almostsinusoidal currents, controllable power factor and convenient dc-link voltage regulation Therefore, they are used to improve the power quality of the two interfaced power ends, by the means of providing active and/or reactive power compensation. This work was supported in part by the National Key R&D Program of China under Grant 2019YFB1312001, the National Natural Science Foundation of China, under grants 62003114 and 62033005, the China Postdoctoral Science Foundation, under grant 2020M681097, the Heilongjiang Postdoctoral Fund, under grant LBH-Z20134, the Heilongjiang Touyan Program, and the Consejeria de Economia, Conocimiento, Empresas, y Universidad, Secretaria General de Universidades, Investigacion y Tecnologia, under project P18-RT-1340. Sergio Vazquez gratefully acknowledge the financial support provided by the project PID2020-115561RB-C31 funded by MCIN/AEI/10.13039/501100011033. Although there are various topologies developed for AFE converters, the three-phase two-level pulse-width-modulation (3P-2L-PWM) voltage source converter is the most popular topology due to its full power controllability and circuit simplicity [1]–[4]. When AFE converters work in rectifier mode, the dc-link voltage can be disturbed by varying load connected to it, which leads to voltage fluctuation. To reduce the undesirable effect brought by this load, disturbance observer can be used to compensate the controller. The disturbance observer-based control is an active disturbance rejection control (ADRC), that is, to exploit the disturbance information to reject its influence by feedforward compensation. There are many works about the ADRC applied in the power converters, combined with various types of controllers, thus the ADRC strategy varies in terms of the form of the disturbance observer, the controller type, and the converter type. Generally, the disturbance observers can be divided into two categories, i.e., linear disturbance observer (LDO) and nonlinear disturbance observer [5]–[9]. Due to the mature development of linear system analysis, LDO is much more employed in the previous works. Among the LDO, a rather commonly used observer is the linear extended state observer, which is an indirect form of LDO in the sense that it treats the disturbance as an extra state when constructing the observer. Its applications in power converters can be found in [10]–[15]. For the dc-link voltage regulation of ac/dc power converters, [13] adopts linear extended state observer based second-order sliding mode controller for the voltage loop, where the load connected to the dc-link capacitor and the system uncertainty are considered as an external disturbance, and the current loop employs second-order sliding mode control under synchronous reference frame; in [15], an linear extended state observer based proportional controller is implemented in the voltage loop, whilst current loop adopts PR regulators under αβ stationary frame. Apart from linear extended state observer, direct forms of LDO are also used load i L R load C dc V a u a u L an v n r  a i  bn v cn v r r L L b i c i b u c u b u c u Fig. 1. Three-phase two-level active-front-end rectifier in power converter control. These observers take use of the plant dynamics to directly derive the disturbance dynamic, and can be designed based on different algorithms, including Luenberger observer [16], PI observer [17], Kalman filter [18], etc.. To author’s knowledge, there is no application of directform LDO used in dc-link voltage control for ac/dc converters. This paper investigates disturbance observer-based PI control for 3P-2L-PWM AFE rectifiers, focusing on the dc-link voltage regulation. The current loop adopts conventional PI control in synchronous reference frame. Since the load from the dc side is time-varying, it is treated as an external disturbance. An LDO is designed to estimate the load value. The designed LDO has the advantage of increasing the transient performance of the system while not influencing the steadystate performance. The rest of paper is organized as follows: Section II presents the converter model and control problems; Section III describes the control scheme for both current loop and voltage loop, where the LDO is designed; in Section IV, experiments are carried out to verify the correctness of theoretical analysis and the robustness of proposed strategy; Section V concludes this paper. II. CONVERTER MODEL AND PROBLEM FORMULATION A. Converter Model The topology of 3P-2L-PWM AFE rectifier is shown in Fig.1. van,vbn and vcn are three-phase ac input voltages. Lis the filtering inductor and ris its equivalent series resistance. ia,iband icare grid currents. ua,uband ucare switching signals. Cis the dc-link capacitor. Vdc is the dc-link voltage to be regulated. RLis an assumed equivalent load connected to C, which can be regarded as an unknown slow-varying external disturbance. iload is load current through RL. To realize the dq control in synchronous reference frame, the mathematical model of the converter is built up as follows [19]:                Ldid dt =−rid+ωLiq+vd−udVdc,(1) Ldiq dt =−riq−ωLid+vq−uqVdc,(2) CdVdc dt =udid+uqiq−iload,(3) where vd, vqare grid voltages, ωis the frequency of grid voltage, id, iqare grid currents, and ud, uqare switching functions generated by controller and executed through a PWM stage [20]. In order to transform the three-phase variables from abc frame to dq synchronous reference frame via Park’s transformation, a PLL should be included in the control system [21]. B. Control Problems As a rectifier, it should be able to reach the desired dc-link voltage reference, and also capable of generating the active and reactive power as required. Thus there are two control problems for this converter, which are: 1) Voltage regulation problem: the dc-link voltage Vdc of the converter should be regulated to reference value V∗ dc, i.e., Vdc →V∗ dc. 2) Current tracking problem: the control of active and reactive power is basically the current control. Therefore, to achieve the power references, the currents id,iqshould track the corresponding reference currents i∗ d,i∗ q, i.e., id→i∗ d and iq→i∗ q. In this situation, the active power reference (consequently i∗ d) is given by the dc-link voltage control, ensuring Vdc to approach V∗ dc, whereas the reactive power reference (consequently i∗ q) is set to a certain value to achieve a desired power factor. III. CONTROL SCHEME To solve the two control problems described in the section II-B, a cascaded control scheme is employed, which includes a current tracking loop as inner loop and a voltage regulation loop as outer loop. As mentioned previously, the focus of this paper is to propose an observer-embedded voltage regulation loop. Therefore, the control algorithms adopted for the current loop and the forward channel of voltage loop are the commonly used PI control. A. Current Tracking Loop Fig.2 shows the current tracking loop based on conventional PI control, under synchronous reference frame. µdand µqare the output signal of the PI controllers of d-axis and q-axis, which are defined as        µd=KpIdeid +KiId Zeiddt, (4) µq=KpIqeiq +KiIq Zeiqdt, (5) where eid =i∗ d−id, and eiq =i∗ q−iq. d i d u * d i d v  d PI 1 dc V          q i * q i  q q u q v 1 dc V PI d i d u * d i d v  d 1 dc V          q i * q i  q q u q v 1 dc V PI PI Fig. 2. Current tracking loop. Then, based on (1) and (2), the following signals can be obtained:        ud=1 Vdc (−µd+vd+ωLiq),(6) uq=1 Vdc (−µq+vq−ωLid),(7) where udand uqare the final output control signals. B. Voltage Regulation Loop From (3) and taking into account that current tracking loop is faster than the voltage regulation loop, the dc-link voltage dynamic can be formulated as: CdVdc dt =1 Vdc (p∗−pload),(8) where p∗=Vdc(udi∗ d+uqi∗ q)and pload =Vdciload. For convenient control design and analysis in following sections, some variables should be defined. Define (V∗ dc)2.2 = z∗,V2 dc2 = z,p∗=uas the control signal, pload =das an external disturbance. Then (8) is equivalent to: C˙z=u−d, (9) Fig.3 shows the control structure of the voltage regulation loop, which is consisted of a conventional PI controller and the disturbance observer LDO. µvis the output of PI controller. ˆ dis the estimated value of external disturbance provided by LDO. Thus the final control signal is u=µv+ˆ d, (10) where µv=Kpvez+Kiv Zezdt, (11) with ez=z∗−z. C. Linear Disturbance Observer (LDO) To actively reject the disturbance in the dc-link and consequently improve the system performance, a linear disturbance  12 2  u 1 ˆ z ˆ d PI控制器  12 2        * dc V * 1 z  vdc 1 z dc V LDO观测器  12 2  * p （）u ˆ z ˆ d PI       * dc V * z  v z dc V LDO  12 2  Fig. 3. Voltage regulation loop compensated by disturbance observer. observer is proposed as: C˙ ˆz=Kldo(u+βˆez),(12) ˆez=z−ˆz, (13) where ˆzis the estimation of z,βand Kldo are the observer gains with Kldo >1. Then the observation error dynamic is obtained as: C˙ ˆez= (1 −Kldo)u−Kldoβˆez−d. (14) Consider ˙ ˆez= 0 in steady state, then βˆez= ((1 −Kldo)u−d)/(Kldo).(15) Observing from (9), when zreaches steady state, the final control output uequals the load power d, and (15) becomes βˆez=−d. Motivated by this fact, the disturbance is estimated as ˆ d=−βˆez.(16) To this end, the estimated value of external disturbance is obtained and can be added to the PI controller output µv. It should be noted that ˙ ˆez= 0 means both zand ˆzreach the steady state, thus during the transient process of z, the observed disturbance ˆ dcan only approach but would not equal to the actual disturbance d. Therefore, to ensure sufficient compensation to the controller, the dynamic of ˆzshould be increased to have faster observation. From above analysis, it can be seen that Kldo can only influence the bandwidth of LDO in transient process, whilst βcan influence the bandwidth in both transient process and steady state. Therefore the transient dynamic can be accelerated by increasing only Kldo, meanwhile the steady state performance can be maintained by fixing the βparameter. IV. SIMULATION RESULTS In this section, simulations are carried out to verify the effectiveness and advantage of the proposed strategy. A. Simulation Parameters Table I shows the plant parameters. The load resistor is connected to the dc-link at a random time to make a step load change. As can be seen, three different load resistors are provided to test the robustness of the proposed strategy. The reactive power reference is set to 0kW to achieve unity power factor. TABLE I PLANT PARAMETERS Parameter Value Description fs20 Sampling Rate (kHz) fsw 10 Switching Rate (kHz) RL{180, 120, 240}Load Resistance (Ω) C3400 DC-Link Capacitor (µF) L15 Phase Inductor (mH) f50 Grid Frequency (Hz) vabc 400 Grid Line Voltage (V) V∗ dc 700 DC-Link Voltage Ref. (V) TABLE II CONTROL PARAMETERS Current loop Voltage loop conventional PI proposed strategy KpId = 15 Kpv = 0.06 Kpv = 0.06 KiId = 400 Kiv = 0.8Kiv = 0.2 KpIq = 15 β= 0.02 KiIq = 400 Kldo = 20 Table II shows the control parameters, which are selected based on a nominal load case, which is RL= 180 Ω. These parameters maintain the same as the load varies. B. Result Analysis 1) Nominal Load (RL= 180 Ω): the load power for nominal case is of the middle level, around 2.7kW. Fig. 4 shows the dc-link voltage responses obtained by the conventional PI and proposed strategy. It can be seen that, the converter performs much better with the proposed strategy. After the load plugs in, comparing with conventional PI, proposed strategy results in much less voltage drop, much shorter transient time, which is defined as when the dc-link voltage reaches the steady-state band (±1% the reference value). Fig. 5 shows the obtained grid current with the proposed strategy, which is three-phase balanced sinusoidal signal. This means that the controller is working effectively. Fig. 6 shows the one phase voltage and the corresponding phase current, 00.2 0.4 0.6 0.8 time (s) 625 645 665 685 705 725 dc output voltage (V) Voltage Ref. PI Controller Proposed Controller PI Controller Proposed Controller Fig. 4. Vdc response with RL= 180 Ω. 0.8 0.81 0.82 0.83 0.84 0.85 0.86 time (s) -5 0 5 grid current (A) Fig. 5. Obtained grid current with proposed strategy. 0.8 0.82 0.84 0.86 0.88 0.9 0.92 0.94 time (s) -10 -5 0 5 10 grid voltage vs. current Fig. 6. Grid voltage vs. current with proposed strategy. from which it can be seen that there is no phase-offset between the voltage and current, which means that the unity power factor is reached. Fig. 9-(a) and Fig. 9-(b) respectively show the grid current spectrum obtained by conventional PI and proposed strategy, demonstrating that the current harmonic content and THD in steady state are maintained with proposed strategy. 2) Increased Load (RL= 120 Ω): this subsection aims to test the performance of proposed strategy when the external load is higher than the nominal case, which is increased to around 4kW. As shown in Fig. 7, the result is consistent with that obtained in the nominal case, i.e., proposed strategy shows obvious advantage over conventional PI in terms of dclink voltage transient response, and maintains current THD. 00.2 0.4 0.6 0.8 time (s) 625 645 665 685 705 725 dc output voltage (V) Voltage Ref. PI Controller Proposed Controller PI Controller Proposed Controller Fig. 7. Vdc response with RL= 120 Ω. 00.2 0.4 0.6 0.8 time (s) 625 645 665 685 705 725 dc output voltage (V) Voltage Ref. PI Controller Proposed Controller PI Controller Proposed Controller Fig. 8. Vdc response with RL= 240 Ω. Comparing with the nominal case, the transient responses under this load are overly slower due to the increase in load power. The obtained grid current THDs for this load are almost the same (1.2%) for conventional PI and proposed strategy, and the harmonic spectrum is similar as that of nominal load, as shown in Fig. 9-(c) and Fig. 9-(d). 3) Decreased Load (RL= 240 Ω): contrary to the Section IV-B2, the proposed strategy is verified with external load power lower than the nominal case, which is decreased to around 2kW. From Fig. 8, it can be seen that the proposed strategy maintains the tracking performance with the decreased load power. Because the load power is decreased, the transient responses are faster than those of nominal load. As in previous cases, proposed strategy demonstrates remarkable improvement over conventional PI. Again, the obtained grid current THD are very similar for conventional PI and proposed strategy, and the harmonic spectrum is maintained, as shown in Fig. 9-(e) and Fig. 9-(f). All the experiment results are summarized in Table III. V. CONCLUSION This paper focused on the dc-link voltage regulation of three-phase two-level pulse-width-modulation active-front-end rectifiers. In the voltage regulation loop, a linear disturbance observer has been proposed to compensate the PI controller with estimated load disturbance. Simulations have been carried out to verify the effectiveness and advantage of the proposed control strategy. Three different loads have been provided to test the robustness of the proposed controller. The results showed that, comparing with conventional PI control, the proposed strategy results in better transient performance and stronger robustness against load variation. REFERENCES [1] S. Vazquez, A. Marquez, R. Aguilera, D. Quevedo, J. I. Leon, and L. G. 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Carrasco, “Adaptive vectorial filter for grid synchronization of power converters under unbalanced and/or distorted grid conditions,” IEEE Transactions on Industrial Electronics, vol. 61, no. 3, pp. 1355–1367, 2014. TABLE III SUMMARY OF SIMULATION RESULTS Vdc drop Vdc overshoot Transient time current THD RL= 180 Ω conv. PI 35 V0V240 ms 0.56 % prop. controller 17 V11 V120 ms 0.50 % RL= 120 Ω conv. PI 50 V0V250 ms 0.29 % prop. controller 25 V15 V130 ms 0.27 % RL= 240 Ω conv. PI 28 V0V220 ms 0.62 % prop. controller 13 V7V110 ms 0.64 % (a) (b) (c) (d) (e) (f) Fig. 9. Obtained current harmonic spectrum: (a) conv. PI with RL= 180 Ω, (b) proposed strategy with RL= 180 Ω, (c) conv. PI with RL= 120 Ω, (d) proposed strategy with RL= 120 Ω, (e) conv. PI with RL= 240 Ω, (f) proposed strategy with RL= 240 Ω.