Memristor Based Event Driven Neuromorphic Nano-CMOS Processor

Memristor Based Event Driven Neuromorphic Nano-CMOS Processor by Charanraj Mohan Submitted to the Department of Electronics and Electromagnetism in partial fulfillment of the requirements for the degree of Doctor of Philosophy at the UNIVERSITY OF SEVILLE November 2020 © University of Seville 2020. All rights reserved. Author ................................................................ Charanraj Mohan Department of Electronics and Electromagnetism November 19, 2020 Certified by............................................................ Bernabé Linares-Barranco Full Professor of Research Thesis Supervisor Certified by............................................................ Teresa Serrano Gotarredona Tenured Scientist Thesis Supervisor Certified by............................................................ José Manuel de la Rosa Full Professor Thesis Supervisor To my parents, sibling and wife. Acknowledgments I would like to thank my advisor Prof. Bernabé Linares-Barranco for being a great instructor and a supportive mentor, and for his patience and intuitive guidance throughout the thesis work. It is my pleasure to acknowledge and thank Prof. Teresa Serrano Gotarredona for her great advice and dedicated guidance in the completion of the thesis. My special thanks and gratitude goes to Prof. José Manuel de la Rosa for his invaluable guidance and motivation throughout the thesis. I owe a debt of gratitude for the knowledge, learnings, and skills acquired through timely discussions and feedback I received from them. I am thankful to Prof. Francesca Campabadal Segura from Institut de Microelectrònica de Barcelona (IMB-CNM), who hosted me for the research stay. Under her guidance and support of her research team members (Marcos Maestro and Mireia Bargalló), I had a very informative and hands-on lab experience in wafer characterization. I thank all members of the ‘Neuromorphic Systems’ group at Instituto de Microelectrónica de Sevilla (IMSE-CNM) for productive meetings and discussions. I thank and appreciate my colleagues- Amir, Laurentiu, Luis Camunas, Javad, Ajay, Ion Vornicu, Angela, and all the other colleagues from IMSE who have been supportive. I also like to thank Joaquin, Antonio, Miguel A., and Juan M. Repiso, who were instrumental in timely availing with the laboratory equipment and tools. I would like to thank my parents- Mohan & Vasanthi who are always my inspiration. I am also thankful to my beloved wife- Abi for being very supportive and encouraging me during tough times. The thesis work was supported by COGNET (63884), Lloyd’s Register Foundation’s ICON (G0086), EU H2020 grants- NeuRAM 3 (687299) , MeM-Scales (871371) and HERMES (824164). 3 4 Memristor Based Event Driven Neuromorphic Nano-CMOS Processor by Charanraj Mohan Submitted to the Department of Electronics and Electromagnetism on November 19, 2020, in partial fulfillment of the requirements for the degree of Doctor of Philosophy Abstract Neuromorphic engineering is an emerging bio-inspired discipline that morphs the biological brain on custom silicon. Although memristors rose as a potential synapse to solve density challenge when monolithically integrated above the silicon structures, scalability remains an important bottleneck. Neuromorphic systems should be made more scalable to realize large networks. To contribute to this, we focus on significant challenges in memristor-based neuromorphic hardware related to– implementation of a low-power inference system that is used for learning or programming and the design of a new current attenuator that is used for efficient crossbar read-outs. The thesis also demonstrates the characterization of different memristors on various test-benches. Thesis Supervisor: Bernabé Linares-Barranco Title: Full Professor of Research Thesis Supervisor: Teresa Serrano Gotarredona Title: Tenured Scientist Thesis Supervisor: José Manuel de la Rosa Title: Full Professor 5 6 This doctoral thesis has been examined by a Committee as follows: ......................................................................... ......................................................................... ......................................................................... 8 Contents List of Figures 13 List of Tables 25 List of Abbreviations and Acronyms 26 1 Introduction 31 1.1 Memristor based neuromorphic processors . . . . . . . . . . . . . . . 31 1.1.1 Moore’s Law and beyond Von Neumann architecture . . . . . 31 1.1.2 Neuromorphic chips . . . . . . . . . . . . . . . . . . . . . . . . 32 1.1.3 Memristor- a favourable synapse . . . . . . . . . . . . . . . . . 34 1.1.4 Memristive crossbar and sneak-path currents . . . . . . . . . . 37 1.1.5 STDP learning rule . . . . . . . . . . . . . . . . . . . . . . . . 38 1.2 Contributions in Memristor based crossbars . . . . . . . . . . . . . . 40 2 Charaterization of memristors 43 2.1 Need for memristor — characterization . . . . . . . . . . . . . . . . . 43 2.2 Characterization of Neurobit memristors using ArC ONE r Platform . 44 2.3 Characterization of 1T1R OxRAM-based memristors using customized PCBs.................................... 48 2.3.1 Design of 4 × 4 and 8 × 8 1T1R crossbars and its packaging . . . 48 2.3.2 Design of circuits for the test-PCBs . . . . . . . . . . . . . . . 53 2.3.3 Assembly and mounting of test-PCBs and customized boards . 56 2.3.4 Description and working of the experimental set-up . . . . . . 57 9 2-28 Switching of resistance of OxRAM of a 1T1R device between HRS and LRS for 10 3 cycles. ............................ 69 2-29 Cycle-to-cycle variability results of LRS for 10 3 switching cycles. . . . 69 2-30 Cycle-to-cycle variability results of HRS for 10 3 switching cycles. . . . 70 2-31 Structure of a MIM based memristor. . . . . . . . . . . . . . . . . . . 71 2-32 Savannah 200 from Cambridge NanoTech Inc. [109]. . . . . . . . . . . 71 2-33 Wafer map showing a preview of a single chip with zoom previews of 5 × 5 µ m 2 and 15 × 15 µ m 2 sized MIM based memristors. . . . . . . 73 2-34 Experimental set-up for characterization of MIM based memristors. . 74 2-35 Experimental results of a 15 × 15 µ m 2 sized MIM based memristor in wafer, W 1 : (a) I-V characteristics during a breakdown attempt, (b) I-V characteristics during 19 full-cycles of switching between HRS and LRS, (c) Currents- I 𝐿𝑅𝑆 and I 𝐻𝑅𝑆 for a read voltage of V 𝑟𝑒𝑎𝑑 = -0.1 V during 19 full-cycles of switching between HRS and LRS. . . . . . . . 75 2-36 Experimental results of a 15 × 15 µ m 2 sized MIM based memristor in wafer, W 2 : (a) I-V characteristics during a breakdown attempt, (b) I-V characteristics during 19 full-cycles of switching between HRS and LRS, (c) Currents- I 𝐿𝑅𝑆 and I 𝐻𝑅𝑆 for a read voltage of V 𝑟𝑒𝑎𝑑 = -0.1 V during 19 full-cycles of switching between HRS and LRS. . . . . . . . 76 2-37 Experimental results of a 15 × 15 µ m 2 sized MIM based memristor in wafer, W 3 : (a) I-V characteristics during a breakdown attempt, (b) I-V characteristics during 19 full-cycles of switching between HRS and LRS, (c) Currents- I 𝐿𝑅𝑆 and I 𝐻𝑅𝑆 for a read voltage of V 𝑟𝑒𝑎𝑑 = -0.1 V during 19 full-cycles of switching between HRS and LRS. . . . . . . . 76 2-38 Experimental results of a 15 × 15 µ m 2 sized MIM based memristor in wafer, W 4 : (a) I-V characteristics during a breakdown attempt, (b) I-V characteristics during 19 full-cycles of switching between HRS and LRS, (c) Currents- I 𝐿𝑅𝑆 and I 𝐻𝑅𝑆 for a read voltage of V 𝑟𝑒𝑎𝑑 = -0.1 V during 19 full-cycles of switching between HRS and LRS. . . . . . . . 77 16 3-1 OxRAM currents for low read voltage pulses. . . . . . . . . . . . . . . 80 3-2 Conceptual diagram of the proposed three-stage calibration scheme in the 4 × 41T1Rcrossbar.......................... 81 3-3 Scheme of a 4 × 4 1T1R crossbar with DC offset voltage calibration in eachwordline................................ 82 3-4 Possible wells used in bulk CMOS process: (a) n-well process, (b) pwell process, (c) Twin-well process, (d) Triple-well process. . . . . . . 83 3-5 Schematic view of the two-stage differential opamp. . . . . . . . . . . 84 3-6 (a) Layout view of the two-stage differential opamp, (b) Parasitics extracted layout view of the two-stage differential opamp. . . . . . . . 89 3-7 (a) Technology-process corner variation of DC transfer curve of opamp, (b) Monte Carlo variation of DC transfer curve of the opamp, (c) Monte Carlo distribution of DC offset voltage of opamp, (d) Comparison of nominal and layout-extracted simulated DC transfer curves of opamp. 90 3-8 Schematic view of the pre-synaptic driver across wordline, 𝑤1 . . . . . 91 3-9 Layout view of a pre-synaptic driver. . . . . . . . . . . . . . . . . . . 92 3-10 Schematic view of the three-stage calibration scheme. . . . . . . . . . 93 3-11 (a) Layout view of the three-stage calibration scheme with the decoders, (b) Parasitic extracted layout view of the three-stage calibration scheme with the decoders. . . . . . . . . . . . . . . . . . . . . . . 94 3-12 Technology-process corner variation results of the three-stage calibration scheme: (a) Technology-process corner variation results of signals - V 𝑟𝑒𝑓 - V 𝑑 , V 𝑟𝑒𝑓 + V 𝑑 , 𝑇𝑜𝑝1 and 𝐵𝑜𝑡𝑡𝑜𝑚1 (b) A zoom-preview of technology-process corner variation results showing signals - 𝑇𝑜𝑝2 , 𝐵𝑜𝑡𝑡𝑜𝑚2 and 𝑂𝑢𝑡 _ 𝑐𝑎𝑙𝑖𝑏 .......................... 95 3-13 Monte Carlo variation results of the three-stage calibration scheme: (a) Monte Carlo variation results of signals - V 𝑟𝑒𝑓 - V 𝑑 , V 𝑟𝑒𝑓 + V 𝑑 , 𝑇𝑜𝑝1 and 𝐵𝑜𝑡𝑡𝑜𝑚1 (b) A zoom-preview of monte Carlo variation results showing signals - 𝑇𝑜𝑝2 , 𝐵𝑜𝑡𝑡𝑜𝑚2 and 𝑂𝑢𝑡 _ 𝑐𝑎𝑙𝑖𝑏 . ........... 96 17 3-14 (a) Monte Carlo variation of DC offset voltage due to temperature with calibration at 27 ∘ C, (b) Sigma of DC offset voltage due to temperature variation with calibration at 27 ∘ C..................... 97 3-15 Comparison of nominal and layout-extracted simulated output, 𝑂𝑢𝑡 _ 𝑐𝑎𝑙𝑖𝑏 of the calibration scheme. . . . . . . . . . . . . . . . . . . . . . . . . 98 3-16 (a) Simulation results during coarse (stage 1) calibration of DC offset voltage across wordline, 𝑤1 targeting the zero-crossing region, (b) Simulation results during fine (stage 2) calibration of DC offset voltage across wordline, 𝑤1 targeting the zero-crossing region, (c)Simulation results during finer (stage 3) calibration of DC offset voltage across wordline, 𝑤1 targeting the zero-crossing region. . . . . . . . . . . . . 99 3-17 (a) Schematic view of the 4 × 4 1T1R crossbar, (b) Layout view of the 4 × 41T1Rcrossbar............................ 100 3-18 Schematic view of the I-pot. . . . . . . . . . . . . . . . . . . . . . . . 101 3-19 Simulated output currents of I-pot for 6 possible control bits of decade current splitter for the reference current, i 𝑟𝑒𝑓 = 100 µ A......... 102 3-20 Scheme of n-bit D-flip flop based shift register. . . . . . . . . . . . . . 103 3-21 (a) Schematic view of edge-triggered D-flip flop, (b) Schematic view of thelatch. ................................. 104 3-22 Simulation results of a 3-bit shift register. . . . . . . . . . . . . . . . 104 3-23 Layout view of I-pot with 14-bit shift-register. . . . . . . . . . . . . . 105 3-24 Layout view of calibration scheme with its decoders and 12-bit shiftregister. .................................. 105 3-25 Layout view of the three-stage calibration scheme implemented along the wordlines of a 4 × 4 1T1R crossbar with highlighted different subcircuits in the outer-ring. . . . . . . . . . . . . . . . . . . . . . . . . . 106 3-26 Layout view of the MAD200 chip highlighting the bulk-based calibration scheme implemented along the wordlines of a 4 × 4 1T1R crossbar with its pads duly labeled. . . . . . . . . . . . . . . . . . . . . . . . . 107 18 3-27 (a) Top view of the chip Packaged in PGA100 package, (b) Top view of the packaged chip after gently removing the top wrapper stuck above the package, (c) A zoom preview of the top view of the packaged chip, (d) An ultra-zoom preview of the top view of the chip captured using a microscope with the highlighted offset calibration circuits with its pads.108 3-28 Functional block diagram of the test-circuit for testing the three-stage calibrationscheme............................. 110 3-29 Scheme of the read circuitry implemented for the calibration scheme. 111 3-30 Comparison of ON/OFF pulses of different widths: (a) 5 ns ON/OFF pulse, (b) 10 ns ON/OFF pulse, (c) 15 ns ON/OFF pulse, (d) 20 ns ON/OFF pulse, (e) 25 ns ON/OFF pulse, (f) 30 ns ON/OFF pulse. . 114 3-31 Experimental set-up of the DC offset calibration scheme. . . . . . . . 116 3-32 FSM used to calibrate DC offset voltage and perform OxRAM operations.117 3-33 Patterns used for recognition-task using 4 × 4 crossbar: (a) Pattern-1, (b) Pattern-2, (c) Pattern-3, (d) Pattern-4. . . . . . . . . . . . . . . . 118 3-34 Model based simulation environment implemented in Simulink environment................................... 119 3-35 Scheme of integrator and comparator implemented in Simulink environment................................... 120 3-36 Pre-synaptic pulses, reset, cycle and batch signals. . . . . . . . . . . . 121 3-37 Integrator output voltage, reset, tposta and simulation time signals. . 121 3-38 Post-synaptic pulsesbefore and after programming. . . . . . . . . . . 122 3-39 Conceptual diagram showing patterns applied on a crossbar that has randomweights............................... 124 3-40 Simulated Pre-synaptic pulses, reset signal and number of cycles showing different regions- A, B, C, D, E and F using STDP learning rule. 124 3-41 Simulated Post-synaptic pulses showing different regions- A, B, C, D, E and F using STDP learning rule. . . . . . . . . . . . . . . . . . . . 125 19 3-42 Crossbar showing binary weights and its evolution- (a) Initial random weight, (b) 1 st weight update, (c) 2 nd weight update, (d) 3 rd weight update, (e) 4 th weight update, (f) Final weights. . . . . . . . . . . . . 125 3-43 Simulation results showing STDP weight updates for five different randominitialweights............................. 127 3-44 Preview of output screen when testing shift-register. . . . . . . . . . . 129 3-45 Preview of output screen when calibrating DC offset across wordline, 𝑤1 ...................................... 130 3-46 Comparison of experimental and simulation results during stage 1 calibration of DC offset voltage across wordline, 𝑤1 . ........... 131 3-47 Comparison of experimental and simulation results during stage 2 calibration of DC offset voltage across wordline, 𝑤1 targeting the zerocrossingregion. .............................. 132 3-48 Comparison of experimental and simulation results during stage 3 calibration of DC offset voltage across wordline, 𝑤1 targeting the zerocrossingregion. .............................. 132 3-49 Active row, column and gate biases applied in the form of pulsesshow- ing a read operation after an erase operation. . . . . . . . . . . . . . 133 3-50 Active row, column and gate biases applied in the form of pulsesshow- ing a read operation after a write operation. . . . . . . . . . . . . . . 134 3-51 LRS and HRS values of OxRAMs of all 16 1T1R devices in the 4 × 4 crossbar where calibration of DC offset voltage is carried out. . . . . . 135 3-52 LRS and HRS values for 10 switching cycles of an OxRAM of the 4 × 4 1T1R crossbar where calibration of DC offset voltage is carried out. . 136 3-53 Switching of resistance of OxRAM of a 1T1R device between HRS and LRSfor400cycles............................. 137 3-54 Conceptual block diagram showing patterns fed as read pulses across the wordlines (or rows) of the calibrated crossbar, whose synaptic weights are switched to learned values. . . . . . . . . . . . . . . . . . 138 20 3-55 Output of integrators and digital signals for template matching for read voltageof0.13V.............................. 138 3-56 Output of integrators and digital signals for template-matching using read voltage of 0.13 V- with a zoom preview showing the integrated voltage. .................................. 139 3-57 Output of integrators and digital signals for template-matching using read voltage of 100 mV. . . . . . . . . . . . . . . . . . . . . . . . . . 140 3-58 Output of integrators and digital signals for template-matching using readvoltageof70mV. .......................... 141 3-59 Output of integrators and digital signals for template-matching using readvoltageof30mV. .......................... 142 3-60 2.4 V signal from power supply directly observed on oscilloscope with 3 bit ‘ERes’ noise filter option. . . . . . . . . . . . . . . . . . . . . . . 143 3-61 Wordlines (or Rows) and digital signals for template-matching using readvoltageof30mV. .......................... 143 3-62 Bitlines (or columns) and digital signals for template-matching using readvoltageof30mV. .......................... 144 3-63 Gate biases and digital signals for template-matching using read voltageof30mV................................ 145 3-64 Flowchart for implementation of SSSP on calibrated crossbar by targeting- ‘col1’ to spike earlier for ‘pattern-1’, ‘col2’ to spike earlier for ‘pattern- 2’, ‘col3’ to spike earlier for ‘pattern-3’ and ‘col4’ to spike earlier for ‘pattern-4’. ................................ 146 3-65 Inference results by programming with the single shot variant of STDP targetingpattern1. ............................ 147 3-66 Flowchart for implementation of STDP learning rule on calibrated crossbar for pattern recognition. . . . . . . . . . . . . . . . . . . . . . 149 3-67 Output of integrators and comparators with other digital signals during 1 st weight-update.............................. 150 21 3-68 Output of integrators and comparators with other digital signals during 2 nd weight-update. ............................ 151 3-69 Output of integrators and comparators with other digital signals during 3 rd weight-update. ............................ 152 4-1 Scheme of a 4×4 1T1R crossbar with pre-synaptic neurons, current attenuators and post-synaptic neurons. . . . . . . . . . . . . . . . . . 154 4-2 Details of MCN circuit schematics. . . . . . . . . . . . . . . . . . . . 155 4-3 Layout view of the MCN circuit. . . . . . . . . . . . . . . . . . . . . . 157 4-4 (a) Minimum to maximum crossbar column inference current Vs Input current to neuron, (b) Comparison of average and standard deviation of output current for different attenuators: MCN circuit, MOS-ladder circuit, and WTA circuit considering process and mismatch variations with 100 Monte Carlo runs. . . . . . . . . . . . . . . . . . . . . . . . 159 4-5 (a) Temperature variations of the output current of the MCN circuit, MOS-ladder and WTA circuit for different values of output currents, (b) Area and input-referred noise of the MOS circuit, MOS-ladder, and WTAcircuit. ............................... 160 A-1 Schematic view of the test-circuit for testing 4 × 4 1T1R crossbar along withitsASIC................................ 180 A-2 Layout view of the PCB used for testing 4 × 4 1T1R crossbar. . . . . . 181 A-3 3-D view of the designed PCB for testing 4 × 4 1T1R crossbar. . . . . 182 A-4 Assembled and mounted PCB for testing 4 × 4 1T1R crossbar. . . . . 183 A-5 Schematic view of the test-circuit for testing 8 × 8 1T1R crossbar along withitsASIC................................ 185 A-6 Schematic view of the test-circuit for testing calibration scheme implemented in 4 × 41T1Rcrossbar....................... 186 A-7 Schematic view of the test-circuit for testing opamp. . . . . . . . . . 187 A-8 Layout view of the PCB used for testing different circuits in the outerring. .................................... 188 22 A-9 3-D view of the designed PCB for testing different circuits in the outerring. .................................... 189 A-10 Assembled and mounted PCB for testing different circuits in the outerring. .................................... 190 A-11 (a) Top view of the front-side of the packaged chip dully labelled with pin numbers, (b) Top view of the rear-side (mirrored) of the packaged chip dully labelled with pin numbers or addresses, (c) Top view of the front-side of the PGA ZIF 14 × 14 socket dully labelled with pin numbers or addresses and marked with the location where the packaged chipsitsonit................................ 195 23 24 List of Tables 2.1 Control-bit for performing different operations for OxRAM in the targeted 1T1R device in the crossbar. . . . . . . . . . . . . . . . . . . . 57 2.2 Bias conditions used for characterizing a single 1T1R device in the crossbars. ................................. 61 2.3 Different dielectrics used in ALD process . . . . . . . . . . . . . . . . 72 2.4 Comparison of V 𝑚𝑎𝑥 , V 𝑚𝑖𝑛 , V 𝑠𝑒𝑡 and V 𝑟𝑒𝑠𝑒𝑡 for wafers- W 1 , W 2 , W 3 and W 4 ................................... 77 3.1 Design parameters of the two-stage PMOS-based differential-pair opamp. 90 3.2 Output of pre-synaptic driver of wordline, 𝑤1 for different combination ofdigitalinputs. ............................. 92 3.3 MOSFET sizing and biasing parameters of the three-stage calibration scheme. .................................. 95 3.4 Values of the control signals for setting output current of I-pot to 40 µ A.102 3.5 Control-bit for performing different operations for OxRAM in the targeted 1T1R device in the crossbar, whose wordlines are calibrated for DCoffsetvoltage.............................. 110 4.1 MOSFET-sizes and biases of proposed MCN circuit. . . . . . . . . . . 156 A.1 Pin addresses for packaged chip and PGA socket for different signals. 191 B.1 Design specifications of the two-stage opamp. . . . . . . . . . . . . . 198 25 ‘Beyond Moore’, under which, devices like nanowire FET, SpinFET, tunneling transistors, atomic switch, memristors, molecular switch, etc. are been investigated. This further kept researchers to explore new approaches of computing that can move beyond the traditional von Neumann architecture [4]. Von Neumann architecture is the architecture that conventional computers and smart devices have today. It comprises the CPU, which operates sequentially on data fetched from memory. ‘Neuromorphic computing’ is one such approach that can be traced back to the 1980s when Caver Mead first proposed the concept of morphing biological neurons on custom silicon [5]. Like the biological brain, the main components in the neuromorphic computing system are the neurons interconnected by synapses. The main idea of silicon neuron is using the sub-threshold currents (in the order of nA) of transistors to mimic the biophysical properties that the neurons have. These brain-inspired neuromorphic computing systems have attracted research interest since they are alternate to classical von Neumann architecture because of the co-existence of memory and processing units. They are also called as non von Neumann architectures. 1.1.2 Neuromorphic chips Neuromorphic chips are chips or ICs designed to focus on using a circuit layout that emphasize a high degree of parallelism, similar to neural net (in software code). The design can be sometimes baked as an ASIC or prototyped in an FPGA. Although early attempts to build neuromorphic chips date back to the late 1980s [6] the first largescale implementations only came in the late 2000s [7]. The renowned neuromorphic chips in the last few decades are Neurogrid [7,8], BrainScaleS [9,10], TrueNorth [11], SpiNNaker [12] and Loihi [13]. Although they don’t meet the complete architecture of biological neurons and synapses, it is always considered as a stepping stone towards it. Neurogrid was one of the early successful neuromorphic platforms that can simulate 1 million neurons and 1 billion synapses [7]. It is also known for its fast neural simulation and energy efficiency. Neurogrid was designed in 2006 and first reported success in 2014 [8]. Its hardware platform consists of 16 neurocores, a cypress EZ-USB 32 FX2LP (for USB communication), a CPLD- to interface FX2 and neurocores and a daughterboard (for realizing primary axon-branching using FPGA and SRAMs). Each neurocore has a 256 × 256 silicon-neuron array, a transmitter, a receiver, a router, and two RAMs. A 12-bit control word, called the Neurogrid packet is used for neurocore-to-neurocore communication. The chip was fabricated in a 180 nm CMOS technology. BrainscaleS’ design was started in 2011 and can simulate about 196k neurons with 50 million synapses [9]. BrainscaleS was designed using wafer-scale integration, which uses the entire wafer (of diameter 20 cm, taped-out using 180 nm CMOS technology) as a single ‘super-chip’. Horizontal and vertical connections on the wafer are used to pick one of the 44 reticles and each reticle has 8 HICANN, which are the integrated block of neuron circuits and its synapses. BrainscaleS 2 (the later version) was designed using 65 nm CMOS technology with built-in plasticity, which modifies both dendritic synaptic composition and synaptic weights to efficiently train large multi-compartment neurons [10]. TrueNorth, designed by IBM in 2014- has 4096 cores with 256 neurons each and each neuron has 256 synapses [11]. TrueNorth chip is designed using 28 nm CMOS technology and the chip architecture comprises a two-dimensional array of cores where long-range connections are implemented by sending spike events over a mesh routed network and local connections are established using a crossbar. Each core has a timemultiplexed neuron block, a memory (SRAM) block for storing data of neurons, a scheduler block for creating axon delays of incoming spike events, a router block for relaying spike events and an event-driven controller block. Comparatively, TrueNorth is an energy-efficient (26 pJ per synaptic event) neuromorphic platform. SpiNNaker, built during 2009 by the University of Manchesteris a massively parallel multicore computing system. The chip is designed using UMC 130 nm CMOS technology. Physical hierarchy of the system in each node comprises two silicon diesthe SpiNNaker chip and the Mobile DDR SDRAM. The SDRAM is mounted on top of the SpiNNaker die and is wire-bonded. The 32 kB and 64 kB are inside the SpiNNaker chip as normal SRAM, like an L1 cache memory. Each processor 33 has 64 kB or tightly-coupled data memory and 32 kB of tightly-coupled instruction memory. Each SpiNNaker chip contains 18 identical ARM968 processors, a SDRAM controller, and a router [12]. The ARM cores communicate with each other and to outside through the router. SPIN-5 board has 48 SpiNNaker chips each with 18 ARM processors (864 ARM processors in total) and three SPARTAN6 FPGAs to communicate with other boards. Loihi, launched by Intel in 2018- is first fully integrated asynchronous SNN chip [13]. The chip is designed using Intel’s 14 nm FinFET process. It has a total of 130k neurons and 130 million synapses. The chip is a manycore mesh that comprises 128 neuromorphic cores, 2 embedded x86 processor cores, and off-chip communication interfaces. An asynchronous NoC facilitates communication between cores in the form of packetized messages with write, read-requests, read-response messages for core management, x86-to-x86 messaging, spike messages for SNN computation and barrier messages for time synchronization between cores. Each core contains 1024 spiking neural units grouped into tree-like structures. Other neuromorphic chips include Darwin [14], ROLLS [15], ODIN [16], DY- NAPs [17] etc. whose comparison based on specifications like technology, feature size, number of transistors, number of neurons, number of synapses, energy, etc. has been done in literature [18,19]. There are also low-cost user-friendly boards like NeuroShield that feature NM500 neuromorphic chip, which can be driven by raspberry pi or arduino [20]. 1.1.3 Memristor- a favourable synapse Memristors emerged as promising circuit elements for neuromorphic computing circuits. It relates electric charge and flux non-linearly. After Chua coined the word ‘Memristor’ and later when HP labs showed its physical existence, many memristor models were implemented to characterize, study and explore its potential applications [21–26]. Memristors are a good choice of a candidate when used as artificial synapses in CMOS-based neuromorphic computing circuits due to its property of non-volatility, analog behavior, and continuously distributed resistive states. Differ- 34 ent switching mechanisms such as redox-based, phase-change, the magnetic junction and ferroelectric, and different physical models such as conductive filament, Schottky barrier, charge trapping and electrochemical migration of point defect have been investigated to better understand the switching phenomenon [27–35]. Figure 1-1: (a) 1T1R structure, (b) Layout preview of 1T1R in MAD200 PDK, (c) Microscopic view of the monolithically integrated hybrid CMOS and OxRAM [36]. Among the different resistive switching memristors, ReRAM memristor devices, that operate by a conductive filament switching mechanism, emerged to be a very promising artificial synaptic device for high-density down-scaled synaptic crossbars. ReRAM memristor technology combines the features of high-speed performance of present SRAMs with the non-volatile property of flash memory, which can be realized at low power consumption. ReRAM memristive devices are also known for their robustness and integration capability [37]. Metal oxide-based ReRAM often referred to as OxRAM, comprises a transition metal oxide layer sandwiched between two-terminal metal electrodes so that it exhibits change in resistance when voltage pulses are applied to the electrodes. The switching-behavior of these ReRAM devices depends on the transition material (also called as dielectric) and metal electrodes. A variety of such transition materials– HfO 2 , NiO, Al 2 O 3 , Nb 2 O 5 , SrTiO 3 , Pr 0.7 Ca 0.3 MnO 3 , CuO 2 , Ag 2 S and AgGeSe– have been experimented and their switching characteristics have been studied in the literature [38–42].One such metal oxide-based ReRAM is HfO 2 -based memristive OxRAM 35 device, which is operated in binary mode, so that, the resistance of the embedded TiN-Ti-HfO 2 -TiN structure can be switched between two different resistance states, namely: LRS– typically in the order of k Ω – and HRS– in the order of hundreds of k Ω to M Ω [43,44]. HfO 2 -based OxRAMs are known for their low-switching energy, high switching speed, and high endurance when compared to other oxide-based ReRAMs [45]. The two resistance states are dynamically selected by a control voltage applied to a seriesconnected MOSFET (or selector MOSFET) transistor, leading to the so-called 1T1R structure, as illustrated in Fig. 1-1(a). With other collaborators in the project- NeuRAM3 1 we have the 1T1R synaptic structure that can be used in a PDK to design our circuits and this synaptic device is used in the thesis. The layout view of the 1T1R synapse in the MAD200 PDK is shown in Fig. 1-1(b). The hybrid process involves- 1) Deposition of 4 Cu Metal layers- M 1 , M 2 , M 3 and M 4 , 2) Deposition of TiN bottom electrode and CMP 2 touch, 3) Memory stack (HfO 2 10nm/Ti 10nm/TiN) deposition by CEA-Leti 3 , 4) 𝜑 300 nm MESA patterning. 5) Encapsulation and CMP and 6) Placing of vias and M 5 layer deposition. Fig. 1-1(c) shows the microscopic view of the monolithically integrated hybrid CMOS and OxRAM. NMOS is used as selector MOSFET with size- W = 6.7 µ m and L = 0.5 µ m, as recommended by Leti. The filament of the OxRAM is formed by applying a bias 𝑉𝑇 𝑆 = 4 V, 10 µ s pulse and gate bias 𝑉𝐺𝑆 = 1 V, with a recommended compliance forming current of about 1 µ A. For a RESET operation, a bias of 𝑉𝑆𝑇 = 3 V, 100 𝑛 s pulse is applied by keeping the gate fully ON ( 𝑉𝐺𝑇 = VDD). For a SET operation, a bias 𝑉𝑇 𝑆 = 2.4 V, 100 𝑛 s pulse is applied along with the gate bias, 𝑉𝐺𝑆 = 1.5 V. For 1 NeuRAM3 (Neural-computing architectures in advanced monolithic 3D VLSI technologies) project was an EU project that worked towards the development of a monolithically integrated 3D technology in CMOS at design rules with integrated ReRAM synaptic elements and implement on-chip learning on a scalable platform using adaptive characteristics of electronic synaptic elements. Webpage: www.neuram3.eu/ 2 Circuits Multi-Projets r (CMP) is a Multi-Project Wafer (MPW) service organization providing support for cost-effective prototyping and low volume production. Circuits are fabricated on mature process lines for academics and industrial. CMP distributes Design-Kits, that contains technology files, simulation models, design rules, and standard cell libraries. Requested design kits are sent to the customer after a non-disclosure agreement (NDA) with CMP. 3 CEA-Leti is one of the participants of the NeuRAM3 project. 36 a read operation, a read voltage of 𝑉𝑇 𝑆 or 𝑉𝑅𝑒𝑎𝑑 = 0.3 V is applied with a gate bias, 𝑉𝐺𝑆 = 3.8 V. 1.1.4 Memristive crossbar and sneak-path currents The term ‘crossbar switch’ has its origin in 1913, when J. N. Reynolds from Western Electric thought of using a crosspoint or a coordinate array to operate a large number of relay contacts by using a small number of magnets [46]. Many crossbar based architectures using two-terminal devices for memory, logic, and neuromorphic applications have been suggested during early 2000 [47–52]. Crossbars based neuromorphic circuits shown in Fig.1-2 (a) comprise of two layers of parallel electrodes that are perpendicular to each other. The two layers of parallel electrodes act as the word-lines ( 𝑊1,2,3,4 ) and bit-lines ( 𝐵1,2,3,4 ). They are arranged in a two-dimensional array, which has a synaptic element at each intersection or crosspoint. The synaptic elements can be programmed to ‘LRS’ or ‘HRS’ that represent logic- ‘1’ or ‘0’ respectively when appropriate voltages are applied to the word-lines and bit-lines. Figure 1-2: (a) A 4 × 4 memristive crossbar, (b) Read current and sneak-path current in a 4 × 4 memristive crossbar. A big setback for the memristive crossbars is the sneak-path current. Sneak-path currents are the currents that pass through the unselected path of word-lines and bit-lines, which can aggravate read and write operation performance of the crossbar thereby limiting the scalability of the crossbar [53]. When a particular synaptic device 37 is targeted in a crossbar and its current is read by applying a read voltage- 𝑉𝑟𝑒𝑎𝑑 , along with the desired read current, sneak-path currents also appear across the inference bit-line, as shown in Fig.1-2 (b). Sneak paths can cause the state of the synaptic device to be misread or changed unintentionally. Sneak paths are relevant when using crossbars as conventional digital memories (select bitline, wordline, and read value). However, when using the crossbar for analog vector-matrix multiplications, sneak paths are not critical. Several architectures, synaptic devices and read/write procedures have been proposed to mitigate the effect of sneak path currents in crossbars. Synaptic devices like two anti-serial memristors [54] and architectures like unfolded crossbar with 1D1M devices [55] have been investigated to mitigate sneak-path currents. Read techniques likemultiport read-out system with mathematical cancellation of sneak-path currents [56], threshold-based read-out system [57], a two-step read process based on “open-column" semantics [58], a three-step read (or multistage read) process for determination of state of the memristor in the presence of sneak paths [59] have been investigated. Write bias schemes- V/2 and V/3 have proven low write energy and high read margins thereby, minimizing the effect of sneak-path currents [60–62]. One approach to avoid sneak-path currents is to use 1T1R synapse [63], but this can limit the scalability. However, a greater crossbar density and smaller area overhead can be achieved by fabricating the memristor fabric on top of the CMOS layer using sub-CMOS feature size nanowires using different fabrication process. This can be achieved using spatially-distributed interface pins to connect the top-level CMOS metal layer to the nanowire crossbars [64,65]. Another interesting approach to eliminate sneak-path currents is using demultiplexer circuits based on encoded nanowire doping [66]. 1.1.5 STDP learning rule STDP is a family of learning mechanisms in computational neuroscience that exploits spike-based computation. STDP date back to 1993, when Gerstner first reported it [67]. Although the experimental existence of STDP in the biological brain has been 38 observed by many neuroscience researchers [68–75] the molecular and electrochemical principles behind it are still a debate [76]. Figure 1-3: A synaptic junction that connects a pre-synaptic and a post-synaptic neuron. Fig.1-3 illustrates a preview of the synaptic junction, where the pre-synaptic and post-synaptic neurons connect. The pre-synaptic neuron sends an action potential— 𝑉𝑚𝑒𝑚−𝑝𝑟𝑒 (= 𝑉𝑝𝑟𝑒+ - 𝑉𝑝𝑟𝑒− ) to the synapse, which cumulatively generates a postsynaptic action potential— 𝑉𝑚𝑒𝑚−𝑝𝑜𝑠 (= 𝑉𝑝𝑜𝑠+ - 𝑉𝑝𝑜𝑠− ) at the membrane of the postsynaptic neuron. Neurotransmitters are released into the synaptic cleft due to the pre-synaptic action potential. Each synapse or synaptic junction is characterized by synaptic weight (or strength)— w, which determines the efficacy of the pre-synaptic spike in contributing the cumulative action at post-synaptic neurons. By STDP, the change in synaptic weight, △ w is a function of the time difference between the presynaptic spike, 𝑡 pre and post-synaptic spike, 𝑡 pos . Hence, change in synaptic weight, △ w = 𝜉(△ T ) , where △ T=t pos − t pre . For positive △ T a potentiation of synaptic weight happens i.e. △ w > 0 and for negative △ T a depression of synaptic weight 39 happens i.e. △ w < 0. Unlike Hebbian learning [77], which considers the mean firing rate of pre and post synaptic spikes, STDP takes into account the spikes’ relative time. The machine learning and computational neuroscience community have been using STDP for applications like pattern learning, object recognition since the early 2000 [78–86]. 1.2 Contributions in Memristor based crossbars Trade-offs such as reduced chip area and energy efficiency are potential challenges that the chip designers of the neuromorphic system have. The thesis mainly focuses to address these challenges on a memristor-based neuromorphic chip which are explained here in brief. The first challenge was to make the neuromorphic system low power or energyefficient during inference. For this, we need to investigate how small read pulses can be sent. Applying such small read pulses go vain when the DC offset of the system is decisively more to ruin the system. To overcome this, we proposed a bulk-based three-stage DC offset calibration scheme across the wordlines of the memristive crossbar via a PMOS-based 2-stage differential opamp. Chapter 3 describes the proposed calibration scheme. It gives an insight view of the design of the proposed calibration scheme in the chip, chip packaging, design, and assembly of the test-PCBs, experimental set-up, and results. The results certainly includepreliminary tests of the chip, characterization of synapses, results of the calibration scheme, template matching results for pattern recognition, pattern recognition using programming and learning algorithms. The second challenge was related to the reduced chip area. During inference operation in a memristor-based fully-connected neural network, the LRS read currents are higher. Due to this, an extremely large integrating capacitor (larger than nF) is needed, which can easily increase the chip area and limit scalability for large networks. To overcome this, we proposed a new current attenuator circuit that can scale down the inference currents by a factor of about 10 4 . The results are compared with other 40 current attenuators. Chapter 4 describes the design of the new current attenuator and its results. The thesis also throws light on characterizing memristors using three different experimental set-ups, which are described in Chapter 2. One experimental set-up was using a commercially available memristor and characterizing it in ArC ONE platform. The second experimental set-up is based on a full custom silicon design that has memristors on top of it by a hybrid nano-CMOS process. Here, the characterization of memristors is done using custom-designed PCBs and FPGA driver. The third experimental set-up is based on wafer-level measurments of memristors, which are characterized using a semiconductor parameter analyzer directly or by a computer using GPIB. These characterization experiments emphasize skill-based learning on different platforms and give a first hands-on experience towards establishing a memristor-based learning system. 41 2.3 Characterization of 1T1R OxRAM-based memristors using customized PCBs Here, we made a full-customized experimental set-up for characterizing 1T1R OxRAM- based memristor, whose design-flow mainly involved— designing 1T1R crossbars using MAD200 4 PDK, packaging of the chip, planning circuits for the test-boards in order to test the packed-chip, designing the test-PCBs, assembling of components on PCB followed-by PCB mounting, making auxiliary boards, setting-up the experimental test-bench and programming drivers to get characterization results. 2.3.1 Design of 4 × 4 and 8 × 8 1T1R crossbars and its packaging Before designing the crossbars, a single 1T1R device (shown in Fig. 1-1(a)) is nominally simulated in eldoD 5 simulator using MAD200 PDK design tool to know the range of resistance values. After forming the device, a sequence of voltage pulses are applied across the terminals of 1T1R device, such that a repetitive sequence of ‘Erase’-‘Read’-‘Write’-‘Read’ operations are performed after forming the device. Voltage biases, drain current of the selector MOSFET, and resistance of the device are shown in Fig. 2-4. The nominal simulation results in LRS = 13.65 k Ω and HRS = 836.4 k Ω for a 1T1R device. Since these are the preliminary analyses, a reasonable amplitude and pulse widths are used for switching. Later, in the experimental set-up, we have used the Leti 6 -recommended biases and pulse-widths for different operations. Fig. 2-5 shows the schematic and layout view of the 4 × 4 1T1R crossbar and Fig. 2-6 shows the schematic and layout view of the 8 × 8 1T1R crossbar. The principle behind operating the crossbar is— 4 MAD200 (or Memory Advanced Demonstrator 200mm) uses monolithic integration of OxRAMs above the four-metal layered 130 nm CMOS technology. Leti collaborates to grow OxRAMs above these metal layers, which is followed by the deposition of the metal layer, M5. 5 EldoD is used as the simulator, as the OxRAM is modeled in SPICE netlist and is used as an add-on in the PDK. 6 CEA-Leti is a foundry and one of the participants of the NeuRAM3 project. Although Leti has recommended and shared the promising bias conditions (amplitude, pulse-width, and compliance current) for the 1T1R device, we did try various amplitudes and pulse-widths with our test-benches to find the optimal values. 48 Figure 2-4: Simulation results showing repetitive sequence of ‘Erase’-‘Read’-‘Write’- ‘Read’ operations carried out on 1T1R device after forming it- (a) Voltage biases applied at the terminals of the 1T1R device, (b) Drain currents of the selector MOSFET, (c) Resistance of the OxRAM, (d) A zoom preview of the resistance of the OxRAM after forming. to choose the active wordline (or row), bitline (or column) and gate-bias and perform the needed operation such as ‘form’, ‘erase’, ‘write’ and ‘read’. The remaining default rows and columns are biased with default values so that their corresponding 1T1R devices are not disturbed. The active and default biases for OxRAM operations slightly vary depending on the configuration of the gate-lines. In 4 × 4 1T1R crossbar the gate-lines are pulled bitline-wise whereas, in 8 × 8 1T1R crossbar, the gate-lines are pulled wordline-wise. 49 Figure 2-5: (a) Schematic view of the 4 × 4 1T1R crossbar, (b) Layout view of the 4 × 4 1T1R crossbar. Figure 2-6: (a) Schematic view of the 8 × 8 1T1R crossbar, (b) Layout view of the 8 × 8 1T1R crossbar. 50 Figure 2-7: Switching biases for active and default wordlines and bitlines for various operations performed in OxRAM when gate-lines are pulled bitline-wise. Figure 2-8: Switching biases for active and default wordlines and bitlines for various operations performed in OxRAM when gate-lines are pulled wordline-wise. 51 Figure 2-9: Layout view of MAD200 chip showing layouts of 4 × 4 and 8 × 8 1T1R crossbars duly connected with their pads. The change in orientation of the gate-lines is made between the two crossbars to differentiate and realize how the active and default biases of bitlines and gatelines vary in both cases. Nevertheless, in both crossbars the principle idea– to target a 1T1R device and perform the desired OxRAM operation is the same. Fig. 2- 7 shows the active and default biases for various operations performed in OxRAM when the gate-lines are pulled bitline-wise in a crossbar whereas, fig. 2-8 shows the active and default biases for various operations performed in OxRAM when the gatelines are pulled wordline-wise. In figuresfig. 2-7 and fig. 2-8 the nomenclature used for the terminals is ‘X_YYYY_ZZZZ’, where ‘X’ denotes the first-letter of the operations such as, ‘F’ (for ‘form’ operation), ‘W’ (for ‘write’ operation), ‘E’ (for ‘erase’ operation) and ‘R’ (for ‘read’ operation). ‘YYYY’ denotes the type of bias, which can be ‘act’ (for active) or ‘def’ (for default). ‘ZZZZ’ denotes the type of the terminal, which can be either wordline (denoted as ‘row’ or ‘post’) or bitline (denoted as ‘col’ or ‘pre’) or gate-terminal (denoted as ‘gcol’ or ‘gate’). 52 Both the crossbars are part of the circuits that are designed and taped out in the MAD200 7 run. MAD200 chip comprises three categories of layouts and they are— layouts of circuits whose pads form the outer-ring 8 , layouts of circuits whose pads form the Inner-ring (which has other circuits submitted for MAD200 run), and the layouts of circuits that are present between the two rings. The layout of 8 × 8 1T1R crossbar along with its pads is part of the outer-ring, whereas the layout of 4 × 4 1T1R crossbar is present between the two rings. The layout view of MAD200 chip highlighting both 4 × 4 and 8 × 8 1T1R crossbars along with their pads are shown in Fig. 2-9. The outer-ring (which has 8 × 8 1T1R crossbar) is packaged in PGA100 package and the 4 × 4 1T1R crossbar is packaged in the PLCC52 package. Fig. 2-10(a) shows the top view of the packaged chip that has a layout of 4 × 4 1T1R crossbar. Fig. 2-10(b) shows the layout view of 4 × 4 1T1R crossbar with its pads numbered for packaging. Fig. 2-11(a) shows the top view of the packaged chip that has outer-ring and Fig. 2-11(b) shows the bonding diagram of the outer-ring using the PGA100 package. 2.3.2 Design of circuits for the test-PCBs Test-circuits are designed on PCBs to characterize the crossbars. Fig. 2-12 and Fig. 2-13 show the functional block diagram for testing 4 × 4 and 8 × 8 1T1R crossbars respectively. The main functional blocks in these test-circuits are the opamps (used for analog biases), switches, level-shifters (used for bi-directional conversion between 4.8 and 3.3 V), decoders, linear voltage regulators (used for ensuring different supply voltages), ADC (used for reading the current) and SPARTAN r -6 FPGA board (used to program and digitally control the PCB and crossbar). The nomenclatures used for the functional blocks in Fig. 2-12 and Fig. 2-13 are— ‘S’ for switches, ‘ADC’ for Analog-to-Digital converter, ‘OA’ for Operational Am- 7 MAD200 is run for tape-out of the microchip in the NeuRAM3 project. The GDS file of the chip was submitted on February 2017 and the chip (also referred to as ‘MAD200 chip’) was received after 18 months due to the complex hybrid fab. procedure. 8 Outer-ring of MAD200 chip comprises layouts of three circuits along with its pads. Layout of 8 × 8 1T1R crossbar is one of the three circuits. 53 Figure 2-10: (a) Top view of a PLCC52 package (with its pin numbers) that is packaged with 4 × 4 1T1R crossbar of MAD200 chip, (b) Layout view of 4 × 4 1T1R crossbar duly labeled and numbered for packaging in PLCC52. Figure 2-11: (a) Top view of a PGA100 package that is packaged with Outer-ring of MAD200 chip, (b) Bonding diagram of the Outer-ring using PGA100 package. plifiers’, ‘LS’ for Level-shifters, and ‘LVR’ for Linear Voltage Regulator. Functional block diagrams also show the control-bits needed to target a device in 4 × 4 (6-bit) and 8 × 8 (9-bit) crossbars. These control-bits are marked in color in each device location of the crossbar array. A detailed schematic of the test-circuits for testing 4 × 4 and 8 × 8 1T1R crossbars are shown in Fig. A-1 and Fig. A-5 respectively in 54 appendix A. Test-circuits for crossbars facilitate targeting a 1T1R device in the crossbar and performing the needed operation without disturbing other devices. The active and defaultwordlines, bitlines, and gates are chosen using decoders. The opamps are used to set optimal values of biases that are needed for the targeted 1T1R device to ‘form’, ‘erase’, ‘write’, ‘read’, or keep ‘idle’ or ‘global’ 9 values. All opamps are also availed with the flexibility to tune the feedback components in the case, if needed for stability reasons. The switches between the opamps and crossbar-terminals are digitally controlled by FPGA to make sure that the desired biases are applied for the corresponding operation. The switches are connected such that, a 3-bit control word, {𝐹𝑃𝐺𝐴 _ 𝐴, 𝐹𝑃𝐺𝐴 _ 𝐵, 𝐹𝑃𝐺𝐴 _ 𝐶} is used to decide the needed operation performed on the OxRAM in the targeted 1T1R device in the crossbar, whose possible control Figure 2-12: Functional block diagram of the test-circuit for testing 4 × 4 1T1R crossbar. 9 ‘Idle’ or ‘Global’ operation of OxRAM is biasing the crossbar terminals with equal voltage amplitudes and keeping the gate-biases to 0V. 55 Figure 2-13: Functional block diagram of the test-circuit for testing 8 × 8 1T1R crossbar. bits and its corresponding OxRAM operations are shown in Table 2.1. Here, ‘ON’ indicates 4.8 V (vdd) and ‘OFF’ indicates 0V. 2.3.3 Assembly and mounting of test-PCBs and customized boards Test-PCBs are made according to the test-circuits described in Fig. A-1, Fig. A-5, Fig. A-6 and Fig. A-7. Two four layered-PCBs are designed using OrCAD r CIS 10 and Allegro r 11 , whose design details are described in appendices A.1 and A.2. One 10 OrCAD r Capture is one of the most widely used schematic design solutions for the creation and documentation of electrical circuits. Coupled with the optional OrCAD CIS product for component data management, the designer can use components in the schematic that can be used later in Allegro r PCB designer suite to design PCBs. 11 Allegro r PCB Designer of Cadence r is a scalable, proven PCB design environment that addresses technological and methodological challenges thereby, making the design cycles shorter and 56 Table 2.1: Control-bit for performing different operations for OxRAM in the targeted 1T1R device in the crossbar. OxRAM operation FPGA_A FPGA_B FPGA_C ‘Form’ ON ON ON ‘Erase’ OFF ON ON ‘Write’ OFF OFF ON ‘Read’ OFF OFF OFF ‘Idle’ or ‘Global’ ON OFF ON of them is designed exclusively for testing 4 × 4 1T1R crossbar and the other is for testing different circuits in the outer-ring. 8 × 8 1T1R crossbar is a part of the circuits in the outer-ring. The components used for the PCB are chosen carefully by going through their data-sheets. Parameters such as, operating voltage range, bandwidth, switching characteristics, etc. are considered for choosing the components, and for those components which have PSpice 12 model— are simulated to visualize their characteristics. Once the PCBs are designed the resulting gerber 13 files are sent to a PCB manufacturing company and the components in the BOM list are ordered. The PCB components are soldered to the PCB and the PCB is mounted using corner screws. Some guidelines for a better PCB assembly and mounting practice are narrated in appendix A.3. Along with the PCBs, few auxiliary boards are made to avail of some buttons (to facilitate programming of driver) and to ease probing of terminals of crossbars. 2.3.4 Description and working of the experimental set-up Experimental set-up for characterizing both 4 × 4 and 8 × 8 1T1R crossbars is similar except few changes. The main components in the experimental set-ups are the packpredictable. 12 PSpice models of more than 33k components can be simulated in Cadence r before making PCB layouts to observe their working characteristics at circuits-level. 13 Gerber format is an open 2D binary vector image file format. It is the standard file used by PCB industry software to describe the printed circuit board images: copper layers, solder mask, legend, etc. The gerber files can be viewed in any third-party gerber viewer such as ViewMate, etc. for verification. Gerber files are the raw files needed by the PCB manufacturing company to make PCBs. 57 Figure 2-22: Default and active biases (in the form of pulses) applied across rows, columns and gates of the 8 × 8 crossbar for the sequential OxRAM operations- ‘Erase_Global_Read’. Figure 2-23: Default and active biases (in the form of pulses) applied across rows, columns and gates of the 8 × 8 crossbar for the sequential OxRAM operations- ‘Write_Global_Read’. 64 Figure 2-24: Default and active biases (in the form of pulses) applied across rows, columns and gates of the 8 × 8 crossbar for the sequential OxRAM operations- ‘Read’. Figure 2-25: Read operation in a single 1T1R device in the 4 × 4 crossbar: (a) Read scheme and biases showing a targeted 1T1R device in a 4 × 4 crossbar, (b) Observation of terminals of the ‘Read’ scheme in oscilloscope after a ‘Write_Global_Read’ operation performed on the targeted 1T1R device, (c) Observation of terminals of the read scheme in oscilloscope after an ‘Erase_Global_Read’ operation performed on the targeted 1T1R device. Fig. 2-23 shows the active and default biases of the rows, columns, and gateterminals when the sequential operation— ‘Write_Global_Read’ is performed on a targeted OxRAM in a 8 × 8 crossbar. Fig. 2-24 shows the active and default biases of the rows, columns, and gate-terminals when the sequential operation— ‘Read’ is performed on a targeted OxRAM in a 8 × 8 crossbar. In all the above figures that 65 Figure 2-26: Output of ADC Vs differential input of ADC for the whole resistance range thereby, highlighting both LRS and HRS of OxRAM. shows the biases (in the form of pulses) needed for different OxRAM operations, the amplitudes and pulse-widths needed are duly labeled on them. The bias conditions for various OxRAM operations are shown in Table 2.2, whose values vary slightly from the one recommended by Leti. The read procedure can be done in two ways. One is by directly observing the differential inputs of the ADC and another way is to check the output of ADC. Fig. 2-25 shows both the read approaches. Here, Fig. 2-25 (a) shows the ‘Read’ scheme implemented where the targeted 1T1R device is operated with a ‘Read’ voltage of 0.3 V. The ‘Read’ task is performed via an opamp and an ADC in order to get the resistance of the OxRAM. When a ‘Write_Global_Read’ operation is performed with a ‘Read’ voltage of 0.3 V, the differential input to ADC becomes 2.4 V - 1.27 V = 1.13 V. This results in, 66 𝐿𝑅𝑆 = ( 40 k Ω 2.4 V −1.27 V )×0.3 V = 10.62 k Ω (2.1) where, 40 k Ω is the read resistor placed across the read opamp. This resistor across the terminals- Ain+ and Ainis shown in Fig. 2-25 (a). Similarly, when a ‘Erase_Global_Read’ operation is performed with a ‘Read’ voltage of 0.3 V, the differential input to ADC becomes 2.4 V - 2.35 V = 0.5 V. This results in, 𝐻𝑅𝑆 = ( 40 k Ω 2.4 V −2.35 V )×0.3 V = 240 k Ω (2.2) Fig. 2-25 (b) and Fig. 2-25 (c) show various biases of the read circuitry when sequential tasks— ‘Write_Global_Read’ and ‘Erase_Global_Read’ are performed on a targeted 1T1R device. One can see how— bias of the terminal ‘Ain-’ changes in both LRS (resistance after the sequential operation- ‘Write_Global_Read’) and HRS (resistance after the sequential operation- ‘Erase_Global_Read’) during ‘Read’ part of the waveform. The second way to determine the resistance state of the targeted OxRAM is to observe the output of ADC, which can be stored in a register in the FPGA for further processing, when doing some learning. The 10-bit ADC is clocked with a 1.25 MHz clock signal and it uses only first 9 bits to quantify the differential input or the resistance of the targeted OxRAM, as the signal of MSB (which is the 10-bit) depends on the sign of the difference of the input signals [108]. The MSB signal– ‘FPGA_ADC_9’ goes high (3.3 V) when the difference of the ADC’s inputs becomes less than zero and goes low (0 V) when the difference of the ADC’s inputs becomes equal to or greater than zero. Signal ‘FPGA_ADC_OTR’ goes low (0 V) when the difference of the ADC’s inputs is in between the range of voltage– -1.030 and +1.36 V for the whole input span of about 2 V and it becomes high (3.3 V) when it is out of this range. Fig. 2-26 shows the output of ADC in decimal for various differential input values of ADC where both LRS and HRS are highlighted. 67 2.3.5 Experimental results of characterization of 1T1R based memristors The OxRAMs in the crossbar are formed initially so that, they are in LRS. Then they are switched between HRS and LRS. All OxRAM operations like ‘form’, ‘erase’, ‘write’ and ‘read’ are carried out as explained in Section 3.4.4. Two tests have been carried out. The first test is a single switch between LRS and HRS for all 64 1T1R devices of 8 × 8 crossbar. The results of this soft-test are shown in Fig. 2-27. The second test is carried out for a 1T1R device of 4 × 4 crossbar by switching the device between LRS and HRS for 10 3 cycles. The switching characteristics of this hard-test are shown in Fig. 2-28. Fig. 2-29 and Fig. 2-30 shows the cycle-to-cycle variability results for LRS and HRS for 10 3 cycles. It is observed from the variability results that standard deviation of HRS, 𝜎𝐻𝑅𝑆 is high and as cycle number increases, the device degrades with HRS approaching LRS. The variability results of LRS appear fine with a 𝜎𝐻𝑅𝑆 of 4.4 k Ω and µ 𝐿𝑅𝑆 of 22 k Ω . Figure 2-27: HRS and LRS values of OxRAMs of all 64 1T1R devices in 8 × 8 crossbar. 68 Figure 2-28: Switching of resistance of OxRAM of a 1T1R device between HRS and LRS for 10 3 cycles. Figure 2-29: Cycle-to-cycle variability results of LRS for 10 3 switching cycles. 69 Figure 2-30: Cycle-to-cycle variability results of HRS for 10 3 switching cycles. 2.4 Characterization of MIM-based memristors using SPA Wafer-level I-V characteristic-measurements are performed on MIM based memristors. The MIM based memristors are built on silicon oxide of thickness 200 nm. Above it, a 200 nm thick layer of Tungsten (W) is built, which acts as the bottom electrode. A dielectric layer is deposited above it, whose thickness and composition depend on the ALD process used. There’s a TiN layer of thickness 200 nm built on top of the dielectric, which acts as the top electrode. Structurally, MIM based memristors are three-layered (as shown in Fig. 2-31), while OxRAMs are 4 layered. When it comes to the fabrication process, 1T1R based memristors are taped out in a complex monolithic integration by growing OxRAMs above the CMOS part while MIM based memristors are grown in layers using Atomic Layer Deposition (ALD) process. ALD processtypically uses two chemicals to create an alternate, saturated, chem- 70 Figure 2-31: Structure of a MIM based memristor. ical reactions on the surface, resulting in a unique self-limiting growth with many excellent features like conformality, uniformity, repeatability and accurate thickness control [109]. These chemicals (precursors) do not exist in the gas phase at the same time as typical CVD processes. Rather, precursors are pulsed sequentially in an inert carrier gas through a heated batch of substrates, with a purge time between the pulses to prevent vapor phase reactions. ALD is, therefore, suitable for the synthesis of thin solid layers of inorganic materials even as thin as one molecular monolayer. Savannah 200 is the equipment used for ALD and it is shown in Fig. 2-32. Figure 2-32: Savannah 200 from Cambridge NanoTech Inc. [109]. 71 2.4.1 Experimental set-up In our experiments, we plan to do wafer-level I-V measurements for nine wafers, whose dielectric compositions are obtained from different ALD processes, which are shown in Table 2.3. The I-V characteristics are obtained on 15 × 15 µ m 2 sized MIM based memristors on all nine wafers. Fig. 2-33 shows the wafer map with a preview of a chip and a zoom preview of 5 × 5 µ m 2 and 15 × 15 µ m 2 sized MIM based memristors. Table 2.3: Different dielectrics used in ALD process Wafer no. ALD process Thickness (nm) W 1 HfO 2 standard process 10.6 ± 0.18 W 2 HfO 2 process with short H 2 O pulse 10.5 ± 0.2 W 3 HfO 2 process with large N 2 flow rates 10.2 ± 0.14 W 4 [HfO 2 (6 cycles) + Al 2 O 3 (1 cycle)] × 14 + HfO 2 (4 cycles) 11.6 ± 0.08 W 5 Al 2 O 3 process at 225 ∘ C 99 ± 0.04 W 6 [Al 2 O 3 (6 cycles) + HfO 2 (1 cycle)] × 14 + Al 2 O 3 (4 cycles) 12.7 ± 0.14 W 7 [Al 2 O 3 (16 cycles) + HfO 2 (75 cycles)] × 14 + Al 2 O 3 (16 cycles) 13 ± 0.1 W 8 [HfO 2 75 cycles) + Al 2 O 3 (16 cycles) 11.9 ± 0.08 W 9 HfO 2 process at 150 ∘ C10.5 ± 0.2 The characterization experiments are performed mainly using the MPITS2000 probe station 16 [110] and HP4155B SPA. Placing the wafer in MPITS2000 probe station is done in three steps. At first, the station is initiated and the wafer is placed on the chuck either by front or loading from side thereby, turning on the vacuum. The second step is to train the contact needles and make two-point alignment of the wafer. The third step is to establish contact on the designed structures using needles for taking measurements. All these are done using the MPI Sentio r 17 software suite. The tri-axial cables connect both the probes of MPITS2000 and the SMUs of 16 MPITS2000-SE from MPI is the first ever 200 mm automated probe system. The probe station is known for its ultra-low noise, very accurate and highly reliable DC/CV, RF and high power measurements. 17 MPI Sentio r is the multi-touch prober control software suite used to probe wafer in MPITS2000 probe station. The GUI of Sentio r is used to make precise alignment of wafers and establish contacts for measurement. 72 Figure 2-33: Wafer map showing a preview of a single chip with zoom previews of 5 × 5 µ m 2 and 15 × 15 µ m 2 sized MIM based memristors. HP4155B SPA. The experimental set-up is shown in Fig. 2-34. One can perform experiments directly using the front panel of SPA or using MATLAB scripts running in a computer by connecting it to SPA by GPIB. Here, the experiments are carried out using MATLAB scripts running in a computer by connecting it to SPA by GPIB. Once the needles are placed on the pads of the MIM structured memristors, DC voltage sweeps are done to characterize the memristors. A full cycle of switching 73 read pulse amplitude little becomes non-trivial as the offset voltages of the system affect the results. To overcome this problem, the opamps used, either in the neuron circuits or the buffers need to be finely calibrated to reduce their input DC offset voltage, which ultimately sets the resting voltage level of the crossbar lines higher than electrical noise. Figure 3-1: OxRAM currents for low read voltage pulses. 3.2 Three-stage bulk-based DC offset calibration approach As conventional calibration schemes can compensate for offset ranges in the order of a few mV [112], we propose a finer calibration technique. Our proposed calibration scheme is based on compensating the DC offset by varying the bulk voltage of one of the transistors that form the input differential pair of the amplifiers. To this end, a cascade of resistor ladders is used, which allows us to increase the accuracy of the reference voltage, yielding to a calibration step lower than 0.1 mV. The calibration scheme is implemented on a 4 × 4 1T1R crossbar, whose conceptual diagram is shown in fig. 3-2. 80 Figure 3-2: Conceptual diagram of the proposed three-stage calibration scheme in the 4 × 4 1T1R crossbar. 3.3 Design of 1T1R crossbar with three-stage DC offset calibration scheme Fig. 3-3 shows the scheme of 1T1R synapses used as programmable interconnects in a 4 × 4 crossbar with the circuitry of DC offset voltage calibration in each wordline. Each wordline has its pre-synaptic driver and each pre-synaptic driver has its opamp (used in buffer configuration), an I-pot (a current bias circuit for opamp) and a threestage DC offset calibration circuit. There is an edge-triggered D-flip flop based shift register to load control-bits for the current-bias circuit and the calibration circuit. There are 16 1T1R structures arranged in a 4 × 4 matrix, whose wordlines𝑤1,2,3,4 are connected to the output of their corresponding pre-synaptic driver. The gates, 𝑔1,2,3,4 are pulled out bitlinewise and a post-synaptic neuron follows the source of the NMOS in each bitline of the 1T1R array. The main sub-circuits used to implement the bulk-based calibration scheme in a 4 × 4 1T1R crossbar are the two-stage PMOS-based differential opamp, pulse-shaping digital block, three-stage calibration scheme, I-pots, shift-register, and post-synaptic drivers. The design details of all these sub-circuits are explained in the forthcoming sub-sections of this chapter, which follows additional 81 Figure 3-3: Scheme of a 4 × 4 1T1R crossbar with DC offset voltage calibration in each wordline. circuits’ detail, their transistor-level electrical simulation results (done using spectre or eldoD simulator 1 ), description and working of the experimental set-up, and finally, the verification of experimental results of the calibration scheme. All circuits, except the post-synaptic drivers, are designed using MAD200 PDK, where the OxRAM devices are monolithically integrated above the CMOS part of the chip. Layout-extracted simulations, taking into account technology-process corners, PVT variations, noise effects, and temperature variation feature that worst-case offset voltage in the order of 3 mV can be compensated down to 200 µ V. This compensated 1 Spectre is a SPICE-class circuit simulator developed at Cadence Design Systems r . EldoD is a pure SPICE simulator developed by Mentor Graphics r . Spectre emerged as a fast, more accurate, and reliable simulator when compared to the SPICE simulator [113]. 82 DC offset voltage is further limited by fabrication defects in OxRAM such as nano battery effect, which is due to non-homogeneous ion distribution in the electrolyte [114,115]. 3.3.1 Design of two-stage PMOS-based differential pair opamp We intend to design an opamp that meets the design criteria and specifications of DC offset calibration schemeimplemented in a crossbar. The main design challenge is to put the differential pair MOSFETs of the opamp in separate wells, as we need to access bulk-terminals of the MOSFETs. The specification we need to meet is to implement a fine calibration in the order of 100 µ V steps or even less. Of course, this calibration output will be limited further by mismatch, electrical noise, parasitics in layout (if critical), experimental set-up, and other factors. Figure 3-4: Possible wells used in bulk CMOS process: (a) n-well process, (b) p-well process, (c) Twin-well process, (d) Triple-well process. MAD200 PDK has front-end design features such asshallow trench isolation, triple well 2 (NISO 3 ), twin-tub (or twin-well) 4 , single poly CMOS process using a 2 Triple-well is using different n-wells on p-substrate, which is lightly doped. It is mainly used to allow bodies of the MOSFETs to be at different potentials. The added n-well (that houses p-well) form a diode, which electrically isolates the p-well from the substrate, as shown in fig. 3-4(d). 3 NISO stands for ‘N Isolation’. It represents burying N-layer to isolate the p-well and underneath the NMOS devices to enable forward bias and back bias. 4 Twin-well is using two wells on the same substrate (either p-substrate or n-substrate), which 83 Figure 3-5: Schematic view of the two-stage differential opamp. type <100>P_EPI(4 µ m; 11.5 Ω .cm)P+substrate(10 m Ω .cm) and back-end design featuring damascene copper process 5 for all four metal levels. Fig. 3-4 shows the possible wells used in the bulk CMOS process [116]. Here, in our work, we used n-well CMOS process. In the n-well CMOS process, if we use NMOS differential pair for the opamp we need to have all the bulks connected to the substrate and hence we opted to keep PMOS for the differential pair. Here, we can make separate wells and bias them at different voltages. The design approach of the opamp is based on iterating betweendesigning, analyzing by simulation, modifying the design; and obtaining new specifications. The opamp specifications such as gain, phase margin, bandwidth, ICMR values, power dissipation, slew rate, etc. are initially set to target values by considering its use as a buffer across the wordline to have two states of resistances as load condition when is lightly doped to reduce excessive doping effects. Twin-well is used when bodies of NMOS are all biased with the same potential. Twin-well is shown in fig. 3-4(c) 5 Damascence copper process - is a novel method of copper metalization to overcome problems like fast diffusion of Cu into Si and SiO2, poor oxidation/corrosion resistance, poor adhesion to SiO2 and difficulty in the conventional dry-etching technique. Unlike the conventional method, it is done by CMP and by using special barrier layers like Ta, TaN, TiN, and TiW to prevent intermixing of materials above and below the barrier. 84 used in a crossbar architecture. We also considered the operating frequency range of the pulses we should apply, bandwidth, and a worst-case of 5 pF load capacitor when setting the initial values of the specifications. We decided to keep mismatch low, wherever possible in the design. After determining the specifications of the opamp through various analyses the design parameterslike the sizing of MOSFETs and capacitance of the compensation capacitor are changed accordingly. Fig. 3-5 shows the schematic view of the two-stage differential opamp, whose differential pair MOS- FETs’ body-inputs are put in separate wells for biasing separately. Opamp comprises MOSFETs- M 1,2,....8 and miller compensation capacitor, 𝐶𝑐 . The opamp design is carried out by biasing 𝑖𝑏𝑖𝑎𝑠 with 40 µ A and keeping the bulks ( 𝐶𝑎𝑙𝑖𝑏𝑟𝑒𝑓 and 𝑂𝑢𝑡 _ 𝑐𝑎𝑙𝑖𝑏 ) at vdd. Fine-tuning of opamp specifications are carried out iteratively by keeping the following design relationships [117,118] and optimizations- 1. For keeping Phase Margin (PM) of minimum 60 ∘ (targeted initial value), the condition for compensation capacitor’s capacitance, 𝐶𝑐≥0.22 ×𝐶𝐿 (3.1) is met. Here, a worst-case capacitance of 5 pF is considered as 𝐶𝐿 . When starting the design, compensation capacitor’s capacitance is considered by taking 𝐶𝑐≥(2 𝑜𝑟 3)×0.22𝐶𝐿 by considering the parasitic effect and to keep flexibility at later design stages for tuning parameters such as gain bandwidth product, slew rate, etc. 2. Slew rate (SR) is tuned by altering the bias current, 𝑖𝑏𝑖𝑎𝑠 and the sizes of the MOSFETs- M 8 and M 5 . Slew rate is related to the drain current of MOSFET, M 5 by the relation, 𝑆𝑅 =𝐼𝐷5 𝐶𝑐 (3.2) Here, I 𝐷5 is the drain current of MOSFET- M 5 and 𝐶𝑐 is the compensation capacitor’s capacitance. 85 3. DC operating point parameters (like 𝛽𝑒𝑓𝑓 , mobility of ions, threshold voltages, etc.) are obtained by simulating the diode-connected (or when MOSFETs are put in saturation region) PMOS and NMOS transistors of size- W = 10 µ m and L=2 µ m. Though the minimum channel length of the MOSFET by PDK’s design rule is 0.5 µ m, we kept the minimum length of all MOSFETs in our design as 2 µ m for mismatch reasons, as short channels, can degrade matching the behavior of MOSFETs by extra mismatch effects like RSCE 6 . 4. Gain Bandwidth Product (GBW) is tuned by changing sizes of differential pair MOSFETs- M 1,2 by the relation, 𝐺𝐵𝑊 =𝑔𝑚1 𝐶𝑐 (3.3) Here, 𝑔𝑚1 is the transconductance of MOSFET- M 1 and 𝐶𝑐 is the compensation capacitor’s capacitance. 5. ICMR+ value can be tuned by changing sizes of current mirror MOSFETs- M 3,4 and ICMR- value can be tuned by resizing MOSFET- M 5 . The relationship of the ICMR values with MOSFET-sizes of M 3,4,5 is given by, (︂𝑊 𝐿)︂3,4 =2𝐼𝐷3 µ𝑛𝐶𝑜𝑥[𝑉𝐷𝐷 −𝐼𝐶𝑀𝑅 + +𝑉𝑡3𝑚𝑎𝑥 |𝑉𝑡1𝑚𝑖𝑛 |]2 (3.4) (︂𝑊 𝐿)︂5 =2𝐼𝐷5 µ𝑝𝐶𝑜𝑥[𝐼𝐶𝑀𝑅 −−√︁2𝐼𝐷1 µ𝑝𝐶𝑜𝑥 − | 𝑉𝑡1𝑚𝑖𝑛 |]2 (3.5) Here, 𝐼𝐷3 and 𝐼𝐷5 are the drain current of MOSFETs- M 3 and M 5 respectively. µ𝑛 and µ𝑝 are the mobilities of electrons and holes respectively. 𝐼𝐷1 is the drain current of MOSFET- M 1 . 𝑉𝑡3𝑚𝑎𝑥 is the threshold voltage of MOSFET- 6 RSCE (Reverse Short Channel Effect) is an increase of threshold voltage with decreasing channel length. At short-channel length the halo doping of the source overlaps that of the drain, increasing the substrate doping concentration in the channel area, and thus increasing the threshold voltage. This increased threshold voltage requires a larger gate voltage for channel inversion. 86 M 3 for maximum common-mode voltage and 𝑉𝑡1𝑚𝑖𝑛 is the threshold voltage of MOSFET- M 1 for maximum common-mode voltage. 6. By current or transconductance relation, (︀𝑊 𝐿)︀7 (︀𝑊 𝐿)︀4 =𝑔𝑚7 𝑔𝑚4 (3.6) we can further tune the size of MOSFETs- M 4 and M 7 or even phase margin (if needed), as for 60 ∘ of phase margin, 𝑔𝑚7≥10 ×𝑔𝑚1 . Here, 𝑔𝑚1 and 𝑔𝑚7 are transconductances of MOSFETs- M 1 and M 7 respectively. 𝑔𝑚1 is determined earlier when tuning GBW using equation 3.3. 7. The design condition, (︀𝑊 𝐿)︀7 (︀𝑊 𝐿)︀4 = 2 ×(︀𝑊 𝐿)︀6 (︀𝑊 𝐿)︀5 (3.7) to keep the opamp’s schematic balanced and to keep minimal systematic DC offset of the opamp is met. Care is also taken that the opamp’s gain is not underestimated during AC analysis. This is done by carefully tuning the DC component of VCM during AC analysis for getting the maximum gain, which is obtained previously in the DC sweep analysis. 8. MOM capacitor is used as a Miller compensation capacitor [119], 𝐶𝑐 because of its characteristics like high density, good matching, and low parasitics. 9. The following relationships are further considered when tuning different parameters and specifications of the two-stage opamp- 𝐶𝑐∝𝑃𝑀 ∝1 𝐺𝐵𝑊 (3.8) 𝐿6∝𝐺𝐵𝑊 ∝1 𝑃𝑀 ∝1 𝐺𝑎𝑖𝑛 (3.9) 87 𝑊7∝𝑃𝑀 ∝1 𝐺𝐵𝑊 ∝1 𝐺𝑎𝑖𝑛 (3.10) 𝐹𝑙𝑖𝑐𝑘𝑒𝑟 𝑛𝑜𝑖𝑠𝑒 ∝1 𝑊𝐿 (3.11) 𝑀𝑖𝑠𝑚𝑎𝑡𝑐ℎ 7 ∝1 𝑊𝐿 (3.12) 10. We also used ‘multiplier’ or ‘number of fingers’ option when making layouts and split the width of the MOSFET to make parallelly-connected MOSFET structures that are arranged in a stack, such that all sources and drains of each element are connected in parallel by suitable metal connections, where some of the drain and source connections serve two different elements thereby, reducing the silicon area and its associated reduction of the parasitic 8 capacitance of the two junctionssource-substrate and drain-substrate. 11. Layouts of the current-mirror MOSFET pairs- M 5,8 and M 3,4 are made using techniques like inter-digitized scheme and common-centroid technique to consume less silicon area and keep parasitic capacitance of the substrate junctions low [120]. Various analyses such as DC sweep analysis- to determine DC systematic offset, maximum DC open-loop gain, AC analysis- to determine AC gain, phase margin, gain bandwidth product, slew-rate determination experiment, Monte Carlo DC offset variation for mismatch and noise analyses- to determine summarized and input-referred noise— are all done for different load configurations. On top of this, a post-layout simulation was done to observe the effect of parasitics in the layout. Table 3.1 shows the values of the MOSFET sizes of the designed opamp. Fig.3-6(a) shows the layout 7 Mismatch reduces on using less area. Mismatch also reduces when QUAD (square-shaped) layout structures are used. One way to do this is to connect MOSFETs in parallel by dividing its width. 8 Parasitic effects are the spurs that appear because of interference between interconnections’ lines and they come from the substrate or can be the consequence of opening switches. Parasitic effects can be reduced by making symmetrical layouts. 88 Figure 3-6: (a) Layout view of the two-stage differential opamp, (b) Parasitics extracted layout view of the two-stage differential opamp. view of the two-stage opamp and fig.3-6(b) shows the layout view of the opamp after parasitic extraction. Fig.3-7(a) shows the technology-process corner 9 and fig.3-7(b) shows Monte Carlo 10 variation (300 runs) of DC transfer curve of the opamp. Fig.3-7(c) shows the Monte Carlo (300 runs) distribution of the DC offset voltage of opamp and comparison of nominal and layout-extracted simulated DC transfer curve of the opamp is plotted in fig.3-7(d). A shift of about 100 µ V between the schematic and layout-extracted simulated DC transfer curve of the opamp is due to the real parasitic components in the extracted layout. The opamp has a gain of 101 dB, a phase margin of 60∘ and a slew rate of 15.07 V/ µ s when connected with a capacitive load of 5 pF. It has a gain of 69.3 dB, a phase margin of 66.2 ∘ and a slew rate of 13 V/ µ s when connected to a R L C L load of R L = 2 k Ω ; C L = 5 pF. It is observed to have a gain of 98.5 dB, a phase margin of 60∘ and a slew rate of 15.04 V/ µ s when connected to a R L C L load of R L = 225 k Ω ; C L = 5 pF. The load resistors are chosen based on the HRS and LRS values of the 1T1R device. 9 Technology-process corners include Front End Of Line (FEOL) corners. The best-case and worst case corners are classified based on different design parameters like mobility, vth variation, the resistance of the actives, body coefficient, oxide thickness, and PVT variations. 10 Monte Carlo simulations include both process (wafer-to-wafer variations), On-Chip Variations (OCV) like device mismatch. 89 Figure 3-13: Monte Carlo variation results of the three-stage calibration scheme: (a) Monte Carlo variation results of signals - V 𝑟𝑒𝑓 - V 𝑑 , V 𝑟𝑒𝑓 + V 𝑑 , 𝑇𝑜𝑝1 and 𝐵𝑜𝑡𝑡𝑜𝑚1 (b) A zoom-preview of monte Carlo variation results showing signals - 𝑇𝑜𝑝2 , 𝐵𝑜𝑡𝑡𝑜𝑚2 and 𝑂𝑢𝑡 _ 𝑐𝑎𝑙𝑖𝑏 . V 𝑑 and V 𝑟𝑒𝑓 - V 𝑑 , which are set to choose a coarse (stage 1) voltage range, which in turn is used to pick finer (stage 2 and stage 3) ranges in the next proceeding stacks. Here, V 𝑑 is the differential voltage and V 𝑟𝑒𝑓 is the reference voltage. In the first stage, it is possible to obtain a (2× V 𝑑 16 ) coarse voltage step, whereas in the second stage a (2× V 𝑑 16×16 ) fine voltage step is obtained and in the third stage it is possible to get a (2× V 𝑑 16×16×16 ) finer voltage step. MOSFET-sizing of switches and biasing parameters of the calibration scheme is shown in Table 3.2. The PMOS switches are controlled by three 4:16 decoders whose control bits are loaded from a 12-bit shift register. The decoders are designed with less number of gates. The analog buffers 96 Figure 3-14: (a) Monte Carlo variation of DC offset voltage due to temperature with calibration at 27 ∘ C, (b) Sigma of DC offset voltage due to temperature variation with calibration at 27 ∘ C. between the different stages in the calibration circuit are not used since they can introduce additional offset voltages. For calibration, one has to properly select the switches using decoders and set the bias for coarse, fine and finer offset calibration at one of the bulk-terminals (in Fig. 3-10 it is ‘ 𝑂𝑢𝑡 _ 𝑐𝑎𝑙𝑖𝑏 ’) of the differential pair MOSFETs, while a reference voltage is set at the other bulk-terminal, ‘ 𝐶𝑎𝑙𝑖𝑏𝑟𝑒𝑓 ’. Fig.3-11(a) shows the layout view of the three-stage calibration scheme with its decoders and Fig.3-11(b) shows the layout view of the calibration scheme with parasitics content, with which a post-layout simulation is also performed to observe the effect 97 Figure 3-15: Comparison of nominal and layout-extracted simulated output, 𝑂𝑢𝑡 _ 𝑐𝑎𝑙𝑖𝑏 of the calibration scheme. of parasitics in the layout, which can be critical during the finer (stage 3) calibration. Simulations considering variations due to mismatch, technology process corners, temperature, and parasitics present in the layout are done during design. Fig. 3- 12 shows the technology-process corner variation results of the calibration scheme of wordline, w 1 , and Fig. 3-13 shows the Monte Carlo variation (12 runs) results of the calibration scheme of wordline, w 1 when its full control words are swept using an ideal ADC. The slight upward jumps in the output voltage of the calibration scheme are due to the interleaved approach of the calibration scheme. Fig. 3-14(a) 98 Figure 3-16: (a) Simulation results during coarse (stage 1) calibration of DC offset voltage across wordline, 𝑤1 targeting the zero-crossing region, (b) Simulation results during fine (stage 2) calibration of DC offset voltage across wordline, 𝑤1 targeting the zero-crossing region, (c)Simulation results during finer (stage 3) calibration of DC offset voltage across wordline, 𝑤1 targeting the zero-crossing region. shows the Monte Carlo (500 runs) variation of DC offset voltage due to different temperatures 11 when DC offset is calibrated and compensated at 27 ∘ C. Fig. 3-14(b) shows the sigma variation of the DC offset voltage due to different temperature when DC offset is calibrated and compensated at 27 ∘ C. Fig. 3-15(a) shows the comparison of the layout-extracted simulation results with the nominal simulation results of the calibration scheme of wordline, w 1 when its full control words are swept using an ideal ADC. A very small voltage difference of about 2 µ V is observed by this comparison, which is due to the presence of real parasitic capacitors and resistors in the extracted layout. Fig. 3-16 shows the simulation results during coarse (stage 1), fine (stage 2), 11 A separate statistical temperature variation result is obtained along with device mismatch. Here 27 ∘ C is the nominal simulation temperature. 99 and finer (stage 3) calibration of DC offset voltage across wordline, 𝑤1 of the crossbar targeting the zero-crossing regions. 3.3.4 Design of 4 × 4 1T1R crossbar A 4 × 4 1T1R crossbar is designed using MAD200 PDK, whose schematic and layout views are shown in Fig. 3-17. The crossbar’s wordlines are connected to the output of the buffer configured opamps that facilitate the calibration of DC offset across the wordlines. The basic operations of the 1T1R devices in a crossbar are simulated and analyzed before designing the crossbar, whose details are explained previously in Section 2.3.1 of Chapter 2. The working principle is to target a synapse using decoders and perform basic OxRAM operations. Initially, each OxRAM device is at very high resistance state of 100 G Ω , called PRS, and hence it has to be electro-formed to make the conductive filament in the oxide layer for the first time [122]. After forming, the OxRAM typically reaches LRS, and hence a RESET (or erase) operation has to be Figure 3-17: (a) Schematic view of the 4 × 4 1T1R crossbar, (b) Layout view of the 4 × 4 1T1R crossbar. 100 carried out to push it to HRS. Now, a SET (or write) operation has to be carried out to push the OxRAM back to LRS. Like this, the OxRAM device can be operated in binary mode, i.e. switching between LRS and HRS. The NMOS transistor connected in series with the memristive device acts as a current limiter for initial high forming current. 3.3.5 Design of I-pots I-pots are digitally programmable current sources which, from a reference current, can provide any desired current with high precision, down to pA [121]. I-pot circuits are used as current bias source circuits for the opamp. The schematic view of the I-pot is shown in Fig. 3-18. It has a decade current splitter, a fine current splitter, and a current sign selector and tester. The current splitter circuits are MOS ladder structures [123]. The decade current splitter has 6 current splitting possibilities, where the reference current, Iref is split by 10 in each stage of a MOS ladder structure. The fine current splitter has 28 combinations, where the output of decade current splitter is split by 2 in each combination using the MOS ladder structure. The control bits Figure 3-18: Schematic view of the I-pot. 101 Table 3.4: Values of the control signals for setting output current of I-pot to 40 µ A. Control signals Value sel<0> ON sel<1> OFF sel<2> OFF sel<3> OFF sel<4> OFF sel<5> OFF sel<6> ON sel<7> OFF sel<8> ON sel<9> ON sel<10> OFF sel<11> ON sel<12> OFF sel<13> OFF for these current splitters are loaded from a 14-bit shift register. The signal- ‘sign’ is used to switch the sign of the current-after splitting, and the signal- ‘test’ is used to test the current before it is used to bias the opamp. Figure 3-19: Simulated output currents of I-pot for 6 possible control bits of decade current splitter for the reference current, i 𝑟𝑒𝑓 = 100 µ A. 102 Ibias 1,2,3,4 are the bias currents of the opamps in all the four wordlines of 4 × 4 1T1R crossbar. Fig. 3-19 shows the output current of an I-pot for the 6 possible control bits of the decade current splitter for the reference current, Iref = 100 µ A when the input voltage of an ideal ADC– connected to the digital controls of the decade and fine current splitters is swept for the full range of control word. Table 3.4 shows the values of the control signals for setting the output current of I-pot to 40 µ A. Here, ‘ON’ represents 4.8 V (vdd) and ‘OFF’ represents 0V. 3.3.6 Design of D-flip flop based shift-register The calibration schemes and I-pots for all four pre-synaptic drivers of the 4 × 4 1T1R crossbar needs 104-bit control lines to control them digitally. Controlling all 104-bit digital lines can easily increase the number of pads, which eventually can increase the number of driver boards or can add complexities in making the test-bench. To overcome this, a shift register is used to load the control bits for the I-pot circuits and the calibration circuit. In each wordline of the 4 × 4 crossbar, the I-pot needs a 14-bit data control word and the calibration scheme needs a 12-bit data control word. So, a 104-bit latched D-flip-flop-based shift register is used to load all the control Figure 3-20: Scheme of n-bit D-flip flop based shift register. 103 Figure 3-21: (a) Schematic view of edge-triggered D-flip flop, (b) Schematic view of the latch. bits for the I-pots and calibration circuits for all the four wordlines in the crossbar. Fig. 3-20 shows the scheme of D-flip flop based shift register and Fig. 3-21 shows the schematic view of edge-triggered D-flip flop and latch. A 2-phase non-overlapping clock generator is used to prevent overlapping of clock signals. Fig. 3-22 shows the transistor-level electrical simulation (done in spectre) results Figure 3-22: Simulation results of a 3-bit shift register. 104 Figure 3-23: Layout view of I-pot with 14-bit shift-register. of a 3-bit D-flip flop based shift register when loading all possible control-bits in a repeating sequence. After 𝑑𝑎𝑡𝑎𝑖𝑛 is loaded, 𝑐𝑙𝑜𝑐𝑘 is stopped and the 𝑙𝑎𝑡𝑐ℎ signal is turned ON. This will hold the 𝑑𝑎𝑡𝑎𝑖𝑛 value, which will be passed as digital inputs of the calibration scheme and I-pots. Since complementary control-bits are needed for some digital inputs of I-pots, complementary outputs are also taken from the shift-registers. Figure 3-24: Layout view of calibration scheme with its decoders and 12-bit shiftregister. Fig. 3-23 shows the layout view of I-pot and the 14-bit shift-register, which is used to load its control-bits. Fig. 3-24 shows the layout view of the three-stage calibration scheme with its decoders and the 12-bit shift-register, which is used to 105 shown in Table 3.5. Here, ‘ON’ indicates 4.8 V (vdd) and ‘OFF’ indicates 0V. Spartan r -6 FPGA board is used to program and digitally control the PCB (that has the test-circuits) and the ASIC part. For wordlines, the three-bit control is established by programming the digital lines of the pulse-shaping digital block through FPGA. Different supply voltages such as 10 V, 3.3 V and 4.8 V for the test-circuits are ensured by the LVR and level-shifters are used for bi-directional voltage level conversion between 4.8 V and 3.3 V, which is needed when using FPGA driver for controlling the overall testing of the chip. A read circuitry is made at each bitline, whose scheme is shown in Fig. 3-29. It mainly comprises switches, decoders, and opamps. Opampa (or Read opamp) and control lines- B 1,2 are used to properly set the value of the feedback component during OxRAM operationssuch as ‘form’, ‘erase’, ‘write’, ‘read’. The objective is to keep the needed bias of the inverting terminal of opampa or bitline, b 1 for various OxRAM operations, as shown in Table 2.2 of Section 2.3.4 in Chapter 2. During a ‘read’ operation, opampa can also be used as an integrator, whose output is compared with V 𝑟𝑒𝑓 by a comparator (using opampb). Here R 𝑟𝑒𝑎𝑑 = 26.71 k Ω and C 𝑖𝑛𝑡𝑒𝑔 = 1 µ F. Here S 1 is chosen by a bitline decoder (not shown in Fig. 3-29). When bitline, b 1 is chosen as active bitline, signal S 1 is kept ‘ON’. This connects the bitline, b 1 to ‘active column bias’. Alternatively, when bitline, b 1 is chosen as default bitline, signal S 1 is kept ‘OFF’. This connects the bitline, b 1 to ‘default column bias’. Both ‘active column bias’ and ‘default column bias’ for different OxRAM operations are established through switches and decoders in such a way that anyone of the bitlines will be kept as active thereby, leaving the rest to default at an instant. The control lines- F(A, B, C) and B 1,2 together facilitate choosing the desired OxRAM operation and keeping appropriate biases across the bitlines. 112 3.4.3 Assembly and mounting of test-PCB and auxiliary boards A test-PCB is made according to the test-circuits described in the detailed Fig. A-6 (of Appendix A). A four layered-PCB is designed using OrCAD r CIS 13 and Allegro r 14 , whose design details are described in appendix A.2. A three-stage bulkbased calibration scheme is part of the circuits in the outer-ring. The components used for the PCB are chosen carefully by going through their data-sheets. Parameters such as, operating voltage range, bandwidth, switching characteristics, etc. are considered for choosing the components and for those components which have PSpice 15 model— are simulated to visualize their characteristics. The main purpose of the PCB is to assure desired analog biases at specific terminals of the chip, which are controlled by switches and digital circuits. Once the PCBs are designed the resulting gerber files are sent to a PCB manufacturing company and the components in the BOM list are ordered. The PCB components are soldered to the PCB and the PCB is mounted using corner screws. The assembled and mounted PCB is shown in Fig. A-10 (of appendix A). Some guidelines for a better PCB assembly and mounting practice are narrated in appendix A.3. Along with the PCBs, few auxiliary boards are made to avail of some buttons (to facilitate programming of driver) and to ease probing of terminals of the crossbar. A button-board is made and added to the experimental set-up, which has header-pins with jumpers, exclusive buttons, and level-shifting ICs. The header-pins with jumpers are used to target a synapse in a crossbar and to provide input bits to the calibration scheme. The buttons are programmed to do OxRAM operations like ‘form’, ‘erase’, ‘write’, ‘read’ or keep ‘idle’ or ‘global’ in a particular sequence. The level-shifters on button-board are used to convert the output of the comparator from 4.8 V to 3.3 V 13 OrCAD r Capture is one of the most widely used schematic design solutions for the creation and documentation of electrical circuits. Coupled with the optional OrCAD CIS product for component data management, the designer can use components in the schematic that can be used later in Allegro r PCB designer suite to design PCBs. 14 Allegro r PCB Designer of Cadence r is a scalable, proven PCB design environment that addresses technological and methodological challenges thereby, making the design cycles shorter and predictable. 15 PSpice models of more than 33k components can be simulated in Cadence r before making PCB layouts to observe their working characteristics at circuits-level. 113 for being used in FSM during programming. Figure 3-30: Comparison of ON/OFF pulses of different widths: (a) 5 ns ON/OFF pulse, (b) 10 ns ON/OFF pulse, (c) 15 ns ON/OFF pulse, (d) 20 ns ON/OFF pulse, (e) 25 ns ON/OFF pulse, (f) 30 ns ON/OFF pulse. 114 3.4.4 FPGA SPARTAN r -6 driver board We need a driver to program the test-PCB to test the chip which rests on the ZIF socket of the PCB. Drivers such as microcontroller- STMF4DISCOVERY kit [124], FPGA SPARTAN r -3 [125], and FPGA SPARTAN r -6 [126] are considered as possible programming platforms for controlling the test-board digitally. It is observed that a full digital strength of 3.3 V can be reached at about 10 ns fast pulse using Spartan r -6 FPGA. Fig. 3-30 shows a comparison of ON/OFF pulses of different widths (5 ns, 10 ns, 15 ns, 20 ns, 25 ns, and 30 ns) programmed using Spartan r -6 FPGA. Here, in Fig. 3-30 (a) the purple-colored trace does not working correctly for the ’OFF’ pulse, as it did not reach the magnitude equivalent to the ’ON’ pulse of the cyan-colored trace. In our experiments Spartan r -6 FPGA driver (also called as ‘Node Board’ 16 [127]) is chosen to program the test-PCB, due to its configurable speed (programming fast pulses), availability of more number of programmable pins and features like QUIETIO mode (slew rate option), which keeps low peak over-shoot and less ringing. The filter in the oscilloscope probes is also tuned to have smoothly settled voltage pulses with no or minimal overshoot or ringing. 3.5 Description and working of the experimental setup of the calibration scheme Fig. 3-31 shows the experimental setup of the DC offset calibration scheme. It mainly comprises the test-PCB that includes the chip under test, a SPARTAN r -6 driver board, a button-board, a resistor plug-and-play board, a mixed-signal oscilloscope, and its digital pod. The test-PCB is controlled through the SPARTAN r -6 driver board. The button-board has dedicated buttons to perform OxRAM operations in a sequencelike ‘Form_Global_Read’, ‘Erase_Global_Read’, ‘Write_Global_Read’, ‘Read’ and to calibrate DC offset during ‘Read’. These tasks or operations are highlighted in Fig. 3-31 for the corresponding buttons on the button-board. The button- 16 The node board contains a XC6SLX150T Spartan r -6 FPGA and four SATA connectors that renders 76 programmable pins. 115 board and SPARTAN r -6 driver board are used together for two main purposes: (i) Target a synaptic 1T1R device in the crossbar and perform operations like ‘form’, ‘erase’, ‘write’ and ‘read’ through a 3-bit control signal, F(A, B, C) and (ii) Set the 12-bit control word for calibration scheme and perform calibration of DC offset during a ‘read’ operation. The resistor plug-and-play board is used to facilitate easy probing of the crossbar terminals and to test with resistor-banks before testing the chip. The SPARTAN r -6 driver board is powered by a 5 V supply line with the short ground to keep the influence of noise low. Calibration can be done once in the beginning irrespective of the OxRAM operation. As we intend to investigate how small ‘Read’ pulses can be used and how we can calibrate DC offset during such tiny ‘read’ pulses, we are doing DC offset calibration during a ‘Read’ operation. An FSM is programmed in FPGA using VHDL language to define functions of each button on the button-board. Different states are made in FSM as shown in Fig. 3-32 in such a way that push-buttons on the button-board are programmed to establish different OxRAM operations in a sequence on the targeted 1T1R device. One of the push-buttons is programmed to do ‘Form_Global_Read’ task, while another button is programmed to do ‘Erase_Global_Read’ task. Other buttons are exclusively Figure 3-31: Experimental set-up of the DC offset calibration scheme. 116 Figure 3-32: FSM used to calibrate DC offset voltage and perform OxRAM operations. programmed to do ‘Write_Global_Read’, a separate ‘Read’ operation and to perform offset calibration during ‘Read’ operation. Before calibrating offset, the control-bits for calibration scheme are set as desired by using jumpers on the auxiliary boards. The push-buttons inherently have bouncing effects [107] for a short time when immediately pressed and released and these can easily cause short unwanted transients to the crossbar terminals, which can be harmful to OxRAMs and hence they must be eliminated. To overcome this, a software-based debouncing technique is used, which is waiting for some time until bouncing finishes and settles to start the next state. 3.6 System-level simulation results for pattern recognition Before starting with the experimental application on an offset calibrated 4 × 4 crossbar for pattern recognition, it is important to verify the results by simulation. Two system-level simulations are carried out on the crossbar for pattern recognition. The 117 Figure 3-33: Patterns used for recognition-task using 4 × 4 crossbar: (a) Pattern-1, (b) Pattern-2, (c) Pattern-3, (d) Pattern-4. first method is by using Supervised Single-Shot Programming (SSSP) for template matching. Here, there isn’t any learning of features, rather a weight-update is done to all synapses for specific post-synaptic spikes to fire earlier. The second method is by using STDP learning, where the weights are changed based on the STDP learning rule. STDP is a learning mechanism by which, change in synaptic weight is a function of the time difference between the pre-synaptic spike and post-synaptic spike [78,79]. The patterns (Pattern-1, Pattern-2, Pattern-3, and Pattern-4) considered are shown in Fig. 3-33 and a model-based design using Simulink of MATLAB r is used to verify the results. Fig. 3-34 shows the behavioral system-level simulation for pattern recognition implemented on a 4 × 4 crossbar. The main blocks are the pattern generator, crossbar, integrators & comparator block, scopes or displays, and STDP processor. The pattern generator is used to feed the pixels of the patterns in the form of ‘read’ pulsestpre{a, b, c, d}. The read pulses or the pre-synaptic pulses are fed into the system (across wordlines, w 1,2,3,4 of the crossbar) in the sequence as they appear in Fig. 3-33. The read pulses have an amplitude of 0.3 V and a pulse width of 50 ms. The total time of each pixel is 200 ms. Since there are 4 pixels in each pattern, 800 ms is used to feed all the pixels of the patterns. The crossbar comprises wordlines, w 1,2,3,4 and bitlines, b 1,2,3,4 interconnected by synapses, W{1, 2,...16}. 118 Figure 3-34: Model based simulation environment implemented in Simulink environment. 119 Figure 3-35: Scheme of integrator and comparator implemented in Simulink environment. The synapses have binary weights and they can be either in LRS or HRS. Fig. 3-35 shows the integrator & comparator block, which mainly comprises an integrating opamp, integrating capacitor (of capacitance 2 µ F) across a reset switch, an opamp used as a comparator, voltage sensors, and converters to convert physical signal to a simulink signal and vice versa. The accumulated currents across bitlines are integrated, whose output voltage is compared with a reference voltage to generate the post-synaptic pulsestpost{a, b, c, d}. A reset signal is applied at the end of each pixel to reset the integrator so that it starts integrating current for the next pixel. 3.6.1 Using Supervised Single-Shot Programming (SSSP) The Supervised Single-Shot Programming (SSSP) for template matching is based on both - (i) updating weights by determining the time of occurrence of pre-synaptic and post-synaptic pulses and (ii) doing opposite weight update for the rest of the synapses that don’t contribute to the targeted post-synaptic spike. The times of occurrence of tpost{a,b,c,d} and tpre{a,b,c,d} pulses are stored in memory for each pixel throughout the simulation. Hence, we will have 4 values of times of occurrence for each 120 Figure 3-36: Pre-synaptic pulses, reset, cycle and batch signals. post-synaptic pulse when the whole pattern is fed into the system. The internally stored time of occurrence of tpost{a,b,c,d} is compared with the time of occurrence of Figure 3-37: Integrator output voltage, reset, tposta and simulation time signals. 121 3.7 Experimental results of memristive processor facilitated with bulk-based calibration scheme across wordlines Results of three-stage bulk-based calibration scheme implemented on a 4 × 4 1T1R memristive crossbar comprise different tests’ results conducted on the experimental setup, shown in Fig. 3-31. It includes results from preliminary tests, calibration scheme results, results of characterization of OxRAMs, pattern recognition results using SSSP on the calibrated crossbar, and pattern recognition results using STDP learning rule on the calibrated crossbar. During preliminary tests of validating the working of I-pots and shift-register, care is taken that– biases of the power supply opamps do not disturb the OxRAMs in the crossbar. This is done by setting the voltage difference between the top and bottom terminals of 1T1R devices and its gate-biases to 0 V. 3.7.1 Preliminary test results The preliminary test-procedure is to validate the functionality of test-PCB and the working of on-chip I-pots and shift-register. The main objective of testing the PCB is to ensure the smooth functioning of all PCB components and to verify the amplitude and pulse-width of the pulses that are applied on the crossbar terminals (by keeping a substitute resistor-bank) consider the different OxRAM operations. The test-PCB is tested by using carbon resistors plugged on resistor plug-&-play board and by applying pulses based on sequential OxRAM operations such as- ‘FORM_GLOBAL_READ’ or ‘ERASE_GLOBAL_READ’ or ‘WRITE_GLOBAL_READ’ or ‘READ’. The power supply opamps are biased with the optimal values for keeping active and default values during various OxRAM operations. Waveforms of the applied pulses are observed by probing the crossbar terminals (-wordlines, gates, and bitlines), which are checked for the desired ones, as shown in Fig. 2-17, Fig. 2-18, Fig. 2-19, and Fig. 2-20 of chapter 2. In this way, the test-PCB is tested for the needed functionality. 128 Figure 3-44: Preview of output screen when testing shift-register. For testing I-pot, the input reference currents for the I-pots, Iref{1, 2, 3, 4} are set to 100 µ A using potentiometers, and the digital signals test{1, 2, 3, 4} are kept ‘ON’. The control-bits for I-pot (as shown in Table 3.4) are programmed together with a clock signal of 2 kHz frequency using SPARTAN r -6 driver board and are loaded to the shift-register. After data 𝑖𝑛 is loaded, the clock is stopped and the latch signal is turned ‘ON’ to observe the output currents, Itest{1, 2, 3, 4} across the load resistors. A current of about 40 µ A (as required for the nominal bias of two-stage differential opamp) is observed across the load resistor, which validates the working of the I-pots. For testing shift-register, the 104-bit control word including the control-bits for calibration is programmed using the SPARTAN r -6 driver board and is loaded to the shift-register. A clock signal of 2 kHz frequency is used and the calibration controlbits are set such that the bulks- Out_Calib{1, 2, 3, 4} and Calibref{1, 2, 3, 4} are both set at 4.8 V, as calibration is not included in the test. Once the data sequence is loaded, without turning ‘OFF’ the clock signal, data 𝑜𝑢𝑡 or data_out_buf signal is observed. Fig. 3-44 shows the observed results of the shift-register, where the data sequence of control-word of data 𝑜𝑢𝑡 of the last D flip-flop is similar to the input data sequence of data 𝑖𝑛 . This validates the working of shift-register. 129 3.7.2 Three-stage bulk-based calibration scheme results of full input control-word After testing shift-register and I-pot, calibration bits are carefully set using the button-board such that a coarse (stage 1) calibration is first carried out. Before calibration, the OxRAMs are carefully formed in a three-step process. The first step is to load shift-register with 104-bit data 𝑖𝑛 , clock (of 2 kHz frequency) signal, latch and other control signals (like digital inputs of pre-synaptic drivers, 3-bit control signal F(A, B, C), etc.) by programming through SPARTAN r -6 driver board in such a way that– when the ‘FORM_GLOBAL_READ’ button is pressed, the resistance of the formed OxRAM is obtained by probing the terminals of opampa (read opamp as shown in Fig. 3-29). The second step is to use the button-board to configure both the Figure 3-45: Preview of output screen when calibrating DC offset across wordline, 𝑤1 . 130 Figure 3-46: Comparison of experimental and simulation results during stage 1 calibration of DC offset voltage across wordline, 𝑤1 . input control-bits for calibration and the input bits for targeting the 1T1R synapse in the crossbar. The final step is to obtain post-forming resistance after pressing the ‘FORM_GLOBAL_READ’ button. Once all OxRAMs are formed, calibration of DC offset is done in a ‘Read’ operation by a three-step process. The first step is to load shift-register with 104-bit data 𝑖𝑛 , clock (of 2 kHz frequency) signal, latch and other control signals by programming through SPARTAN r -6 driver board in such a way thatwhen the ‘Calibrate DC offset’ button is pressed on the button-board, the clock runs as long as the 104-bit data sequence is loaded, which is followed by stopping the clock and turning ‘ON’ the latch . The second step is to set the calibration input control-bits on the button-board. The third step is to observed DC offset voltage by pressing the ‘Calibrate DC offset’ button. Fig. 3-45 shows a preview of the output screen when wordline 𝑤1 is calibrated during a ‘Read’ operation of 𝑉𝑟𝑒𝑎𝑑 = 0.33 V. Here 𝑣𝑎1 is the input voltage of opamp1 (as shown in Fig. 3-3) and opamp1’s output leads to wordline, w 1 of the crossbar. The ‘Data loading time’ comprises the time for loading data 𝑖𝑛 and clock . Once the datasequence is loaded, the latch is turned ‘ON’ and the DC offset voltage is calibrated. 131 Figure 3-47: Comparison of experimental and simulation results during stage 2 calibration of DC offset voltage across wordline, 𝑤1 targeting the zero-crossing region. Figure 3-48: Comparison of experimental and simulation results during stage 3 calibration of DC offset voltage across wordline, 𝑤1 targeting the zero-crossing region. Here, DC offset voltage is the difference between the input and output of the opamp connected in buffer configuration across the wordline, w 1 . The results are taken by averaging 100 million samples to filter out noise, whose standard-deviation is about 200 µ V. The power dissipation during inference ‘READ’ operation is about 132 0.8 µ W for a 4 × 4 crossbar when using a 50 mV read pulse whose DC offset voltage is finely calibrated. Fig. 3-46 shows the comparison of experimental and simulation results when wordline, 𝑤1 of the crossbar is calibrated for DC offset voltage during coarse (stage 1) calibration for 𝑉𝑅𝑒𝑎𝑑 = 0.33 V. The zero-crossing region in Fig. 3-46 is targeted and DC offset voltages are calibrated during fine (stage 2) and finer (stage 3) calibration, whose results are shown in Fig. 3-47 and Fig. 3-48. Experimental results of the three-stage calibration scheme match simulation results. 3.7.3 Characterization results of OxRAMs in 4 × 4 1T1R crossbar with on-chip DC offset calibration across wordlines In this section, several characterization results of the OxRAMs of 4 × 4 1T1R crossbar where calibration of DC offset is implemented are discussed. Unlike the characterization of individual crossbars (as discussed in Section 2.3.5), characterizing OxRAMs in the crossbar that is equipped with a calibration scheme is not straight-forward. Figure 3-49: Active row, column and gate biases applied in the form of pulsesshowing a read operation after an erase operation. 133 It is due to the presence of pre-synaptic drivers across the wordlines, whose controlbit for calibration and i-pots are loaded from the shift-register. Therefore, there is always a ‘data-loading’ part, where the clock is ‘ON’ and data 𝑖𝑛 is loaded. Following this, the clock is stopped, the latch is turned ‘ON’and the sequential OxRAM operation such as- ‘FORM_GLOBAL_READ’ or ‘ERASE_GLOBAL_READ’ or ‘WRITE_GLOBAL_READ’ or ‘READ’- is carried out. Utmost care is taken to the OxRAMs such that none of them are disturbed during the ‘data-loading’ part. Also for the ‘ERASE’, ‘WRITE’, and ‘READ’ part of the pulses the active gate is switched ‘ON’ after a short delay to avoid transients, which could be harmful to the OxRAMs. Like other tests, here also the active and default wordlines, bitlines, and gates are chosen using jumper pins on the button-board to pick a 1T1R device. Figure 3-50: Active row, column and gate biases applied in the form of pulsesshowing a read operation after a write operation. Once a device is targeted the desired sequential operation is carried out on it. All OxRAMs are carefully formed and are switched between LRS and HRS. Fig. 3- 49 shows the biases of the row (or wordline), column (or bitline), gate bias, output of inference opamp, and digital signals when ‘ERASE_GLOBAL_READ’ operation 134 is carried out. Fig. 3-50 shows the biases of the row, column, gate bias, output of inference opamp, and digital signals when ‘WRITE_GLOBAL_READ’ operation is carried out. Here, during ‘Ideal default’ and ‘Active default’ both top and bottom terminals of the targeted 1T1R device are biased at 0 V and the gate is turned ‘OFF’. Initially, the ‘data-loading’ part is programmed for 52.5 ms. This follows ‘Ideal default’, ‘Erase’, ‘Ideal active’, ‘read’, and ‘Ideal active’. During ‘read’, first, the row and column biases are switches and after 15 ms time, the gate for is turned ‘ON’. The values of the control signals- A, B, and C for different OxRAM operations are digitally set based on Table 3.5. The LRS and HRS resistance values of the OxRAM are calculated from Fig. 3-49 and Fig. 3-50, where we have the values of the ‘Active row’, ‘Active column’, ‘Active gate’, and ‘Output voltage of the inference opamp’. A feedback resistor of resistance value 26.71k Ω is used at the inference opamp. The ‘Read’ voltage is 2.4 - 2.27 = 0.13 V. The output of the inference opamp goes to 2.261 V during a ‘Read’ after ‘Erase’ when the active gate is turned ‘ON’. Similarly, the Figure 3-51: LRS and HRS values of OxRAMs of all 16 1T1R devices in the 4 × 4 crossbar where calibration of DC offset voltage is carried out. 135 Figure 3-52: LRS and HRS values for 10 switching cycles of an OxRAM of the 4 × 4 1T1R crossbar where calibration of DC offset voltage is carried out. output of the inference opamp goes to 0.453 V during a ‘Read’ after ‘Write’ when the active gate is turned ‘ON’. The LRS and HRS values are calculated as follows- LRS = ( 26.71 k Ω 2.27 V −0.453 V )×0.13 V = 1.91 k Ω (3.13) HRS = ( 26.71 k Ω 2.27 V −2.261 V )×0.13 V = 385.81 k Ω (3.14) Fig. 3-51 shows the LRS and HRS values of OxRAMs of all 1T1R devices in the 4 × 4 crossbar where calibration of DC offset voltage is implemented. Fig. 3-52 shows the LRS and HRS values for 10 switching cycles of an OxRAM of the 4 × 4 1T1R crossbar where calibration of DC offset voltage is implemented. Fig. 3-53 shows the LRS and HRS values for 400 switching cycles of an OxRAM of the 4 × 4 1T1R crossbar where calibration of DC offset voltage is implemented. This plot shows high variability in the distribution of HRS. 136 Figure 3-53: Switching of resistance of OxRAM of a 1T1R device between HRS and LRS for 400 cycles. 3.7.4 Template-matching results implemented on a calibrated 4 × 4 1T1R crossbar This section discusses various template-matching results done using a 4 × 4 1T1R crossbar where calibration scheme is implemented across wordlines. The patterns for which template-matching is done is shown in Fig. 3-33. Fig. 3-54 shows the conceptual block diagram showing how patterns are fed as ‘read’ pulses across the rows of the calibrated crossbar, whose synapses are switched to learned weights. Initially, the OxRAMs in 4 × 4 1T1R crossbar are formed one-by-one and are set to learned weights as shown in the crossbar of Fig. 3-54. Following this, an inference is carried out across bitlines by carefully reading the OxRAMs using tiny read pulses. For a specific pattern when the contributing weights are strengthened (or when resistance is low), the pulse-width of the inverted version of the output of the comparator becomes minimum. Hence, achieving minimum pulse-width during inference using a pattern is an indication of achieving learned weights for that pattern. 137 Figure 3-62: Bitlines (or columns) and digital signals for template-matching using read voltage of 30 mV. as desired for template matching are 84 mV, 54 mV, and 14 mV respectively. Fig. 3-57 shows the output of integrators and digital signals for the templatematching experiment performed on the calibrated crossbar by using ‘read’ pulses of amplitude 100 mV. Fig. 3-58 shows the output of integrators and digital signals for the template-matching experiment performed on the calibrated crossbar by using ‘read’ pulses of amplitude 70 mV. And Fig. 3-59 shows the output of integrators and digital signals for the template-matching experiment performed on the calibrated crossbar by using ‘read’ pulses of amplitude 30 mV. Fig. 3-59 also shows how the system is capable to result in the desired output during inference even when read with tiny read pulses that have amplitude as low as 30 mV. Fig. 3-61 shows the wordlines (or rows) and digital signals for the template-matching experiment performed on the calibrated crossbar by using ‘read pulses’ of amplitude 30 mV. The read voltage of 30 mV is carefully set such that none of the signal’s data-point after noise filtration touches 144 Figure 3-63: Gate biases and digital signals for template-matching using read voltage of 30 mV. or exceeds the high level of the read pulse (2.4 V). Fig. 3-62 shows the bitlines (or columns) and digital signals for the template-matching experiment performed on the calibrated crossbar by using ‘read’ pulses of amplitude 30 mV. Fig. 3-63 shows the gate signals (or gcol{1,2,3,4}) and digital signals for the template-matching experiment performed on the calibrated crossbar by using ‘read’ pulses of amplitude 30 mV. A bias of 4.6 V is applied to the gate of the 1T1R devices to read the current of the OxRAMs and it is applied for 15 ms after switching the wordlines and bitlines to avoid transients from harming the OxRAMs. 3.7.5 Pattern recognition results using SSSP on calibrated crossbar In this section, the experimental results of Supervised Single Shot Programming (SSSP) for pattern1 on calibrated crossbar are discussed. With reference to the model- 145 based system-level simulation carried out for pattern recognition in Section 3.6.1, each pattern is targeted for a particular post-synaptic pulse to spike earlier. The synapses that contribute weight for a particular pattern to spike earlier are programmed to face a weight update, while the rest of the synapses that don’t contribute face an opposite weight update. Similarly, other post-synaptic pulses are programmed to spike earlier for other specific patterns by their corresponding weight updates. Here, we target ‘col1’ to spike earlier for ‘pattern-1’, ‘col2’ to spike earlier for ‘pattern-2’, ‘col3’ to spike earlier for ‘pattern-3’, and ‘col4’ to spike earlier for ‘pattern-4’. The flowchart Figure 3-64: Flowchart for implementation of SSSP on calibrated crossbar by targeting- ‘col1’ to spike earlier for ‘pattern-1’, ‘col2’ to spike earlier for ‘pattern- 2’, ‘col3’ to spike earlier for ‘pattern-3’ and ‘col4’ to spike earlier for ‘pattern-4’. 146 Figure 3-65: Inference results by programming with the single shot variant of STDP targeting pattern1. for implementing the SSSP on calibrated crossbar is shown in fig. 3-64. The FPGA driver board is programmed such that the user can initially calibrate DC offset and then choose the pattern for programming. Dedicated push-buttons are used to do calibration and weight update. When a particular pattern is chosen and the weight update is carried out, the inference outputs of both before and after weight update is visualized to see if the targeted post-synaptic pulse is programmed to spike earlier for the specific pattern or not. If not the push-button is pressed again to visualize the results. Fig. 3-65 shows the inference results by programming a single shot variant of STDP targeting pattern1. Here the push-button is pressed for the 3 rd time and observed thatbitline1 (or column1) spiked earlier for pattern1, which 147 results in a shorter pulse-width of the comparator’s output. It also appears that the bitline1 spiked earlier for pattern1 when the push-button is pressed for the 1 st or 2 nd time. Similarly, other patterns can be chosen for targeted post-synaptic pulses to spike earlier by programming the devices. 3.7.6 Pattern recognition results using STDP learning rule on calibrated crossbar In this section, experimental results of pattern recognition using ‘STDP learning rule’ implemented on calibrated crossbar are discussed. With reference to the model-based system-level simulation carried out for pattern recognition in Section 3.6.2, weight updates are done based on the time of occurrence of pre-synaptic and post-synaptic pulses. When the post-synaptic pulse spike after the pre-synaptic pulse, the weight of the corresponding synapse is strengthened by decreasing the resistance. Alternately, when the pre-synaptic pulse spike after the post-synaptic pulse or when there is no pre-synaptic pulse, the weight of the corresponding synapse is weakened by increasing the resistance. A condition (to give priority to minimum index and to those which did not face weight update earlier) is used when two or more post-synaptic pulses spike at the same time. Initially, the weights are kept random or even unknown. Fig. 3-66 shows the flowchart for implementing the STDP learning rule on the calibrated crossbar for pattern recognition. The FPGA driver board is programmed such that the user can initially calibrate DC offset and then go for the pattern recognition task. The objective to keep tiny read inference pulses, calibrate DC offset for it, and use the same tiny read pulses for pattern recognition using the STDP learning ruleis all done. Dedicated push-buttons are used to do tasks such as calibration and weight update with inferences. For a specific pattern when the contributing weights are strengthened (or when resistance is low), the pulse-width of the inverted version of the output of the comparator becomes minimum. Hence, achieving minimum pulse-width during inference using a pattern is an indication of achieving learned weights for that pattern. The STDP weight 148 Figure 3-66: Flowchart for implementation of STDP learning rule on calibrated crossbar for pattern recognition. 149 Figure 3-67: Output of integrators and comparators with other digital signals during 1 st weight-update. update is done on the synapses that contribute minimum pulse-width, whereas the rest of the weights are kept untouched. When two or more pulse-widths are similar and minimum, priority is given to the one that has minimum index number and those contributing synapses which did not face weight update earlier. The index number is the number of the bitline or column. The trained patterns and its index number are both stored in a register, which is used later to learn future patterns in order to check if the synapses faced weight update earlier or not when two or more pulse-widths become minimum and similar. The integrators have feed-back capacitors whose capacitance is 0.64 µ F. Fig. 3-67 shows the output of the integrators and comparators with other digital signals during 1 st weight-update, where ‘col3’ spiked earlier for both ‘pattern- 150 Figure 3-68: Output of integrators and comparators with other digital signals during 2 nd weight-update. 1’ and ‘patterns-4’. Also, ‘col1’ spiked earlier for both ‘pattern-2’ and ‘patterns-3’. Fig. 3-68 shows the output of the integrators and comparators with other digital signals during 2 nd weight-update, where ‘col3’ spiked earlier for both ‘pattern-1’ and ‘patterns-4’. Here, there is some learning and due to this ‘col1’ spiked earlier for ‘pattern-2’ and ‘col4’ spiked earlier for ‘pattern-3’. Fig. 3-69 shows the output of the integrators and comparators with other digital signals during 3 rd weight-update, where the synapses had almost learned weights. Here, ‘col1’ spiked earlier for ‘pattern- 2’, ‘col2’ spiked earlier for ‘pattern-4’, ‘col3’ spiked earlier for ‘pattern-1’, and ‘col4’ spiked earlier for ‘pattern-3’. Until we have different index numbers the weight-update is carried out. 151 Figure 3-69: Output of integrators and comparators with other digital signals during 3 rd weight-update. 152 Chapter 4 MCN Attenuator for Efficient Memristive Crossbar Read-Out 1 4.1 Need for a current attenuator In a typical memristor-based fully connected feed-forward neural network that mainly comprises the pre-synaptic neurons, the memristive crossbar and the post-synaptic neurons [129]. As the LRS current across a crossbar line is high due to the typical low resistance during an inference read operation (after a ‘write’ operation), an extremely large integrating capacitor would be needed (larger than nFs) at the post-synaptic neuron for reasonable integration speed, making IC integration impossible. Hence, a current attenuator is needed to scale down the read current. 4.2 Design of Modified Current Normalizer (MCN attenuator) Several current attenuating strategies exist such as Gilbert’s current normalizer circuit [130], MOS-ladder [131] and the WTA [132] based current attenuator [133]. The proposed current normalizer considers Gilbert’s current normalizer circuit as a refer- 1 This chapter has been published as a paper [128] 153