A New Fast Peak Current Controller for Transient Voltage Faults for Power Converters

Article A New Fast Peak Current Controller for Transient Voltage Faults for Power Converters † Jesús Muñoz-Cruzado-Alba 1,*, Javier Villegas-Núñez 1,‡, José Alberto Vite-Frías 1,‡ and Juan Manuel Carrasco Solís 2,‡ Received: 17 September 2015; Accepted: 27 November 2015; Published: 22 December 2015 Academic Editor: Rodolfo Araneo 1R & D Department, GPTech, Av. Camas N26, Bollullos de la Mitacion 41703, Spain; [email protected] (J.V.-N.); [email protected] (J.A.V.-F.); [email protected] (J.M.C.S.) 2Electronics Engineering Department, Seville University, Av. de los Descubrimientos S/N, Seville 41092, Spain *Correspondence: [email protected]; Tel.: +34-954-181-521; Fax: +34-955-776-734 † The original paper was presented in A New Fast Peak Current Controller for Transient Voltage Faults for Power Converters. In Proceedings of the EEEIC 2015, Rome, Italy, 10–13 June 2015. ‡ These authors contributed equally to this work. Abstract: Power converters are the basic unit for the transient voltage fault ride through capability for most renewable distributed generators (DGs). When a transient fault happens, the grid voltage will drop suddenly and probably will also suffer a phase-jump event as well. State-of-the-art voltage fault control techniques regulate the current injected during the grid fault. However, the beginning of the fault could be too fast for the inner current control loops of the inverter, and transient over-current would be expected. In order to avoid the excessive peak current of the methods presented in the literature, a new fast peak current control (FPCC) technique is proposed. Controlling the peak current magnitude avoids undesirable disconnection of the distributed generator in a fault state and improves the life expectancy of the converter. Experimental and simulation tests with high power converters provide the detailed behaviour of the method with excellent results. Keywords: distributed generators (DGs); voltage ride through (VRT); fast peak current control (FPCC); phase-jump ride through (PJRT); photo-voltaic (PV) systems; dip voltage 1. Introduction Power is typically produced at a wide range of generation plants. Some years ago, for renewable power sources, it was allowed to switch off the source when a voltage fault occurred. Back then, disconnection of that power sources had little, if any, impact on the recovery capability of the electric power grid after a fault. Nowadays, a high penetration of renewable distributed generators (DGs) [1–4] has toughened the grid connection minimum technical requirements (MTRs) worldwide [5–13]. MTRs include voltage sags and phase-jump capability, frequency active power regulation and anti-islanding techniques, among others. The voltage ride through (VRT) capability requirement has been widely described in recent grid codes [5–13]. Tables 1and 2point out some of the most popular MTRs for photo-voltaic (PV) plants about VRT. First, a maximum allowed voltage profile is defined for voltage excursions. If the fault reaches the error profile, the inverter is allowed to disconnect. German legislation [5] usually is taken as the reference for other legislation. A zero-voltage transient fault is required for 0.15 s. Recent legislation imposes a zero-voltage fault, too, like the Puerto Rican or Jordanian legislation [7,13]. However, other Energies 2016,9, 1; doi:10.3390/en9010001 www.mdpi.com/journal/energies Energies 2016,9, 1 2 of 18 legislation is imposing smaller voltage sag magnitude requirements, but longer in time, for example the Chilean and Romanian grid codes [11,12]. Table 1. Minimum technical requirements (MTRs) review for voltage ride through (VRT) capabilities of photo-voltaic (PV) plants (A). German association of energy and water industries: BDEW; Puerto Rico Electric Power Authority: PREPA; National energy regulator of South Africa: NERSA; Spanish electric grid: REE. Country Germany Puerto Rico Standard BDEW PREPA VRT profile VPCC (p.u.) T (s) 1.00 0.90 0.30 0.0 0.15 0.60 1.50 3.00 VPCC (p.u.) T (s) 1.00 0.90 0.00 0.0 0.6 3.0 1.15 1.25 1.30 1.40 0.15 1.0 IqVRT ΔIQ (p.u.) V (p.u.) 1.00 1.11.2 -1.00 0.50.0 0.9 ΔIQ (p.u.) V (p.u.) 1.00 -1.00 V1 0.0 0.85 IdVRT 0 0 Recovery time 5 s 5 s Phase jump N/D N/D Country South Africa Spain Standard NERSA REE VRT profile VPCC (p.u.) T (s) 1.00 0.90 0.00 0.0 0.15 2.0 20.0 0.80 1.10 1.20 VPCC (p.u.) T (s) 1.00 0.80 0.20 0.0 0.5 1.0 15.0 0.95 IqVRT ΔIQ (p.u.) V (p.u.) 1.00 1.1 1.2 -1.00 0.50.0 0.9 IQ (p.u.) V (p.u.) 1.00 0.90 0.00 0.5 0.85 -1.00 IdVRT Previous fault Id0 Recovery time 5 s N/D Phase jump Up to 40◦N/D Energies 2016,9, 1 3 of 18 Table 2. MTRs review for VRT capabilities of PV plants (B). National Commission of Energy: CNE; Electrotechnical Italian Committee: CEI; Electricity Regulatory Commission: ERC; Romanian Electricity Authority: Transelectrica. Country Chile Italy Standard CNE CEI VRT profile VPCC (p.u.) T (s) 1.00 0.80 0.10 0.0 T2+0.02 1.0 VPCC (p.u.) T (s) 1.00 0.85 0.00 0.0 0.2 0.4 0.40 1.10 IqVRT ΔIQ (p.u.) V (p.u.) 1.00 1.11.2 -1.00 0.50.0 0.9 IQ (p.u.) V (p.u.) 1.00 0.00 0.9 -1.00 IdVRT Previous fault Id0 Recovery time N/D N/D Phase jump N/D N/D Country Jordan Romania Standard ERC Transelectrica VRT profile VPCC (p.u.) T (s) 1.00 0.90 0.00 0.0 0.25 1.5 180 0.80 1.10 1.20 60 VPCC (p.u.) T (s) 1.00 0.90 0.00 0.0 0.625 3.0 0.15 1.10 IqVRT ΔIQ (p.u.) V (p.u.) 1.20 -0.4 1.2 -1.00 0.40.0 IQ (p.u.) V (p.u.) 1.00 0.00 0.9 -1.00 IdVRT 0 0 Recovery time 60 s 350 ms Phase jump N/D N/D Then, some requirements are imposed over the power generation during the voltage excursions in order to help the system stability. An injection of reactive current (Iq) is always required. Older grid codes, like the Spanish or Italian legislation [8,9], usually require generating the maximum possible capacitive current. However, most recent grid codes usually require a droop relationship between capacity current and the depth of the voltage sag, in order to provide a softener recovery [6,7,12,13]. Energies 2016,9, 1 4 of 18 There are two choices for the active current (Id) requirement: to follow the previous value to the fault state, for example the South African and Chilean cases [6,12]; or to drop the reference to zero, but consumption is not allowed, like the German and Puerto Rican cases [5,7]. A recovery time after the fault requirements could be needed, as well. It could vary from milliseconds [11] to minutes [13]. Finally, most recent grid codes are also including phase-jump fault requirements, for example the South African grid code [6]. The worst scenarios cover the necessity to remain connected against 40◦phase-jumps and 0.0 p.u. low voltage excursions, for three-phase and mono-phase faults. A sudden occurrence of this type of fault could cause a peak in the converter output current. Therefore, these current peaks cause unit errors and disconnections, being a hazard to the unit safety. Together with the operation mode and the imposed limits, response time is crucial in these kinds of events, whose durations are in the order of milliseconds. At the beginning of the fault, any delay could be critical, because the grid voltage could change very fast. Figure 1shows an uncontrolled peak current due to a severe low voltage excursion in a three-phase power converter. −1.0 0.0 1.0 Vg (p.u.) (a) 1.72 1.73 1.74 1.75 1.76 1.77 −2.0 −1.0 0.0 1.0 2.0 IL (p.u.) Time (s) (b) Figure 1. Peak current fault under a severe low voltage excursion. (a) Transient low voltage profile; (b) stack converter output currents; uncontrolled peak currents marked with green circles. There is much research on power converter controllers during grid fault conditions [14–19], but unfortunately, there is not enough analysis about the uncontrolled beginning of the fault. A new fast peak current control (FPCC) is proposed to help the converter control limiting the over-current peak of the converter at the beginning of the fault. Consequently, hardware and software current protection could be avoided, improving the MTRs compliance. Further, lower peak current reduces insulated gate bipolar transistors (IGBTs)’ degradation and unexpected disconnections from the grid of the power converters, so mean time between failures (MTBF) increases. This manuscript is organized as follows: Section 2 analyzes in detail the proposed method theory; Sections 3 and 4 show the test results; discussions are given in Section 5; Finally, the materials and methods used are pointed out in Section 6. 2. Fast Peak Current Control Method 2.1. Power Converter Control Strategy A two-level three-phase topology has been selected for the study. Industrial high-power grid-tie converters usually use a single-stage inverter topology, with an LC output filter [20,21]. Figure 2shows a classical DG converter control block scheme. The controller is divided into four layers. The highest level controller generates the appropriate references for the middle controller. The middle level controller reacts by modifying the response as a function of the environment agents, which could limit the inverter capability. Typically, special voltage sag control will be placed at this Energies 2016,9, 1 5 of 18 layer. Then, the low level controller includes the inner current control loop that sets the inverter control actions following the references. Finally, the hardware level controller translates the control signals to the physical pulses of the converter. PrefSP QrefSP Pmax Pmin Pref’ Qref Pref Qmin Qmax Id ref Iq ref Current controller Pref sat lim calculation Qref sat lim calculation High level L ow level Middle level Middle level F PPC S I GB T Drive System DSUI RST/ DQ0 Idq Hardware level I rst Duty C ontrol V rst V dc Figure 2. Simplified control block scheme of a distributed generator (DG) power converter. The proposed FPCC will be improved with two individual actions. Gray boxes in Figure 2 show where these actions take place. On the one hand, in the lower level, the duty cycle control signal is saturated with a theoretical current limit, called the fast predictive peak current saturation (FPPCS) method. On the other hand, at the hardware level, the delay of duty control signal updating is reduced without modifying pulse width modulation (PWM) switching frequency with a technique denoted as duty signal updating improvement (DSUI). 2.2. Fast Predictive Peak Current Saturation Method Figure 3shows a simplified single-line model of the converter as an ideal controlled voltage source. This model has been widely presented in the literature [22]. The converter output line-to-line voltage (VgRS,VgST) is defined by an impedance (Zsc) and a grid voltage source. The measured voltage could be used to build up an equivalent voltage source model (VnR,VnS,VnT) connected to the virtual neutral point of the converter model (noted by the dashed lines in Figure 3). Equation (1) shows the relationship of the inductor voltage (VL) with the voltage source model of Figure 3and with the differential equation of an inductor: VL=(DVdc 2−Vn LdIL dt (1) where Vdc is the DC-link voltage, Vnis the grid voltage, Dis the DG duty control signal in the range of [−1,1],Lis the inductive value of the filter value and ILis the current across the inductance. Since the controller is executed periodically at a fixed frequency Fs, Equation (1) could be discretized, and Dwould be given by Equation (2): Dk=2L(ILk+1−ILk)Fs+Vnk Vdck (2) Energies 2016,9, 1 6 of 18 DRVdc/2 LC Zsc ILR VLR LC Zsc VgRS ILS VLS LC Zsc VgST ILT VLT DSVdc/2 DTVdc/2 VnR VnS VnT Figure 3. Simplified inverter voltage source model. Equation (2) gives the relationship between ILtime evolution and the control signal value. Consequently, the current measurement on the next step control could be predicted. Imposing a control law restriction with a maximum current threshold IFPPCS, Equation (3) sets a theoretical maximum control signal: DmaxRk=2L(IFPPCS−IRk)Fs+Vgk Vdck DmaxSk=2L(IFPPCS−ISk)Fs+Vgk Vdck DmaxTk=2L(IFPPCS−ITk)Fs+Vgk Vdck (3) where DmaxRk,DmaxSkand DmaxTkare the maximum duty allowed control signals for the defined IFPPCS in each phase and IRk,ISkand ITkare the measured currents of the three phases at the kinstant. 2.3. Duty Signal Updating Improvement Method Typically, PWM techniques update only their control signals in the valleys and peaks of the triangular carrier, T0and T2respectively (see Figure 4), guaranteeing non-desirable firing, the switching frequency remaining constant and avoiding extra power losses [23]. Figure 4shows a typical delay added in a power converter controller. If the control processor needs the computational time (Tc) since the last sampling time (T0), then an additional delay of Tm will be inserted before the action will be executed, because the control signal can only be updated in the peaks and the valleys. The proposed technique updates the control signal at T1with some restrictions. Then, only Tcdelay happens, and the peak current under faulty conditions will drop. T0T1T2 Control delay Modulation delay PWM carrier Duty control signal Tc Tm Figure 4. Typical delay added in a power converter controller. The measures are taken at T0, but Tc is needed to calculate the next control signal. Finally, the control signal is updated and applied at T2. Pulse width modulation: PWM. As an example, Figure 5shows all four possible cases in the up-slope PWM carrier semi-cycle, but similar cases could be exposed in the down-slope semi-cycle. On the one hand, during the Energies 2016,9, 1 7 of 18 up-slope, if the previous control signal (D0) is greater than the triangular carrier value at T1, no extra transition is guaranteed, and the new control signal (D1) could be updated without any additional switching in the semi-cycle (Cases c and d in Figure 5). On the other hand, if D0is lower than the triangular carrier at T1, at least three transitions may occur if D1is updated at T1: the first one belongs to the D0level; a second transition happens at T1; and a third transition will happen at the D1level. Consequently, the control signal will be updated in the next valley or peak to avoid extra switching (Case a in Figure 5). Finally, Case b does not produce any extra-switching, but neither modifies the control output. T1 D0 D1 T0T2 aT1 D0 D1 T0T2 b T1 D1 D0 T0T2 cT1 D1 D0 T0T2 d D Figure 5. All four possible duty updating cases in the rising PWM semi-cycle. The control signal could be updated at T1in Cases c and d, but must be updated at T2in Cases a and b. Graphically, Figure 6shows an example of PWM signals generated in Cases a and c. In Case c, the duty signal is updated (blue line) without producing extra switching, reducing the on state of the semiconductor. However, in Case a, the control signal must be updated in T2(solid blue line); otherwise, two switching events will happen (dotted red line). T1 D0 D1 T0T2 a 0 PWM 1 T1 D1 D0 T0T2 c 0 1 Figure 6. PWM signals generated with Cases a and c of the rising PWM semi-cycle. The red dotted line points out possible malfunctioning with two switchings in the same semi-cycle if the proposed rule is not applied. The blue line points out PWM signals generated with the duty signal updating improvement (DSUI) method. Following the same steps, along the modulation down-slope cycle, if D0is lower than the modulation value at T1, the control signal could be updated without any change in the switching frequency. Figure 7shows all four possible cases on the down-slope semi-cycle. Energies 2016,9, 1 8 of 18 T1 D0 T0T2 aT1 D0 D1 T0T2 b T1 D1 D0 T0T2 cT1 D0 D1 T0T2 d D1 Figure 7. All four possible duty updating cases in the falling PWM semi-cycle. The control signal could be updated at T1in Cases a and b, but must be updated at T2in Cases c and d. Fortunately, not all cases are relevant with respect to current faults. Therefore, a study could be made to determine the effectiveness of the improvement in these special cases. There are two fault conditions: a positive and a negative over-current peak. From here, the up-slope case will be analyzed, but a similar reasoning could be done for the down-slope semi-cycle. According to Equation (2), at instant k= 1, the worst over-current peak (IL0) would happen if the current peak fault was add up over the maximum current value modulated. Consequently, D0 is expected to be positive and big enough. In addition, if a dangerous peak current happened, the controller would have to drop ILto a safety region. According to Equation (2), to take down IL1,D1 will be very low. Therefore, if a positive over-current peak happens, Case c of Figure 5is expected. As previously mentioned, this is one of the allowed cases to refresh the control signal, so the over-current peak will be reduced. A similar reasoning could be made with a negative over-current fault. On the one hand, now, D0is expected to be negative and big enough. On the other hand, from Equation (2), the D1expected value will be very high. Consequently, if a negative over-current peak happens, Case a or d of Figure 5 is expected. If Case d happens, the control signal will be updated, and the over-current peak will be reduced. Unfortunately, if Case a happens, the method will not act in this semi-cycle. Figure 5points out that Tcinfluences the effectiveness of the method. If Tcis forced to zero, all control steps will be in the c and d cases, so it is important to have a small delay Tcto short the measured peak current in most situations. Finally, one more action could be performed to reduce the over-current peak. A fault happening in semi-cycle kwill be measured at the beginning of the next semi-cycle k+1, and the control action will be placed at T1in the best case or at the beginning of k+2 in the worst case. Therefore, the maximum delay could be 2Tsor Ts+Tc. If Tcis relatively short, a new control step could be done at the middle of the semi-cycle. This control signal will be applied with the same rules as the others, so in a general way, it will be placed at the final part of the semi-cycle. In this case, if a fault happens at the middle of the semi-cycle k0, it will be measured at the beginning of the next control step k0+1, and the control action will be placed at T1in the best case or at the beginning of k0+2 in the worst case. Therefore, the maximum delay could be Tsor 0.5 ·Ts+Tc. Assuming VLconstant in a short period of time during the fault condition: IL=1 LZVLdt−→ ∆IL=VL L·Tdelay (4) Energies 2016,9, 1 9 of 18 where ∆ILis the expected increment on the peak current induced by the fault and Tdelay is the time necessary to control the fault. Therefore, according to Equation (4), the peak current will be reduced in: PImax = VL L·1.5Ts VL L·2Ts =0.75 p.u. PImin =limTc→0 VL L·(0.5Ts+Tc) VL L·Ts+Tc =0.5 p.u. (5) where PIis the proportion of the peak current reduced with the improvement (between 50% and 75%). 3. Simulations A high power industrial PV solar inverter has been modeled to test FPCC. However, similar results could be obtained with other applications. The following devices have been modeled in the simulation: a solar panel field; a detailed commercial model of a two-level three-phase power inverter; a medium voltage transformer; the point of interconnection (POI) with the utility grid; a RL divider to generate voltage sags and phase-jumps. Two types of faults have been analyzed at full power. The worst cases described in the international legislation [5–13] have been selected. The system will be tested against symmetric and asymmetric voltage sags and phase-jump faults. Figure 8shows line-to-line voltages of the deepest faults of each type used to test the system. Case a shows a three-phase voltage fault with zero remaining voltage. Case b shows an asymmetric voltage fault with two phases overlapped. Case c shows a three-phase 45◦voltage phase-jump. Finally, Case d shows the same phase-jump for only one phase. −1.0 −0.5 0.0 0.5 1.0 Vg (p.u.) (a) −1.0 −0.5 0.0 0.5 1.0 Vg (p.u.) (b) −1.0 −0.5 0.0 0.5 1.0 Vg (p.u.) (c) −1.0 −0.5 0.0 0.5 1.0 Vg (p.u.) (d) Figure 8. Line-to-line three-phase grid voltage for all types of faults tested. (a) Three-phase zero-voltage fault; (b) asymmetric zero-voltage fault; (c) three-phase 45◦voltage phase-jump and (d) mono-phase 45◦voltage phase-jump. Energies 2016,9, 1 16 of 18 The main parameters of the commercial two-level three-phase grid-tie inverter are summarized in Table 6. Nominal values, inner current control PIDs, switching frequency, software protections and the FPCC setup are detailed. Table 6. Grid-tied inverter setup. Parameter Value Parameter Value Nominal active power PDG 500 kW Over-current software protection SP 1.3p.u./0.1 ms Nominal output current In1202 A Over-current hardware protection HP 1.4 p.u. Nominal grid voltage Vn240 V Active current control kpD=0.05 kiD=5 FPPCS limit IFPPCS 1.05 p.u. Reactive current control kpQ=0.05 kiQ=5 Delay control time Tc0.6 p.u. PWM frequency fPWM 1980 Hz The POI is simulated with an ideal three-phase voltage source at VL= 23 kV and f= 60 Hz, with a short circuit power (Ssc) of 500 MVA. Additionally, the medium voltage transformer is detailed in Table 7. Finally, faults are modeled with an RLthree-phase impedance, regulating values to desired faults. Table 7. Medium voltage transformer setup. Parameter Value Parameter Value Primary winding voltage 23 kV Nominal power 0.6 MWe Secondary winding voltage 0.24 kV Nominal grid frequency 60 Hz Winding type Y∆Leakage reactance 0.12 p.u. Copper losses 0.01 p.u. 6.2. Testbench FPCC results had been verified experimentally with a real high power test bench. Figure 16 shows a diagram (a) and a photo (b) of the test bench used for the experiments. ELECTRIC GRID 400 V 50Hz 1000 kVA 400V/240V AUXILIARY SYSTEM 400 V AC DC DC AC DUT AC DC Electronic generator Rectifier 100 kVA 400V/230V (a) (b) Figure 16. Test-bench scheme (a) and panoramic view (b); the device under test (DUT) is on the right side of the photo, and the rectifier and generator are in the background. The power transformer is inside the metallic jail. The utility grid was emulated with an electronic power converter generator in order to perform controlled faults. A three-phase two-level converter was used. A grid of 240 V and 60 Hz was generated to perform all tests. Energies 2016,9, 1 17 of 18 The DUT selected was a commercial high-power three-phase two-level grid-tied inverter DG for PV applications. The converter was set according to Table 6. PV panels were emulated with a controlled rectifier that provided a suitable DC voltage input for both the DG and the electronic generator. A three-phase two-level converter was used. The rectifier could provide a DC-link input voltage from 425 V–825 V. The transformer has a YY configuration, with winding voltages of 400 V:400 V and a short-circuit impedance of 0.09 p.u. Finally, all wiring in the test bench was enough to fulfil the power demands, and no significant inductance was added (three wires of 240 mm in diameter per phase). Acknowledgments: This work was supported by GPTech Spain (http://www.greenpower.es) and the Electronic Engineering Department of the University of Seville. Author Contributions: Jesús Muñoz-Cruzado-Alba conceived of and designed the proposed control strategy and significantly contributed to the implementation of the simulation and test bench. Javier Villegas-Núñez and José Alberto Vite-Frías helped in the laboratory tests and the writing of the paper. Juan Manuel Carrasco Solís responsible for guidance and a number of key suggestions. Conflicts of Interest: The authors declare no conflict of interest. References 1. Hashemi, S.; Yang, G.; Ostergaard, J.; You, S.; Cha, S. Storage application in smart grid with high PV and EV penetration. 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Overall Efficiency of Grid Connected Photovoltaic Inverters; European Committee for Electrotechnical Standardization (CENELEC): Brussels, Belgium, 2010. c 2015 by the authors; licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons by Attribution (CC-BY) license (http://creativecommons.org/licenses/by/4.0/).