A modular current-mode high-precision winner-take-all circuit

557 A Modular Current-Mode High-Precision Winner-Take- All Circuit T. Serrano and B. Linares-Barranco National Microelectronics Center (CNM), Ed. CICA, AV. Reina Mercedes s/n, 41012 SPAIN. Phone: 34-5-4239923 Fax: 34-5-4624506, E-mail: [email protected] Abstract In this paper we present a Winner-Take-All (WTA) circuit realized using current-mode circuit design techniques. The operation of the WTA is based on current comparators and current mirrors. Speed and precision is determined primarily by the characteristics of the current mirror used. Using special current mirrors, resolutions below 1% and settling times below loons were simulated. The circuit remains operative with reasonable speed and precision for an input signal range wider than two decades. It requires current input signals and provides voltage output signals. I. Introduction In the last years the field of current-mode signal processing has been receiving considerable attention, and more circuit designers are using current-mode circuit design techniques to develop compact and fast A/D converters [I], filters [2], neural networks [31, and fuzzy operators [4]. In the area of ixural networks and fuzzy signal processing a very common building block is the Winner-Take-All (WTA) circuit (also called Mar-operator). Several WTA circuit topologies have been reported in the literature. Some of them operate with voltage signals [5], and others operate with current input signals [6]. However, all of them rely on the good matching of the VT of an array of transistors. The number of transistors in this array is equal to the number of inputs. This fact imposes that all transistors of a WTA have to be inside the same chip (or, at least, the same wafer). If there is a need to assemble a large neural net composed of several chips and with a WTA circuit distributed among these chips, the performance in precision of the WTA may become drastically degraded. In this paper we present a current-mode WTA circuit which requires current input signals, and is therefore suitable for a current signal processing environment. The circuit can be extended between several chips, without loss of precision for the overall system performance. In the present paper we will first describe the mathematical principle of operation of the WTA. Afterwards, we will study the stability of the equilibrium point, followed by the verification of the global stability of the circuit. Then we will consider several current mirror topologies to be used in the circuit. Finally we will present Hspice simulation results that characterize the operation of the current-mode WTA circuit. 11. Description of WTA Operation Analytically, the problem of finding the maximum value among a set of input values {xi} can be stated as the solution y of the following nonlinear algebraic equation N Y = CaiU(xi-Y) (1) i= 1 where ai are positive parameters that need to meet some conditions, and U(.) is the step function 1 if x>o U(x) = E (0, 1) if x = 0 (2) i 0 if x<O For example, consider the special case for eq.( I) in which N=4, as shown in Fig. 1. In this case, the solution of eq.( 1) is given by the intersection of the curves f, (y) = caiU (xi - y) and f2 (y) = y, which is point A. At point A we have (3) which is the maximum of the input set values. Looking at Fig. 1 we can see that if we impose the condition then the curvesfi(y) andfi(y) will intersect at the point that defines the maximum of the set {xi}. In order to implement eq.(l) in an electronic circuit, some dynamics need to be added. Practical circuits are described by time-domain differential equations, therefore we need a differential equation whose solution is eq.( 1). Consider, for example, the following time-domain first order differential equation, (5) The steady-state solution of this equation is precisely eq.( 1). For this solution to be stable, it is required that (6) y = x4 = max{xi> ai>xi Vi (4) N z$ = -y+ C a,u(xi-y) i=I - q <o d~ Solution This means that the stability condition for eq.(5) is XI x2 x3 x4 Fig. 1: Graphical representation of a particular case of eq.(l) 558 PMOS-mirror with multiple outputs L >I1 Fig. 2: Circuit diagram of complete current-mode WTA - 1 - ai6(xi-y) <O (7) xi2y 6(.) being the derivative of the step function. This condition is always fulfilled. 111. Current-Mode Circuit Implementation The circuit implementation that follows implements the mathematical model of eq.(l) with the coefficients {ai} defined as The circuit that implements each of the terms aiU(xi-y) of eq.(l) can be seen in Fig. 2. The equivalences between this circuit parameters and the parameters in eq.(l) are as follow: (9) In its steady state, the WTA circuit (see Fig. 2) solves the following equation, ai = xi Vi (8) x.=I. a.=Ii 11 y = I, aiU(xi-y) =Iloi N I, = c IOi with I,i = IiU(Ii-Io) (10) i= 1 For the current comparator a simple inverter can be used, or a high performance comparator [7]. The precision of the WTA circuit of Fig. 2 is limited by the current mirrors mismatch errors. Current replication through current mirrors is subject to errors produced by the mismatch between transistors inside the same current mirrors. Therefore, if it is needed to extend the WTA among several chips, the precision can be made insensitive to inter-chip electrical parameters spread by keeping all the transistors of the same current mirror inside the same chip. This can be achieved by using the assembling technique depicted in Fig. 3, which requires the addition of only one extra current mirror. By this approach, the precision of the overall WTA circuit is insensitive to electrical parameters spread between different chips. IV. Stability Considerations In this Section we will first study the conditions to make stable the unique steady-state equilibrium point, followed by a global stability study of the complete system. The stability of the equilibrium point is based on local considerations and is therefore performed through a small signal linear circuit analysis. The global stability, however, needs nonlinear large signal considerations, and is based on Liapunov's stability theory [8]. A. Local Stability of the Equilibrium Point If the operation of the WTA circuit of Fig. 2 is stable, there should be a unique steady state in which all N-mirror cells, except one, are OFF (Zoi=O), and Z0=Zim. In this case, the active part of the circuit is given by the diagram shown in Fig. 4(a), where transistor MI is in its ON state and driving I II 1; I I I All II I I II YYI I 1 Fig. 3: Modular inter-chip connection for current-mode WTA (PMOS-mirror I Fig. 4: Steady state representation of WTA current-mode circuit. (a) Circuit diagram, (b) small signal equivalent circuit the complete I,, current. Fig. 4(b) represents the corresponding small signal equivalent circuit, where the main delay elements have been included. Elements C, and G, represent the input impedance of the current comparator, A its voltage gain, and O, accounts for its internal delay. Conductances go, represent the output impedance of the NMOS current mirror, and for the PMOS current mirror gip is its input impedance, g, its output impedance, and Or, defines its delay. For transistor MI, only the static parameters g,, and gdsn are considered. Its delay has been included in parameter OA. Analysis of this small signal equivalent circuit yields the following second order characteristics equation, which is stable if (12) Therefore, stable steady-state WTA operation requires fast current mirrors and comparators, but dominating input comparator dynamics and small comparator voltage gain. B. Global Stability of the System Note however, that now there are N dominant dynamic elements in the complete WTA during the transient regimes: capacitors C, at the input of each current comparator. Therefore, the dynamics of the system is not a first order one as was supposed in eq.(5), but it is of order N. Nevertheless, Cc(gmn+gon)'A 1 1 >-+- gmngon OA "p 559 I b) (d) Fig. 5: Current mirror t&ologies: (a) simple, (b) cascode, (c) (;;kgulated cascode [lo], (d) active-inpu&], (e) active-input regulated cascode 1121 stability analysis can be performed through the use of LiupunovS stability theorems [8]. The dynamics of the WTA, assuming capacitors C, are the dominant dynamic elements, are described by the following set of N first order nonlinear differential equations, N CCGxi = - G, ( vxi - vM) - Ii + Ii U ( vM - vxj) (1 3) j= 1 where vM is the voltage trip point at the comparators input, and the cell current l<,i is described now by, Note that, since IOi = IiU(VM-vxi) (14) (15) there still exists the unique steady-state solution of eq.( 10). Under these circumstances, the following scalar function', d ,dt Io - Ii = G, ( vxi - vM) + C - ( vxi - vW) U (VXi - Vw) (16) +GCE I ~'(B)~.S+C(~~-~I,)U(V~~-VM) 1 i lo is a Liapunov function of the Nth order WTA system. Computing the time derivative of this function yields, N .k = U' ( vxi - VM) vxpi PI= ~~IJ(l-u(vxJ-vM))~-GC(vxl-~M) =I -I[ where pi is, by eq.(13), equal to C,v,,, thus N (18) Since U(.) is monotonically increasing (U' (x) t 0, Vx), it then results that our WTA circuit will make decrease in time the Liapunov function E. Since E is bounded from below the circuit described by eq.( 13) will have a steady state ( vxl = 0) which is a minimum of the Liapunov function E. By Liapunov's theorems [8] this means that eq.( 13) describes a stable system that converges asymptotically to its unique solution given by (see eq.(3)), .2 .k = -c, U ( Vx1 - VM) vx, 2 0 I= 1 Io = max { Ii} (19) I. In order to apply Liapunov's theorems let us approximate the step function U(.(.) by !he following continuous and differentiable function with EzO but close to zero, U (z) = ___ 1 1 + %. V. Election of Current Mirrors The precision of the overall WTA current mode circuit is determined by the election of the kind of current mirrors used. Since a current comparator has virtually no offset [7], the current error at the input of each current comparator is determined by mirror mismatches. The error at the positive current I, available at the input of each current comparator results from one p-mirror reflection, preceded by an n-mirror reflection of the winning cell, (20) while the error of the negative current li at the current comparators inputs results from a single n-mirror reflection, The total current error at the input of each current comparator is therefore given by, (22) However, the error introduced by a current mirror is not only the random mismatch contribution, as considered by eqs.(20)-(22), but also its systematic error contribution, which results from different drain-to-source voltages at the reflecting transistors, poor impedance coupling, and inherent nonlinear MOS transistor operation. The random mismatch error contribution of a current mirror is almost topology independent and is determined primarily by the area of the reflecting transistors [9]. However, the systematic error contributed by a current mirror is highly topology dependent. Consider, for example, the five current mirror topologies of Fig. 5. If they all have the same reflecting transistors (MI and M2) sizes (W=lOOpm and L=20pm), VD= 1.5v and they are loaded by their complementary PMOS current mirrors with equivalent input impedance, their total current error defined as is shown in Fig. 6. This error is expressed in bits, and is a function of the input current linl which in this case varies from IO@ to 8OOM. For the active-input regulated cascode current mirror, two curves are given: one with A=lOO and the other with A=1000, where A is the voltage gain of the differential voltage amplifiers. Also shown in Fig. 6 is the random mismatch error contribution (0, in eq.(23)) which is approximately the same for all the topologies. According to our precision requirements, Fig. 6 can help us to select the most appropriate current mirror topology for our application. In our case we would like to maintain a good accuracy over a very wide signal range. Therefore, we will choose the active-input regulated cascode current mirror. VI. Simulation Results o2 (I,) = 0; + 0; 02(li) = 02 N (21) O;,tal = 02 (I,) + 02 (Ioi) = 20; + 0; "Total = A$ystematic + (23) A current-mode WTA prototype has been designed for the digital 1.5pm single-poly CMOS process provided by ES2 560 5.0 1 10.0 9.0 - 8.0 v) - ._ s ._ 0 E a 7.0 6.0 f. ,. k ’ ’ e-05 1 e-04 Ii absolute relative Table I1 l0pA 50pA l00pA 500pA I.0mA 2.0mA 272nA 640nA 977nA 3.21pA 5.93pA 11.6pA 2.72% 1.28% 0.98% 0.64% 0.58% 0.55% VII. Conclusions We have presented a current-mode WTA circuit that can be extended by inter-chip modular connections without loss of precision in its operation. Stability of the circuit has been studied theoretically and verified through Hspice simulations. A design has been performed and characterized through extensive simulations. Precision values below I % have been obtained. VIII. References [I] D. G. Nairn and C. A. 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