MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time Sigma-Delta Modulators

(*)This wo k has been suppo ed by he EU ESPRIT IST P ojec 2001-34283/TAMES-2 and he Spanish CICYT P ojec TIC2001-0929/ADAVERE. MATLAB/SIMULINK-Based High-Le el Syn hesis o Disc e e-Time and Con inuous-Time 6' Modula o s J. Ruiz-Amaya, J.M. de la Rosa, F. Medei o, F.V. Fe nández, R. del Río, B. Pé ez-Ve dú and A. Rod íguez-Vázquez Ins i u o de Mic oelec ónica de Se illa  IMSE-CNM (CSIC) Edi icio CICA-CNM, A da. Reina Me cedes s/n, 41012- Se illa, SPAIN Phone: +34 95 5056666, Fax: +34 95 5056686, E-mail: [email p o ec ed] Abs ac This pape desc ibes a ool ha combines an accu a e SIMULINK-based ime-domain beha iou al simula o wi h a s a is ical op imize o he au oma ed high-le el syn he- sis o 6' Modula o s ( 6' Ms). The combina ion o high accu acy, sho CPU ime and in e ope abili y o di e en ci cui models oge he wi h he e iciency o he op imiza- ion engine makes he p oposed ool an ad an ageous al e - na i e o 6' M syn hesis. The implemen a ion on he well-known MATLAB/SIMULINK pla o m b ings nume - ous ad an ages in e ms o da a manipula ion, lexibili y and simula ion wi h o he elec onic subsys ems. Mo eo e , his is he i s ool dealing wi h he syn hesis o 6' Ms using bo h Disc e e-Time (DT) and Con inuous-Time (CT) ci cui echniques(*). 1. In oduc ion 6' Analog o Digi al Con e e s (ADCs) ha e demon- s a ed o be an a ac i e solu ion o he implemen a ion o analog-digi al in e aces in sys ems-on-chip. Compa ed o Nyquis - a e ADCs, 6' a chi ec u es p esen a be e pe - o mance in e ms o esolu ion, speed and powe consump- ion oge he wi h a high obus ness agains he una oidable ci cui pa asi ics and ole ances [1][2][3]. Howe e , he need o design high-pe o mance 6' ADCs in ad e se dig- i al echnologies oge he wi h he e iginous a e imposed by he echnology e olu ion has mo i a ed he in e es o CAD ools which can op imize he design p ocedu e in e ms o e iciency and sho ime- o-ma ke . Fo his pu - pose, se e al ools o o e sampling con e e syn hesis ha e been epo ed in he las yea s [1][4][5][6][7]. These ools use di e en syn hesis s a egies ha can be oughly classi ied in o wo main ca ego ies [1][8]: •Knowledge-based syn hesis- ools, which a e based on cap u ing he knowledge o expe ienced designe s [4][5]. Al hough he execu ion imes a e e y sho , he esul s s ill mus be op imized because design p oce- du es a e usually based on app oxima e equa ions and e y simple models. Addi ionally, hey a e closed ools, e.g., limi ed o a educed numbe o opologies and he addi ion o new ones is a e y cos ly p ocess and usually es ic ed o he ool de elope s. •Op imiza ion-based syn hesis ools [1][6][7], which a e based on an i e a i e op imiza ion p ocedu e wi h a pe - o mance e alua o in he loop. Pe o mance e alua ion can be done by means o equa ions o simula ions. In he la e case, he cha ac e is ics o he simula o de e mine he accu acy and openness o he ool. Mos mode n app oaches [1][6][7] belong o he second class o ools. Fig.1 shows he concep ual block diag am o a con en ional op imiza ion-based syn hesis ool. The design p ocess o a 6'0s a s om he high-le el modula- o speci ica ions ( esolu ion, signal bandwid h, e c.). The objec i e is o ge he building block speci ica ions (design pa ame e s) ha op imize he pe o mance o he modula- o ; ha is, hose speci ica ions which sa is y he modula o - le el speci ica ions wi h he minimum powe consump ion and silicon a ea. A each i e a ion o he op imiza ion p oce- du e, ci cui pe o mances a e e alua ed a a gi en poin o he design pa ame e space. Acco ding o such an e alua- ion, a mo emen in he design pa ame e space is gene a ed and he p ocess is epea ed again. The i e a i e na u e o he op imiza ion p ocedu e equi es a e y e icien mechanism o pe o mance e alu- a ion. E en -d i en 6' beha io al simula ion is used in he syn hesis app oaches in [1][6][7]. This echnique enables e y e icien analysis while p o iding high accu acy le els. In hese ools, bo h, simula ion engine and models, a e implemen ed using a p og amming language like C. Modu- la o lib a ies a e usually a ailable, con aining a limi ed Fig. 1: Concep ual block diag am o an op imiza- ion-based 6'M syn hesis ool. New design poin Pe o mance e alua ion Specs OK? End No Yes Modula o speci ica ions Modula o a chi ec u e Ini ial design poin P oceedings o he Design, Au oma ion and Tes in Eu ope Con e ence and Exhibi ion Designe s’ Fo um (DATE’04) 1530-1591/04 $20.00 © 2004 IEEE numbe o a chi ec u es. Al hough a ex o g aphical in e - ace is usually p o ided o c ea e new a chi ec u es, block models canno be easily changed. On he o he hand, he possible ci cui echniques used o implemen he modula- o s a e cons ained by he capabili ies o he simula ion engine and he a ailable block models. Fo his eason, he syn hesis ools in [1][6][7] a e limi ed o disc e e- ime Swi ched Capaci o (SC) 6'modula o s. To o e come hese p oblems he p oposed 6' syn hesis Tool has been implemen ed using he MATLAB/SIMULINK pla o m [9][10]. The embedded beha iou al simula o is able o e icien ly e alua e he pe o mances o LowPass (LP) o BandPass (BP) 6' Ms implemen ed using ei he SC, SwI ched Cu en (SI) o CT ci cui echniques. This enables he syn hesis ool o deal wi h all hose ypes o 6' Ms. The implemen a ion on he MATLAB/SIMULINK pla - o m p o ides a numbe o ad an ages: (a) i is a widely used pla o m, amilia o a la ge numbe o enginee s, whe eas special-pu pose ools [6][7] equi e o lea n a p op ie a y ex -based o g aphical in e ace; (b) i has di ec access o e y powe ul ools o signal p ocessing and da a manipu- la ion; (c) i has comple e lexibili y o c ea e new 6' M a chi ec u es, and e en o include di e en blocks, ei he con inuous- ime o disc e e- ime; and (d) i enables a high lexibili y o he ex ension o he block lib a y whe eas add- ing new blocks o models o exis ing lib a ies in p e ious ools equi es he quali ied con ibu ion o a p og amme . A comple e lis o non-ideali ies o he building blocks o all ci cui echniques (SC, CT and SI) ha e been consid- e ed [1][2][3]. The p ice o pay o he implemen a ion o he beha io al models o he 6'M blocks (in eg a o s, quan ize s, e c.) using elemen a y SIMULINK lib a y blocks is a high compu a ional cos . To pallia e his p oblem he beha io al models a e inco po a ed as SIMULINK S- unc ions [11]. This app oach dec eases he compu a- ional cos o accep able le els o syn hesis pu poses. The op imiza ion ool a he co e o he syn hesis oolbox con ains adap i e s a is ical op imiza ion echniques o wide space explo a ion and de e minis ic echniques o ine uning [1]. Besides, he addi ion o knowledge abou speci ic a chi ec u es has been enabled. Such knowledge can be coded using a s anda d p og amming language: C o C++, is compiled a un- ime and inco po a ed in o he op i- miza ion p ocess. This makes his syn hesis oolbox an op i- miza ion-based syn hesis ool bu wi h he appealing ea u es o knowledge-based sys ems. This pape is o ganized as ollows. The cha ac e is ics o he op imiza ion co e a e b ie ly desc ibed in Sec ion 2. Sec ion 3 is de o ed o he pe o mance e alua o : he beha iou al simula o SIMSIDES. Finally, Sec ion 4 gi es se e al simula ion and syn hesis examples o he p oposed oolbox. 2. Op imiza ion co e The p esen ed syn hesis ool uses an op imiza ion co e o design pa ame e selec ion as desc ibed abo e. De e - minis ic op imiza ion me hods, like hose a ailable in he MATLAB s anda d dis ibu ion [9], a e no sui able because ini ially we may ha e li le o no idea o an app op ia e design poin . The e o e, he op imiza ion p ocedu e is quickly apped in a local minimum. Fo his eason, we de eloped an op imize which com- bines an adap i e s a is ical op imiza ion algo i hm inspi ed in simula ed annealing (local minima o he cos unc ion can hen be a oided) wi h a design-o ien ed o mula ion o he cos unc ion (which accoun s o he modula o pe o - mances). Fig.2 shows he low diag am o he op imize whe e s a ing om a modula o opology, e.g., a modula o whose design pa ame e s (building block speci ica ions) a e no known and a bi a y ini ial condi ions, a se o design pa ame e pe u ba ions is gene a ed. Wi h he new design pa ame e s, a se o simula ions a e pe o med o e alua e he modula o pe o mance. F om he simula ion esul s, i au oma ically builds a cos unc ion ( ha has o be mini- mized). The ype and alue o he pe u ba ions as well as he i e a ion accep ance o ejec ion c i e ia depend on he selec ed op imiza ion me hod. The op imiza ion p ocess is di ided in o wo s eps: • The i s s ep explo es he design space by di iding i in o a mul i-dimensional coa se g id, esul ing in a mesh o hype cubes (main op imiza ion). A s a is ical me hod is usually applied in his s ep. • Once he op imum hype cube has been ob ained, a inal op imiza ion is pe o med inside his hype cube (local op imiza ion). A de e minis ic me hod is usually used in his s ep. DESIGN SPACE DISCRETIZATION MAIN OPTIMIZATION COST FUNCTION EVALUATION END? UPDATE DESIGN PARAMETERS LOCAL OPTIMIZATION No Yes MODULATOR TOPOLOGY Fig. 2: Ope a ion low o he op imiza ion co e. END? UPDATE DESIGN PARAMETERS No PERFOMANCE EVALUATOR P oceedings o he Design, Au oma ion and Tes in Eu ope Con e ence and Exhibi ion Designe s’ Fo um (DATE’04) 1530-1591/04 $20.00 © 2004 IEEE In addi ion, he op imiza ion co e is e y lexible, in so a as he cos unc ion o mula ion is e y e sa ile: mul i- ple a ge s wi h se e al weigh s, cons ain s, dependen a iables, and loga i hmic g ids a e pe mi ed. This op imi- za ion p ocedu e has been ex ensi ely es ed wi h design p oblems in ol ing beha iou al simula o s as well as elec- ical simula o s [1][7]. This op imize has been in eg a ed in he MATLAB/SIM- ULINK pla o m by using he MATLAB engine lib a y [9], so ha he op imiza ion co e uns in backg ound while MATLAB ac s as a compu a ion engine. 3. Beha iou al simula o : SIMSIDES As desc ibed in Sec ion 1, he p oposed syn hesis ool uses a simula o as a pe o mance e alua o . 6'Ms a e s ongly non-linea ci cui s and, he e o e, e alua ion o hei main pe o mance speci ica ions has o be ca ied ou in he ime-domain. Due o he o e sampling na u e o 6'Ms, his means ha long ansien simula ions (se e al housands o clock cycles) a e necessa y o e alua e hei main igu es o me i . T ansis o -le el simula ions using SPICE-like simula o s lead o excessi e CPU imes ( ypically om days o weeks [12]), because hey base i s analysis in nume ical in eg a- ion, wi h small in eg a ion s eps and complex de ice mod- els. To o e come his p oblem, di e en al e na i es ha e been de eloped, which a he p ice o losing some accu acy in hei esul s, educe he simula ion ime [1]. One o he bes accu acy-speed ade-o s is achie ed by using he so-called beha iou al simula ion echnique using unc ional models [6][7][13][14]. This app oach equi es ha he ci - cui can be pa i ioned in o basic blocks wi h independen unc ionali y. This implies ha an ins an aneous block ou - pu canno be ela ed o i sel , ha is, ei he he e is no global eedback loop, o , in case such a loop exis s, he e is a delay ha a oids he ins an aneous dependence. These blocks a e desc ibed by equa ions ha ela e he ou pu s in e ms o he inpu s and he in e nal s a e a iables. Thus, he accu acy o he simula ion depends on how p ecisely hose equa ions desc ibe he eal beha iou o each block. This has been he echnique used in ou simula o , called SIMSIDES (SIMulink-based SIgma-DEl a Simula o ). This simula o has been implemen ed as a oolbox in he MAT- LAB/SIMULINK pla o m. Modelling and simula ion o 6' Ms in his pla o m was i s epo ed in [15][16], al hough limi ed o SC a chi ec u es. Al hough e y in ui i e, he implemen a ion o he beha io al models o each basic build- ing block equi es se e al se s o elemen a y SIMULINK blocks. This means a penal y in compu a ion ime which may become c i ical in an op imiza ion-based syn hesis p ocess in which hund eds o housands o simula ions mus be exe- cu ed. To o e come his p oblem, beha iou al models in SIMSIDES ha e been inco po a ed in SIMULINK by using S- unc ions [11]. As a consequence, he CPU ime o he ime-domain simula ion o a DT/CT 6' M in ol ing 65536 samples is ypically a ew seconds † . Besides, SIMSIDES is able o deal wi h any ci cui echnique: SC, SI o CT. SIMSIDES con ains a se o 6'M block lib a ies which a e classi ied acco ding o he modula o hie a chy le el and he ci cui echnique. The basic building blocks mod- elled in SIMSIDES, as well as i s non-ideali ies a e summa- ized in Table 1. A de ailed desc ip ion o hese non-ideali ies and hei beha iou al models can be ound in [1], [2] and [3] o SC, CT and SI ci cui s, espec i ely. Fig.3 shows he gene al s uc u e o SIMSIDES. Fi s , he modula o a chi ec u e is de ined by connec ing he building blocks o he SIMSIDES lib a ies. A e he ci cui diag am is c ea ed, he use se s some pa ame e s and op ions which a e aken in o accoun by he ool o pe o m he ime-domain simula ion. Mon e-Ca lo simula ion as well as pa ame ic analysis a e also possible. Ou pu da a gene a ed by simula ion consis s o ime-domain se ies which can be p ocessed o ge di e en igu es o me i . Thus, his og ams and ou pu spec a a e compu ed using he ou ines p o ided by he signal p ocessing oolbox o MAT- LAB. O he analyses such as Signal- o-Noise Ra io (SNR), ha monic o in e modula ion dis o ion, a e done using a collec ion o unc ions speci ically de eloped o SIM- SIDES. The quali y o he syn hesis app oach is no only gi en by i s e iciency in e ms o CPU ime. I also c i ically depends on he accu acy o he pe o mance e alua o . To illus a e †. All simula ions shown in his pape we e done using a PC wi h an AMD XP2400 CPU@2GHz @512MB-RAM. TABLE 1: Basic building blocks and non-ideali ies modelled in SIMSIDES. Ci cui echnique Block Non-ideali ies SC In eg a o s Opamps Fini e and non-linea gain, dynamic limi a ions (incomple e se ling e o , ha monic dis o ion), ou pu ange, he mal noise. Swi ches The mal noise, ini e and non-linea esis ance. Capaci o s Non-linea i y, misma ching. Resona o s Non-ideali ies associa ed o he in eg a o s. SI In eg a o s Fini e and non-linea gain, ini e ou pu and inpu con- duc ance, dynamic limi a ions (incomple e se ling, ha monic dis o ion, cha ge injec ion), he mal noise. Resona o s Feedback gain e o , non-ideali ies associa ed o he in eg a o s. CT In eg a o s Fini e and non-linea gain, dynamic limi a ions (pa a- si ic capaci o s, high and low equency poles), he - mal noise, ou pu ange and lineal inpu ange, o se . Resona o s Non-ideali ies associa ed o he in eg a o s. ALL Clock Ji e . Compa a o s O se , hys e esis. Quan ize s /DACs In eg al non-linea i y, gain e o , o se , ji e noise, delay ime. P oceedings o he Design, Au oma ion and Tes in Eu ope Con e ence and Exhibi ion Designe s’ Fo um (DATE’04) 1530-1591/04 $20.00 © 2004 IEEE he accu acy achie ed by he beha iou al models in SIM- SIDES, Fig.4 shows he ou pu spec um o a SC cascade 2-1-1 modula o in ended o ADSL applica ion [17]. The h ee plo s co espond o a beha iou al simula ion using SIMSIDES, an elec ical simula ion using HSPICE (5 days o CPU ime o 8192 samples) and eal measu emen s aken om a chip p o o ype. A di e en signal equency has been chosen o HSPICE o be e compa ison. 4. The 6' Syn hesis oolbox in ope a ion The p oposed ool has been concei ed as a MATLAB ool- box o he simula ion and syn hesis o 6' Ms. The G aphical Use In e ace (GUI) included in he oolbox allows o na i- ga e easily h ough all s eps o he simula ion, syn hesis and pos -p ocessing o esul s. Fo illus a ion pu poses, Fig.5 shows pa o he oolbox GUI o a chi ec u e desc ip ion. By using his GUI, he use can ei he open an exis ing 6'M a chi ec u e o c ea e a new one in he SIMULINK pla o m. When a simula ion is inished, di e en pe o - mance igu es such as ou pu spec um, in-band noise powe , ha monic dis o ion, e c. can be compu ed om he ou pu da a h ough he analysis/da a p ocessing menu. In addi ion, pa ame ic analysis and Mon eCa lo simula ions can be pe o med. High-le el syn hesis is s a ed om he syn hesis menu, whe e cons ain s, pe o mance speci ica ions, design pa ame e s, op imiza ion algo i hms, e c., can be speci ied. Then, he op imiza ion co e s a s he explo a ion o he design space o ind ou he op imum solu ion by using SIMSIDES esul s o pe o mance e alua ion. To illus a e he simula ion and syn hesis capabili ies o his oolbox wo 6'M a chi ec u es ha e been selec ed: • An SC 2-1 cascade single bi 6' M (SC 2-1 sb) (Fig.6(a)) . • A CT 5 h-o de LP 6'M (CT 5 h-o de LP) (Fig.6(b)). One o he mos impo an deg ading ac o s in SC cas- cades 6'Ms is he misma ch e o . This is illus a ed in he Mon eCa lo simula ion o Fig.7(a), whe e a andom Gauss- ian misma ch e o wi h ze o mean and 0.5% s anda d de i- a ion has been assumed. Each plo co esponds o a pa ame ic analysis o he SNR e sus he inpu ampli ude. Abou 450 simula ions wi h 32768 samples we e done o ob ain his igu e and i only ook 541s CPU ime. Apa om mis ma ch e o , he mal noise can deg ade conside - ably he esolu ion. Fig.7(b) illus a es he pe o mance deg ada ion o he 2-1 sb modula o caused by all he mal noise sou ces. On he o he hand, one o he majo ad an ages o CT 6' Ms lies in ha hey can achie e highe sampling equen- cies. Howe e , CT 6' Ms deg ade d as ically hei pe o m- ance as a esul o wo impo an e o s: clock ji e noise and delay ime be ween he quan ize clock edge and DAC esponse. Fig.8(a) shows he impac o he delay on he ou pu spec um o he modula o o Fig.6(b). Two di e en cases Fig. 3: S uc u e o SIMSIDES. SIMSIDES -TBOX SIMSIDES CIRCUIT DESCRIPTION MONTECARLO SNR SIMSIDES -TBOX SIGNAL TIME DOMAIN PSD TOPOLOGIC THD HISTOGRAM SIGNAL LIBRARIES DESCRIPTION SIMULATION PROCESSING PROCESSING TOOLBOX ANALYSIS PARAMETRIC ANALYSIS MATLAB/SIMULINK En i onmen / MATLAB Fig. 4: Simula ion o a SC cascade 2-1-1. 104105106107 -200 -150 -100 -50 F equency (Hz) PSD (dB/Hz) Measu ed HSPICE SIMSIDES Fig. 5: Illus a ing he GUI o edi ing modula o opolo- gies o he 6' Syn hesis Toolbox. P oceedings o he Design, Au oma ion and Tes in Eu ope Con e ence and Exhibi ion Designe s’ Fo um (DATE’04) 1530-1591/04 $20.00 © 2004 IEEE ha e been conside ed: a ixed delay, which is independen on quan ize inpu ol age magni ude; and a signal-dependen delay, which is p ac ically cons an o la ge quan ize inpu ol ages, bu ises o dec easing inpu s [2]. Fig.8(b) illus- a es he pe o mance deg ada ion caused by ji e noise whe e a andom Gaussian ji e noise wi h ze o mean and s anda d de ia ion has been assumed. To show he capabili ies o he Syn hesis Toolbox, he high-le el sizing o he modula o s in Fig.6 is pe o med. The modula o speci ica ions a e: 15bi s@20kHz o he SC 2-1 sb 6'M and [email p o ec ed] o he CT 5 h-o de LP 6'M. The objec i e is o mee hose speci ica ions wi h he minimum powe consump ion and silicon a ea.Once design pa ame e s, design speci ica ions, and cons ain s ha e been speci ied h ough he oolbox GUI, a wide explo a ion o he design space is pe o med by he op imize . A each poin o he design space a SIMSIDES simula ion is done o e alua e he modula o pe o mances. Table 2 and Table 3 show he esul s o he high-le el syn hesis o bo h modula o s. The op imiza ion p ocedu es equi ed 817 i e a ions o he SC 2-1 sb modula o and 674 i e a- ions o he CT 5 h-LP6' aking 16.4 minu es and 52.1 minu es o CPU ime, espec i ely. Finally, Fig.9 illus a es bo h ou pu spec a and Signal- o-Noise plus Dis o ion Ra io (SNDR) co esponding o he high-le el sizing p o- ided by he syn hesis oolbox. Conclusions A ool o he syn hesis o CT and DT 6' Ms in he MAT- LAB/SIMULINK en i onmen has been desc ibed. Based y Thi d In eg a o Second In eg a o Fi s In eg a o Cancela ion Logic Cancella ion Logic gmC-in eg a o 5gmC-in eg a o 4gmC-in eg a o 3gmC-in eg a o 2gmC-in eg a o T ansconduc o 6 T ansconduc o 5 T ansconduc o 4 T ansconduc o 3 T ansconduc o 2 T ansconduc o 1 T ansconduc o y To Wo k s p a Sine Wa e Real_DAC_Mul ibi _delay_ji e Ideal_Compa a o G ound1G ound (a) (b) Fig. 6: Block diag ams o he (a) SC 2-1 sb 6' M and (b) CT 5 h-o de LP 6' M . 104106 -120 -100 -80 -60 -40 -20 0 F eque n cy ( Hz ) Rela i e Magni ude (dB) Ideal The mal noise Fig. 7: E ec o (a) misma ch e o and (b) he mal noise on SC 2-1 sb 6' M . (a) (b) -60 -50 -40 -30 -20 -10 0 40 50 60 70 80 90 100 SNR R e l a i e In pu Am p li ude (d B ) (dB) 10-6 10-5 10-4 10-3 70 75 80 85 90 95 U SNR (dB) 104106108 -160 -140 -120 -100 -80 -60 -40 -20 F e q uenc y( Hz ) Rela i e Magni ude (dB) Ideal ixed delay signal-dependen delay (a) (b) Fig. 8: E ec o (a) loop delay ime and (b) clock ji e noise on CT 5 h-LP 6' M . Vji UTs = P oceedings o he Design, Au oma ion and Tes in Eu ope Con e ence and Exhibi ion Designe s’ Fo um (DATE’04) 1530-1591/04 $20.00 © 2004 IEEE on he combina ion o an accu a e and e icien SIM- ULINK-based ime-domain beha iou al simula o and an ad anced s a is ical op imize , he p oposed ool allows o e icien ly map he modula o speci ica ions in o build- ing-block speci ica ions in easonable compu a ion imes. To he bes o ou knowledge, his is he i s ool ha is able o syn hesize an a bi a y 6' M a chi ec u e using any ci cui echnique (SC, SI o CT). The implemen a ion in he MAT- LAB/SIMULINK pla o m b ings also nume ous ad an- ages wi h a ela i ely low penal y in compu a ion ime. Re e ences [1] F. Medei o, B. Pé ez-Ve dú, and A. Rod íguez-Vázquez: Top-Down Design o High-Pe o mance Modula o s, Kluwe , 1999. [2] J. A. Che y and W. M. Snelg o e: Con inuous-Time Del a-Sigma Modula o s o High-Speed A/D Con e sion: Theo y, P ac ice and Fundamen al Pe o mance Limi s, Kluwe , 2000. [3] J. M. de la Rosa, B. Pé ez-Ve dú and A. Rod íguez-Vázquez: Sys em- a ic Design o CMOS Swi ched-Cu en Bandpass Sigma-Del a Mod- ula o s o Digi al Communica ions Chips, Kluwe , 2002. [4] G. F.M. Beenke , J.D. Conway, G. G. Sch oo en and A. G.J. Slen e : “Analog CAD o Consume ICs”, in P oc. Wo kshop on Ad ances in Analog Ci cui Design, pp. 343-355, 1992. [5] M.F. Ma and R.W. B ode sen: “A Design Sys em o On-Chip O e - sampling A/D In e aces”, IEEE T ansac ions on VLSI Sys ems, Vo l . 3, pp. 345-354, Sep embe 1995. [6] K. F ancken, P. Vanco enland and G. Gielen: “DAISY: A Simula- ion-Based High-Le el Syn hesis Tool o '6 Modula o s”, P oc. IEEE In . Con . Compu e -Aided Design, pp. 188-192, 2000. [7] F. Medei o, B. Pé ez-Ve dú, A. Rod íguez-Vázquez and J.L. Hue as: “A e ically In eg a ed ool o Au oma ed Design o Modula- o s”, IEEE Jou nal o Solid-S a e Ci cui s, Vol. 30, No. 7, July 1995. [8] G.G. E. Gielen and R.A. Ru enba : “Compu e -Aided Design o Ana- log and Mixed-Signal In eg a ed Ci cui s”, P oceedings o he IEEE, Vol. 88, pp. 1825-1852, Decembe 2000. [9] The Ma hWo ks Inc.:Using MATLAB Ve sion 6”, July 2002. [10] The Ma hWo ks Inc.: “Using Simulink Ve sion 5”, July 2002. [11] The Ma hWo ks Inc.: “W i ing S-Func ions Ve sion 5”, July 2002. [12] V. F. Dias, V. Libe ali and F. Malobe i: “Design Tools o O e sam- pling Da a Con e e s: Needs and Solu ions”, Mic oelec onics Jou - nal, Vol. 23, pp. 641-650, 1992. [13] C. H. Wol and L. Ca ley: “Simula ion o '6 Modula o s Using Beha io al Models”, P oc. IEEE In . Symp. Ci cui s and Sys ems, pp. 376-379, 1990. [14] V. Libe ali, V.F. Dias, M. Ciapponi and F. Malobe i, “TOSCA: a Sim- ula o o Swi ched-Capaci o Noise-Shaping A/D Con e e s,” IEEE T ans. Compu e -Aided Design, Vol. 12, pp. 1376-1386, Sep . 1993. [15] S. B iga i, F. F ancesconi, P. Malco a i, D. Tonie o, A. Baschi o o and F. Malobe i: "Modeling Sigma-Del a Modula o Non-ideali ies in SIMULINK", P oc. IEEE In . Symp. Ci cui s and Sys ems, pp. II.384-387, 1999. [16] P. Malco a i, S. B iga i, F. F ancesconi, F. Malobe i, P. Cusi ano and A. Baschi o o: “Beha iou al Modeling o Swi ched-Capaci o Sigma-Del a Modula o s”, IEEE T ans. on Ci cui s and Sys ems-I, pp. 352-364, Ma ch 2003. [17] F. Medei o e al.: “Design o a B oadband 6' Modula o in 2.5V CMOS”, P oc. Design, Au oma ion and Tes in Eu ope: Designe s’ Fo um, pp. 219-223, 2002. TABLE 2: High-le el syn hesis esul s o SC 2-1 sb 6'M . OPTIMIZED SPECS FOR: 15bi s@20kHz In eg. I In eg. II-III Modula o Sampling equency (MHz) 5.12 O e sampling a io 128 In eg a o s Sampling capaci o 61.5 Feed-back capaci o 24 3 MOS swi ch-ON esis ance ( ) Opamps DC-gain (dB) DC-gain non-linea i y Ou pu swing (V) 2.7 Inpu noise PSD Ou pu cu en (mA) Inpu ansconduc ance (mA/V) Compa a o s Hys e esis (V) Technology Cap. non-linea i y (ppm/ ) TABLE 3: Syn hesis esul s o CT 5 h-o de LP 6'M. OPTIMIZED SPECS FOR: [email p o ec ed] In eg. I O he In eg. Modula o Sampling equency (MHz) 300 O e sampling a io 40 T ansconduc o s T ansconduc ance (mA/V) 0.6 0.15 DC-gain (dB) Pa asi ic ou pu capaci o (pF) Inpu linea swing (V) HD3 (dB) DAC Clock ji e (ps) Excess loop delay ime (ns) CipF CopF k:0.84d1.7d 58.5 56 V2–  22%d22%d nV sq Hze8.1d278d 0.5 0.23 0.5 0.14 0.2d V289d 34 42 0.66d0.04d 0.5 0.32 50–d30–d 0.5d 0.77d 104105106 -150 -100 -50 0 Rela i e Magni ude (dB) F e q uenc y( Hz ) SNDR=77.40dB 103104105 -150 -100 -50 0 Rela i e Magni ude (dB) F e q uenc y( Hz ) SNDR=91.78dB (b) (a) Fig. 9: Ou pu spec a and SNDR o he syn hesized (a) SC 2-1 sb and (b) CT 5 h-o de LP 6' M s. 6' P oceedings o he Design, Au oma ion and Tes in Eu ope Con e ence and Exhibi ion Designe s’ Fo um (DATE’04) 1530-1591/04 $20.00 © 2004 IEEE