Serial architecture for fuzzy controllers: hardware implementation using analog/digital VLSI techniques

SERIAL ARCHITECTURE FOR FUZZY CONTROLLERS: HARDWARE IMPLEMENTATION USING ANALOG/DIGITAL VLSI TECHNIQUES J. L. Hue as, S. Sánchez Solano, A. Ba iga, I. Ba u one Ins i u o de Mic oelec ónica de Se illa - Cen o Nacional de Mic oelec ónica A da. Reina Me cedes s/n, (Edi . CICA) E-41012, Se illa, Spain Second In e na ional Con e ence on Fuzzy Logic and Neu al Ne wo ks (IIZUKA’92), Vol. 1, pp. 535-538, Iizuka, Japan, July 17-22 1992. This ma e ial is p esen ed o ensu e imely dissemina ion o schola ly and echnical wo k. Copy igh and all igh s he ein a e e ained by au ho s o by o he copy igh holde s. All pe sons copying his in o ma ion a e expec ed o adhe e o he e ms and cons ain s in oked by each au ho ’s copy igh . In mos cases, hese wo ks may no be epos ed wi hou he explici pe - mission o he copy igh holde . Abs ac A new a chi ec u e is p esen ed o he implemen a ion o uzzy sys ems using analog-digi al echniques. This a chi ec u e is di ec ed owa ds allowing he implemen a ion o many ules on he same chip, including he uzzy in e ence engine and he de uzzi ie . This app oach is based on a o al o pa ial sequen ial ope a ion o bo h he uzzi ie and he de uzzi ie . A basic ope a- ional cell o a membe ship unc ion ci cui as well as i s p o- g ammable e sion a e desc ibed and used o ealizing he p oposed a chi ec u e in a CMOS echnology. 1. INTRODUCTION Ha dwa e implemen a ions o uzzy logic a e a ac ing mo e and mo e he a en ion o esea che s, he e ec i eness o he ac ual ci cui s being a c i ical poin o sys em builde s o adop uzzy solu ions. Besides he esul s ob ained om pu ely digi al app oaches, i seems in e es ing o explo e he possibili ies o e ed by analog echniques, especially in e ms o using he bes o bo h wo lds o come up wi h e icien ci cui s. This communica ion add esses he de elopmen o uzzy ci cui s combining analog and digi al echniques. This is ca ied ou a wo le els: a chi ec u e, and cell design. A he i s le el, he bo lenecks o epo ed ci cui s a e conside ed. In pa icula , we will ocus on Yamakawa’s (1) since, al hough his a chi ec u e is a alid solu ion in many p ac ical cases, i seems in e es ing o look o modi ica ions able o handle he design o sys ems wi h many ules. A way o do ha may be based on ading speed and in e connec ion complexi y by eso ing o he use o a sampled da a app oach. An addi ional ad an age o his app oach is he compa ibili y wi h some well- ounded analog echniques ha can help in he design o he de uzzi ie . 2. SERIAL ARCHITECTURE An al e na i e a chi ec u e is p oposed o cope wi h sys ems wi h many ules. The new a chi ec u e uses essen ially he same basic cells p oposed by Yamakawa, bu he coe icien s a e s o ed in a digi al memo y, he numbe o ules pe chip is s ongly inc eased, and bo h he uzzi ie and he de uzzi ie may be included in he same chip. An o e all iew o he new a chi ec u e is shown in Figu e 1, whe e i s main blocks a e de ailed. Essen ial o his echnique is he de ini ion o an ope a ion cycle, whose du a ion will depend on he p ecision we y o a ain. This ope a ion cycle will be de ined in e ms o N+1 cycles o a undamen al clock. Each Con- ol Rule is implemen ed by a digi al RAM, a Digi al/Analog Cu - en Con e e , some Membe ship Func ion Ci cui s (MFC) and MIN ga es. S a ed an ope a ion cycle, he D/A con e e will p o- ide e e y clock cycle one alue o cu en o unca ing he al- ues coming om he MFC’s. Hence, he con e e pe o ms as a se ial Membe ship Func ion Gene a o (MFG) ins ead o wo king in pa allel (as p oposed by Yamakawa). In o he wo ds, he N bus lines used by Yamakawa as a uzzy wo d a e changed in o N suc- cessi e samples ep esen ing such a wo d on o a simple wi e. The ou pu s om e e y Con ol Rule a e p ocessed by a MAX ga e and ed he de uzzi ie , which implemen s a cen e o g a i y me hod. The i s s age o his is o med by wo i e a i e analog adde s (disc e e- ime), p epa ing he nume a o and he denomi- na o o a disc e e di ide . A e N clock cycles he di ide will gi e he inal ou pu . A amp gene a o is equi ed o p o ide he de uzzi ie wi h bo h he uppe adde coe icien s and he in e nal iming o he di ide . In p inciple his a chi ec u e is slowe han a pa allel coun- e pa . Howe e , since he a ea equi ed o a pa allel implemen- a ion is eno mous (mainly because o he numbe o bus lines), solu ions epo ed a e based on connec ing se e al (o e en many) chips ins ead o a one-chip al e na i e. Then, he ex e nal in e - connec ion delays b ing o h a p oblem associa ed wi h highe delay ime as compa ed wi h he ideal implemen a ion in jus one chip. The aim o he p oposed se ial app oach is o es ablish a ade-o be ween ope a ional speed and silicon a ea occupa ion, bu aking in o accoun he alue o ac ual delays when se e al chips mus be connec ed. Thus, we can sac i ice a pa o he in e - nal speed ( h oughou a sequen ial ope a ion) o be su e ha many mo e ules can be implemen ed on-chip, his a oiding ex e nal connec ions o he han I/O pins. 3. DESIGN SPACE Be o e going in dep h in o ac ual ci cui s, we need o dis- cuss he abs ac design space whe e we can make mo es. Since speed is essen ial and cu en -based p ocessing is no mally as e han ol age-based, we decided o handle any in o ma ion p o- cessing by means o cu en s. The only excep ion a e hose ci - cui s equi ing o s o e his in o ma ion ei he empo a ily o pe manen ly, as well as I/O pads. P ocessing using MOS cu en mi o s is a na u al candi- da e, especially a e he esul s in (2). Howe e , he e a e a ew d awbacks o conside . Channel modula ion e ec s, ma ching e o s and h eshold o se s may deg ade hei pe o mance. Also, p e iously epo ed ci cui s (3) (4) a e a kind o piecewise- linea unc ions, he esul ing ans e cha ac e is ic being o med by conca ena ing 2-piece componen ope a o s. Adjus men o hese cha ac e is ics a e s ongly in luenced by dimension e o s, he SERIAL ARCHITECTURE FOR FUZZY CONTROLLERS: HARDWARE IMPLEMENTATION USING ANALOG/ DIGITAL VLSI TECHNIQUES J. L. Hue as, S. Sánchez-Solano, A. Ba iga, I. Ba u one Dep . o Design o Analog Ci cui s. Cen o Nacional de Mic oelec ónica, Edi icio CICA, A da. Reina Me cedes s/n, 41012-Se illa (Spain) Key wo ds: uzzy logic, disc e e- ime echniques, membe ship unc ion, CMOS in eg a ed ci cui s. esul being especially signi ican when p ecise cancella ion o compensa ion o slopes a e equi ed. Then, besides a dimensions educ ion, an implemen a ion p ocedu e less sensi i e o mis- ma ching mus be looked o . Ano he conside a ion is conce ning he ype o cu es encoun e ed when “ ypical” ules a e implemen ed. Ins ead o a bi a y ans e cha ac e is ics, we usually need symme ical, equally spaced iangula and/o apezoidal unc ions, wi h p o- g ammable slopes and a ela ionship in ol ing he di e en pa ame e s o be p og ammed. Wi h his in mind, a cell p o iding a symme ical wo-b anch inpu -ou pu cha ac e is ic would be p e e able o any o he implemen a ion. In wha ollows he in eg a ed ci cui ealiza ion o his s uc u e will be discussed. A e p esen ing he se ial a chi ec u e he nex s ep is o deal wi h al e na i e implemen a ions o he basic cells. Ou aim is o ind an op imal implemen a ion aking ad an age o VLSI echniques and ollowing he same p inciples ha ha e o ien ed ou sea ch o a p ac ical a chi ec u e, we ocus on p ac ical aspec s a he han in gene ali y. The on-going ac i - i y has a ge ed he implemen a ion o he uzzy in e ence engine. Fo he sake o space, only he basic cells o he uzzi ie will be p esen ed he ein. In pa icula , le us concen a e in he implemen- a ion o he MFC’s. 4. BASIC CELL The ke nel o ou uzzi ie is a MFC able o p o ide a wide numbe o membe ship unc ions as hose e e ed abo e as well as allow some kind o econ igu abili y h oughou elec ical p o- g amming. Figu e 2-a shows a ci cui implemen a ion o his basic cell. Be o e explaining he ci cui ope a ion, we need o de ine he ou pa ame e s equi ed o iden i y any apezoid ep- esen ing a uzzy se . In Figu e 2-b, all hese pa ame e s a e depic ed; wi h he excep ion o he slope m, hese pa ame e s a e named Ij because hey a e associa ed o ac ual cu en s in he ci - cui o Figu e 2-a. T ansis o s T1 and T2 in Figu e 2-a oge he wi h he cu en mi o M1 pe o m as a cu en ec i ie o he signal di e ence Iin−Iaux (5). Iin is he MFC inpu cu en and Iaux is a cu en alue o se up he symme y axis o he membe ship unc ion. When his di e ence is posi i e, ansis o T2 is o , ansis o T1 is con- duc ing and o ces a cu en ou o he mi o M1, his cu en is a copy o −(Iin−Iaux) and d i es he mi o M2. On he con a y, when Iin−Iaux is nega i e, ansis o T1 is o , ansis o T2 con- duc s, and he mi o M2 is d i en by a copy o he inpu cu en di e ence. Fig. 2: (a) Ci cui schema ic o he MFC basic cell, (b) pa ame e s used o iden i y a symme ical apezoid. Io I e Isa Iin Iaux Vb T1 T2 M1 M2M3 Ia 1 : m Iaux I e Isa m (a) (b) RAM D/A MFG MFC MFC MIN MAX Ramp Gene a o ∑ j Ij ∑ Ij j ÷ Xj Yj Ck Ck Ope a ion Cycle Coun e Z To o he Con ol Rule Modules F om o he Con ol Rule Modules Fig. 1: P oposed a chi ec u e o he uzzy con olle . In bo h si ua ions desc ibed abo e, a cons an cu en Isa is sub ac ed a he inpu o he mi o M2. This mi o mul iplies i s inpu cu en by a ac o m, o p o ide some con ol on he mem- be ship unc ion slope. The alue m can be ixed by selec ing he aspec a ios o ansis o s o ming his cu en mi o . Finally, I e is added be o e he inal s age (mi o M3). Then he ou pu cu - en can be exp essed by: whe e These exp essions lead o a geome ical o m o he inpu - ou pu ela ionship o he shape in Figu e 2-b. A ew simula ion esul s can be seen in Figu e 3. Fou di - e en se s wi h all hei unc ions o he same wid h a e depic ed in Figu e 3-a. Cases whe e he wid h is di e en migh be ound in p ac ice, like he wo se s ep esen ed in Figu e 3-b. 5. PROGRAMMABLE CELL The ci cui in Figu e 2-a does no only gi e an inpu -ou pu cha ac e is ic as is equi ed o a membe ship unc ion bu i pa es he way o adding p og ammabili y in a a he s aigh o wa d manne . Since he e a e h ee pa ame e s in Figu e 2-b ha co e- I e − mIai I e > mIa 0 o he wise Io = |Iin − Iaux|− Isa i |Iin − Iaux| > Isa 0 o he wise Ia = spond o cu en s, hey can be ac ually changed by changing he bias cu en supplied o he in ol ed node. On he o he hand, o he ou h pa ame e o be changed, he a ea a io o ansis o s in mi o M2 is made p og ammable by spli ing hese ansis o s in o se e al ones, and connec ing and disconnec ing he ex a ansis o s depending on he pa icula a io equi ed. Fo he sake o p og amming simplici y, we ha e de eloped a ci cui s uc u e ha uses 8 bi s o ix he ac ual unc ion imple- men ed by he ci cui in Figu e 4. This s uc u e can gene a e a amily o 5, 7, 9 o 11 membe ship unc ions, depending on he alue o bi s C0 and C1. Wi hin each amily we can selec ei he iangles o apezoids wi h a slope con olled by D0 and D1. Once he numbe o labels and he unc ion ype ha e been chosen, bi s A0 o A3 allow o selec he pa icula unc ion o be implemen ed. Figu e 5 is in ended o ep esen ing he di e en se s o membe - ship unc ions ha can be implemen ed by means o he ci cui in Figu e 4. Since his is a p elimina y ci cui , he e is s ill oom o dealing wi h a ew mo e se s using he same numbe o bi s o e- p og am he sys em. In he ac ual ci cui we ha e ca ied ou a ade-o ela ing dynamic ange, a ea occupa ion, powe and speed. Fo he a ail- able echnology we selec ed I e = 15 uA, and a maximum dynamic ange o Iin o 6 I e . Since his ci cui mus handle a a iable numbe o labels on a ixed in e al, he e a e a ew ela ionships cons aining he pa ame e s. I we ix an o e lap o 25% be ween wo adjacen unc ions, and we call 2Ib he wid h o lowe base o he apezoid and E he numbe o labels: Ib 4I e ⋅ E1– ---------------------= Fig. 3: Simula ion esul s o he MFC. (a) Fou se s o unc ions wi h he same wid h, (b) wo se s o unc ions wi h di e en wid h. The cu en Ib d i es he ou -ou pu mi o a he op o Fig- u e 4 o gene a e he pa ame e Iaux wi h an exp ession gi en by: On he o he hand, he pa ame e Isa is ob ained om Ib, I e and m acco ding o he exp ession: Wi h he cons ain s chosen in he implemen a ion o he p og ammable MFCs, he scaling o I e o ob ain Ib and Isa is pe - o med by he wo iden ical ci cui s su ounded by dashed lines in Figu e 4. Finally, he block su ounded by a do ed line in Figu e 4 co espond o he p og ammable e sion o he mi o M2 in he basic cell o Figu e 2-a. 6. CONCLUDING REMARKS We ha e epo ed a new a chi ec u e o a uzzy con olle . Ou app oach akes he ad an ages o e ed by analog and digi al echniques. A sampled da a implemen a ion has been chosen o he uzzy in e ence engine and he de uzzi ie . We ha e also p o- posed and implemen ed a CMOS basic cell o he MFC and i s p og ammable e sion, able o gene a e di e en se s o membe - ship unc ions selec ed by an eigh -bi digi al egis e . REFERENCES [1] T. Yamakawa, “High-Speed Fuzzy Con olle Ha dwa e Sys em:The Mega FIPS Machine”, Else ie Science Pub. Comp. Inc., 1988. [2] T. Yamakawa, T. Miki and F. Ueno, “The design and ab ica ion o he cu en mode uzzy logic semi-cus om IC in he s anda d CMOS IC echnology”, P oc. 15 h IEEE In . Symp. Mul iple-Valued Logic, pp. 76-82, May 1985. [3] T. Yamakawa and H. Kabuo, “A P og amable Fuzzi ie In eg a ed Ci cui : Syn hesis, Design and Fab ica ion”, Else ie Science Pub. Comp. Inc., 1988. [4] T. Inoue, F. Ueno and T. Mo omu a, “Analysis and Design o Analog CMOS Building Blocks o In eg a ed Fuzzy In e ence Ci cui s”, ISCAS, 1991. [5] Z. Wang, “No el Pseudo RMS Cu en Con e e o Sinusoidal Signals Using a CMOS P ecision Cu en ec i ie ”, IEEE ans. Ins umen a ion and Measu emen , Vol. 39, N. 4, Augus 1990. Iaux 3 2 ----Ib ⋅∝ Isa Ib I e m ------------–= Membe ship unc ions C1 C0 D1 D0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 Ii n Iaux Vb T1 T2 M1 C0C1 D1D0 A0A2A3 I o I e Isa IbA1 D1D0 : 1 : 1: 10.5 1 : 1 : 0.5 1 : 1 : 1 : 0.5 1: 3/2 : 2·3/2 : 4·3/2 : 8· 3/2 : 1 M3 Ia Fig. 4: Ci cui schema ic o he p og ammable MFC. Fig. 5: Func ion se s implemen ed by he p og ammable MFC.