A CMOS 0.8- µm transistor-only 1.63-MHz switched-current bandpass ΣΔ modulator for AM signal A/D conversion

1220 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 A CMOS 0.8-  m Transistor-Only 1.63-MHz Switched-Current Bandpass 61 Modulator for AM Signal A/D Conversion José M. de la Rosa, Belén Pérez-Verdú, Rocío del Río, and Angel Rodríguez-Vázquez Abstract—This paper presents a CMOS 0.8m switched-current (SI) fourth-order bandpass 61 modulator (BP61 M) IC capable of handling signals up to 1.63 MHz with 10.5-bit resolution and 60-mW power consumption from a 5-V supply voltage. This modulator is intended for direct A/D conversion of narrowband signals within the commercial AM band, from 540 kHz to 1.6 MHz. Its architecture is obtained by applying a lowpass-tobandpass transformation ( 1 2 ) to a 1-bit second-order low-pass 61 modulator (LP61 M). The design of basic building blocksisbaseduponadetailedanalysisoftheinfluenceofSIerrors on the modulator performance, followed by design optimization. Memory-cell errors have been identified as the dominant ones. In order to attenuate these errors, fully differential regulated-folded cascode memory cells are employed. Measurements show a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. A correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz. Index Terms—Analog-to-digital conversion, bandpass sigma– delta modulation, switched-current circuits. I. INTRODUCTION THE TREND toward the realization of complete mixedsignal systems on chip has motivated the exploration of analog design techniques compatible with standard digital CMOS technologies. This is the case of switched-current (SI) circuits [1], which during the last few years have been explored for the construction of different analog functions, including filtering and analog-to-digital conversion (ADC) [2]–[5]. Manyof the SI ADC’s reported in literature use low-pass modulator (LPM) architectures for handling audio-frequency signals. Particularly, a CMOS 0.9m prototype that features 13-bit effective resolution and 300–3400 Hz signal band using a single-loop second-order modulator has been presented in [2]. The use of SI circuits to design cascade LPM’s capable of handling larger operating frequencies has also been explored in [3];however, the achieved frequencies are well below the MHz range. Reported SI ADC’s for signal frequency in the MHz range employ a Nyquist-type architecture [4]–[5]. Specifically, the CMOS 0.8m converter in [4] features 8 bit at 7.5 MHz with 350-mW power consumption; while that in [5], also in CMOS 0.8m, features 7.2 bit at 20 MHz and dissipates 82.5 mW. This paper presents a CMOS 0.8mSI modulator circuit capable of handling signals up to 1.63 MHz with 10.5-bit resolution and 60-mW power consumption from a Manuscript received December 7, 1999; revised March 23, 2000. This work was supported by the Spanish CICYT Project TIC 97-0580. TheauthorsarewiththeInstitutodeMicroelectrónicade Sevilla,IMSE-CNM (CSIC),41012Sevilla,Spain(e-mail:[email protected];[email protected]; [email protected]; [email protected]). Publisher Item Identifier S 0018-9200(00)06436-2. 5-V supply voltage. This modulator is of the bandpass type (BPM) and has been designed to handle narrowband signals within the commercial AM band, from 540 kHz to 1600 MHz. The advantages of BPM’s, as compared to wideband Nyquist-rate converters, for digitizing narrowband signals have been discussed elsewhere [6], and a number of standard CMOS switched-capacitor prototypes have been reported [7]–[8]. The SI BPM in this paper features a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. Correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz, thus demonstrating the possibility of using SI BPM’s in narrowband high-frequency communication systems. Circuit design is based upon a detailed analysis of the influence of SI errors, followed by design optimization. Memory-cell errors have been identified as the dominant ones. However, unlike LPM’s, S I memory cells [9] cannot be employed to attenuate these errors because signals are sampled at a rate close to the signal frequency; hence they change quite significantly during sampling, thereby destroying the SI performance. Instead, fully differential regulated-folded cascode memory cells are employed for error attenuation in our circuits. Another consequence of the high-frequency operation is the increased influence of bonding-pad parasitics, which in our circuit is handled through the use of fully differential current-mode buffers [10]. Section II of the paper describes the modulator architecture. Section III describes the design process of the memory cell and outlines other modulator subcircuits. Section IV presents experimental results. Finally, conclusions are given in Section V. II. MODULATOR ARCHITECTURE Fig. 1 shows the block diagram of the modulator. It is a single-loop fourth-order BPM with a 1-bit quantizer. On the one hand, this choice renders the modulator easy to understand and simple to design. On the other hand, such a simple architecture is capable of achieving high resolution together with robust stable operation; actually, 1-bit quantization and fourth-order filtering suffices to accomplish the specifications intended in this paper. Note that Fig. 1 is obtained by applying a transformation to a single-loop second-order LPM. Such a transformation keeps the stability properties of the latter, and hence allows us to exploit the knowledge already available for the low-pass modulator [11] in order to design the bandpass one—another reason for choosing such an architecture. Fig. 1 includestworesonators,resultingfromthetransformationofthe integratorsintheLPM,twoadditionaldelayblocks,needed to achieve the required delay in the feedback loop, and three 0018–9200/00$10.00 © 2000 IEEE IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 1221 Fig. 1. Block diagram of the modulator. scaling factors. The values of the latter have been optimized to obtain similar signal ranges for both resonators, giving (1) Assuming that the quantization error is modeled as white additive noise [6], the -domain output can be expressed as (2) where and representthesignaltransferfunction and the noise transfer function, respectively, (3) By making , where is the sampling frequency, it can be seen that has 2 transmission zeros at , and that the filtering around this frequency is actually of the band-stop type. The in-band quantization noise power can be calculated by integrating the output power spectral density within the signal bandwidth, as follows: (4) where is the power spectral density of the quantization noise, is the quantization step, is the signal bandwidth, and is the oversampling ratio. From (4), and assuming that the modulator input is a sinewave of amplitude , the signal-to-noise ratio (SNR) and the dynamic range (DR) are given by SNR DR (5) This shows that the modulator resolution increases with at a rate of about 2.5-bit/octave. However, such an ideal feature can only be achieved provided that the scaling coefficients and the resonator transfer functions in Fig. 1 arerealized without errors. Modeling of these errors and circuit optimization are needed to cope with the SNR and DR degradation observed in actual SI circuits. III. SWITCHED-CURRENT IMPLEMENTATION Fig. 2(a) shows the block diagram of the resonators in Fig. 1. It consists of a feedback cascade of two lossless discrete integrators (LDI).1Fig. 2(b) shows a conceptual SI realization of this resonator employing second generation SI memory cells. As shown in [1], the major error sources of SI memory cells are three, namely: conductance error (represented by parameter ) due to finite input/output conductances, incomplete settlingerror(representedby ), andswitchchargeinjectionerror (represented by ). Besides, the resonator behavior becomes degraded by the finite conductances [ and in Fig. 2(b)] of the current mirrors employed to realize the scaling coefficients. Their associated errors are defined respectively by (6) where is the input conductance of the memory cells and is the on-resistance of the steering switches. The above-mentioned errors modify the noise-transfer function . Thus the zeros of this function are shifted from their nominal positions—located at —degrading noise shaping and making the in-band quantization noise power increase. As we demonstrated in [13], the dynamic range of a fourth-order BPM degraded by SI errors is DR (7) where (8) Note that SI errors do not affect DR in the same way, the largest degradationbeingproducedby .Equation(7)wasused to find the maximum value for each error in order to fulfill digital AM radio receiver specifications, i.e., DR 60 dB at 2.16 MHz 6.4 MHz at 10 kHz. This yields 0.25%, 0.35%, 0.5% and 1%. Modulator building blocks were designed to satisfy these conditions as detailed in the next section. 1This structure has been chosen because it keeps the poles inside the unit circleuponchanges dueto errorsofthe feedback loopgain.However,as demonstrated in [12] for lowpass modulators, it may happen that unstable resonators result in stable modulators. 1222 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 Fig. 2. Implementation of the resonator. a) Block diagram. b) Conceptual schematic considering SI errors. A. Design of the Memory Cell and the Resonator A second generation regulated-folded-cascode (RFC) memory cell [14] was used to reduce . This cell increases the input conductance through the incorporation of a local feedback inthesignalpath,thusreducingboth and .Fig.3shows theschematicofthefullydifferentialRFCmemorycellincluding the common-mode feedback circuit (CMFB) (M ). The local feedback stage is formed by transistors M , the memory transistorsareM andthecurrentsourcetransistorsareM . The steering switches are pMOS whilethe memory switches are nMOS with minimum size; the latter include dummy devices which, in combination with fully differential circuitry, attenuate .Althoughthereareotherapproachestoreduce ,wehavenot used them for different reasons. That in [15] uses zero-voltage switching to attenuate the signal-dependent component of . However, its power dissipation is penalized by the amplifier employedtocreatethevirtualground.Thealternativeisusingthe so-calledS Imemorycell[9].However,thiscellisnotwellsuited for BPM’s because the input signal is not stationary during thesamplingphasesinceislocatedat .Hence,unlessasampling-and-hold (S/H) is placed at the front end of the modulator, theadvantagesofusingtheS Imemorycellaredestroyed. Because of the local feedback, the memory cell exhibits third-order dynamics with a single pole at (where is the small-signal transconductance and is the gate–source capacitance) and a pair of complex conjugate poles whose values depend on the transconductances and the parasitic capacitances of M and the steering switches. Two additional MOSFET capacitors, , are connected to the memory transistor gates (see Fig. 3) to create a dominant pole at . Thus, can be controlled by sizing the memory transistor. These extra capacitances also reduce the common-mode component of . The memory cell has been designed by using the transistorlevel optimizer reported in [11] to attain the specifications required for AM digital radio receivers and, at the same time, optimize the trade-off between speed and dynamic range. The resulting bias currents are 212.6 A, 20 A and 2.8 pF (realized through a 36m/36m nMOS transistor). Table I summarizes the simulated performance of the memory cell. This table also includes the memory-cell errors. Their values are low enough to achieve the targeted modulator resolution. On the other hand, the in-band integrated thermal noise is given by Sinc (9) where isthefractionoftheclockperiod duringwhich the noise is being sampled, Sinc is the sample-and-hold transfer function, and is the equivalent noise bandwidth. Assuming that the reference current level of the digital-to-analog converter (DAC) is , the thermal dynamic range of the cell is DR . In our design, 100 A, and the worst case is obtained for the minimum AM sampling frequency, MHz, giving DR 86 dB, which clearly does not limit the performance of the modulator. The SI resonator is implemented by replacing the memory cells in Fig. 2(b) by Fig. 3. The scaling stages are realized through simple current mirrors. Note that the required gain inversion is straightforward because of the fully differential structures. Current steering switches (realized through pMOS transistors) are sized such that , which bounds IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 1223 Fig. 3. Schematic of the memory cell. TABLE I SIMULATED PERFORMANCE (HSPICE) OF THE MEMORY CELL and according to AM digital radio receiver requirements. B. Other Modulator Subcircuits Other building blocks of the modulator in Fig. 1 are the quantizer and the DAC. The 1-bit quantizer is made up of a regenerative latch [16] and a NOR flip-flop which maintains the output value in the phase in which the resonators are fed back. A fast comparison is obtained with low input-current levels. Layout extracted simulations show 4% hysteresis—which is not problematicbecausethepowerofthe in-bandnoise remainsvirtually unchanged for hysteresis as large as 10% of the full-scale converter input [11]. The 1-bit DAC used in the modulator consists of a current source controlled by the comparator output [3]. A stacked-cascode current mirror was chosen because it resembles the structure of the memory cell. The differential output current, with values 50 A , change the flow direction depending on the comparator output. In addition to the mentioned blocks, other circuits have been included for practical reasons. On the one hand, a fully differential current-mode buffer has been incorporated at the front end of the modulator [10]. This buffer is used to isolate the on-chip circuitry from the parasitic time constants at the chip input pads, thus allowing us to take full advantage of the speed capabilities of SI circuits. Apart from this function, this circuit also converts the single-ended external input voltage into a fully differential current through the use of an external resistance. On the other hand, we have included an internal clock phase generator that provides a 4–phase clock diagram in order to avoid transient current spikes. Thus, overlapping clock phases (and ) are used for current-steering switches and nonoverlapping clock phases ( and ) are used for memory switches (see Fig. 3). IV. EXPERIMENTAL RESULTS The fourth-order SI BPM was fabricated in a CMOS 0.8m double-metal single-poly technology. Fig. 4 shows the microphotograph of the modulator chip. It occupies an active area of 0.48 mm and consumes 60 mW from a 5-V power supply. For testing purposes, the modulator chip has been attached to a two-layer PCB, which has been designed following the indications in [17]. The input is applied using the HP3341A single-ended sinusoidal signal source with an off-chip resistor (for V/I conversion) connected to the input pad and then to the on-chip current buffer. The output bit streams were captured with the HP82000 data system. Kaiser 20)-windowed 32768-pointFFT’swereperformedon eachof those bit streams using MATLAB [18]. 1224 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 Fig. 4. Microphotograph of the modulator. Fig. 5. Measured modulator output spectrum for a sinusoidal signal of 0 6 dB input level and 1.63 MHz frequency (6.67 MHz sampling frequency). 0 dB represents 6 50  A. Fig. 5 shows the measured modulator output spectrum for a sinusoidal input signal of 6 dB input level2and 1.63 MHz frequency—maximum frequency in the AM range—( 6dB at 1.63 MHz) with the sampling frequency being 6.67 MHz. A correct noise shaping is obtained. The presence of out-of-band spikes suggest that the quantization error is not a white noise. However, this behavior does not degrade the modulator performance. To demonstrate this, the harmonic distortion at the modulator output has been measured at the maximum AM sampling frequency of 6.67 MHz. The input signal consisted of two 7 dB tones at 1.62 MHz and 1.63 MHz. Fig. 6 shows the central part of the output spectrum. Two third-order intermodulation products appear at both sides of the signals with amplitudes of 69.6 dB and 67 dB respectively, which corresponds to an of 60 dB. This results in an IP of 23 dB, which is low enough for digital AM receivers. Fig. 7 shows several measured SNR versus input level curves obtained in a 10 kHz bandwidth (commercial AM bandwidth). The measurements were made with a single input tone centered at several AM frequencies. Note that, as a consequence of the larger oversampling, the best SNR peak in the AM bandwidth is 65 dB for a 6.67 MHz sampling frequency. 2InputlevelisdefinedastheinputsignalamplitudereferredtotheDACoutput level, 6 I = 6 50  A (= 0 dB in Fig. 5). Fig. 6. Measured intermodulation distortion. Fig. 7. Measured SNR versus input level for an input tone with different AM IF frequencies and B = 10 kHz. Table II summarizes the modulator performance when clocked at 2, 4, and 6.67 MHz for the conversion of commercial AM signals centered at 488, 976, and 1.63 MHz respectively. The DR is larger than 57 dB in all the frequency range, in accordance with the requirements of digital AM receivers. The modulator also operates correctly at clock frequencies aboveAMfrequencies.Asan illustration, Fig. 8 showsthe modulator output spectrum for a 6 dB at 3.8 MHz input tone when clocked at 16 MHz. Observe that, as a consequence of the sampling frequency increase, the settling error dominates the in-band error power, thus degrading the performance of the modulator. Finally, Fig. 9 compares measured and predicted results. In order to separate the effect of SI errors, the half-scale SNR (corresponding to a 6 dB input level signal) was obtained for different clock rates and a 50 kHz bandwidth. Note that, for clock frequencies below about 3 MHz, the SNR increases with at a rate of about 15 dB/octave, which corresponds to a dependence on as predicted in (7). This means that the quantization noise dominates the performance of the modulator. However, for clock frequencies above 3 MHz, the SNR increases with at a rate of only 3 dB/octave, which reflects a dependence on IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 8, AUGUST 2000 1225 TABLE II MEASURED PERFORMANCE OF THE MODULATOR Fig. 8. Measured modulator output spectrum for a 0 6 dB at 3.8 MHz input tone when clocked at 16 MHz. Fig. 9. Measured and theoretical Half-Scale SNR versus f obtained in a 50 kHz band centered at f = 4 . , and therefore, white noise is the dominant error source. Finally,for clockfrequenciesexceeding10MHz,thesettlingerror dominates and the noise power in the signal band increases very rapidly, as predicted by theory. Fig. 9 demonstrates that the dynamic range of the prototype modulator is limited by circuit noise, not by quantization noise. However,asshowninSectionIII,thermal noiseofmemorycells isbelowthe measurednoisefloor. Apossibleexplanationforthe noise increase may be digital switching noise which is coupled to sensitive nodes via the additional MOST capacitance, , connected between the substrate and the gate of the memory transistor (see Fig. 3). V. CONCLUSIONS A current-mode bandpass modulator has been designed in a CMOS 0.8m single-poly double-metal technology. The circuit has been realized using switched-current fully differential regulated-folded cascode cells. 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