IC design for spread spectrum communication exploiting chaos

IC design o sp ead spec um communica ion exploi ing chaos Manuel Delgado-Res i u o, Ma ias Li ian and Angel Rod iguez-Vhzquez Cen o Nacional de Mic oelec 6nica (CNM) Ed. CICA, A da. Reina Me cedes s/n 41012 - Se ille, SPAIN. Abs ac - This pape p esen s a 2.4pm CMOS IC p o o ype which includes a p og ammable chao ic gene a o and some in e ace ci cui y o chao ic en- c yp ion. I ealizes a membe o he amily o he ca- nonical Chua’s s a e equa ion. I exhibi s se e al bi u ca ion pa ame e s by changing a ew ex e nal bias cu en s and can be used o he chao ic enc yp- ion o audio signals. 1.In oduc ion This pape ollows a p e ious pape o he au- ho s in [l]. The e he undamen als o design chao ic oscilla o s using Gm-C echniques we e es ablished and a IC p o o ype o he Chua’s ci cui buil . I was able o gene a e a numbe o chao ic oscilla o s by he i s ime using a ully monoli hic con inuous ime IC. Howe e , i s con ollabili y was a he icky. Hence, i was nei he con enien o expe imen al demon- s a ion o chao ic phenomena no o chao ic enc yp- ion. This pape p esen s a new chao ic CMOS chip al- so in 2.4pm echnology. The new chip has much be - e con ollabili y han he p e ious. We p esen i s a chi ec u e and a numbe o measu emen s o illus- a e i s pe o mance. II.Chip A chi ec u e ses he ollowing blocks: Fig. 1 shows he chip a chi ec u e which comp is- A co e Gm-C chao ic oscilla o . A Gm-C e e ence in eg a o . Th ee ol age bu e s. As Fig. 1 illus a es, he chip has 14 pins g ouped 2 supply ol ages. 1 analog g ound. 3 con ol inpu s (low impedance). 2 uning pins. 3 unbu e ed ou pu pins (one pe s a e a i- 3 bu e ed ou pu pins (one pe s a e a iable). as ollows: able). As s a ed in [l], he design o he monoli hic Chua’ s oscilla o is educed o ansis o le el imple- men a ion o one single ansconduc ance ampli ie o g,, gain and a nonlinea ansconduc o . The ansconduc o uni has a olded-cascode s uc u e, a X Y Z Xbu Ybu Zbu ~~ FIGURE 1. Chip a chi ec u e. whose inpu s age p esen s a linea iza ion scheme h ough sou ce degene a ion [2] cha ac e ized by an ample ange o linea i y in he ol age-cu en con- e sion, low sys ema ic o se , and e y high ou pu esis ance. The ansconduc ance alue is con olled by he biasing cu en Icon , applied o pin can l. The nonlinea i y o he cha ac e is ics is less han 1 .O% e - o in he inpu ol age anging om -1.5 o 1.5 , assuming a symme ical biasing o +. 2.5~. Ob iously, p ope ope a ion o he ci cui implies ha he chao ic a ac o be comp ised inside his ange. The nonlinea ansconduc o has been imple- men ed ia he cascaded connec ion o a uni ans- conduc o and a cu en -mode PWL block, as explained in [l] and [3]. Fig.2(a) and (b) show he a ia ion o he nonlinea cha ac e is ics o di e en slopes so and s1 o he cen al and ou e pieces, e- spec i ely. They can be ex e nally con olled h ough biasing cu en s Icon 2 and Icon 3 applied o pins con z and con , . The alues o hese cu en s can be ega ded as he c yp og aphic key o he secu e com- munica ion scheme. III.Chip Measu emen s Figs.6 and 7 show a bi u ca ion sequence ob- ained by changing he biasing cu en Icon 2. A dou- ble sc oll is ob ained h ough a pe iod-doubling ou e o chaos. A Rossle -like chao ic a ac o and se e al pe iodic windows a e obse ed as well. Fig.3 and Fig.4 demons a e he easibili y o 0-7803-3073-0/96/$5 .OO O1996 IEEE 178 Nonlinea T ansconduc o D i ing-Poin Cha ac e is ic c) I .o .o ‘ii -3.0 11 11 1 I 11 I -2.5 -1.5 -0.5 0.5 1.5 2.5 Inpu Vol age (V) 0.5 ldi (a> 3 -3 Nonlinea T ansconduc o D i ing-Poin Cha ac e is ic -2.5 -1.5 -0.5 0.5 1.5 2.5 Inpu Vol age (V) 0.5 ldi FIGURE 2. Nonlinea T ansconduc o . Va ia ion o he PWL cha ac e is ics wi h: (a) he cen al slope, so (con ol a iable !con 2); and (b) he ou e slopes, s1 (con ol a iable 1cnn 3 chao ic synch oniza ion be ween wo o he manu ac- u ed IC p o o ypes. Fig.3(a) conside s a linea di u- sion coupling be ween equi alen s a e a iables o he wo chao ic oscilla o s [4]. I shows he phase plo s ob ained om a y-coupled expe imen al se -up, buil in p ac ice by inse ing an Ry linea esis o be- ween he y e minals o bo h p o o ypes (see Fig.1). I was ound ha whene e he coupling esis ance is Ry < 27k0, he (xl, x2) phase plo ollows a nea ly pe ec s aigh line, hus con i ming synch oniza ion in spi e o he chao ic beha io exhibi ed by he oscil- la o s, as he (xl, 21) phase plo illus a es. A simila se -up was buil by inse ing an R, linea esis o be- ween he x e minals o he oscilla o s, hus leading o an x-coupled sys em. In his case, ajec o ies o bo h ci cui s app oach each o he asymp o ically i R, < 745 k0, o he same in e nal con igu a ions as be o e. A z-coupled con igu a ion was also buil in he labo a o y, bu , in his case, he sys em exhibi s spo adic losses o synch oniza ion. Fig.T)(b) conside s a d i e- esponse scheme as o iginally p oposed by Peco a and Ca oll [4]. I shows he phase plo s ob ained om a x-d i e expe - imen al se -up, buil by inse ing a ol age bu e om he x e minal o he d i ing p o o ype o he same e minal a he ecei ing sys em. As can be seen om he (yl, y2) phase plo , nea ly ideal synch oniza- ion is ob ained. The same conclusion also applies when conside ing a y-d i e scheme, bu no o a z- (a) (b) FIGURE 3. (a) y-coupled synch oniza ion esul s. Ho . axis: xl. Ve . axis: xz a he op, z1 a he bo om. (b) -d i e synch oniza ion esul s. Ho . axis: yp Ve . axis: yz a he op, l a he bo om. d i e con igu a ion as p edic ed by heo y [4]. Fig.4 illus a es he pe o mance o he whole secu e com- munica ion scheme. Inpu signal (FigA(a)) consis s o a segmen o speech. The wo s -case signal o noise a io o he eco e ed signal (Fig.4(b)) is g ea e han +40dB ( his occu s a e y low equencies) wi h less han -0.2dB loss o he inpu signal powe . A highe equencies, he signal- o-noise a io ises up o +60dB, while e aining simila losses a he ecei e . As can be seen om Fig.4, he ansmi ed signal (Fig.4(c)) keeps no esemblance o he in o ma ion con en . 1V.Re e ences [ 11 A. Rod iguez-VBzquez and M. Delgado-Res i u- o: “CMOS Design o Chao ic Oscilla o s Using S a e Va iables: A Monoli hic Chua’s Ci cui ”. IEEE T ansac ions on Ci cui s and Sys ems II, [2] E K ummenache and N. Joehl: “A 4MHz CMOS Con inuous-Time Fil e wi h On-Chip Au oma ic Tunings”. IEEE J. Solid-s a e Ci - cui s, SC-23, pp. 750-758, 1988. [3] M. Delgado-Res i u o and A. Rod iguez-VBzqu- ez: “Swi ched-Cu en Chao ic Neu ons”. Elec- onics Le e s, Vo1.30, N.5, pp. 429-430. [4] M. Ogo zalek: “Taming Chaos--Pa I: Synch o- niza ion”. IEEE T ansac ions on Ci cui s and Sys ems I, Vol. 40, N.lO, pp. 693-699, Oc . 1993. V01.40, N.lO, pp. 596-613, Oc . 1993. Chao ic Enc yp ion -5.0 1 ‘ ,..- O.0ms 100.0ms 200.0ms Time (20msldi ) FIGURE 4. Audio T ansmission Sys em. 179 ni u: START 0.001 n 20.00 10.00 STOP PO 000 000 H HEW: 100 1-L ST: 44 6 sec RAF.GE' 1- ..O, T--lObBm JIV DIY s ~n 0.001 H 10 00 10.00 STOP 20 000.000 H R8h 100 H S1- 44 6 5cc RANGE. 8- 10. T- iOdBm (e) FIGURE 5. Expe imen al Lissajous igu es (p ojec ions on o he (x, y) and (x,z) planes), and powe spec a o : (a) Icon 2 = 1.0 PA ; (b) = 1.05 PA ; (c) Icon 2 = 1.125 PA ; (d) Icon 2 = 1.2 PA ;(e) Icon 2 = 1.35 PA. 180 A REF @REF lo 00 -10 00 ' dBm 1 [ ~- 1 I- DIY OIV STAili 0.001 Pi 10.00 20.00 STOP PO 000 000 Hi RBW: 10'2 HZ ST: 44.6 sec RANGC. 1- 10, T- -1OdOm oi OIV B an- 0 001 iz IO 00 30.00 STOP 20 000.000 WZ i~Bn: 100 h7 8'?:44.6 DEC UAhGF'2:: 10 'i-?OOH71 (i) FIGURE 6. Expe imen al Lissajous igu es (p ojec ions on o he (x, y) and (x,z) planes), and powe spec a o : (0 Zcon 2 = 1.52 pA ; (g) Zcon 2 = 1.67 pA ;(h) Zcon 2 = 1.7 pA ; (i) Zcon 2 = 1.912 pA ; (j) = 1.97 PA. 181