IC design for spread spectrum communication exploiting chaos

IC design for spread spectrum communication exploiting chaos Manuel Delgado-Restituto, Matias Lifian and Angel Rodriguez-Vhzquez Centro Nacional de Microelectr6nica (CNM) Ed. CICA, Avda. Reina Mercedes s/n 41012 - Seville, SPAIN. Abstract - This paper presents a 2.4pm CMOS IC prototype which includes a programmable chaotic generator and some interface circuitry for chaotic encryption. It realizes a member of the family of the canonical Chua’s state equation. It exhibits several bifurcation parameters by changing a few external bias currents and can be used for the chaotic encryption of audio signals. 1.Introduction This paper follows a previous paper of the authors in [l]. There the fundamentals to design chaotic oscillators using Gm-C techniques were established and a IC prototype of the Chua’s circuit built. It was able to generate a number of chaotic oscillators by the first time using a fully monolithic continuous time IC. However, its controllability was rather tricky. Hence, it was neither convenient for experimental demonstration of chaotic phenomena nor for chaotic encryption. This paper presents a new chaotic CMOS chip also in 2.4pm technology. The new chip has much better controllability than the previous. We present its architecture and a number of measurements to illustrate its performance. II.Chip Architecture ses the following blocks: Fig. 1 shows the chip architecture which compris- A core Gm-C chaotic oscillator. A Gm-C reference integrator. Three voltage buffers. As Fig. 1 illustrates, the chip has 14 pins grouped 2 supply voltages. 1 analog ground. 3 control inputs (low impedance). 2 tuning pins. 3 unbuffered output pins (one per state vari- 3 buffered output pins (one per state variable). as follows: able). As stated in [l], the design of the monolithic Chua’ s oscillator is reduced to transistor level implementation of one single transconductance amplifier of g,, gain and a nonlinear transconductor. The transconductor unit has a folded-cascode structure, a X Y Z Xbuf Ybuf Zbuf ~~ FIGURE 1. Chip architecture. whose input stage presents a linearization scheme through source degeneration [2] characterized by an ample range of linearity in the voltage-current conversion, low systematic offset, and very high output resistance. The transconductance value is controlled by the biasing current Icont, applied to pin cantl. The nonlinearity of the characteristics is less than 1 .O% error in the input voltage ranging from -1.5 to 1.5v, assuming a symmetrical biasing of +. 2.5~. Obviously, proper operation of the circuit implies that the chaotic attractor be comprised inside this range. The nonlinear transconductor has been implemented via the cascaded connection of a unit transconductor and a current-mode PWL block, as explained in [l] and [3]. Fig.2(a) and (b) show the variation of the nonlinear characteristics for different slopes so and s1 of the central and outer pieces, respectively. They can be externally controlled through biasing currents Icont2 and Icont3 applied to pins contz and cont, . The values of these currents can be regarded as the cryptographic key for the secure communication scheme. III.Chip Measurements Figs.6 and 7 show a biffurcation sequence obtained by changing the biasing current Icont2. A double scroll is obtained through a period-doubling route to chaos. A Rossler-like chaotic attractor and several periodic windows are observed as well. Fig.3 and Fig.4 demonstrate the feasibility of 0-7803-3073-0/96/$5 .OO O1996 IEEE 178 Nonlinear Transconductor Driving-Point Characteristic c) I .o .o ‘ii -3.0 11 11 1 I 11 I -2.5 -1.5 -0.5 0.5 1.5 2.5 Input Voltage (V) 0.5 ldiv (a> 3 -3 Nonlinear Transconductor Driving-Point Characteristic -2.5 -1.5 -0.5 0.5 1.5 2.5 Input Voltage (V) 0.5 ldiv FIGURE 2. Nonlinear Transconductor. Variation of the PWL characteristics with: (a) the central slope, so (control variable !cont2); and (b) the outer slopes, s1 (control variable 1cnnt3 chaotic synchronization between two of the manufactured IC prototypes. Fig.3(a) considers a linear diffusion coupling between equivalent state variables of the two chaotic oscillators [4]. It shows the phase plots obtained from a y-coupled experimental set-up, built in practice by inserting an Ry linear resistor between the y terminals of both prototypes (see Fig.1). It was found that whenever the coupling resistance is Ry < 27k0, the (xl, x2) phase plot follows a nearly perfect straight line, thus confirming synchronization in spite of the chaotic behavior exhibited by the oscillators, as the (xl, 21) phase plot illustrates. A similar set-up was built by inserting an R, linear resistor between the x terminals of the oscillators, thus leading to an x-coupled system. In this case, trajectories of both circuits approach each other asymptotically if R, < 745 k0, for the same internal configurations as before. A z-coupled configuration was also built in the laboratory, but, in this case, the system exhibits sporadic losses of synchronization. Fig.T)(b) considers a drive-response scheme as originally proposed by Pecora and Carroll [4]. It shows the phase plots obtained from a x-drive experimental set-up, built by inserting a voltage buffer from the x terminal of the driving prototype to the same terminal at the receiving system. As can be seen from the (yl, y2) phase plot, nearly ideal synchronization is obtained. The same conclusion also applies when considering a y-drive scheme, but not for a z- (a) (b) FIGURE 3. (a) y-coupled synchronization results. Hor. axis: xl. Vert. axis: xz at the top, z1 at the bottom. (b) r-drive synchronization results. Hor. axis: yp Vert. axis: yz at the top, rl at the bottom. drive configuration as predicted by theory [4]. Fig.4 illustrates the performance of the whole secure communication scheme. Input signal (FigA(a)) consists of a segment of speech. The worst-case signal to noise ratio of the recovered signal (Fig.4(b)) is greater than +40dB (this occurs at very low frequencies) with less than -0.2dB loss of the input signal power. At higher frequencies, the signal-to-noise ratio rises up to +60dB, while retaining similar losses at the receiver. As can be seen from Fig.4, the transmitted signal (Fig.4(c)) keeps no resemblance to the information content. 1V.References [ 11 A. Rodriguez-VBzquez and M. Delgado-Restitu- to: “CMOS Design of Chaotic Oscillators Using State Variables: A Monolithic Chua’s Circuit”. IEEE Transactions on Circuits and Systems II, [2] E Krummenacher and N. Joehl: “A 4MHz CMOS Continuous-Time Filter with On-Chip Automatic Tunings”. IEEE J. Solid-state Circuits, SC-23, pp. 750-758, 1988. [3] M. Delgado-Restituto and A. Rodriguez-VBzqu- ez: “Switched-Current Chaotic Neurons”. Electronics Letters, Vo1.30, N.5, pp. 429-430. [4] M. Ogorzalek: “Taming Chaos--Part I: Synchronization”. IEEE Transactions on Circuits and Systems I, Vol. 40, N.lO, pp. 693-699, Oct. 1993. V01.40, N.lO, pp. 596-613, Oct. 1993. Chaotic Encryption -5.0 1 ‘ f,..- O.0ms 100.0ms 200.0ms Time (20msldiv) FIGURE 4. Audio Transmission System. 179 niv u:v START 0.001 nr 20.00 10.00 STOP PO 000 000 Hr HEW: 100 1-L ST: 44 6 sec RAF.GE' 1- ..O, T--lObBm JIV DIY sr~nr 0.001 Hr 10 00 10.00 STOP 20 000.000 Hr R8h 100 Hr S1- 44 6 5cc RANGE. 8- 10. T- iOdBm (e) FIGURE 5. Experimental Lissajous figures (projections onto the (x, y) and (x,z) planes), and power spectra for: (a) Icont2 = 1.0 PA ; (b) = 1.05 PA ; (c) Icont2 = 1.125 PA ; (d) Icont2 = 1.2 PA ;(e) Iconr2 = 1.35 PA. 180 A REF @REF lo 00 -10 00 ' dBm 1 [ ~- 1 I- r DIY OIV STAili 0.001 Pi 10.00 20.00 STOP PO 000 000 Hi RBW: 10'2 HZ ST: 44.6 sec RANGC. 1- 10, T- -1OdOm oiv OIV Bran- 0 001 tiz IO 00 30.00 STOP 20 000.000 WZ i~Bn: 100 h7 8'?:44.6 DEC UAhGF'2:: 10 'i-?OOH71 (i) FIGURE 6. Experimental Lissajous figures (projections onto the (x, y) and (x,z) planes), and power spectra for: (0 Zcont2 = 1.52 pA ; (g) Zcont2 = 1.67 pA ;(h) Zcont2 = 1.7 pA ; (i) Zcont2 = 1.912 pA ; (j) = 1.97 PA. 181