On the design and characterization of femtoampere current-mode circuits

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 8, AUGUST 2003 1353 On he Design and Cha ac e iza ion o Fem oampe e Cu en -Mode Ci cui s Be nabé Lina es-Ba anco and Te esa Se ano-Go a edona Abs ac —In his pape , we show and alida e a eliable ci cui design echniquebasedonsou ce ol ageshi ing o cu en -mode signal p ocessing down o em oampe es. The echnique in ol es speci ic-cu en ex ac o s and loga i hmic cu en spli e s o ob aining on-chip subpicoampe e cu en s. I also uses a special on-chip saw oo h oscilla o o moni o and measu e cu en s down o a ew em oampe es. This way, subpicoampe e cu en s a e cha ac e ized wi hou d i ing hem o chip and equi ing expensi e ins umen a ion wi h complica ed low leakage se ups. A special cu en mi o is also in oduced o eliably eplica ing such low cu en s. As an example, a simple log-domain i s -o de low-pass il e is implemen ed ha uses a 100- F capaci o and a 3.5- A bias cu en o achie e a cu o equency o 0.5 Hz. A ech- nique o cha ac e izing noise a hese cu en s is also desc ibed and e i ied. Finally, ansis o misma ch measu emen s a e p o ided and discussed. Expe imen al measu emen s a e shown h oughou he pape , ob ained om p o o ypes ab ica ed in he AMS 0.35- m h ee-me al wo-poly s anda d CMOS p ocess. Index Te ms—Analog VLSI design, leakage cu en s, misma ch, noise, sub h eshold, ul alow cu en s, weak in e sion. I. INTRODUCTION HOW SMALL can we make he cu en in MOS ansis o s and s ill be able o build eliable ci cui s wi h hem? The smalles MOS ansis o cu en is limi ed by i s leakage cu - en . Fo example, in a ypical p esen -day submic on CMOS p ocess, he oom empe a u e e e se diode leakage cu en o he d ain o sou ce di usions o a minimum size ansis o is ypically a ound 10 aA (10 A). Howe e , his cu en is usually no he one ha limi s he bo om cu en ange o a MOS ansis o . Because o ion implan a ion o lowe ing he h eshold ol age o mode n CMOS echnologies, he e ec i e leakage cu en (i.e., o ) o minimum size MOS an- sis o s may be as la ge as 10 pA. Fo example, Fig. 1(b) shows he simula ed e sus cu es (wi h , V) o minimum size nMOS and pMOS ansis- o s [as seen in Fig. 1(a)] o a 0.35- m CMOS p ocess, using heco ne analysispa ame e sp o idedby hemanu ac u e .As can be seen, he wo s case co ne yields a minimum cu en o a ound 1 pA o a minimum size pMOS and mo e han 10 pA o a minimum size nMOS. Fo V (nMOS) o (pMOS), he MOS cu en has no eached he diode e e se cu en , yielding a Manusc ip ecei ed Feb ua y 4, 2002; e ised Ap il 10, 2003. This wo k was suppo ed in pa by Spanish MCyT unde P ojec s TIC-1999-0446-C02-02, FIT-070000-2001-0859, TIC-2000-0406-P4-05, TIC-2002-10878-E, and EU P ojec IST-2001-34124. The au ho s a e wi h he Ins i u o de Mic oelec ónica de Se illa, 41012 Se illa, Spain (e-mail: [email p o ec ed]). Digi al Objec Iden i ie 10.1109/JSSC.2003.814415 (a) (b) (c) Fig. 1. Typical mode n submic on CMOS nMOS and pMOS ansis o I e sus V cha ac e is ics. (a) Schema ic. (b) Co ne analysis simula ion. (c) Expe imen al measu emen s. much la ge o cu en . Fig. 1(c) shows wo expe imen ally measu ed e sus cu es. Cu e co esponds o am m nMOS ansis o . The minimum cu - 0018-9200/03$17.00 © 2003 IEEE 1354 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 8, AUGUST 2003 (a) (b) Fig. 2. Illus a ion o he sou ce ol age shi ing echnique. (a) Ci cui schema ic. (b) Co ne analysis simula ed I e sus V cha ac e is ics. en o se e al picoampe es is eached o mV. This is he leakage cu en in oduced by he pad p o ec ion diodes. Cu e co esponds o he pa allel o 120 ansis- o s and di iding he measu ed cu en by 120. This way, he pad diodes cu en is di ided by 120. As can be seen, he e is ansis o cu en well below V. In his pape , we will p o ide echniques o eliably ex- ploi ing MOS ansis o ope a ion down o a ew em oampe es, as well as measu emen and cha ac e iza ion echniques o such small cu en s. II. SOURCE VOLTAGE SHIFTING The undamen al me hod o exploi ing he comple e a ail- able cu en ange (down o he di usion diodes e e se leakage cu en s) is by ei he biasing he ga e ol agesbeyond he powe supply ails [as done in Fig. 1(c)] o by sligh ly shi ing he sou ce ol ages. Fo example, i o he ansis o s in Fig. 1 he sou ce ol ages a e connec ed o a ound 400 mV wi h espec o he powe supply ails [as shown in Fig. 2(a)], we eco e he comple e cu en ange ha he de ice physics allows us, as seen in he co ne analysis simula ion o Fig. 2(b). The co ne s wi h he highes leakage cu en (69 A) a e hose ob ained o high empe a u e (85 C). Howe e , i we can gua an ee oom empe a u e ope a ion, he limi ing cu en can be o he o de o 10 aA (10 A) o less.1Fo he CMOS p ocess used (AMS 1In he simula ions, he cu en esolu ion needs o be se acco dingly o such low alues. In ou simula ions, we se i o 10 A. Fig. 3. Speci ic cu en ex ac o ci cui . 0.35- m) he e e se biased di usion diodes’ leakage cu en densi y is es ima ed by he ound y o be a ound 0.02 A m a oom empe a u e. This cu en densi y has imp o ed up o a ac o o wo o h ee wi h espec o p e ious CMOS p ocesses o e he las decade,which is no much. Howe e ,minimumdi - usion sizes ha e been educed signi ican ly, om abou 6 m 6 m o a ypical 2- m p ocess o abou 1 m 1 m o a 0.35- m p ocess. Consequen ly, minimum size ansis o di u- sion diode leakage has imp o ed by abou a ac o o 100. Shi ing he sou ce ol age implies educing he a ailable ol age ange. Howe e , his is no a se e e p oblem o subpi- coampe e cu en -mode ci cui s. No e ha o such cu en s he ga e- o-sou ce ol ageisex emelysmall( woo h eehund eds o milli ol s). Shi ing he sou ce ol age also implies he need o p o iding on-chip ol age sou ces and . Howe e , he shi ed ol age alues a e no c i ical (as long as a minimum alue is gua an eed) and he cu en d i ing capabili y o hese on-chipsou cesisqui elow.Consequen ly, omnowon wewill no conside he implemen a ion o hese sou ces. The main d awbacks o ope a ing a e y low cu en le els a e ansis o noise and ansis o misma ch, which a e a con- sequence o ope a ing he MOS ansis o s in he sub h eshold egime [1]. Consequen ly, by ope a ing a subpicoampe e cu - en le els, we inhe i all he incon eniences o weak in e sion. Howe e , known weak in e sion noise models seem o be p e- se ed and ela i e cu en misma ch is supposed o s ay con- s an wi hin weak in e sion ope a ion. Expe imen al e idence o hese ac s will be shown in la e sec ions. III. ON-CHIP INVERSION-LEVEL-BASED CURRENT REFERENCES The p ocess o h eshold ol age adjus men in mode n CMOS p ocesses ende s signi ican a ia ions in he posi ion o he weak in e sion e sus exponen ial cu e [see Fig. 1(b) and Fig. 2(b)]. Consequen ly, biasing ansis o s deep inside he weak in e sion egion esul s in impo an a ia ions in he equi ed ol ages. Fu he mo e, when wo king below picoampe es, a sligh shi in ol age can u n he ansis o o o p oduce decades o a ia ion in he ope a ing cu en . The posi ion o he weak in e sion e sus exponen ial cu e changes signi ican ly no only om chip o chip (o wa e o wa e ) bu also wi h empe a u e [see Fig. 1(b) and Fig. 2(b)]. Fo una ely, i su e s li le a ia ions o LINARES-BARRANCO AND SERRANO-GOTARREDONA: DESIGN AND CHARACTERIZATION OF FEMPTOAMPERE CURRENT-MODE CIRCUITS 1355 (a) (b) Fig. 4. (a) Ci cui schema ic o gene ic cu en spli ing a io N . (b) Implemen ed cu en spli e . ansis o s wi hin he same die (assuming cons an empe a u e dis ibu ion). Consequen ly, he p ope way o p oceed is o design on-chip cu en e e ences ha a e based on ansis o in e sion le el [1], [3] and bias all ansis o s a p ede e mined in e sion le els. P esen -day MOS models ha p o ide con inuous analy ical unc ions o he ansis o cu en omweak os ongin e sion exploi he in e sion le el concep . The cu en is exp essed as he di e ence be ween o wa d and e e sed componen s (1) whe e is speci ic cu en , is he mal ol age, is sub h eshold slope ac o , and , a e he dimensionless in e sion le els o he o wa d and e e se cu en s. Te minal ol ages a e ela ed o he in e sion le els by (2) whe e is he pinch-o ol age and is a nonlinea unc ion. Fo he EKV model [1], i is a ma hema ical in e pola ion: (3) while o he ACM [3] model, i was de i ed om physical p in- ciples: (4) The speci ic cu en changes wi h p ocess pa ame e s and empe a u e, bu i a ci cui is designed so ha ansis o s op- e a e a p ede e mined in e sion le els and/o hen hese will emain independen o p ocess a ia ions and empe a u e. To achie e his, an on-chip speci ic cu en ex ac o ci cui is equi ed. Once is a ailable, ansis o s can be biased wi h scaled e sions o i , hus assu ing he desi ed in e sion le els. Fo weak in e sion ope a ion, needs no o be known wi h e y high p ecision. Since he e a e se e al decades o a ailable cu en ange, can usually be ex ac ed wi h up o a ac o o wo e o wi hou signi ican impac . In ou case, we used he ci cui shown in Fig. 3 [4]. This ci cui equi es he b anch o ope a e in s ong in e sion, he b anch in weak in e sion, and he b anch in mode a e in e sion. Fo he sizes in Fig. 3, i au obiases a . Since is in sa u a ion, i s e e se cu en can be neglec ed, esul ing in (5) whe e is ansis o -size independen . In ou case,we useda0.35- mCMOSp ocessanddesigned oha e a ypical alue o A, nA, and nA. Co ne 1356 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 8, AUGUST 2003 Fig. 5. Ve y low cu en -con olled saw oo h oscilla o o on-chip subpicoampe e cu en moni o ing. analysis simula ions e eal ha he maximum- o-minimum cu - en a io o hese alues is less han bu close o 2. IV. CURRENT SPLITTING The ci cui in Fig. 3 is capable o p o iding a e e ence cu - en in he o de o nanoampe es. I we wan o gene a e cu - en s well below picoampe es, we can use he cu en spli ing echnique [5], [6]. The ci cui in Fig. 4(a) illus a es his ech- nique. The ansis o s ha e a size a io o ei he , ,o . This way, he cu en p o- duced a he di e en ou pu b anches is p og essi ely di ided by a ac o o . In s anda d applica ions, his ci cui is usually used wi h , hus p o iding a se o bina y-weigh ed cu - en s, which can be con olled digi ally by means o swi ches o p oduce any combina ion o hem. In ou case, we a e in e es ed in ob aining e y low cu en s. Consequen ly, in o de o scale down quickly, we choose and selec only one o he ou pu b anches. The es o he b anches a e connec ed o a ol age sou ce p o iding a pa h o he cu en s, as shown in Fig. 4(b). The 3-bi digi al wo d selec s one ou pu b anch o connec o node . Since isa na u al numbe be ween 0 and 7, he ou pu cu en would be . Acco ding o Fig. 4(a), a spli e o equi es ansis o o be a uni ansis o , o be nine uni ansis o s, and o be uni ansis o s. To a oid oo much leakage cu - en because o such a high numbe o uni ansis o s, was app oxima ed o (one uni ansis o ). The e o e, consecu i e ou pu cu en s will no ha e an exac a io o 10, al hough close o 10, and we a e s ill able o scale down quickly o a ew em oampe es. V. ON-CHIP LOW-CURRENT SAWTOOTH OSCILLATOR Measu ing em oampe e cu en s o chip is a cumbe some and edious ask which equi es expensi e ins umen a ion and e y ca e ul wi ing and handling o a oid undesi ed pa asi ic leakage. To a oid all his, we designed a simple on-chip saw- oo h oscilla o d i en by a cu en ha se s i s equency o ope a ion. The oscilla o should keep ope a ing o cu en s as small as he di usion diodes’ e e se cu en s. Using such an oscilla o would allow us o ha e a easonably good es ima e o he cu en s we a e injec ing in o i . The ci cui is shown in Fig. 5. Inpu cu en discha ges capaci o , while an- sis o s and a e OFF and is ON. No e ha and ha e hei sou ce ol ages shi ed so ha when hei ga es Fig. 6. Saw oo h oscilla o in e ed inpu cu en s e sus measu ed slopes. I =1 nA and digi al con ol wo d w was se om 7 o 0. a econnec ed o andg ound, espec i ely, heydono d i e anycu en (only hei e e sedbiasedd aindi usiondiodecu - en s). As he capaci o ol age eaches , he ol age com- pa a o ou pu will go om low o high. The posi i e eedback h ough ansis o speeds his ansi ion up signi ican ly. A e a small delay p oduced by he h ee in e e s and capaci- o s and , ansis o is u ned OFF while goes ON, echa ging capaci o quickly o i s s a ing alue . This will make he compa a o ou pu ip back o low, which a e he in e e chain delay u ns again OFF and ON.A his poin , inpu cu en s a s o discha ge again . The capaci o ol age a is moni o ed h ough a high-speed analogbu e .Thissignalcanbeobse ed omou side he chip. The discha ge slope a is di ec ly p opo ional o he dis- cha ge cu en (6) A e measu ing his slope wi h a known e e ence cu en (p o- ided ex e nally), we can in e he alue o any in-chip cu en by compa ing bo h slopes. By combining he oscilla o o Fig. 5 wi h he cu en spli e in Fig. 4(b), we can p oduce and measu e ex emely small cu - en s. The e e ence cu en lowing in o he cu en spli e was se ex e nally o 1 nA. Ex a swi ches a e added so ha he spli e ou pu cu en can be d i en o chip and measu ed p ecisely (calib a ed). Fo he maximum cu en ( ), he spli e ou pu was 1.05 nA. This alue is used o de i e in (6). Consequen ly, once is known (i.e., he oscilla o is calib a ed), any in (6) can be in e ed by measu ing he co - esponding discha ging slope. Fig. 6 shows he in e ed cu en s e sus he measu ed slopes o he eigh possible alues o he spli e con ol wo d . The smalles in e ed cu en was 3.51 A, ob ained when se ing and . This cu - en alue includes he sum o all leakage cu en s a ailable a capaci o p oduced by he ci cui y o he oscilla o and he cu en spli e . Fig. 7 shows he oscilla o in e ed inpu cu en s when se ing he digi al con ol wo d cons an and equal o 3 while sweeping om 2 A o 30 pA. Fig. 8 LINARES-BARRANCO AND SERRANO-GOTARREDONA: DESIGN AND CHARACTERIZATION OF FEMPTOAMPERE CURRENT-MODE CIRCUITS 1357 Fig. 7. Saw oo h oscilla o in e ed cu en e sus I while se ing w cons an equal o 3. Fig. 8. Snapsho s o oscilla o o I =100 nA while he con ol digi al wo d w is main ained cons an se o 3 ( I =7 pA ) . shows one snapsho o wa e o m o an oscilla o inpu cu - en nA and he digi al con ol wo d o he cu en spli e se o . The measu ed slope o he oscilla o in his case is V/s. Acco ding o Fig. 6, his slope co esponds o an oscilla o inpu cu en o app oxima ely 7 pA which also co e- sponds o he measu emen shown in Fig. 7 o nA. VI. SUBPICOAMPERE CURRENT MIRRORS A undamen al building block o any cu en -mode signal p ocessing ci cui is he cu en mi o . Fig. 9(a) shows he schema ic o a con en ional simple nMOS cu en mi o . Simula ing i s inpu –ou pu cha ac e is ics by sweeping om 10 A o1 A while pe o ming co ne analysis e eals he esul s shown in Fig. 9(b) (d ain ol age o ou pu ansis o was connec ed o ). The wo s case minimum ope a ing cu en o his mi o is 15.6 pA, well abo e he wo s case e e se biased di usion diode cu en s. This is (a) (b) Fig. 9. Con en ional simple cu en mi o . (a) Schema ics. (b) Inpu –ou pu cu en cha ac e is ics co ne analysis. (a) (b) Fig. 10. New cu en mi o opology sui able o subpicoampe e cu en ope a ion. (a) Schema ics. (b) Inpu –ou pu cha ac e is ics co ne analysis. because ansis o s canno be u ned comple ely o . Shi ing he sou ce ol ages o his mi o does no sol e he p oblem because he ga e ol age canno go below he sou ce ol age o his opology. Using he opology in Fig. 10(a) allows he ga e ol age o adap below he shi ed sou ce ol ages. T ansis o s – implemen a ol age shi e ha makes he ga e ol age o one h eshold ol age below i s d ain. Pe o ming co ne analysis simula ions on his opology p o ides he esul s shown in Fig. 10(b). The high- empe a u e co ne s sa u a e a he di usion diodes leakage cu en s (69 A), while he o he s emain ully ope a i e down o 10 aA (10 A). 1358 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 8, AUGUST 2003 Fig. 11. Tes ing o subpicoampe e cu en mi o s using cu en spli e s and low cu en saw oo h oscilla o . In o de o expe imen ally es his cu en mi o opology, pMOS and nMOS e sions we e used in combina ion wi h he cu en spli e and he saw oo h oscilla o , as shown in Fig. 11. By se ing signal selec 1 high (and all o he s low) he cu en spli e ou pu is connec ed di ec ly o he saw oo h oscilla o . Se ing selec 2 high (and all o he s low) makes his cu en go h ough he wo subpicoampe e nMOS and pMOS cu en mi - o s. By se ing signal cal1 high (and all o he s low), while se - ing he spli e o i s maximum alue, we can measu e ex e - nally he maximum cu en p o ided by he spli e . This allows us o calib a e he slopes o he oscilla o when i is connec ed di ec ly o he spli e . By se ing cal2 high (and all o he s low), wi h he spli e a i s maximum alue, we calib a e he slopes o he case he wo cu en mi o s a e in he pa h. No e ha in (6) is di e en i he mi o s a e o a e no in he pa h. Fig.12shows heexpe imen al esul so hisnewsubpicoam- pe e cu en mi o opology. Fig. 12(a) shows he in e ed inpu cu en s in he saw oo h oscilla o e sus he measu ed slope o he wo abo e-men ioned si ua ions: when he cu en spli e is di ec ly connec ed o he inpu o he oscilla o [cu e ma ked wi h ci cles in Fig. 12(a)] and when he cu en goes h ough he combina ion o he nMOS and pMOS subpicoampe e cu - en mi o s [cu e ma ked wi h s a s in Fig. 12(a)]. F om he esul s shown in Fig. 12(a), he cu e in Fig. 12(b) can be in- e ed, which shows he cu en a he oscilla o when he cu - en spli e is connec ed di ec ly o he oscilla o [labelled Ics in Fig. 12(b)] e sus he inpu cu en in he oscilla o when he cu en om hecu en spli e goes h ough hecombina iono he nMOS and pMOS subpicoampe e cu en mi o s [labelled Icm in Fig. 12(b)]. This way, he cu e in Fig. 12(b) ep esen s he inpu cu en (Ics)–ou pu cu en (Icm) ela ion o he com- bina ion o he nMOS and pMOS subpicoampe e cu en mi - o s. Ano he ansis o opology app op ia e o subpicoampe e cu en p ocessing, because i implici ly uses sou ce ol age shi ing,was epo edelsewhe e[7]. This opologyadds he ea- u e o clamping he mi o inpu ol age, a he expense o in- c easing ci cui a ea and powe consump ion. VII. LOG-DOMAIN LOW-PASS FILTER WITH SUBHERTZ CUTOFF FREQUENCY A e y in e es ing applica ion o subpicoampe e cu - en -mode signal p ocessing is he capabili y o implemen ing ex emely high ime cons an ci cui s. To illus a e his, a con- en ional i s -o de log-domain CMOS il e was ab ica ed and es ed. The schema ic o he selec ed i s -o de sec ion (a) (b) Fig. 12. Expe imen al esul s o he subpicoampe e new cu en mi o opology. (a) Inpu cu en in e ed in he saw oo h oscilla o e sus measu ed slopes when he cu en spli e is connec ed o he oscilla o inpu and when he cu en goes h ough he nMOS and pMOS subpicoampe e cu en mi o s. (b) In e ed inpu –ou pu cu en beha io o he compound nMOS and pMOS subpicoampe e cu en mi o s. Fig. 13. Schema ic o i s -o de log-domain low-pass il e sec ion o subpicoampe e ope a ion. LINARES-BARRANCO AND SERRANO-GOTARREDONA: DESIGN AND CHARACTERIZATION OF FEMPTOAMPERE CURRENT-MODE CIRCUITS 1359 Fig. 14. Fab ica ed ci cui y o es o subpicoampe e log-domain low-pass il e . Fig. 15. Measu ed equency esponse o he log-domain low-pass il e o di e en I alues. is shown in Fig. 13 [8]. and a e cascode ansis o s o keeping he d ain ol ages o and equal. The low-pass il e ing unc ion is ealized by ansis o s and capaci o . Assuming all ansis o s in hei weak in e sion sa u a ion egion, he equa ions desc ibing he ci cui ope a ion a e (7) Assuming , (7) esul s in he ollowing ime domain di e en ial equa ion: (8) which desc ibes a i s o de low-pass il e wi h 3-dB cu o equency . Fo a 1-Hz cu o equency wi h pF, , and mV, he bias cu en should be A. Fig. 16. Measu ed 3-dB cu o equency o low-pass il e when se ing con ol wo d w =3 and sweeping I om 55 nA o 70 pA. Fig. 17. Measu ed spec al noise densi y a discha ging oscilla o capaci o . The log-domain low-pass il e o Fig. 13 wi h pF was ab ica ed in a 0.3- m CMOS p ocess oge he wi h an nMOS cu en spli e , a saw oo h oscilla o , and a se o subpicoampe e cu en mi o s, as shown in Fig. 14. 1360 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 8, AUGUST 2003 Fig. 18. Misma ch measu emen s o ansis o s o 30 di e en sizes in a 0.35-  m CMOS p ocess. Ve ical scale shows ela i e cu en misma ch s anda d de ia ion in pe cen . Ho izon al scale shows bias cu en . Cu en o he cu en spli e was supplied o chip, as well as , , and he wo 1-M esis o s. , , and we e adjus ed o make he dc alues and he low-pass ans e unc ion was measu ed om o . The se up in Fig. 14 allows us o con ol he alue o o he low-pass il e , while in e ing ha alue by means o he saw oo h oscilla o . Fig. 15 shows he measu ed low-pass il e equency esponse o se e al alues o . He e was se o 1 nA and he digi al con ol wo d changed om 1 o 5. The alues o he 3-dB cu o equency we e, espec i ely, 0.5, 0.7, 1.0, 3.5, and 25 Hz, while was in e ed o be 3.51 A, 6.25 A, 9.53 A, 77.8 A, and 1.24 pA (using he saw oo h oscilla o me hod o Sec ion V). When keeping cons an and changing om 55 nA down o 70 pA, he se o alues e sus o Fig. 16 we e measu ed. Figs. 15 and 16 we e no measu ed using a spec um/ne wo k analyze , because he equencies we e oo low. Ins ead, inpu and ou pu sinusoids we e di ec ly obse ed on an oscilloscope and he ou pu wa e o m ampli ude was manually measu ed as a unc ion o inpu equency. VIII. NOISE ESTIMATION I is possible o es ima e he noise p oduced by he subpicoampe e MOS ansis o s by simply obse ing he saw oo h oscilla o wa e o ms. Measu ing i s equency ji e is no a good way because i is p oduced no only by he inpu cu en noise bu also by he compa a o inpu equi alen noise. Howe e , i we look a he saw oo h oscilla o wa e only du ing he ime in e als ha capaci o is being discha ged, he ol age noise obse ed a he capaci o is p oduced by he inpu cu en noise and he analog bu e noise (see Fig. 8). Designing his bu e wi h su icien ly low noise, he noise obse ed a i s ou pu will be p oduced by he e y low cu en s discha ging capaci o . Na u ally, he ol age noise obse ed a he ou pu will be an in eg a ed e sion o he inpu cu en noise. Consequen ly, i he inpu cu en noise is whi e he mal noise, we should obse e a ( 20 dB/dec) ou pu ol age noise. To measu e he noise we p oceeded as ollows. The oscil- la o wa e o ms we e eco ded using a 16-bi analog- o-dig- i al con e e o se e al alues o he inpu cu en . The dis- cha ging slopes we e isola ed and i ed o s aigh lines. These lines we e sub ac ed om he discha ging slopes esul ing in ze o mean noise signals. These signals we e analyzed using Welch’s me hod o spec al es ima ion [10]. The esul s a e shown in Fig. 17 o capaci o discha ge cu en s equal o 7 A, 40 A, 600 A, and 7 pA. Na u ally, he noise spec al densi y could only be measu ed o equencies as low as he saw oo h equency i sel . E en mo e, o equencies close o he oscilla- ion equency, spec al con en es ima ion can be mis aken by LINARES-BARRANCO AND SERRANO-GOTARREDONA: DESIGN AND CHARACTERIZATION OF FEMPTOAMPERE CURRENT-MODE CIRCUITS 1361 dis o ion in he discha ging slope. As can be seen in Fig. 17, all ou noise measu emen s show he expec ed 20 dB/dec slope. Consequen ly, only whi e noise is being p oduced by he inpu cu en s o he obse ed equency anges. The he mal (whi e) noise powe spec al densi y expec ed o be p oduced by weak in e sion MOS ansis o s is [9] (9) whe e is he elec on cha ge. Since his cu en noise is in- eg a ed on capaci o du ing he discha ging amps, he ol age noise p esen a i s e minal will be (10) This heo e ical noise is also shown in Fig. 17, o each dis- cha ging cu en , wi h s aigh lines. As can be seen, he mea- su ed noise esembles easonably closely he heo e ically p e- dic ed noise. Flicke noise should become no iceable by lowe ing he op- e a ing equencies. Howe e , no e ha wi h his noise measu e- men me hod he lowes measu able equency is limi ed by he saw oo h signal equency, which is di ec ly p opo ional o he biasing cu en . The o al equi alen ga e ol age spec al noise densi y o a sub h eshold MOS is gi en by [2] (11) We can calcula e he ela ion be ween bias cu en and e- quency o which he mal and licke noise in sub h eshold a e equal: (12) Fo ou p ocess, Vm As, which means ha o a m m ansis o , licke and he mal noise densi ies be- come equal when (13) Consequen ly, o pA Hz, o A Hz, o A Hz, and o A Hz. No e ha all hese equencies all ou side he measu ed anges in Fig. 17, limi ed by he saw oo h wa e o m equencies. IX. MISMATCH CONSIDERATIONS Misma ch is a nonideal e ec ha becomes s onge o weak in e sion ope a ion. Howe e , p esen -day MOS ansis o models p edic ha ela i e cu en misma ch should end o s ay cons an when en e ing his bias egime [2]. We ha e pe o med misma ch measu emen s on de ices o 30 di e en sizes in a 0.35- m CMOS p ocess, o cu en s anging om s ong o weak in e sion. The cu en s we e measu ed using an ex e nal ins umen , hus limi ing he minimum measu able (a) (b) Fig. 19. Misma ch measu emen s o he cu en spli e in Fig. 4. (a) Measu ed inpu –ou pu cu en s o he op se en spli e ou pu s and he ou ab ica ed samples. (b) Compu ed ela i e s anda d de ia ion o he cu en s in (a). cu en . Fu he mo e, hey we e measu ed using a misma ch measu emen chip [11] whe e 1920 ansis o s (30 sizes 8 ows 8 columns) a e connec ed in pa allel and only one does no ha e i s ga e sho ed o i s sou ce. This implies ha 1920 d ain di usions a e in pa allel, con ibu ing a signi ican leakage cu en . The esul s can be seen in Fig. 18, whe e he minimum cu en o which misma ch could be measu ed was a ound 100 pA. Howe e , we can see he endency o misma ch becoming cons an as he ansis o s a e biased deepe inside weak in e sion. This is p edic ed by he heo y o mode n single-equa ion MOS models ha a e con inuous om s ong o weak in e sion [2], [3]. We migh expec ha , as we dec ease he ope a ing cu en below he picoampe es, he ela i e cu en misma ch should keep cons an . As an illus a i e example, we measu ed he ou ab ica ed samples o he cu en spli e in Fig. 4, using an o -chip