Nonlinear switched-current CMOS IC for random signal generation

Nonlinea swi ched-cu en CMOS IC o andom signal gene a ion M. Degaldo-Res i u o, F. Medei o, and A. Rod iguez- Vazquez Indexing e m: Swi ched-cu en ci cui s. Oscilla o s, Chaos signal gene a o s ~~ A nonlinea swi ched<u en ci cui is p esen ed ha implemen s a chao ic algo i hm o he gene a ion o b oadband, whi e analogue noise. The ci cui has been ab ica ed in a double-me al, singleply 1.6~ CMOS echnology and uses a no el, highly accu a e CMOS ci cui s a egy o ealise piecewise-linea cha ac e is ics in he cu en -mode domain. Measu emen s om he silicon p o o ype show a la spec um om DC o -30% o he clock equency, o a clock equency o 500kHz. In oduc ion: Du ing he las ew yea s, he s udy o chao ic beha iou displayed by nonlinea de e minis ic sys ems has a ac ed an ex ao dina y amoun o esea ch a en ion in many di e en scien i ic and echnologic disciplines. Today, he e is enewed enginee ing in e es in he opic, based on he expec a- ions c ea ed by ad anced signal p ocessing [l] and compu a ion pa adigms [2] ha ope a e in he con ex o chaos. In pa icula , de e minis ic chaos p o ides excellen algo i hms o designing imp o ed elec onic andom signal gene a o s o whi e [3] and colou ed [4] analogue noise, and o andom numbe ime se ies [5]. I is based on he ex eme sensi i i y o chao ic equa ions o ini ial condi ions, ha ende hei solu ions (consequen ly, he wa e o ms p o ided by elec onic ci cui s ha implemen hese equa ions) s ochas ic-like [6]. Few o he p e iously epo ed chao ic ci cui s a e ealisable in monoli hic o m. To he bes o ou knowledge, he only mono- li hic chaos-based noise gene a o epo ed in he li e a u e ealises a piecewise-linea (PWL) disc e e- ime sys em employing swi ched- capaci o (SC) ci cui echniques [3] which a e e y well sui ed o double-poly echnologies. The ci cui p oposed in his Le e uses swi ched-cu en (SI) echniques o compa ibili y wi h s anda d, single-poly VLSI echnologies. Measu emen s om a silicon p o- o ype show as e ope a ion han o he p e iously epo ed SC ci cui [3], wi h much less silicon a ea occupa ion. Also, he p o- posed ci cui is much simple han digi al noise gene a o s uc- u es composed o eedback shi egis e and lowpass il e s, and p o ides ully ape iodic wa e o ms. PWL unc ion scaled delay L I a b1557/11 Fig. 1 Analogue compu e cuncep o noi.se g ne u iun algo i hm. und nunl nea Junc ion ha uc e iwc a Analogue compu e b Nonlinea unc ion cha ac ens ic Noise gene a ion algo i hm and ci cui concep : Fig. la shows a block diag am o he p oposed ci cui , consis ing o a PWL unc- ion ans o ma ion, shown in Fig. Ib, whose ou pu is ed back o he inpu h ough a delay block wi h scaling pa ame e B. Thus, he ollowing PWL disc e e- ime sys em is implemen ed Bin +A x, < 0 n=0,1,2, ... (1) Bx,-A z,>O X"C1 = { whe e X, deno es he alue o x a he n h disc e e ime ins ance. We may conside eqn. 1 as a signal gene a o , p o iding a sequence (x.) o a gi en ini ial alue x,. Pa ame e B de e mines he dynamic p ope ies o he gene a ed signal (also called o bi o ajec o y), while pa ame e A ac s only as a scale ac o . Fo 1 s. B a 2, all s eady-s a e o bi s s a ing wi hin in e al J = [-A, A], a e ape iodic and emain con ined inside J; he sys em is in he 2190 EL ECTRO NI1 chao ic eghe. In his egime, sligh di e ences in he ini ial con- di ions a e g ea ly ampli ied in a ew i e a ions: he sys em has a sensi i e dependence on ini ial condi ions [6]. Also, o B > '(2). and wi h he excep ion o a coun able se o pe iodic poin s, any a bi a ily small subio e al inside J is eached ega dless o he ini ial poin : he map is e godic in he ange B E [d(2,2)]. Ac ually, o B nea 2, he dis ibu ion o i e a es is e y uni o m, allowing map exploi a ion o imp o ed andom numbe and whi e noise gene a o s. 4 4 Fig. 2 Scaled delay block and schema ic diag am o ealisa ion o PWL cha ac e is ic a Delay block b Schema ic diag am Conside implemen a ion o eqn. 1 in he cu en -mode domain, acco ding o he concep o Fig. la. The scaled delay ope a ion can be ealised as a cascade o wo ack-and-hold swi ched-cu - en s ages, ollowing he p oposal by Hughes e al. [7]. Fig. 2a shows schema ic diag ams o his block; pa ame e B is se by adjus ing he geome y ac o s and bias cu en o he second ack-and-hold s age. Fig. 2b, which consis s o wo cu en sou ces ( ealised in p ac ice by cu en mi o ou pu b anches), ou ansis o s and wo digi al in e e s, shows a concep ual sche- ma ic diag am o he ealisa ion o he PWL cha ac e is ics o Fig. Ib. T ansis o s Mcs. and Mcsp in Fig. 2b ope a e as a cu en - con olled-cu en -swi ch, and ansis o s M, and M, ope a e as ol age-con olled cu en swi ches. Any posi i e inpu cu en inc eases he inpu ol age, u ning he M, de ice on, and since bo h de ices in he cu en swi ch ha e he same ga e ol age, Mcs. o . Simul aneously, he ol age a he second in e e ou pu e ol es o he high logic s a e, u ning M, on and M, o . Thus, a cu en i, - A (ob ained by KCL a node A',) is di ec ed o he ou pu node h ough ansis o M,; he igh -hand sec ion o Fig. Ib is implemen ed in his manne . Simila ly, nega i e inpu cu en s u n Mcs. and M, on, so ha a cu en ih + A ci cula es h ough M, o he ou pu node. Because cu en disc imina ion in he p oposed ci cui elies on he in eg a ion unc ion pe - o med a he inpu node, esolu ion is e y high, and no in lu- enced by ansis o misma ches. Also, he eedback c ea ed by in e e IN, yields signi ican educ ion o he dead zone exhibi ed by he d i ing poin cha ac e is ics measu ed a he inpu node, ha is p opo ional o (VTm + lVml)/K, whe e VTn and VTp a e he h eshold ol ages o he ansis o s and K is he in e e DC gain. This is an appealing ea u e ha enables educ ion o in e - s age loading e o s caused by ini e equi alen MOS ansis o s Ea ly ol ages. CMOS p o o ype and expe imen al esul s: A p o o ype o he p o- posed ci cui has been ab ica ed in a 1.6~ CMOS doubleme al single-poly n-well echnology. In his p o o ype, he ou pu an- sis o o he second ack-and-hold s age is a bina y-weigh ed ansis o a ay, hus allowing digi al con ol o pa ame e B. Also, some ex a miscellaneous ci cui y has been added o enable es ing o he ou pu cu en and he possibili y o ei he open o close he eedback loop. Bias cu en I, o he delay s ages was se o 50 pA wi h A = 20d. Slopes o he cha ac e is ic, which co espond o he B pa ame e in eqn. 1, we e se o a alue sligh ly less han 2, o a oid di e gen o bi s ha may a ise as a consequence o non-ideal e ec s, such as clock eed h ough. To al a ea occupa ion, including miscellaneous ci cui y, amoun s o 0.096mm'. The cha ac e is ics o Fig. 3 ha e been measu ed in he open loop con igu a ion. Fig. 3a anges om -20 o 20pA and shows he ac ual global PWL cu en ans e cha ac e is ics displayed by he p o o ype. Measu ed de ia ion om linea i y in his ange is less han 0.2%. Fig. 36 shows a de ail o he global cha ac e is ics, ?S LETTERS 9 h Decembe 1993 Vol. 29 No. 25 -7 Au ho ized licensed use limi ed o: Uni e sidad de Se illa. Downloaded on Ma ch 26,2020 a 16:39:54 UTC om IEEE Xplo e. Res ic ions apply. Fig. 3 Measu ed cha ac e is ic o nonlinea block, and de ail o dis- c imina ion unc ion U Nonlinea block cha ac e is ic h Disc imina ion unc ion whe e he inpu cu en changes om -21 o 21pA. I is in ended o illus a e esolu ion achie ed in he cu en disc imina ion which amoun s o ew picoamps. Fig. 4 Measu ed cu en wa e o m and powe densi y spec um a Cu en wa e o m b Powe densi y spec um Fig. 4 illus a es he closed loop ope a ion o he p o o ype o a clock equency o 500kHz. Fig. 4a shows he measu ed cu en wa e o m, and Fig. 4b i s associa ed powe densi y spec um. The wa e o m o Fig. 4u shows ha appa en ly coinciden alues o i, esul in qui e di e en alues a e ew i e a ions, he eby con- i ming he expec ed unp edic able ea u e. Rega ding Fig. 46, de ailed measu emen s show a e y la spec um om DC up o -30% o he clock equency (de ia ion was less han 1 dB). I is use ul o compa e he pe o mance o his ci cui wi h ha o he SC ci cui epo ed p e iously o he same unc ion [3]. A ea occupa ion o he SI p o o ype is abou one o de o magni- ude smalle han o he SC p o o ype. Also. o hal he powe consump ion, he speed o he SI p o o ype is abou h ee imes g ea e han ha ob ained om he SC p o o ype. Ideas in he Le e a e di ec ly ex ensible o he design o cha- o ic neu al ci cui s, because signal agg ega ion is easily achie ed in cu en -mode, by simply oo ing componen cu en s o a com- mon node. In pa icula , he Be noulli ci cui can be ex ended in his way o implemen he chao ic neu on model p oposed in [2], which models expe imen ally obse ed pa e ns o squid gian axons. Also, he ci cui s a egy used o implemen he nonlinea unc ion can be ex ended o suppo a sys ema ic app oach o high-accu acy unc ion gene a ion in he cu en domain. Such ex ensions will be epo ed in sepa a e pape s. 0 IEE 1993 Elec onics Le e s Online No: 19Y314ZY M. Degaldo-Res i u o, F. Medei o and A. Rod iguez-Vbzquc (Cen o Na ional de Mic oele onica-Uni e sidad de Se illu, Edi icio CICA. (7 Ta @ s/n, 4/012-Se illa, Spain) Re e ences 1 OPPENHEIM. A. ., WORNELL. G.W , ISABELLE. s H , and C!!DMO, K M : ‘Signal p ocessing in he con ex o chao ic signals’. P oc. 1992 In . Con . on Acous ics, Speech and Signal P ocessing IV, 1992, pp. 117-120 AIHARA. K , TAKABE. T., and TOYODA, M.: ’Chao ic neu al ne wo ks’, Phys. Le . A, 1990, 144, pp. 333-340 3 RODRIGUEZ-V~ZQUEZ, A., and DELGADO-RESTITUTO. M.: ‘Swi ched capaci o b oadband noise gene a o o CMOS VLSI’. Elec on. Le ., 1991, 27, pp. 1913-1915 4 MURCH. A.R., and BATES, R.H.T.: ‘Colo ed noise gene a ion h ough de e minis ic chaos’, IE€€ T ans., 1990, CAS-37, pp. 608~-6l3 5 BERNSTEIN. G.M , and LIEBERMAN. M.A : ‘Secu e andom numbe gene a ion using chao ic ci cui s’, IEEE T uns., 1990, CAS-37, pp. 1157-1 I64 I Sep emb 1993 2 6 DEVANEY. R.L.: ‘An in oduc ion o chao ic dynamical sys ems’ (Benjamid Cummings, 1986) 7 HUGHES. I B., MACBETH. I.C, and PATIULLO, D.M.: ‘Swi ched cu en il e s’, I€€ P oc. G, 1990, 137. (2), pp. 156162 Se ling ime educ ion echnique o high speed DACs 0. Kim. G. Kim and W. Kim Indexing 1e m. : Digi d o unulogunu on e sion, In eg a ed ci cui s The inging mechanism o he high impedance ou pu node was analysed. To educe his inging, a new compensa ion ci cui was de eloped and implemen ed in a s anda d CMOS p ocess. This ci cui can be p og ammed o co e a ange o pa ame e s. I is e ec i e in minimising he se ling ime o a DAC. In oduc ion: The e is an e e -inc easing need o monoli hic dig- i al o analogue con e o s (DACs) ha ha e a esolu ion ange o 8 - lobi s. The segmen a ion a chi ec u e wi h cu en ou pu [I] is widely used o ob ain bo h high speed and high esolu ion using a s anda d CMOS echnology. In his a chi ec u e, he ou pu impedance needs o be high o ob ain good linea i y. This high ou pu impedance coupled wi h he induc ance o he packaging p oduces pa asi ic poles in he ans e unc ion. These poles lead o inging a he ou pu node and an inc ease in he se ling ime. The inging mechanism was analysed and a new ou pu com- pensa ion ci cui was de eloped. This ci cui e ec i ely elimina es he inging a he ou pu node. VI + +j&F{RL VO + j887/11 Fig. 1 Equi ulen ci cui o DAC ou pu sec ion ModeNing q ou pu pad: Fig. la shows he equi alen ci cui o a DAC ou pu sec ion. Node i is he in e nal node o he de ice. Node o is he ex e nal node like ha on he p in ed ci cui boa d. R, is he ou pu esis ance o he de ice. C, is he equi alen capac- i ance associa ed wi h node i which includes he pa asi ic capaci- ance o he cu en swi ch ou pu , me al layou and bonding pad. Lp is he pa asi ic induc ance be ween node i and o [2]. I com- p ises he pa asi ic induc ance o a bonding wi e and he lead ame o he package. C, is he pa asi ic capaci ance a node U, and R, is he e mina ion esis o . The e ec i e alue o R, is 37.59 when he ou pu node is doubly e mina ed wi h 759. Ideally, R, is m, C, and L, a e 0. The s ep esponse a node o is gi en by whe e T = R,C,. F om his, he wo s case se ling ime o wi hin 1i2 LSE o he a ge alue is gi en by Yo = IRL(1 -e-+) (1) T,,,, = (n + 1)Tln2 (2) whe e n is he esolu ion o he de ice. I C, and L, a e included, he ans e impedance Z(s) becomes (3) I R, >> R, and C, >> C,, The poles a e ELECTRONICS LETTERS 9 h Decembe 1993 Vol. 29 No. 25 2191 Au ho ized licensed use limi ed o: Uni e sidad de Se illa. Downloaded on Ma ch 26,2020 a 16:39:54 UTC om IEEE Xplo e. Res ic ions apply.