Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time ΣΔ Modulators With NRZ DAC

Effect of Clock Jitter Error on the Performance Degradation of Multi-bit Continuous-Time Σ∆ Modulators With NRZ DAC R. Tortosa, J.M. de la Rosa, A. Rodríguez-Vázquez and F.V. Fernández Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC), Ed. CNM-CICA, Av. Reina Mercedes s/n, 41012 Sevilla, SPAIN. Phone: +34955056666, Fax: +34955056686, E-mail: {tortosa|jrosa|angel|pacov}@imse.cnm.es Abstract - This paper analyses the effect of the clock jitter error in multi-bit continuous-time Σ∆ modulators with non-return-to-zero feedback waveform. Derived expressions show that the jitter-induced noise power can be separated into two main components: one that depends on the modulator loop filter transfer function and the other one due to the input signal parameters, i.e amplitude and frequency. The latter component, not considered in previous approaches, allows us to accurately predict the resolution loss caused by jitter, showing effects not taken into account up to now in literature which are specially critical in broadband telecom applications. Moreover, the use of state-space formulation makes the analysis quite general and applicable to either cascade or single-loop architectures. Time-domain simulations of several modulator topologies intended for VDSL application are given to validate the presented analysis. † I. INTRODUCTION Continuous-Time (CT) Sigma-Delta Modulators (Σ∆Μs) are good candidates for the implementation of Analog-to-Digital Converters (ADCs) in broadband communication systems. In addition to offer an intrinsic antialiasing filtering, these modulators provide potentially higher sampling rates with lower power consumption than their Discrete-Time (DT) counterparts [1][2]. However, CT Σ∆Μs are more sensitive than DT Σ∆Μs to several circuit non idealities. One of their major degrading factors, especially in high-speed applications, is due to uncertainties in the clock-signal edges, commonly referred to as clock jitter [1]. As sampling rates increase, clock jitter is becoming an ever-important consideration for the design of CT Σ∆Ms. In fact, this error has been object of several studies reported in open literature [1][3]-[7]. Most of them were carried out considering Σ∆M architectures with an internal single-bit quantizer and a Return-to-Zero (RZ) DAC. However, multi-bit quantization has been used in most silicon prototypes achieving medium-high resolutions ( ) within high signal bandwidths ( ) [8]-[10]. The combined used of high-order ( ) single-loop architectures with multi-bit ( ) quantization allows to reduce the oversampling ratio (normally ) while guaranteeing stability and robustness with respect to circuit parameter tolerances − the latter being a very critical error in CT Σ∆Ms [1][2]. In addition to improve resolution, multi-bit quantization can reduce the sensitivity of CT Σ∆Ms to clock jitter if a Non-Return-to-Zero (NRZ) feedback waveform is used in the DAC [9]. Therefore, its study is needed in order to optimize the modulator performance in terms of sensitivity to jitter error. The analysis of clock jitter in CT Σ∆Ms considering a NRZ feedback waveform is mathematically more complex than using a RZ pulse shaping. This is the reason why, in most cases, designers resort to semi-empirical estimations based on simulation results and consider a white-noise model for the jitter error [1][5][9]. To the best of the authors’ knowledge, only the work in [7] takes into account the effect of the modulator loop filter transfer function on the in-band jitter noise power of CT Σ∆Μs with NRZ DAC. However, the analysis in [7] does not consider the effect of input signal for the sake of simplicity. This paper analyzes the effect of signal-dependent clock jitter in multi-bit CT Σ∆Ms with NRZ embedded DAC. State-space formulation [11] is used to derive closed-form relations among jitter error, sampling frequency, modulator specifications (resolution and signal bandwidth), circuit topology (loop filter transfer function and number of bits of the internal quantizer) and input signal parameters (amplitude and frequency). The results of this study show effects not considered in previous approaches which might become critical in mediumand high-frequency applications. In addition, the use of the state-space formulation allows for the generalization of the analysis, being applicable to any kind of CT Σ∆Ms considering either cascade or single-loop architectures. As an illustration several modulators using either single-loop or cascaded topologies, designed for VDSL, are simulated to demonstrate the theoretical predictions. †. This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contracts TEC2004-01752/MIC and TIC2003-02355. 11-14 bit 1-15 MHz 3rd-4th order 3-6 bit 12< II. MODELING THE CLOCK JITTER ERROR IN NRZ CT Σ∆Ms Fig.1 shows the conceptual block diagram of a single-loop CT Σ∆M. The loop filter is CT and the sampling operation is realized before quantization instead of at the modulator input as done in the case of DT Σ∆Ms. Thus, the output signal, †† , is DT, the input signal, , is CT and a DT-to-CT transformation is implemented by the DAC to create the CT feedback signal, . Therefore, there are two clocked building blocks subject to jitter error: the sampler and the DAC. The error introduced through the sampling process is reduced by the loop gain and shaped in the same way as the quantization noise and hence, its effect can be neglected. On the contrary, the jitter error associated to the DAC directly adds with the input signal, thus increasing the in-band noise power and degrading the modulator performance. Traditionally, RZ feedback DACs have been used in CT Σ∆ Ms in order to overcome inter-symbol interference due to unequal rising and falling edges of the feedback DAC waveform. However, a multi-bit RZ DAC is more sensitive to clock jitter than a multi-bit NRZ DAC [9]. This is illustrated in Fig.2 by showing the arbitrary output feedback waveform ††† of a multi-bit DAC considering both a NRZ and a RZ pulse shaping with a 0.5 duty cycle. Note that, as the output signal ( ) of RZ DAC goes back to zero at each clock cycle, signal transitions ( ) will be larger than in the case of NRZ DACs ( ). Furthermore, increasing the number of bits of the quantizer and DAC reduces significantly the signal transitions in the case of NRZ DAC and hence, lower amounts of charge ( ) are loss during clock transitions as a consequence of the time uncertainty, . However, in a RZ DAC this reduction is practically non-existent. Note from Fig.2 that the DAC output waveform with jitter can be seen as the sum of an unjittered output waveform and a stream of pulses with amplitude and width − often referred to as jitter error sequence [1]. In the case of a NRZ DAC, the jitter error sequence can be related to the modulator output signal using the following relationship [12]: (1) where is the sampling period. Assuming that the input signal and the quantization error are uncorrelated and that is a Gaussian random process with zero mean and standard deviation , the power of the jitter error signal can be written as: (2) where , stands for the mathematical expectation [13] and is the shaped quantization noise, given by: (3) where represents the quantization Noise Transfer Function and is the quantization error − assumed to be a white noise source. Considering a sinewave input signal of amplitude and angular frequency , can be simplified as: (4) and hence, (5) The expectation value of can be derived from (3) giving: ††. In order to simplify the notation, is written as with being the sampling period. †††. A current-mode DAC is assumed in this example. Fig. 1: Conceptual block diagram of a single-loop CT Σ∆M. − + Loop Filter DAC Gs() xt() yt() yn() yn() ynT s () yn() T s xt() yt() I DAC ∆I DAC n() ∆Tn() Time (a) T s I DAC Time ∆I DAC n() ∆Tn() (b) T s Fig. 2: Feedback DAC pulse shaping. (a) RZ DAC. (b) NRZ DAC. I DAC I DAC n() I DAC n()≡∆ I DAC n() I DAC n() I DAC n1–()–≡∆ Qn() I DAC n()∆Tn()⋅∆≅∆ ∆Tn() I DAC n()∆∆Tn() εn() yn() yn 1–()–() ∆Tn() T s --------------- = T s ∆Tn() σ ∆T P ε Eεn() 2 {} σ 2∆T T s 2 ------------ Eyn() yn 1–()–[] 2 {}≅== σ 2∆T T s 2 ------------ E∆x n () 2 {}Eqn() qn 1–()–() 2 {}+()≅ ∆x n xn() xn 1–()–[]≡E.{} qn() qz() N TF z()ez()= N TF z() ez() Aω i 2πf i =∆x n ∆x n td dxt() tnT s = T s ⋅≅ Aω i T s ω i n1–()T s ()cos= E∆x n () 2    = T s 2 A 2 ω i 2 Eω i n1–()T s ()cos() 2    T s 2 A 2 ω i 2 2 ------------------- == ∆q n qn() qn 1–()–[]≡ (6) where and are the full-scale and the internal number of bits of the quantizer, respectively. From (2), (5) and (6), we obtain: (7) where is the sampling frequency. In some modulator topologies, the integration in (7) may become mathematically too complex, thus requiring the use of numerical solving methods. This can be simplified if the state-space formulation is used to derive as shown in next section. III. STATE-SPACE FORMULATION Fig.3 shows the state-space representation of , which can be described by the following finite difference equations [13]: (8) where is the state matrix, is the state vector, and are vectors and is the order of . Equation system (8) can be solved recursively to find the relation between the initial state ( ), previous input ( ), present input ( ) and output ( ) of the system [13]. This gives: (9) Considering that for , and assuming , it can be shown from (9) that: (10) Diagonalizing and considering that the system in Fig.3 is stable, the expression in (10) can be re-written as: (11) where are the eigenvalues of and and are respectively the elements of and , with being the matrix of the eigenvectors of . Using a similar procedure, it can be shown that: (12) Taking into account that ,and that , the value of can be derived from (11) and (12) as: (13) where (14) Replacing (6) with (13) in (7) and assuming that the jitter noise is an additive noise source at the input of the modulator, the Signal-to-Noise Ratio (SNR) dominated by jitter can be written as: (15) where is the signal bandwidth. Assuming that the jitter noise and the quantization noise are not correlated, their powers can be added and the total , considering both noise sources is: E∆q n () 2    EZ 1– 1z 1– –()N TF z()ez()[]() 2    == X FS 2 12π2 B 1–() 2 -------------------------------- 1e jω– –()N TF e jω– () 2 ωd 0 π ∫ = X FS B P ε σ ∆T T s ---------   2 A 2 ω i 2 2f s 2 -------------   +⋅≅ X FS 2 12π2 B 1–() 2 -------------------------------- 1e jω– –()N TF e jω– () 2 ωd 0 π ∫     + f s 1T s ⁄≡ E∆q n () 2 [] Fig. 3: State-space representation of N TF (z). en() qn() p 0 g 0 vn 1+() 0 vn() 0 F 0 z 1– N TF z() vn 1+() 0 F 0 vn() 0 p 0 en()⋅+⋅= qn() g 0 T vn() 0 en()+⋅= F 0 vn() 0 L1× p 0 g 0 L1×L N TF vn 0 () 0 ek() en() qn() qn() g 0 T F 0 nn 0 – vn 0 () 0 +⋅⋅= g 0 T F 0 n1– k– p 0 ek() en()+⋅⋅⋅ k0= n1– ∑ + Eek()ej(){}0= kj≠ vn 0 () 0 0= Eq 2 n(){}Ee 2 n(){}1+(= g 0 T F 0 n1– k– p 0 ⋅⋅[] 2 ) k0= n1– ∑ + F 0 Eqn() 2 {}Een() 2 {}1–(= g k p k g j p j λ k 1– λ j 1– 1λ k 1– λ j 1– – --------------------------) j1= L ∑ k1= L ∑ – λ i F 0 g i p i g T g 0 T T⋅= p T 1– p 0 ⋅=T F 0 Eqn()qn 1–(){}= Een() 2 {}g T p⋅g k p k g j p j λ k 1– 1λ k 1– λ j 1– – -------------------------- j1= L ∑ k1= L ∑ –     = Een() 2 {}= X FS 2 12 2 B 1–() 2 ⋅[]⁄=Eqn()() 2 {}= Eqn1–()() 2 {}=E∆q n () 2 [] E∆q n () 2    2Eqn()() 2 {}Eqn()qn 1–(){}()–[]= X FS 2 62 B 1–() 2 --------------------------ψgpλL,,,()⋅= ψgpλL,,,()1g T p⋅–+= g k p k g j p j λ k 1– λ k 1– λ j 1– – 1λ k 1– λ j 1– – ------------------------------- j1= L ∑ k1= L ∑ + SNR j A 2 2⁄ B w σ ∆T ()⋅ 2 A 2 ω i 2 f s -------------X FS 2 f s ⋅ 32 B 1–() 2 --------------------------ψgpλL,,,()+⋅ ------------------------------------------------------------------------------------------------------------- = B w SNR (16) where and are the jitter and quantization in-band noise powers, respectively given by: (17) Note that in is multiplied by a factor that is the sum of two terms: one depending on the input signal parameters ( and ) and the other one which is a function of the modulator topology parameters ( , , ). The first term decreases with while the second term increases with . This is illustrated in Fig.4 where the two terms in brackets in (17) are plotted versus for a 5-bit 3rd-order single-loop CT Σ∆M with . Note that there is an optimum value of , , that minimizes the in-band jitter noise power and hence, maximizes †††† . Thus, using (17) as a figure of merit in multi-bit CT Σ∆Ms with NRZ DAC in which jitter is the main limiting factor, the modulator performance can be optimized for given specifications in terms of loop filter parameters, sampling frequency and the number of bits of the internal quantizer. IV. COMPARISON WITH PREVIOUS APPROACHES The analysis in this paper presents a new way of quantifying the amplification effect of the loop filter through the calculation of instead of using integration as in previous approaches. Using (15) as a figure of merit, the resolution of those modulators limited by clock jitter can be improved by modifying the noise shaping characteristics in order to reduce the in-band jitter noise power. Another important part of the analysis described in this paper is the inclusion of the influence that the input signal has on the jitter sensitivity of the modulator. This has not been considered in any previous analysis of CT Σ∆Μs, even though it may become the dominant factor as it will be shown in Section V. Implications of the latter aspect are further explored next. Assuming that is dominated by the signal-dependent term, and that , the maximum achievable resolution in a CT Σ∆M with clock jitter can be derived from (15), giving: (18) where is the oversampling ratio. Note that (18) is the same relation as that one obtained in DT Σ∆Ms [14]. What is expressed in this relation is a simple idea: any converter (not only those based in Σ∆ modulation) clocked with an imperfect signal cannot be better than an ideal sampler clocked with the same signal. In DT Σ∆Ms, this fact manifests itself through the input sampler, whereas in CT Σ∆Ms it is introduced by the feedback DAC. The fundamental limit shown in (18) is valid for either single loop or cascade modulators, since jitter-induced noise introduced in the first stage is not affected by latter stages which only process quantization error. This is also valid for any type of loop filter, since (18) is independent of the particular loop filter. Note that in those cases where the dominant factor in (15) is the modulator dependent term, the maximum achievable is lower than the value given by (18). That is generally the case in those modulators that use single bit quantization, where, due to the much larger quantization step , is the dominant factor. To illustrate this point, let us consider the single-bit 2nd-order CT Σ∆M shown in Fig.5, with an input signal with frequency, , and an amplitude of 80% of the reference level, with and . In this case, the modulator dependent term is more than one thousand times higher than the signal-dependent term. In other words, jitter sensitivity in this modulator is completely dominated by , making jitter-induced noise power practically independent of the input signal. Under these conditions, the general equations derived in this paper provide similar predictions to those given by other expressions reported in literature, obtained for single ††††. The values of for are shown in Fig.4. SNR A 2 2⁄ P εb P Qb + ------------------------- = P εb P Qb P εb 2B w σ ∆T () 2 A 2 ω in 2 2f s ---------------X FS 2 f s 62 B 1–() 2 --------------------------ψgpλL,,,()⋅+= P Qb X FS 2 6f s 2 B 1–() 2 ------------------------------N TF f() 2 fd 0 B w ∫ = σ ∆T () 2 P εb Aω i BX FS ψgpλL,,,() f s f s 120 140 160 180 200 220 240 260 280 300 0 0.5 1 1.5 2 2.5 x 10 7 f s (MHz) V2·Hz Modulator-dependent term Input-dependent term Jitter amplification factor λ 0.22+j0.55 0.22-j0.55 -0.79 = p 0.66-j0.39 0.66+j0.39 -4.464 = g 0.74 0.74 0.87 = F ig. 4: Jitter components vs. for a 5-bit 3rd order CT Σ∆ M f s Jitter amplification factor Modulator-dependent term Signal-dependent term f s f i B w 20MHz== f s f sop 170MHz= SNR g i p i and λ i , f s f sop 170MHz== E∆q n () 2 [] SNR j f i B w = SNR MAX 10 M 4π 2 σ ∆T 2 B w 2 --------------------------    log= Mf s 2B w ()⁄≡ SNR ∆E∆q n () 2 [] 1 T s s k in 1 T s s k 1 DAC k 2 k 3 Fig. 5: Block diagram of a single-bit 2nd-order CT Σ∆M. k in 14k 1 ;⁄14k 2 1k 3 ;38⁄==;⁄==() f i B w = f s 40MHz= M64= E∆q n () 2 [] bit quantization [3]: (19) As an illustration, Fig.6 compares (15), (16) and (19) with simulation results of the modulator in Fig.5. Predictions of equations (15) and (19) are indeed very similar and, in the area where jitter dominates the resolution, close to the simulated values. The fundamental limit imposed by (18) is also shown in Fig.6, and it is clear that, in this case, it is not a limiting factor. However, considering the more general case of multi-bit CT Σ∆Ms which are not dominated by either the modulator-dependent term or the signal-dependent term, expressions derived in this paper should be used instead of (18) and (19). In case that the modulator-dependent term dominates the signal-dependent term, predictions given by (15) and (16) will approach those given in [7]. However the work in [7] does not take into account the impact of signal-dependent jitter term, which can be very critical in broadband applications as demonstrated in the next section. V. SIMULATION RESULTS: APPLICATION TO VDSL The presented study has been validated through time-domain behavioural simulation using SIMSIDES, a SIMULINK-based simulator for Σ∆Ms [15]. Fig.7 shows the multi-bit NRZ CT Σ∆Ms under study. Fig.7(a) is a 3rd-order single-loop and Fig.7(b) is a cascaded 2-1 topology. In both architectures, feed-forward stabilization is used and a feedback coefficient is used to move one of the poles to an optimum position [16]. The modulators were synthesized to handle signals within for VDSL application. Three different cases are considered: •CT Σ∆M1: Fig.7(a), and •CT Σ∆M2: Fig.7(a), and •CTΣ∆M3: Fig.7(b), and where and are respectively the number of bits of the internal quantizer in the firstand secondstage in Fig.7(b). Table 1 shows the values of the loop-filter coefficients ( ) as well as the position of the poles and Table 2 shows the values of for the three cases mentioned above. Fig.8 shows several simulated output spectra of cases CT Σ∆M1 (Fig.8(a)) and CT Σ∆M2 (Fig.8(b)) corresponding to different values of and . Note that in Fig.8(a), the in-band noise power does not depend on as predicted by [7]. However, as increases from to , the modulator-dependent term in (15) decreases and hence, the in-band noise is dominated by the signal-dependent term as illustrated in Fig.8(b). This effect is better shown in Fig.9, where the of the modulaSNR jitter 10 1 16Mσ ∆T 2 B w 2 -----------------------------    log= 0 510 15 20 25 30 66 68 70 72 74 76 78 80 Clock jitter standard deviation σ ∆ T (ps) SNR (dB) 015 30 100 105 110 115 SNR Limit, Equation (30) Equation (29) Equation (31), [3] Equation (26) Simulated [7] Quantization error-dominated Jitter-dominated Fig. 6: Comparison of theory and simulations for the modulator of Fig.5. (18) (16) (19) (15) k r B w 20MHz= f s 400MHz= B 2= f s 160MHz= B 5= f s 160MHz= B 1 B 2 5== B 1 B 2 Fig. 7: Multi-bit NRZ CT Σ∆Ms under study. (a) 3rd-order single-loop architecture. (b) Cascaded 2-1 architecture. k in k fb 1 T s s k g2 1 T s s k g3 k g1 k r 1 T s s k ff1 k ff2 DAC k in 2 1 T s s k fb 2 k g 1 1 T s s Cancellation Logic k ff 1 k r 1 T s s k fb k in (a) (b) DAC DAC xt() yn() xt() yn() TABLE 1. Loop-filter coefficients of CT Σ∆Ms in Fig.7 CT Σ∆M1 CT Σ∆M2 CT Σ∆M3 1.5 2 1.6 -1.5 -2 -1.6 111.6 -0.1 -0.37 -0.24 0.6 1 _ 0.5 1.2 _ 111 0.5 1 _ __1 __-1 Poles k in k fb k g1 k r k g2 k g3 k ff1 k ff2 k in2 k fb2 ω10= ω235⁄2πBw ⋅⋅= k i TABLE 2. Values of for the CT Σ∆Ms in Fig.7 CT Σ∆M1 CT Σ∆M2 CT Σ∆M3 [-0.328 0.664-j0.438 0.664-j0.438] [0.122+j0.39 0.122-j0.39 -0.667] [-0.543+j0.64 -0.543-j0.64] [-0.56 0.853 0.853] [0.81 0.81 0.959] [0.766 0.766] [3.503 0.016-j0.184 0.016+j0.184] [1.476+j1.722E-3 1.476-j1.722E-3 -5.69] [-1.78-j1.81 -1.78+j1.81] g i p i and λ i , λ g p g i p i and λ i , f i σ ∆T 25 ps= f i B B 2= B 5= SNR-peak tors in Fig.7 is plotted vs. for several values of , showing simulation results and theoretical predictions. For comparison purposes, predictions given by [7] are also included. Note that, simulated and theoretical data matched very well when the combined effect of signaland modulator-dependent jitter noise is taken into account as shown in this work. CONCLUSIONS The effect of clock jitter on multi-bit CT Σ∆Ms with NRZ DAC has been analyzed. Based on the use of state-space formulation, easy-to-compute closed-form expressions have been derived for the noise power and signal-to-noise ratio. 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(b) 1.9 MHz input frequency 19 MHz input frequency 0 510 15 20 25 30 52 54 56 58 60 62 64 66 68 70 Clock jitter standard deviation σ ∆ T (ps) Peak SNR (dB) Calculated, fin=4 MHz Calculated, fin=12 MHz Calculated, fin=19 MHz Simulated, fin=4 MHz Simulated, fin=12 MHz Simulated, fin=19 MHz [7], no input signal dependency 0 510 15 20 25 30 53 54 55 56 57 58 59 60 61 Clock jitter standard deviation σ ∆ T (ps) Peak SNR (dB) Calculated, fin=1.9 MHz Calculated, fin=10.5 MHz Calculated, fin=19 MHz Simulated, fin=1.9 MHz Simulated, fin=10 MHz Simulated, fin=19 MHz [7], no input signal dependency 0 510 15 20 25 30 42 44 46 48 50 52 54 56 Clock jitter standard deviation σ ∆ T (ps) Peak SNR (dB) Calculated, fin=1.9 MHz Calculated, fin=10.5 MHz Calculated, fin=19 MHz Simulation, fin=1.9 MHz Simulation, fin=10.5 MHz Simulation, fin=19 MHz [7], no input signal dependency Fig. 9: vs. for different values of : (a) CT Σ∆M1. (b) CT Σ∆M2. (c) CT Σ∆M3. SNR σ ∆T f i (a) (b) (c) [7] σ ∆T f i