Optimization of adaptive fuzzy processor design

OPTIMIZATION OF ADAPTIVE FUZZY PROCESSOR DESIGN I. Ba u one, S. Sánchez Solano, A. Ba iga, J. L. Hue as. Ins i u o de Mic oelec ónica de Se illa - Cen o Nacional de Mic oelec ónica A da. Reina Me cedes s/n, (Edi . CICA), E-41012, Se illa, Spain XIII Con e ence on Design o Ci cui s and In eg a ed Sys ems (DCIS’98), pp. 316-321, Mad id, No iemb e 17-20. 1998 This ma e ial is p esen ed o ensu e imely dissemina ion o schola ly and echnical wo k. Copy igh and all igh s he ein a e e ained by au ho s o by o he copy igh holde s. All pe sons copying his in o ma ion a e expec ed o adhe e o he e ms and cons ain s in oked by each au ho ’s copy igh . In mos cases, hese wo ks may no be epos ed wi hou he explici pe - mission o he copy igh holde . Abs ac A uzzy p ocesso is p og ammed o p o ide an op imum ou pu o sol ing a gi en p oblem. I could heo e ically sol e any p oblem ( om a s a ic poin o iew) i i is an uni e sal app oxima o . This pape add esses he design o uzzy p ocesso s aiming a a wo old objec i e: e icien adap i e app oxima ion o di e en and e en dynamically changing su aces and ha dwa e simplici y. Adequa e p og ammable pa ame e s and a ully-pa allel a chi ec u e a e selec - ed. Mixed-signal blocks based on digi ally p o- g ammed cu en mi o s a e employed. E o -de- scen lea ning algo i hms o uning a e discussed. Adap i e beha io is illus a ed wi h an applica ion o he on-line iden i ica ion o a nonlinea plan . I. In oduc ion Fuzzy sys ems ha e d awn a g ea a en ion o hei capabili y o ansla ing expe knowledge ex- p essed by linguis ic ules in o a ma hema ical ame- wo k. This is e y in e es ing because as p ocesses become mo e complex (non-linea and/o changing o e ime), he abili y o desc ibe hem ma hema ical- ly dec eases and all ha can be a ailable is a linguis ic desc ip ion. A ypical mul i-inpu single-ou pu uzzy sys em con ains a se o IF-THEN ules like he ollowing: Rule i:IFx1 is A1i and ... and xu is Aui THEN y is Bi whe e xj (j=1,..., u) a e he inpu and y is he ou pu a iables while Aji(i=1, ..., R) and Bi a e, espec i e- ly, he an eceden s’ and consequen ’s uzzy se s ha ep esen linguis ic alues like “ e y big”, “small”, e c. The in e ence is accomplished a e h ee s ages. The i s one is uzzi ica ion o calcula ion o he membe ship deg ees, µji, o xj o Aji. The second s age is ule p ocessing, which is pe o med by (a) compu - ing each ule’s ac i a ion deg ee, hi = ∧jµji (whe e ∧ is a T-no m ope a o like he minimum, p oduc , e c.), (b) by calcula ing each ule’s conclusion, y’i = hi∧ Bi, and (c) by compu ing i s agg ega ion, y’ = ∨iy’i (whe e ∨ is a T-cono m ope a o like he maximum, sum, e c.). The las s age is de uzzi ica ion, which is aimed a ob aining a c isp ou pu (by implemen ing a mean-o -maximum ope a o , a cen oid, e c.) [1]. The c isp ou pu p o ided by he uzzy sys em no only depends on i s ule base and i s an eceden s and con- sequen s bu also on he di e en ope a o s employed o implemen he T-no ms, he T-cono m, and he de- uzzi ica ion. To make an e icien selec ion o hese ope a o s, he designe should conside owa ds which applica ions he uzzy sys em is add essed and how i is going o be implemen ed. Fuzzy sys ems ha e been widely implemen ed wi h so wa e on s anda d digi al p ocesso s. Howe - e , when eal- ime ope a ion and/o low a ea and powe consump ion a e equi ed he adequa e solu- ion is o implemen hem wi h dedica ed ha dwa e. An applica ion speci ic uzzy in eg a ed ci cui is he op imum solu ion o a pa icula p oblem. On he o he side, a gene al-pu pose uzzy chip o uzzy p o- cesso is be e when a wide ange o applica ions is conside ed. Among he applica ions o uzzy sys ems he e a e ields like con ol and iden i ica ion o non- linea dynamical p ocesses, nonlinea channel equal- iza ion, adap i e noise cancella ion, and gene a ion o linea izing o condi ioning unc ions o nonideal senso s o signal p e-dis o ion [2-3]. While an appli- ca ion speci ic uzzy IC p o ides a ixed ou pu su - ace, a uzzy p ocesso should p o ide an op imum su ace o di e en p oblems. Hence, he alue o a uzzy p ocesso inc eases i i is a uni e sal app oxi- ma o o su aces. This pape add esses he design o uzzy p oces- so s aiming a a wo old objec i e: e icien app oxi- ma ion o di e en and e en dynamically changing su aces and ha dwa e simplici y. We will ocus on implemen ing uzzy in e ence engines wi h ixed T- no m, T-cono m and de uzzi ica ion ope a o s sui - able o hese pu poses. App oxima ion o a gi en ou pu su ace is achie ed by p og amming adequa e Op imiza ion o adap i e uzzy p ocesso design I. Ba u one, S. Sánchez Solano, A. Ba iga, J. L. Hue as. Ins i u o de Mic oelec ónica de Se illa, I.M.S.E.-C.N.M. A da. Reina Me cedes s/n. Edi icio CICA. 41012-Se illa. Phone: 95 423 99 23 FAX: 95 423 18 32 E-mail: [email p o ec ed] pa ame e s ha de ine he an eceden s and conse- quen s o he ules. This is discussed in Sec ion II. Ano he ele an poin is o choose an e icien a chi- ec u e. The selec ed a chi ec u e is b ie ly desc ibed in Sec ion III. Digi al p og ammabili y is p e e ed o ease use in e ace and o s o e he di e en pa ame- e s. This also eases manual o au oma ic uning o he uzzy p ocesso when adap a ion is equi ed. Mixed- signal cu en -mode blocks a e employed o imple- men ule p ocessing. They admi digi al p og amma- bili y and p o ide he uzzy p ocesso wi h an analog I/O in e ace ha allows di ec communica ion wi h he usually analog senso s and ac ua o s. These blocks a e desc ibed in Sec ion IV. Sec ion V discuss- es adequa e lea ning algo i hms o une he desc ibed uzzy p ocesso . A mixed-signal design is e icien because no high esolu ion is equi ed in mos o uzzy applica ions. This is illus a ed in Sec ion VI wi h an example o applica ion o he on-line iden i i- ca ion o a non-linea plan . II. A uni e sal app oxima o uzzy p ocesso Many ypes o uzzy sys ems ha e been p o ed o be uni e sal app oxima o s [4-5] so ha gi en a pa - icula p oblem, hey a e heo e ically e ec i e. The p oblem is o selec he mos app op ia e one. F om a ha dwa e poin o iew, i is con enien o implemen single on uzzy sys ems, also known as ze o-o de Takagi-Sugeno’s sys ems. They ep esen he consequen s by single on alues, ci, and p o ide he ollowing ou pu : (1) Rega ding ep esen a ion o an eceden s’ uzzy se s, piece-wise linea membe ship unc ions a e easy o implemen (especially wo king in cu en -mode) as well as e y sui ed o be digi ally p og ammed [6]. Ano he choice o do is he selec ion o he ope a o ha combines he an eceden s o a ule ( o calcula e hi). The mos popula ones a e he minimum and he p oduc ope a o s. A mul i-inpu minimum ci cui is simple o design in cu en -mode while a mul iplie is mo e complex [6]. Howe e , he ou pu su ace p o- ided by a uzzy sys em ha employs he minimum ope a o is gene ally non-linea while employing he p oduc ope a o i is piece-wise mul i-linea o mul i- a ine. The au ho s in [7] demons a e ha uzzy sys- ems whose inpu membe ship unc ions co e he in- pu uni e ses o discou ses as shown in Figu e 1 ha e be e app oxima ion accu acy when employing he p oduc ins ead o he minimum connec i e. Since one o ou objec i es i o achie e e icien app oxi- ma ion, we will ocus on implemen ing hese uzzy sys ems wi h he p oduc ope a o . They p o ide he ollowing ou pu : wi h (2) whe e K is a cons an (Σihi = K). The p og ammable pa ame e s a e he poin s ai o each inpu a iable and he single ons o he ules. We desc ibe he a chi ec u e and he building blocks o hese p ocesso s in he ollowing. III. A ully-pa allel a chi ec u e The building blocks equi ed o implemen he se- lec ed uzzy sys em a e: (a) MFC’s ha implemen an eceden s’ membe ship unc ions, (b) T ci cui s o compu e hi by an eceden s’ connec ion (by p oduc ope a o ), and (c) CONS blocks ha implemen he p oduc hi•ci. A inal di ide ci cui is no equi ed be- cause he sum Σihi is cons an . Since a single on uzzy sys em is inhe en ly pa al- lel in i s inpu a iables and ules, he e is always a ade-o be ween high in e ence speed (pa allel p ocessing) and low silicon a ea (sequen ial p ocess- ing). F om he inhe en g id pa i ion o he selec ed ype o uzzy sys ems, an a chi ec u e ha sha es he MFC’s is p e e ed. A ele an ea u e o uzzy sys- ems is ha inpu a iables ypically igge a small numbe o he o al numbe o ules, so ha he max- imum numbe o ules ha a e simul aneously ac i e is αu, whe e α is he o e lap ac o , ha is, he maxi- mum numbe o ac i e uzzy se s pe inpu . In ou case, α is 2. Fully-digi al uzzy chips ha e been e- po ed in he li e a u e ha ake ad an age o his ea- u e, hus p ocessing only he αu ac i e ules [8-9]. To allow pa allel p ocessing o hese ules, he p oposal in [8] is o employ αu copies o he ule memo y and o use mul ibi compu ing ope a o s, which a e e y a ea consuming. On he o he side, he digi ally-p o- g ammable analog uzzy chips epo ed in he li e a - u e o e pa allel compu ing wi h lowe ha dwa e e- sou ces bu hey implemen much less ules han he ully-digi al ones ( o ins ance 4 [10], 9 [11], 15 [12], o 49 [13] agains 102 [14], 128 [15], 512 [16], o 960 [9]). In addi ion, hese digi ally-p og ammable ana- log uzzy chips do no op imize digi al pa because he p og ammable pa ame e s a e s o ed in digi al egis e s and he selec ion ci cui y consis s in ex en- si e ma ixes o swi ches (mul i-po -like digi al zh ici ⋅ i1= R ∑hi i1= R ∑ ⁄= Fig. 1: Choice o he co e ing o he inpu spaces. a0a1a2a3a4a5a6a7 x-inpu space µ(x) K zh ici ⋅ i1= R ∑K⁄=hiµj i j1= u ∏ = D/A- ou e in mi o xodd Iu x-x0 mi o ou e in D/A- xe en Iu mi o in ou e A/D- x µ µl xlMFC Iu Iu om X-Mem Fig. 4: (a) Scheme o he MFC. (b) The wo ac i e labels pe inpu . xodd xe en M U Xx0 x0 xl-x0 x-inpu x0x1 KAlA x µ(x) space (a) (b) memo ies) which occupy a la ge a ea ( o ins ance, he 93% o he o al a ea o he p og ammable chip desc ibed in [12] is occupied by he digi al pa ). To a oid hese p oblems we ha e selec ed he a - chi ec u e p esen ed in [17] ha sha es he MFC’s bu no he CONS’s and ha implemen s all he possible ules, Lu, o be sui able o many applica ions (whe e L is he numbe o uzzy se s pe inpu ). This a chi ec- u e allows op imiza ion o bo h he analog and digi al pa o a ully-pa allel uzzy p ocesso . The analog co e is op imized by using an ac i e- ule d i en scheme. This scheme educes no only he numbe o MFC’s equi ed, om L•u o 2•u, bu also he numbe o T’s and CONS’s, om Lu o 2u. The analog co e mainly depends on u, and basically emains he same independen ly o he numbe o labels, L, pe inpu , and he o al numbe o ules, Lu ( o example, i is ba- sically he same o chips wi h 3x3=9 ules o 13x13=169 ules). The digi al pa is also op imized by using an adequa e memo y o ganiza ion ha makes i possible o e ie e all he equi ed pa ame- e s in pa allel om s anda d digi al RAM’s wi hou a need o eplica ion o mul i-po cos ly memo ies. Figu e 2 illus a es his a chi ec u e o he uzzy sys- em he e selec ed in he case o wo inpu a iables. Figu e 3 shows he pa i ion o he an eceden s’ and consequen s’ memo ies o he case o ou labels pe inpu . In his example, he odd ai poin s o he inpu a iables a e s o ed in he M1 pa s o he co espond- ing inpu memo y while he e en ai poin s a e s o ed in he M2 pa s. Rega ding he consequen s, he M1 pa o he Z-Mem, o ins ance, s o es he single ons c1,c3,c9, and c11. Conside ing adap i e uzzy p oces- so s, his a chi ec u e is also ad an ageous since, gi - en an inpu , only he pa ame e s associa ed wi h he ac i e ules ake pa in he adap i e phase, simila ly o ha happens in he in e ence phase. IV. Building blocks o he in e ence co e The MFC’s ha e o gene a e he ollowing exp es- sion (acco ding o Figu e 4b): (3) whe e x is he usually analog inpu and x1, x0 a e he digi ally p og ammable pa ame e s (ai poin s) gi en by he X-Memo y. Two subs ac ions and a di ision ha e o be imple- men ed. I digi al ci cui y is employed, one A/D con- e e is equi ed o con e each inpu a iable o he digi al domain. Ou p oposal is o employ mixed-sig- nal p ocessing so ha an A/D is exploi ed o imple- men he di ision (see Figu e 4a). Since no high esolu ion is equi ed by mos o uzzy applica ions (we will see an example in Sec ion VI), his A/D can be designed as a con inuous- ime algo i hmic con- Z-Mem x1 MFCx1 x2 CONS1 CONS2 CONS3 CONS4 z In e ence co e M1 M2 M3 M4 b1x2 ... bnx2 b1x1 ... bnx1 T Tll T l Tl Fig. 2: Selec ed a chi ec u e [17]. X2-Mem M21 M22 X1-Mem M11 M12 M U X M U X M U X M U X MFCx2 c13 (M3)c 14 (M4)c 15 (M3)c 16 (M4) c9 (M1)c 10 (M2)c 11 (M1)c 12 (M2) c5 (M3)c 6 (M4)c 7 (M3)c 8 (M4) c1 (M1)c 2 (M2)c 3 (M1)c 4 (M2) Fig. 3: Rule able ha illus a es he pa i ions o he an eceden s’ and consequen s’ memo ies. x1 example o ac i e ules a1 (M11)a2 (M12)a3 (M11)a4 (M12) x2 b1x1b2x1:00 01 11 Kxx 0 –() x1x0 – --------------------- e e based on cu en mi o s (Tha is why i is named A/D-mi o in Figu e 4a). The es o he MFC consis s o wo digi ally p og ammed cu en mi o s, named D/A-mi o in Figu e 4a. They enable o im- plemen he subs ac ion x-x0 and x1-x0 by wi e con- nec ion (supposing ha he inpu a iable is ep esen ed by a cu en ). Desc ip ion o hese A/D and D/A-mi o s, ha is he selec ion o hei s uc- u es and da a abou hei silicon a ea occupa ion, powe consump ion and ope a ion speed can be ound in [18]. As an example, he combina ion o a 5-bi A/ D- and a D/A-mi o occupy an ac i e a ea o 0.08 mm2 in a 2.4-µm CMOS echnology. F om Hspice simula ions, he esponse ime o he combina ion is 120 ns o a s a ic powe consump ion o 409 µW (wo king a a 3-V powe supply). The ou pu s o an MFC so designed a e wo digi al wo ds, as ollows: and (4) whe e Q(.) is a quan iza ion ope a o . The T ci cui s implemen a p oduc connec i e by also employing digi ally p og ammed cu en mi o s as shown in Figu e 5a. The ou pu cu en s o hese ci cui s ep esen he ac i a ion deg ees o he ac i e ules. The CONS’s a e also digi ally p og ammed cu en mi o s (Figu e 5c). Thei ou pu cu en s a e wi ed ou o p o ide he global c isp ou pu o he uzzy p ocesso . A ea u e o an ac i e- ule d i en a chi ec u e is he need o addi ional ci cui y o selec he an eced- en s’ pa ame e s, ai, and he consequen s’ pa ame e s, ci, om he digi al memo ies. This addi ional ci cui - y compa es each inpu a iable wi h he poin s ai o i s co esponding space o ob ain a con ol digi al wo d o n bi s, (b1, ..., bn) in Figu e 3, n being he in- ege bigge han o equal o log2(L-1). The compa i- son can be done in pa allel, using L-2 cu en compa a o s and p og ammable cu en mi o s, o in se ies, ollowing a bina y- ee scheme. In he las case, he ope a ion akes n clock phases. The n-bi wo d con ols which ai poin is x0 and x1 ( his is he pu pose o he MUX blocks wi hin he MFC’s) and which ci is c ,cll, e c. ( his he pu pose o he MUX blocks be ween he T’s and he CONS’s). The MUX blocks a e digi al swi ches con olled by his wo d. Once he con ol digi al wo d is ob ained, he whole p ocessing o all he ac i e ules is ca ied ou in pa - allel, in a ew hund eds o nanoseconds (depending on he echnology). V. Adequa e lea ning algo i hms A uzzy p ocesso designed wi h he desc ibed a - chi ec u e and building blocks app oxima e a gi en ou pu su ace by p ope ly p og amming he alues o he ai poin s and o he single ons. I he uzzy p oces- so wo ks in a dynamically changing en i onmen , i has o be combined wi h a uning/lea ning block ha upda es he p og ammable pa ame e s o ma ch he new si ua ion. We b ie ly desc ibe in he ollowing simple lea ning me hods ha can be implemen ed o - chip o on-chip wi h he uzzy p ocesso . We will o- cus on supe ised lea ning me hods, which can be employed when a se o aining pa e ns is a ailable. Tuning o single on alues Since he ou pu o a single on uzzy sys em is a linea unc ion o he single on alues, a g adien -de- scen me hod is e y sui able o op imize hem. The gene ic g adien -descen upda ing equa ion o a sin- gle on alue, ci, is: (5) whe e η, he lea ning a e, is a sui ably chosen con- s an and E, he e o , is a pe o mance index o how well he desi ed unc ion, g, is app oxima ed by he uzzy sys em ou pu , z. E is usually de ined as he mean quad a ic e o o e a ini e se o aining da a o a ini e ime in e al [k+1-T, k]: (6) Taken o z he exp ession in (2), he pa ame e ci is hen adjus ed as: (7) This upda ing can be pe o med o - o on-chip. The ci cui y equi ed o on-chip implemen a ion is desc ibed in [19]. Equa ion (7) ep esen s a block o ba ch lea ning algo i hm whe e each single on alue µ x() Qxx 0 – x1x0 – --------------   =µlx() µ x()= D/A- ou e in mi o Fig. 5: (a) T and (b) CONS ci cui s used. D/A-mi o ou e in µ I D/A- ou e in mi o µl I •µ •µl T hi hi•ci CONS om Z-Mem (a) (b) cinew ciold ηci ∂ ∂E ⋅–= E1 T --- zg–() 2 p pk1T–+= k ∑ ⋅= cik1+()cik1T–+() 2η T ------ zg–() hi K ---- p pk1T–+= k ∑ ⋅–= is upda ed a e he p esen a ion o T pa e ns. Mo e adequa e o on-chip implemen a ion, al hough less e ec i e in gene al, is on-line lea ning, whe e he sin- gle on alue is upda ed a e he p esen a ion o 1 pa - e n (T=1). Fo ce ain applica ions like adap i e noise cancella ion ba ch lea ning is equi ed. Fo o h- e applica ions, like iden i ica ion o non-linea dy- namical plan s, on-line lea ning can be enough. Tuning o an eceden s’ alues In some cases, he inpu spaces can be uni o mly pa i ioned and only he single on alues can be ad- jus ed. Howe e , he e a e se e al applica ions o which his solu ion would conduc o e y ine pa i- ions and consequen ly many ules o achie e a gi en app oxima ion accu acy. In hese cases, adjus ing o an eceden s pa ame e s is also con enien , al hough his is much mo e di icul han consequen uning. One o he causes is ha he dependence o he uzzy sys em’s ou pu on he an eceden s’ pa ame e s is nonlinea so ha he op imiza ion p ocess based on g adien -descen echniques can be apped a local minima. The uning pa ame e s a e he poin s, ai, o he inpu spaces ( emembe Figu e 1). I L labels co - e an inpu space, we will ha e L-2 uning pa ame e s in ha space because he ex eme poin s a e ixed. Ano he cause ha makes i di icul an eceden uning is ha he exp essions o he pa ial de i a i es o he e o unc ion a e much mo e complex han o he consequen s. To a oid his p oblem, a weigh -pe - u ba ion lea ning algo i hm has been chosen [20]. This is an e o -descen me hod wi h a e y simple upda ing equa ion: (8) whe e β is a sui ably chosen cons an and ∆E|p is he e o a ia ion o he pa e n p and o a small pe u - ba ion in he pa ame e ai.∆E|p is calcula ed as: (9) whe e zpe is he ou pu o he uzzy sys em when pa- ame e ai is pe u bed. Signal β•(z-g) is supposed o be p o ided om ou side he chip, as in he conse- quen s and equa ion (8) can be implemen ed o - o on-chip [19]. VI. Example o applica ion: on-line iden i ica ion o a non-linea plan Adap i e uzzy chips o low esolu ion (below 8 bi s) and wi h a ew pa ame e s o adjus can be suc- ces ully employed in se e al applica ions. To illus- a e his, we ha e applied he abo e desc ibed lea ning algo i hms o une a uzzy p ocesso o iden- i y he ollowing nonlinea p ocess (Figu e 6a): (10) An adap i e uzzy p ocesso wi h 8 labels pe in- pu (6+6+64=76 uning pa ame e s) has been de- sc ibed by C language. A esolu ion o 7 bi s has been conside ed o he D/A and D/A-mi o s o he build- ing blocks. 121 aining pa e ns ha e been used. When only he 64 single on alues a e on-line uned, he inal oo -mean squa ed e o (RMSE) eached a - e 9 epochs is 3.4% (Figu e 6b). I he an eceden s’ aik1+()aik1T–+()β ∆Ep pk1T–+= k ∑ ⋅–= ∆Epzpe g–zg––= xy,() xsin x ---------- ysin y ---------- ⋅= wi h x,y [-1,1]∈ (a) -1 1-1 1 0 1 (b) -1 1 -1 1 0 1RMSE=3.4% (c) RMSE=0.9% -1 1-1 1 0 1 Fig. 6: On-line iden i ica ion o a nonlinea p ocess: (a) Desi ed su ace. App oxima ion ob ained: (b) wi h only consequen uning and (c) when an eceden s and consequen s a e uned. xy xy xy pa ame e s (12 poin s) a e also uned on line, he RMSE dec eases o 0.9% a e 85 epochs (Figu e 6c). Ini ially, he an eceden s’ membe ship unc ions co - e ed uni o mly he inpu spaces and all he single on alues we e 0.5. Robus ness o an adap i e uzzy p ocesso agains e o s in i s ci cui y has been con i med in his exam- ple. A 20% gain e o was in oduced in one o he D/ A-mi o s o a T ci cui and he same aining was pe o med. An RMSE o 1.0% was ob ained a e 170 epochs. VII. Conclusions. This pape has ocused on he design o adap i e uzzy p ocesso s. Op imiza ion o his design has been done aking in o accoun heo e ical and p ac i- cal issues. Conside ing heo e ical issues, we ha e de- cided o implemen ze o-o de Takagi-Sugeno’s sys- ems ha employ he p oduc as he connec i e ope - a o o he an eceden s and ha co e he inpu spaces wi h iangle-shaped membe ship unc ions whose o e lapping is 50%. These sys ems o e good ap- p oxima ion and uning p ope ies. Conside ing ha d- wa e implemen a ion, we ha e employed a ully-pa - allel ac i e- ule d i en a chi ec u e, whe e he p o- g amm-able pa ame e s a e s o ed in s anda d digi al RAM’s and he compu ing blocks a e implemen ed wi h mixed-signal ci cui s based on cu en mi o s. E o -descen lea ning algo i hms ha e been applied o une his p ocesso . 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