Log-domain implementation of complex dynamics reaction-diffusion neural networks

IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003 1337 Log-Domain Implementation of Complex Dynamics Reaction-Diffusion Neural Networks Teresa Serrano-Gotarredona, Associate Member, IEEE, and Bernabe Linares-Barranco, Member, IEEE Abstract—In this paper, we have identified a second-order reaction-diffusion differential equation able to reproduce through parameter setting different complex spatio-temporal behaviors. We have designed a log-domain hardware that implements the spatially discretized version of the selected reaction-diffusion equation. The logarithmic compression of the state variables allows several decades of variation of these state variables within subthreshold operation of the MOS transistors. Furthermore, as all the equation parameters are implemented as currents, they can be adjusted several decades. As a demonstrator, we have designed a chip containing a linear array of ten second-order dynamics coupled cells. Using this hardware, we have experimentally reproduced two complex spatio-temporal phenomena: the propagation of travelling waves and of trigger waves, as well as isolated oscillatory cells. Index Terms—Analog circuit design, analog very large scale integration (VLSI), current mode, logdomain, neural networks, nonlinear circuits, piecewise-linear circuit, subthreshold, weak inversion. I. INTRODUCTION MANY pattern formation and wave propagation phenomena that appear in nature can be described by systems of coupled nonlinear differential equations, generally known as reaction-diffusion equations [1]. These wave propagation phenomena are exhibited by systems belonging to very different scientific disciplines. For example, in neurophysiology, the propagation of electrical impulses through the nervous system and the propagation of the cardiac movement through the cardiac muscle are classical examples of active wave propagation. It is known that anomalies causing disorganization of autowave structures result into patient’s clinical syndromes [2], [3]. Some groups have also investigated the application of active mediums in image processing tasks [4]. However, the huge amount of calculations involved in the simulations of these spatio/temporal phenomena makes the process tedious and extremely time consuming. In such an scenario, the existence of a specialized parallel/processing hardware able to reproduce these behaviors at very high speed, would be a valuable tool to study and understand more deeply these phenomena. Recently, there have been several research groups realizing circuit implementations of reactiondiffusion equations [5]–[7]. Manuscript received September 15, 2002. This work was supported by ONR under Research Grant “Design of High Density and Neuromorphic CNN Universal Chips as Image Microprocessors” and by a Spanish Grant TIC19990446-C02-02. The authors are with the Instituto de Microelectrónica de Sevilla, Centro NacionaldeMicroelectrónica,Sevilla41012,Spain(e-mail:[email protected]). Digital Object Identifier 10.1109/TNN.2003.816374 The equations describing active wave propagation have the general form (1) where is an -dimensional vector which defines the system state at position (where ) at time . is a set of nonlinear functions of the state variable vector . is an matrix. The diagonal elements of , are known as the diffusion coefficients of the th state variable. And is the Laplacian operator, which defined in is (2) Table I contains some well-known reaction–diffusion equations commonly used in the literature [8]–[13] to model complex spatio-temporal behaviors that appear in several disciplines. All the equations in Table I correspond to the general form of (1). These equations can generate patterns and waves including travelling waves, trigger waves, and spiral waves. These phenomena have been also successfully reproduced in case where the continuum medium description is approximated by a discretely spaced one [14]–[16]. If we do this spatial discretization, in two dimensions , (1) takes the form (3) where is the vector of state variables for the cell located at spatial position ( ). Equation (3) can be interpreted as a regular array of cells. Each cell has complex dynamics described by state variables and is coupled to its neighbors through linear synapses. Equations in Table I, show different levels of complexity, that is, number of state variables, number and type of nonlinearities and number of couplings between state variables of adjacent cells. We selected an equation that captures all the complex spatio-temporal behaviors: Turing pattern formation, traveling waves,trigger waves and spiral waves propagation, while at the same time maintains the lowest possible level of complexity [16]. The selected equation that fulfills the above requirements is (4) 1045-9227/03$17.00 © 2003 IEEE 1338 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003 TABLE I REACTION-DIFFUSION EQUATIONS REPORTED IN LITERATURE TO DESCRIBE ACTIVE SYSTEMS PERTAINING TO SEVERAL SCIENTIFIC DISCIPLINES Fig. 1. Piecewise-linear approximation of the nonlinearity of (4). where the nonlinear term has been approximated by the piecewise-linear nonlinearity depicted in Fig. 1. Through proper parameter setting, this equation is able to exhibit Turing’s patterns formation, trigger wave, travelling wave propagationand spiralwaveformation.As willbe demonstrated in the next Section, all the behaviors are robust against random variations in the equation parameters higher than 20% [16]. II. BEHAVIORAL SIMULATIONS The spatially discretized version of (4) have been simulated in MATLAB to reproduce the different spatio-temporal phenomena and to check the tolerance of these behaviors to random fluctuations in the parameters of (4). A one-dimensional (1-D) array of cells has been simulated in MATLAB. The cell parameters were set to obtain two different behaviors: a travelling wave propagating with constant amplitude through the array and a trigger wave behavior. We have found points in the parameter space where the traveling wave behavior is robust against cell parameters random deviationsaswideas 20%.Deviationswere introducednotonlyinthe cell parameters, but also in the coupling parameters and . SERRANO-GOTARREDONA AND LINARES-BARRANCO: LOG-DOMAIN IMPLEMENTATION 1339 TABLE II TOLERANCE IN THE PARAMETER DEVIATIONS OF DIFFERENT SPATIO-TEMPORAL BEHAVIORS Fig. 2. Simulation of the formation of Turing’s patterns in an array of N 2 N = 32 2 32 cells. Final pattern obtained in the u state variable with the u values coded in a scale of gray levels. (top) Simulation results when the cell parameters are set to their nominal values. (bottom) Simulation results when the cell parameters are generated with a deviation of  =30% around the nominal values. The robustness of the behavior has also been checked for the trigger wave propagation. A tolerance of a standard deviation of 20% in the cell parameters and coupling parameters has been found through MATLAB simulations. Simulations of the different behaviors in a two dimensional array of cells have also been performed. Table II shows, for different spatio-temporal behaviors, the maximum standard deviations allowed simultaneously in all the cell parameters and coupling parameters that maintain the same qualitative behavior in all the cells in the array. Also shown in Table II, are the nominal cell and coupling parameters used in the different simulations. TherobustnessofTuring’spatternsformationagainstrandom parameter deviations is illustrated in Fig. 2. Fig. 2(top) depicts the Turing’s patterns developed in the two-dimensional (2-D) array when the cell parameters are set to the values , , , , , , , and coupling parameters and . Afterwards, a simulation with random parameters deviations of was performed. The deviations were introduced not only in the cell parameters but also in the coupling parameters betweencells.Fig.2(bottom)showstheresultofthissimulation. Fig. 2 shows the final patterns developed in the state variable with the values of the state variable coded as levels of gray. As deduced from our system simulations, the transistors in our design must be dimensioned in order to ensure that the parameters in our hardware implementation have a standard deviation lower that 20%. This level of precision is achievable in subthreshold MOS implementations for moderate transistor sizes. MOS transistors operating in subthreshold have a relative current precision almost independent of the operating current level [17]. Transistors of size , fabricated in the AMS 0.35 technology have in the weak inversion regime a standard deviation [18]. In the rest of the paper, simulations of tolerance at the transistor level are omitted. The reason is that transient simulations of large arrays of cells have to be performed. These simulations at the transistor level would require days of computing. III. CIRCUIT SYNTHESIS Our target is to synthesize an array of second-order cells () implementing the discretely spaced version of the nonlinear differential (4) (5) were the continuous 2-D Laplacian operator has been substituted by its discretized version [see (3)]. 1340 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003 In order to reproduce different spatio-temporal phenomena throughparametersetting,thehardwaremusthavethefollowing properties. 1) Parameters must be tunable in a wide range without degrading the behaviors. 2) State variables and must have a wide range of operation without saturation of the behavior. 3) Forsomelocomotion applications, thetime constant must be scalable to arbitrarily low values. These requirements are met in a log-domain implementation [19]–[22]. In a log-domain circuit, the voltages in the circuit nodes are a logarithmically compressed versionof the state variables. Thus, the state variables can vary severaldecades without saturation of the behavior. Also the cell parameters are currents that can be adjusted several decades in the MOS subthreshold regime [17], [23]. Furthermore, it is possible to scale down simultaneously all the currents in the circuit making the operation arbitrarily slow. In the proposed circuit implementation we have to distinguish between mathematical state variables and circuital state variables. In the log-domain circuit technique, state variables {} are currents and are related to node voltages {} through exponential relationships (6) This means that the circuital state variables { } cannot be negative. Consequently, a coordinate transformation is required [21] to map the mathematical state variables { }in (5) to the circuital ones { } (7) where is the translation vector and is the scaling factor. After substituting the original state variables, and , of (4) by the scaled and translated variables and , the following differential equation results: (8) where , and the breakpoints of the piecewise-linear nonlinearity have been redefined as (9) Terms and are two offset terms defined as follows: (10) Applying the log-domain mapping given by (6) to the discretely spaced version of (8) that results after the translationand scaling of the state variables, yields the following relation between circuit voltages: Coupling Coupling (11) where the terms called Coupling account for the Laplacian operator and are given as Coupling Coupling (12) Notice that the translated and scaled state variables have been renamed as and for shortness of notation. Parameters in (11) and (12) are related with the ones in (8) through the following relations: (13) where, as it will become clear later, in our implementation is a free design current parameter that for a given capacitance controls the characteristic time constant of the response. Reducing current , the global response of the circuit can be appropriately slowed down. is also a current parameter that, fora givenrelation betweencapacitances , must betuned to set the original parameter to its appropriate value. Circuit implementation is focused on the realization of (11) and (12), and will be explained in two steps: • implementation of the core cell dynamics (11), excluding coupling, • implementation of the coupling terms (12). A. Uncoupled Cell Each uncoupled cell has a second-order dynamics described by (14) as derived from (11) by making the coupling terms null. Fig. 3 shows the block diagram of the circuit implementing (14). The blocks denoted as and are transconductors obeying an exponential law called -elements [20], [21]. That is,theoutputcurrent ofthese transconductorsdepends exponentially on the difference between the positive and negative controlling voltages. Fig. 4(a) shows the schematics of the bipolar implementation of the -element. The circuit in Fig. 4(a) belongs to the class of translinear networks [24]. Using a reformulation of the translinear principle [25], this circuit can be easily SERRANO-GOTARREDONA AND LINARES-BARRANCO: LOG-DOMAIN IMPLEMENTATION 1341 Fig. 3. Block diagram of the second-order circuit implementing (14). Fig. 4. E -element. (a) Bipolar implementation. (b) and (c) Two possible subthreshold MOS implementations. analyzed. It is found that the circuit in Fig. 4(a) gives as output currents (15) where is the thermal voltage. The currentis considered positive when it goes out of the -element; the corresponding -element is then considered a positive -element. The current is negative when it enters the -element, and the -element is then called a negative -element. Fig. 4(b) and (c) shows two possible implementations of an -element using MOS transistors operating in the subthreshold regime. The circuit in Fig. 4(b) verifies also an exact translinear relationship giving an output current (16) where is a PMOS subthreshold parameter [17]. The output current of the circuit in Fig. 4(c) would be (17) In our particular implementation we have chosen to implement all the -elements using the block shown in Fig. 4(c). It is easy to show that with this selection of the transconductance elements, the circuit of Fig. 3 implements the system of differential equations given by (14) with (18) The block denoted as in Fig. 3 implements in current mode the piecewise-linear nonlinearity shown in Fig. 1. A positive -element biased by a current and controlled by the voltagedifference (seeFig.3)providesasourcing current . This current is used as theinput of the nonlinear block . Fig. 5. Schematic of the piecewise-linear block. Fig. 6. Biasing of the piecewise-linear block. The output current of this nonlinear block is the bias current of a positive -element controlled by a voltage difference . Hence, a current term is fed into the capacitor as required in (14). B. Piecewise-Linear Block As shown in Fig. 1, the PWL function can be decomposed as the sum of three components (19) where denotes the one-sided rectification operation ( if and zero if ), , , and are the slopes of the three pieces of the nonlinearity and and are the breaking points. Fig. 5 depicts the schematics of the current mode block that implements the PWL function of Fig. 1 [26]. The transistors are intended to operate in the subthreshold region, so that the slopes of the different pieces of the piecewise-linear characteristics can be controlled through the bias voltages , , , , , and . In particular (20) However, the large variability of the factors , and the current factors from run to run, makes impractical to control the slopes , , and by controlling directly the voltage biases. This inconvenience can be solved by using current biases to control the three slopes. Fig. 6 shows the biasing block which is common to all the cells in the chip. The amplifiers in Fig. 6 must deliver enough current for all the output branches in the different neurons. This means that the output stage of the amplifier must be scaled with the number of neurons in the chip. 1342 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003 Fig. 7. Extra blocks needed to implement the coupling terms between cells. C. Coupling Between Cells To implement the coupling terms among cells in (12) eight additional -elements are required per cell: four -elements to couple the voltage of cell ( ) with the voltages of its four nearest neighbors , , , and . Four other -elements to couple the voltage of each cell ( ) with the voltage of its four nearest neighbors , , , and . Fig. 7 shows a diagram of the extra blocks needed to implement the coupling terms that appear in (12). D. Initial Conditions Circuitry To generate the different spatio-temporal behaviors, appropriate initial conditions must be set in the and state variables of all the cells in the array [16]. In our design, binary initial conditions are used. That is, for each cell in the array, we set the initial values of the and state variables to one of two possible continuously programmable states ( ,)or( , ). Afterwards, the system switches to its normal evolution mode, and different spatio-temporal behaviors are generated on chip, depending on the parameters and initial condition settings. A careful design of the initial conditions circuitry is needed in order to avoid erasing or modification of the stored initial states during this switching. This switching problem is particularly severe in log-domain operation where the and state variables depend exponentially on the log-compressed and voltages stored on capacitors and . Small deviations of or due to charge injection during the switching are exponentially amplified producing large errors in the initial state. Hence, avoiding any feedthrough injection during switching is essential for correct operation. Fig. 8(a) depicts a block diagram of the circuitry added to set the initial conditions in the and voltages. A set of inverters configured as a shift register selects which initial conditions ( ,)or( , ) are set in each cell. Fig. 8(b) shows the schematic of the boxed block in Fig. 8(a) that sets the initial voltage (or ) in cell capacitor (or ). In Fig. 8(b), and are two switched voltages. switches from , when the initiation signal is high, to , when signal is low (normal operation mode). Signal switches from , when is high, to , when is low. When signal is high the initial conditions are being set in the cells. During this period, all the components in the circuit are disconnected from nodes (or ), except one of the boxed elements of Fig. 8(b). In the steady state, when the input current to capacitor (or ) is zero, the output current of the negative -element [current in Fig. 8(b)], is forced to be equal to the supplied current (or ). Hence, the output voltage (which is connected to capacitor nodes or ) is forced to be (21) hence (22) When signal is low, currents (or ) and are cut off. The switching of the currents is done by switching the source terminals of the current supplying transistors, with their gate terminal being kept at constant voltages. This switchingstrategy avoids any undesired charge injection in the output node [27]. As explained before, during the setting of the initial conditions all the other components in the circuit must be delivering a zero output current to the and nodes. This can be achieved by substituting all the -elements and current sources in Figs. 3 and 7 by switched -elements and switched current sources. The schematic of a switched positive -element is showninFig.9(a).Fig.9(b)showstheschematicoftheswitched negative -element. And Fig. 9(c) depicts the schematic of a switched sinking current source. Note that all the switching is done through the sources of the output current supplying transistors to avoid any charge injection in the capacitors during switching [27]. IV. EXPERIMENTAL RESULTS A 1-D array of coupled cells has been integrated in a 0.35m three-metal double-poly CMOS technology provided by the AMS foundry. Each cell occupies an area of 116 m 227 m. Thus, an array of 32 32 cells would occupy in this technology an area of 27 mm . Fig. 10 shows the layout of one cell in the array. About one third of the cell area corresponds to the cell capacitors and , which are implemented as standard double-poly capacitors available in the technology. Each unit capacitor occupies an area of approximately 62 m 11.5 m. The area of each -element is approximately 50 m 15 m. Fig.11showsamicrophotographofthefabricatedchip.Inthe prototype chip, we have also included an isolated current-mode piecewise-linear block and an isolated cell for characterization purposes. A. Current-Mode Piecewise-Linear Block All the biasing currents , , , , , , (see Figs. 5 and 6) are derived from the same reference current , through 5-bit DAC converters. The value of each current can be varied between . The functionality of the block has been verified for at least four decades of variation of the working currents. Fig. 12(a) shows the measured input–output current characteristics of the block for , , , , , , , and pA. Fig. 12(b) SERRANO-GOTARREDONA AND LINARES-BARRANCO: LOG-DOMAIN IMPLEMENTATION 1343 Fig. 8. (a) Block diagram of the initial conditions circuitry. (b) Schematic of the boxed block in Fig. 8(a). Fig. 9. Schematics of (a) switched E + -element, (b) switched E 0 -element, and (c) switched current source. depicts the measured input-output current characteristics for the same parameters but with . Fig. 13(a) illustrates the controllability of the central slope . In the measurements of Fig. 13(a) nA, , , , , while is varied from 0 to . The values of and are simultaneously swept from to , so that as can be observed the and slopes remain constant and approximately equal to one. Fig. 13(b) illustrates the programmabilityofthe slope.Inthesecurves, , , , , , and , while is varied from 0 to . The controllability of the breaking point is demonstrated in the measurements of Fig. 13(c). In the curves of Fig. 13(c), , , , , , , , and varies from to . 1344 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003 Fig. 10. Layout of one cell. Fig. 11. Microphotograph of the fabricated chip. B. Isolated Cell An isolated cell where the nodes and (see Fig. 3) are directly connected to external pins has been included in the prototype chip. This allows us to do a complete dc characterization of the different sub blocks in the cell. Fig. 14 shows measurements of the input–output characteristics of a positive -element. The measured -element is the one whose bias current is . In these measurements, bias currents and were set to zero. Fig. 14(top) shows current versus the voltage applied to this node , for different values of the voltage applied to node . Voltage was swept from 1.2 to 1.8 V in 50-mV steps. The bias current was held constant at 1 nA. Fig. 14(bottom) depicts current versus the voltage applied to this node , for different values of the bias current . In these 32 curves, the bias current was varied linearly in the range [1 nA/16, 2 nA], while voltage was held constant at 1.5 V. The dots in Fig. 14 correspond to the experimentally measured points. The solid lines are the theoretical curves (23) fitted for a value . SERRANO-GOTARREDONA AND LINARES-BARRANCO: LOG-DOMAIN IMPLEMENTATION 1345 (a) (b) Fig. 12. Input-output behavior of the piecewise linear block for (a) input current u 2 [0 ; 100 pA] and (b) u 2 [0 ; 1  A] . Fig. 13. Measured input–output characteristic. (a) For different values of the central slope m . (b) For different values of the m slope. (c) For different values of the u breaking point. Fig. 15 shows measured results of a negative -element. The measured negative -element is the one with bias current in Fig.3.Biascurrents and weresettozeroisthesemeasurements. Fig. 15(top) shows current versus the applied voltage for different values of the voltage applied to node with current at 1 nA. Fig. 15(bottom) plots current versus the voltage applied to this node , for different values of the bias current . In these 32 curves, the bias current was varied linearly in the range [1 nA/16, 2 nA], while voltage was held constant at 1.5 V. The dots in Fig. 15 correspond to the experimentally measured points. The solid lines are the theoretically predicted curves (24) fitted for the same value . 1352 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003 Fig. 21. Experimental measurements of a trigger wave propagating through a 1-D array of ten cells. (a) Waveforms of the u state variables versus time. (b) Waveforms of the v state variables versus. , , and for the coupling elements . Experimentally, we observed that each uncoupled cell has a unique equilibrium point (excitable medium) in which the state variables settle to the values , . All the cells in the array are initialized to their equilibrium state except for the first cell which is initialized to a nonresting state , . As can be observed in Fig. 20, this cell becomes excited going back to the equilibrium state after a refractory period. The perturbation of the first cell affects (through the coupling synapses) the next cell, which becomes also excited and leaves its resting state SERRANO-GOTARREDONA AND LINARES-BARRANCO: LOG-DOMAIN IMPLEMENTATION 1353 Fig. 22. Measured waveforms of the (a) u and (b) v state variables for an oscillatory medium. during a refractory time, exciting also the third array cell. This way, a travelling wave propagates through the array. The total delay that occurs between the perturbation of the first cell (by the initial condition circuitry) and the perturbation affecting the tenth cell in the array is approximately 0.9 ms. For these biasing conditions, the power consumption of the circuits generating the common biasing currents is 5.5 W. The power consumption of each cell in the steady state is 3.5 W from a power supply voltage of 3.3 V. Fig. 21 shows results of a trigger wave propagating through the array. The reference currents were also set to , and . The circuit parameters were set to: , , , , , , for the nonlinear block, , , , , , and for the coupling elements . Fig. 21(a) shows the waveforms of the state variable versus time, while Fig. 21(b) depicts the waveforms of the state variable versus time. Experimentally, we observed that the uncoupled cell has two equilibrium points (biestable medium) in which the state variables settle to one of the pair of values: ( , ), (, ). All the cells in the array are initialized to the second equilibrium state ( , ) except for the first one which is initialized to a nonresting condition , ). The first cell evolves toward the equilibrium state ( , ) and perturbs (through the coupling synapses) the second cell which is triggered also to the ( , ) equilibrium state. The perturbation is propagated through the array until all the cells have been triggered to the (, ) state. The time that occurs between the triggering of the second and the tenth cells in the array is approximately 0.5 ms. For these biasing conditions, the power consumption of the circuits generating the common biasing currents is 6.5 . The power consumption of each cell in the ( , ) equilibrium state is 5.6 . The power consumption is 3.9 for each cell in the ( , ) equilibrium state. Fig. 22 shows the measured waveforms of the (upper trace) and (lower trace) state variables of one of the cells in the array when the circuit parameters are set to emulate an oscillatory medium. In this case, each isolated cell has only one unstable equilibrium point. Independently of the initial conditions, during its normal operation each cell describes a limit cycle around the equilibrium point. The reference currents were again set to , and . The circuit parameters used in this measurement were: , , , , , , for the nonlinear block, , , , , , and for the coupling elements . V. CONCLUSION A second-order reaction-diffusion equation has been selected which is the simplest equation able to generate, through parameter setting, trigger wave, traveling wave propagation, spiral wave and Turing pattern formation. A hardware implementing the spatially discretized version of the selected equation has been designed. In the hardware implementation the cell state variables are logarithmically encoded as voltages stored in some capacitors. This logarithmic compression of the state variables allows several decades of variation of 1354 IEEE TRANSACTIONS ON NEURAL NETWORKS, VOL. 14, NO. 5, SEPTEMBER 2003 these state variables without saturation of the elements and with low distortion. All the parameters of the implemented equation are set as biasing currents that can be adjusted several decades. Furthermore, by scaling some biasing currents of the circuit the time constant of theimplemented equation can alsobe appropriately scaled. This can be helpful to make the waveforms generated on chip easily observable and for some applications where an extremely slow time constant may be needed (i.e., in locomotion applications). A 1-D array of ten coupled cells has been integrated. The correct operation of the designed hardware has been verified through experimental measurements. We have performed a detailed characterization of the behavior of one isolated cell. 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TeresaSerrano-Gotarredona(S’95–A’00)received the B.S. degree in electronic physics in June 1992 and the Ph.D degree in VLSI neural categorizers in December 1996 from the University of Seville, Sevilla, Spain, after completing all her research at the Sevilla Microelectronics Institute (IMSE), which is one of the institutes of the National Microelectronics Center (CNM) of the Spanish Research Council (CSIC). She received the M.S. degree from the Department of Electrical and Computer Engineering, Johns Hopkins University, Baltimore, MD. She was on a sabbatical stay at the Electrical Engineering Department, Texas A&M University, College Station, during spring 2002. From 1998 to 2000, she was Assistant Professor at the University of Seville. Since June 2000, she has held a Tenured Scientist position at the Sevilla Microelectronics Institute (IMSE), Sevilla, Spain. Her research interests include analog circuit design of linear and nonlinear circuits, very large-scale integration (VLSI) neural-based pattern recognition systems, VLSI implementations of neural computing and sensory systems, transistor parameters mismatch characterization, address-event-representation VLSI, RF circuit design, and real-time vision processing chips. Dr. Serrano-Gotarredona was corecipient of the 1997 IEEE TRANSACTIONS ON VLSISYSTEMS BestPaperAwardforthepaper“AReal-TimeClusteringMicrochip Neural Engine” and of the IEEE CAS Darlington Award for the paper “A General Translinear Principle for Subthreshold MOS Transistors.” She is Coauthor of the book “Adaptive Resonance Theory Microchips.”She was sponsored by a Fulbright Fellowship during her time at Johns Hopkins. SERRANO-GOTARREDONA AND LINARES-BARRANCO: LOG-DOMAIN IMPLEMENTATION 1355 Bernabe Linares-Barranco (S’90–M’92) received the B.S. degree in electronic physics in June 1986 and the M.S. degree in microelectronics in September 1987, both from the University of Seville, Sevilla, Spain. He received the Ph.D. degree in high-frequency OTA-C oscillator design in June 1990 from the University of Seville, Spain, and the Ph.D, degree in analog neural-network design in December 1991 from Texas A&M University, College Station. Since September 1991, he has been a Tenured Scientist at the Sevilla Microelectronics Institute (IMSE), which is one of the institutes of the National Microelectronics Center (CNM) of the Spanish Research Council(CSIC).InJanuary2003,hewaspromotedtoTenuredResearcher.From September 1996 to August 1997, he was on sabbatical stay at the Department of Electrical and Computer Engineering of the Johns Hopkins University, Baltimore, as a Postdoctoral Fellow. During spring 2002, he was Visiting Associate Professor at the Electrical Engineering Department, Texas A&M University. He has been involved with circuit design for telecommunication circuits, VLSI emulators of biological neurons, very large-scale integration (VLSI) neural-based pattern recognition systems, hearing aids, precision circuit design for instrumentation equipment, bio-inspired VLSI vision processing systems, transistor parameters mismatch characterization, address-event-representation VLSI, RF circuit design, and real-time vision processing chips. He is coauthor of the book “Adaptive Resonance Theory Microchips.” Dr. Linares-Barranco was corecipient of the 1997 IEEE TRANSACTIONS ON VLSI SYSTEMS Best Paper Award for the paper “A Real-Time Clustering Microchip Neural Engine,” and of the 2000 IEEE CAS Darlington Award for the paper “A General Translinear Principle for Subthreshold MOS Transistors.” He organized the 1994 Nips Post-Conference Workshop “Neural Hardware Engineering.” From July 1997 to July 1999, he was Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART II, and since January 1998, he has been Associate Editor for the IEEE TRANSACTIONS ON NEURAL NETWORKS. He is Chief Guest Editor of the 2003 IEEE TRANSACTIONS ON NEURAL NETWORKS Special Issue on Neural Hardware Implementations.