Equalization-Based Digital Background Calibration Technique for Pipelined ADCs

322 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014 Equalization-Based Digital Background Calibration Technique for Pipelined ADCs Behzad Zeinali, Tohid Moosazadeh, Mohammad Yavari, Member, IEEE,and Angel Rodriguez-Vazquez, Member, IEEE Abstract—In this paper, we present a digital background calibration technique for pipelined analog-to-digital converters (ADCs). In this scheme, the capacitor mismatch, residue gain error, and amplifier nonlinearity are measured and then corrected in digital domain. It is based on the error estimation with nonprecision calibration signals in foreground mode, and an adaptive linear prediction structure is used to convert the foreground scheme to the background one. The proposed foreground technique utilizes the LMS algorithm to estimate the error coefficients without needing high-accuracy calibration signals. Several simulation results in the context of a 12-b 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. Circuit-level simulation results show that the ADC achieves 28-dB signal-to-noise and distortion ratio and 41-dB spurious-free dynamic range improvement, respectively, compared with the noncalibrated ADC. Index Terms—Adaptive linear prediction, digital background calibration, LMS algorithm, pipelined ADCs. I. INTRODUCTION PIPELINED analog-to-digital converters (ADCs) are the best candidate for medium to high resolutions between 10 and 16 bits and conversion rates between 10 and 250 MHz [1]–[4]. To achieve higher conversion rates, nanometer CMOS technologies are usually utilized where the intrinsic gain of transistors is very poor. On the other hand, in the pipelined ADCs, the resolution is mainly limited by the capacitor mismatch and limited and nonlinear DC gain in the amplifiers. Therefore, calibration techniques are needed to achieve both high speed and high resolution where they can also reduce the power consumption and analog circuits’ complexity [1]–[4]. Moreover, digital calibrations are very interesting because digital circuits are almost fast and reliable in nanometer CMOS technologies. The digital calibration algorithms are classified into two main foreground and background categories. The foreground calibration scheme interrupts the ADCs normal conversion whereas in background techniques, the normal operation of the Manuscript received June 1, 2012; revised December 2, 2012; accepted January 13, 2013. Date of publication February 12, 2013; date of current version January 17, 2014. B. Zeinali, T. Moosazadeh, and M. Yavari are with the Department of Electrical Engineering, Integrated Circuits Design Laboratory, Amirkabir University of Technology, Tehran 15914, Iran (e-mail: [email protected].ir; [email protected]; myav[email protected]). A. Rodriguez-Vazquez is with the Institute of Microelectronics of Seville, Centro Nacional de Microelectrónica, Universidad de Sevilla, Seville 41004, Spain (e-mail: [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2013.2242208 ADC is not interrupted. Nonetheless, in background schemes, the isolation of the calibration process from the normal operation of the ADC is an important issue [3]. The calibration techniques can also be categorized as the correlation-based [1]–[3], statistical-based [4], and equalization-based [5]–[7] approaches. Both the correlationand statistical-based algorithms utilize the statistical properties of orthogonal pseudorandom calibration signals resulting in a very long convergence time. In equalization-based schemes, the errors are generally measured by calibration signals. But, the precision of these signals in nanometer CMOS technologies is an important issue. Several techniques have been proposed to alleviate this problem [5]–[7]. Nonetheless, they still need accurate analog elements or additional calibration cycles. In this paper, a new equalization-based digital background calibration algorithm for pipelined ADCs is presented without needing any accurate calibration signal. It uses the adaptive LMS algorithm [8] to estimate the errors in foreground mode. To convert any foreground calibration scheme to a background one, different algorithms such as those presented in [9] and [10] can be used. In these techniques, some input samples are occasionally skipped to create time slots for calibration and then the missing input samples are digitally filled using a nonlinear digital interpolation filter. However, employing a nonlinear interpolation filter makes the maximum input signal frequency to be limited. Also, there is a large delay between the sampled input and its corresponding digital output due to using a relatively higher order finite-duration impulse response (FIR) filter. To alleviate these problems, a new digital background structure is proposed by using an adaptive linear predictor to fill the skipped input samples randomly. The paper is organized as follows. In Section II, the structure of pipelined ADCs and their nonidealities are briefly reviewed. The proposed new calibration technique in foreground mode is presented in Section III. In Section IV, a new background calibration scheme is proposed. The ADC circuit implementation details are discussed in Section V. Section VI provides the circuit-level simulation results, and finally, Section VII concludes the paper. II. PIPELINED ADC STRUCTURE A. ADC Architecture The general block diagram of pipelined ADCs includes several low-resolution stages to produce the digital output, Dout, where the final stage is usually a Flash ADC [6]. The 1063-8210 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. ZEINALI et al.: DIGITAL BACKGROUND CALIBRATION TECHNIQUE FOR PIPELINED ADCs 323 stages (except the flash ADC) are composed of a sub-ADC and a multiplying digital-to-analog converter (MDAC). The sub-ADC compares the stage analog input with reference voltages and generates the corresponding stage digital output. The digital output is selected from {−1, 0, 1} for 1.5-bit stages and {−1.5, −0.5, 0.5, 1.5} for 2-bit back-end flash ADC. The front-end sample and hold amplifier (SHA) circuit is not generally utilized due to its additional noise and power consumption. The capacitor non-flip-around (CNFA) MDAC structure is utilized in this paper instead of the mostly used capacitor fliparound (CFA) MDAC scheme for the ADC stages. This is because, in this scheme, the input signal and digital-to-analog converter (DAC) voltage exhibit the same errors and hence the capacitor mismatch and amplifier gain error are modeled in the same way [6]. Nonetheless, for more generality, all of the steps are also briefly explained for CFA MDAC structure. The fully differential circuit implementation of a 1.5-bit/stage with CNFA structure is shown in Fig. 1 where VCMiis the amplifier input common-mode voltage and CPis the equivalent parasitic capacitance at the amplifier input. In sampling phase 1, the input signal Viniis sampled in sampling capacitors CS, while the amplifier output is connected to the output common-mode voltage VCMo.Inthe next phase 2, the sampled input signal is transferred to the output by feedback capacitors CF. In this phase, the DAC operation is also performed. B. MDAC Modeling In this section, the effects of capacitor mismatch and amplifier imperfections in the CNFA structure are modeled. In this model, the impact of error due to eliminating the frontend SHA, especially in the first stage, is neglected since it is compensated by time matching between the MDAC and sub-ADC paths [11]. The distortion introduced by a practical residue amplifier could be modeled as a memoryless and weakly nonlinear function of the amplifier’s input voltage. So, it can be approximated accurately by its nfirst Taylor series coefficients where n≤5 is common [1], [2], although, in some previous reports, nonidealities greater than third order are neglected [6]. The following calculations are performed by considering nonlinearities up to fifth order while they can be easily extended for any arbitrary order. The open-loop I–O static characteristics of a fully differential amplifier in the ith stage can be approximated by a fifth-order polynomial as [6] Vouti≈AVx+γ1V3 x+γ2V5 x(1) where Aand Vxare the amplifier DC gain and its input voltage, respectively, and γ1and γ2are the gain nonlinearity coefficients. When the amplifier is placed in a closed-loop configuration, by neglecting higher order harmonics, the inverse of (1) can be approximated by another fifth-order polynomial as Vx≈ρ1Vouti+ρ3V3 outi+ρ5V5 outi(2) ρ1=1 A,ρ 3=−γ1 A3,ρ 5=3γ2 1−γ2 A5.(3) Fig. 1. Fully differential circuit implementation of a CNFA MDAC. The I–O transfer function of the fully differential CNFA MDAC shown in Fig. 1 is given by Vini[n−1]−VDAC[n]=CF CSVouti[n] −CS+CF+CP CSVx[n].(4) By assuming CF/CS=0.5+εand substituting the relations (2) and (3) in (4), we have Vri=(0.5+ε−k)Vouti+γ1k A2V3 outi+(3γ2 1−γ2)k A4V5 outi(5) where kand Vriare defined as (1.5+ε+CF/CS)/Aand Vini−VDAC, respectively. But, a model as Vouti=f(Vri)is more interesting, so the inverse of (5) is defined by another fifth-order polynomial as Vouti≈2(1−α1)Vri−α3V3 ri−α5V5 ri(6) where α1,α3,andα5are the MDAC imperfection coefficients. The error coefficients can be different in ADC’s stages where their indexes associated with stage numbers are omitted in (6) for simplicity. Equation (6) indicates that in the calibration of the CNFA MDAC, the estimation of three different coefficients is required. In CFA MDAC topology, there are two different paths and consequently two different errors for the input signal and subDAC output voltage. So, its modeling, such as relation (6), needs the estimation of 12 error coefficients. Nonetheless, as presented in [7], if Viniis modeled as a function of Voutiand VDAC,thatis,Vini=g(Vouti,VDAC), the number of required error coefficients is significantly reduced. In this case, the capacitor mismatch is considered as CF=C(1+δ) and CS=C(1−δ) while the amplifier imperfection is modeled by (2). So, the sampled analog input is estimated as Vini=(1−δ) 2VDAC+(1+δ) 2−ρ1Vouti−ρ3V3 outi−ρ5V5 outi. (7) As seen from (7), the CFA MDAC needs the estimation of four coefficients while three coefficients are used in CNFA MDAC for the same error. So, in this paper, the CNFA MDAC structure is utilized to simplify the calibration process. 324 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014 2 Sub-ADC Sub-DAC V ri PN={1,-1} f 5 (.) V l i th stage c l Mux V DACi V out i ideal backend ADC D out i D di LMS Machine D ri 0.5 α 1 V ri + α 3 V 3ri + α 5 V 5ri V di Fig. 2. ith stage in the calibration mode in ECS method. Vout(i+1) Sub-ADC Sub-DAC Vr(i+1) D(i+1)={-1,1} Extra DAC 2 Vouti Sub-ADC Sub-DAC Vri PN={1,-1} f5(.) Vl Vl cl 2 VDAC(i+1) VDACE i th stage cl Mux (i+1) th stage VDACi Fig. 3. Proposed error estimation method for calibration of ith stage implemented in CNFA MDAC structure. III. CALIBRATION ALGORITHM IN FOREGROUND MODE A. Error Estimation With Calibration Signals To explain the error estimation with calibration signals (ECS) method as illustrated in Fig. 2, the ADC’s ith stage is modeled by (6), and the calibrated back-end stages are lumped as an ideal ADC. If the calibration procedure begins from the final stages and moves to the first stages, this condition will be easily satisfied. In Fig. 2, Vriis the residue voltage of the ith stage, Vdiis its distorted value, and Voutiis the stage analog output. Also, Dri,Ddi,andDoutiare Nvectors defined as their N-bit digital values, respectively, where Nis the backend ADC number of bits. Since the LMS algorithm is utilized to estimate the model parameters in relation (6), at least four independent equations are required [8]. According to Fig. 2, the stage’s sub-DAC utilizes eight different voltage levels (±Vl for l={1,2,3,4}) in the calibration mode. They are applied by independent control signals of PN and cl.PN is a random two-level signal altering between −1and1toselectthesign of the calibration signals and clspecifies the analog value of the calibration signals. The accuracy of estimation improves with increasing the number of calibration voltages and their distances, since this decreases the minimum LMS error [8]. The main drawback of this method is that the calibration signals should be implemented at least with the back-end ADC accuracy. In conventional implementations, voltage levels with more than 10-bit accuracy cannot be easily realized [7]. So, some methods are needed to alleviate the high accuracy requirement in calibration signals. B. Proposed Calibration Method In this section, the proposed method is described for 1.5-bit/stage with CNFA MDAC topology. Fig. 3 shows the proposed method for the calibration of ith stage named the error estimation with nonprecision calibration signals. The calibration process recursively works backward through pipelined stages. The procedure is explained for the state of PN =−1. So, firstly the input of the ith stage is connected to the ground and PN =−1 is injected. In this situation, VDACi=−(Vl+εl) for l={1,2,3,4}where Vlis the desired voltage level and εlis a random error due to the fabrication process. By substituting Vri=−VDACiin the MDAC model and assuming Vlεl, the output of the ith stage will be Vouti≈2(1−α1)(Vl+εl)−α3V3 l−α5V5 l.(8) When |Vl|>0.125 Vref, the signal given by (8) is entered to the (i+1)th stage and generates the digital output of D(i+1)=1. In contrary to the conventional pipelined ADCs, the same Vlis utilized in the sub-DAC of the (i+1)th stage and hence we have VDAC(i+1)=(Vl+εl). Furthermore, as shown in Fig. 3, one additional voltage level, VDACE =(Vl+εl),is subtracted from the input of (i+1)th stage. So, the residue voltage of the (i+1)th stage will be Vr(i+1)=Vouti−VDAC(i+1)−VDACE =−2α1(Vl+εl)+α3V3 l+α5V5 l ≡−2(α1εl+Vei)(9) where Veiis the error due to the ith-stage nonidealities. In system level, subtracting the additional voltage level is equivalent to add an extra 1-bit DAC in the (i+1)th stage using the (Vl+εl) voltage level. As seen in (9), the extra DAC output, VDACE, would be subtracted from the (i+1)thstage input in the sampling phase to attenuate εlby α1. So, by using this configuration, the effect of nonprecision calibration signals is significantly alleviated. Next, an equation should be derived for Ddibecause according to Fig. 2, it is used in the LMS machine to estimate the value of Dri. In an ideal ADC, Vei, and consequently, its digital value Dei, will be zero. So, according to (9), independent of the Vlvalue, the (N−1)-bit back-end ADC digitizes the value of α1εlwhich is negligible. In this situation, Ddiis also denoted by Dideal. It can be easily shown that Dideal is equal to 1,0···0,0.5where · is defined as the bit alignment operation. It means that the (i+1)th and 2-bit flash stages generate digital outputs equal to 1 and 0.5, respectively, and the digital code produced in other stages is 0. On the other hand, in a nonideal ADC, the ith stage feeds a nonzero error into the back-end ADC resulting in Ddias Ddi=Dideal −Dei=Dideal −α1Dri+α3D3 ri+α5D5 ri. (10) In driving (10), this fact that Vri=−VDACi=−Vlwas used. In (10), Dideal is independent of Vlwhile α1Dri+ ZEINALI et al.: DIGITAL BACKGROUND CALIBRATION TECHNIQUE FOR PIPELINED ADCs 325 Ground the ADC’s input and insert V l in i th stage after 0.5(i-1)T s V l ≈PN×V ref /2 Yes No Reconfigure (i+1) th stage D ideal = -PN×<1,1,…,1,1.5> D ideal = -PN×{1,0,0,…,0,0.5} Yes No D ri = -PN×<1,0,0,…,0,0.5> Yes No D ri = -PN×<1,1,0,…,0,0.5> D ri = -PN×<1,1,1,0,…,0,0.5> V l ≈PN×7V ref /16 D ei =D ideal -D di D ri = -PN×<1,1,…,1,1.5> update α’s when D ei =α 1 . D ri +α 3 .D ri3 +α 5 .D ri5 D di : Distorted digital value of D ideal D ei : Digital value of error in i th stage T s : Sampling period The length of vectors is N V l ≈PN×V ref /4 V l ≈PN×3V ref /8 Fig. 4. Proposed procedure for calibration of ith stage. α3D3 ri+α5D5 ridepends on the value of Vl. So, the different independent equations can be achieved by changing the value of Vlwhere Driis altered and Dideal is constant. For different values of Vl,Dideal and Driare shown in Fig. 4. In this figure, the values of Vlare specified for different quantities of Dri. For instance, in the case of Vl=3Vref/8, the value of Driis equal to −1,−1,0···0,−0.5which is extracted from a conventional ADC. Also, it should be regarded that the DAC voltages from the (i+2)th stage to the end are chosen between {−Vref/2,0,Vref/2} similar to the conventional pipelined ADCs. Therefore, in the ith-stage calibration, it is enough to add an extra 1-bit DAC in the (i+1)th stage and use the same voltage levels in the ith and (i+1)th stages. For the circuit implementation of the proposed method, when the ith stage is under calibration, the MDAC of the (i+ 1)th stage is reformed as in Fig. 5 where the fully differential circuit implementation of the extra 1-bit DAC is shown. During ith-stage calibration, an additional Vlis subtracted from the (i+1)th-stage input in its sampling phase 1, and so it does not need a higher resolution DAC. As shown in Fig. 5, this extra DAC is implemented in the MDAC structure with only four additional switches. The switches turn on in 2phase and add some extra series resistance in the amplifying path and hence degrading the stage amplifier settling performance. Besides, such implementation needs that the amplifier input and output common-mode voltages to be the same. For CFA MDAC, the relation (7) is utilized to model the ith stage, and the calibration procedure is performed in two steps. In the first step, the calibration signals of |Vl|<Vref/2 are applied to the ith stage where the stage is configured as a multiply-by-two circuit. In other words, VDAC is zero in (7) and the remained error coefficients can be estimated as Dl=(1+δ) 2−ρ1Dri−ρ3D3 ri−ρ5D5 ri(11) + − − + + − + − + − Fig. 5. Circuit implementation of extra 1-bit DAC in the CNFA MDAC structure. where Dlis the digital equivalent of Vl. In this case, VDAC in (i+1)th and (i+2)th stages is selected equal to Vl where the extra DAC voltages are subtracted through CF and CScapacitors in (i+1)th stage and CScapacitor in (i+2)th stage. It could be easily proved that εlwill be attenuated by ρ1. In the second step, the coefficient of VDAC in (7) is estimated. In this case, Viniis forced to zero and the calibration signal is applied through sub-DAC path. So, in this case, the estimation of error coefficient is similar to the CNFA structure. For the case of n-bit stages, there are 2nsampling units resulting in (2n−1) different error coefficients in sub-DAC’s path. Also, there are three error coefficients due to the amplifier nonidealities (by supposing a fifth-order modeling). However, to utilize the proposed method in multibit-per-stage case, the errors in sub-DAC should be firstly calibrated. So, using a linear DAC is a simple way and the best alternative is the dynamic element matching DAC [1], [2]. By using a linear DAC, the errors due to the amplifier nonidealities can be calibrated by the proposed method as well. C. LMS-Based Coefficient Extraction The LMS is a simple form of the steepest descent algorithm [8] where the correlation of error and input vector is replaced by a one-point sample multiplication. In this way, the parameters of (10) are estimated as e(n)=Ddi(n)−Dideal(n)− k={1,3,5} αk(n)Dk ri(n) αk(n+1)=αk(n)+μkDk ri(n)e(n)k={1,3,5}(12) where nis the update index and μ’s are the update step sizes of the LMS algorithm in coefficient extraction. The same procedure can also be done in the case of (11) as follows: First step: e1(n)=Dl(n)− α   (1+δ) 2−ρ1Dri + k={3,5} ρk(n)Dk ri(n) α(n+1)=α(n)+μαDri(n)e1(n) ρk(n+1)=ρk(n)+μkDk ri(n)e1(n)k={3,5}. 326 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014 Second step: e2(n)= β   (1−δ) 2Dl(n)+α(n)Dri − k={3,5} ρk(n)Dk ri(n) β(n+1)=β(n)+μβDl(n)e2(n). (13) In [8], the acceptable interval for the update step sizes is calculated such that it guarantees the stability of LMS algorithm. Here, the update parameters are selected using the relation given in [8] and by considering the compromise between the convergence time and the steady-state error. IV. BACKGROUND CALIBRATION METHOD A. Conventional Background Structure Tracking time-dependent variations in ADC performance requires the calibration process to work continuously. It means the background calibration is inevitable. There are several structures recommended to change the foreground methods to their corresponding background versions. The nonlinear interpolation method [6], [9], [10] suffers from the large delay between the sampled input and its corresponding digital output. Besides, this limits the maximum input signal frequency. The split structure [3] has the matching problem between the channels. The nested structure [12] needs extra power and area consumption in the reference ADC. Also, queue-based structures [13] suffer from the extra power consumption and silicon die area. In the following sections, a new method with prominent features is proposed to achieve an efficient background calibration scheme. B. Digital Adaptive Prediction Structure The linear prediction of a signal using an FIR filter is defined by Dpredicted(n)= L  i=1 Din(n−i)wi(14) where Lis the prediction order and wi’s are the filter coefficients. Also, Dpredicted and Din denote the predictor’s output and input, respectively. In prediction concept, the nth sample of the input signal is predicted by previous Lsamples. The prediction error is defined as the difference between (14) and the nth sample of the input signal. When this error converges to the minimum value, the optimal value of the filter coefficients is achieved. There are several methods to estimate the optimal value of wi’s [8]. One useful and common method is to use an adaptive algorithm. Here, by using the adaptive linear prediction, a background calibration structure is proposed in digital domain as shown in Fig. 6. While the ADC works in the normal conversion mode, the predictor updates its weight vector to minimize the error between the input signal and the desired value. The input vector and the desired value at the nth sample are as follows: Din(n)=[Dout(n−1), Dout(n−2),...,Dout(n−L)]T Ddesired(n)=Dout(n)(15) V in Outpu t z -1 m-bit m-bit Pipelined ADC input Desired Digital Predictor Calibration Mode 0 1 Calibration Mode 0 1 Calibration Mode 01 D out D predicted D in D desired Fig. 6. Proposed background calibration by using the prediction structure. where Dout(n)is the ADC’s output at the nth input sample and Tdenotes the transpose operation. When the ADC enters into the calibration mode, the predictor output is used as ADC’s digital output and Ddesired(n)=Dpredicted(n−1)in (15). To validate the performance of the proposed predictor in different calibration conditions, several simulation scenarios are examined. The filter length and skipping rate are two effective parameters on the predictor performance. Moreover, the skipping rate affects the calibration process. As the skipping rate is increased, the calibration time is decreased, while the predictor performance is also decreased. The MSE criterion between the output of the ideal ADC and the proposed background structure is utilized to evaluate the predictor performance. The MSE is defined as MSE =1 N N  n=1Dideal −Dproposed2(16) where Dideal and Dproposed are the outputs of an ideal 12-bit ADC and the ADC calibrated by the proposed architecture, respectively. In Fig. 7, the MSE is sketched for different skipping rates and ADC analog input frequencies where the filter length is 64. By skipping 10% of input signal samples, the maximum predictor MSE is below −75 dB in the Nyquist band. The MSE of the adaptive linear predictor is also sketched for different filter lengths and analog input signal frequencies in Fig. 8. As is seen, an adequate performance in the whole of input frequency band is achieved by a filter length of 64. By this selection, the predictor has the maximum MSE of −70 dB for Nyquist frequency although a proper performance in the middle input frequency is also achieved by a lower filter length. As seen in Figs. 7 and 8, the proposed adaptive linear predictor used to convert the foreground calibration algorithm to a background scheme can recover the skipped samples in the Nyquist band with a proper performance. Furthermore, the behavior of the calibration routine for input frequencies in the second Nyquist zone is almost similar to the Nyquist band. Moreover, because of using the prediction algorithm in the background structure, no further latency will be added to the digital outputs of the calibrated pipelined ADC. To evaluate the performance of the proposed background structure for other input signals, an autoregressive (AR) signal is utilized. The AR signal shown in Fig. 9(a) is obtained by filtering a white zero mean Gaussian random sequence ZEINALI et al.: DIGITAL BACKGROUND CALIBRATION TECHNIQUE FOR PIPELINED ADCs 327 0 10 20 30 00.2 0.4 0.6 0.8 1 -100 -90 -80 -70 -60 -50 Normalized frequency Skipping rate (%) MSE (dB) Fig. 7. MSE for different input signal frequencies and skipping rates of input samples. 0 50 100 150 00.2 0.4 0.6 0.8 1 -90 -80 -70 -60 -50 Normalized frequency Filter Length (L) MSE (dB) Fig. 8. MSE for different input signal frequencies and predictor lengths. through a sixth-order all-pole system. Fig. 9(b) shows the predictor convergence behavior by considering the MSE criterion defined as the difference between the input signal and the predictor output. Also, the performance of the background calibrated ADC is evaluated by using the MSE that is equal to −53 dB for a 10% skipping rate. The MSE can be improved by reducing the skipping rate but with an increased convergence time. V. CIRCUIT IMPLEMENTATION To prove the usefulness of the proposed calibration algorithm, a prototype 12-bit 100-MS/s pipelined ADC is designed in a 90-nm CMOS technology with 1.2-V power supply. The ADC input SHA is eliminated by time matching between the first-stage MDAC and sub-ADC paths [11]. A. Amplifiers and Comparators A two-stage Miller-compensated operational amplifier, shown in Fig. 10(a), comprising of two simple commonsource stages is used to realize the MDACs. The cross-coupled loads are used in the first stage to improve the amplifier DC gain as well as to establish the common-mode voltage at 0 0.1 0.2 0.3 0.4 0.5 -100 -80 -60 -40 -20 0 Normalized Frequency Normalized Power (dB) 0 100 200 300 400 50 0 -46 -44 -42 -40 -38 -36 Iterations MSE (dB) MSE in each iteration is calculated for 256 samples (b) (a) Fig. 9. (a) Spectrum of the AR input signal. (b) Predictor MSE. the first-stage output. A simple switched-capacitor commonmode feedback circuit is used to control the second-stage common-mode voltage. In sampling phase, both the first and second stages of the amplifier are reset. Minimum channel length devices are used in amplifying transistors to achieve higher bandwidth larger than 1.5 GHz in the first-stage MDAC. However, this limits the DC gain to only 38 dB. To reduce the power consumption and die area, the capacitors, amplifier devices, and bias currents are scaled down in the next stages. The time-matching requirement without the input SHA needs fast regenerative comparators in the first stage to ensure that the first MDAC has enough time for settling. A simple dynamic latch [14] shown in Fig. 10(b) is employed with a designed regeneration time less than 0.25 ns to realize the sub-ADCs. B. Reformed Decoder for Stage Sub-ADC Another important point in the circuit implementation is the time to produce the DAC voltage sign. In conventional MDAC structure, the stage digital output is produced at the beginning of the amplification phase, so, the DAC voltage sign is distinguished in this phase. However, in the proposed structure shown in Fig. 5, the circuit needs the DAC voltage sign in the sampling phase when it is in the calibration mode. So, the sub-ADC structure has been altered to eliminate this problem. As mentioned in Section III, in the calibration of the ith stage when PN is equal to −1, the digital output of the (i+1)th stage must be 1 in order to the extra 1-bit DAC to alleviate the destructive effect of nonprecision calibration signals. Also, in PN =1, the digital output must be −1.So, 328 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014 V inM1 M2 V in+ V out+ M10 V DD V outM3 M4 M5 M8 M6M7 M9 Φ 1 Φ 1 Φ 1 Φ 1 V cmfb M7 M9 V b V inM8 R C C c M5 M6 M3 M4 M1 M2 V out+ M11 V cmfb V DD V outM10 R C C c V in+ Φ 1 MS (a) (b) Fig. 10. (a) Amplifier architecture. (b) Dynamic latch. with this information, we can produce the digital output of the (i+1)th stage without comparators. Hence, the decoder at the output of the stage sub-ADCs is reconstructed as Fig. 11. In this figure, Qiand Qib are the comparator outputs and diis used as the multiplexer input in the sub-ADC configuration. When the (i+1)th stage is in the calibration mode (Ci+1=1), the PN is injected to the sub-DAC input. Also, when the ith stage is in its calibration mode (Ci=1), this configuration can produce the proper digital output in the (i+1)th stage. Another point in circuit implementation is the necessity of shift in controller signals coming from the under calibration stage to its next stage. Due to a half-cycle difference between two consecutive stages, the calibration signals coming from the previous stage should also be shifted by a half-cycle. C. Digital Implementation of the Predictor To prove the adequate performance of the proposed adaptive linear prediction, it was implemented in MATLAB with fixedpoint precision. To update the lattice filter coefficients, the Affine Projection Algorithm (APA) is utilized. The APA is based on affine subspace projections and it is a useful family of adaptive algorithms to speed up the convergence of the LMS algorithm especially for the colored signals. Whereas the LMS-type filter updates the weights based only on the current input vector, the APA updates the weights on the basis of the last Ninput vectors where Nis the affine order. The recursive algorithm called pseudo APA with Gauss-Seidel recursion (GS-PAP) is utilized to simplify the implementation [15]. The computational complexity of the GS-PAP algorithm is almost 2L+14Nper sample, whereas LMSs complexity is 2Lper sample. The further computational complexity is neglected against GS-PAP’s improvements [15], especially in higher values of L, where in the interpolation concept, a filter length of 122 is necessary [6]. Fig. 12 shows the implementation of the proposed digital background calibration scheme with fixed-point precision. This implementation is compatible with an ADC with 14-bit as the number of digital output comprised of twelve 1.5-bit/stage structure and one 2-bit flash ADC as the 13th stage. The first six stages are calibrated only for the achievement of 12-bit resolution. Since only 7-bit accuracy is considered in the calibration signals, the proposed error estimation method with nonprecision calibration signals is applied to the d2 d1 d0 b0 b1 Ci Ci+1 PN Ci Ci+1 Φ2 VDD PN (CiVCi+1) (CiVCi+1)(CiVCi+1)(CiVCi+1 ) Q1 Q0 Q1b Q0 Q1b Q0b Fig. 11. Decoder used in the (i+1)th stage sub-ADC. first four stages, and the other two stages utilize the ECS technique. In Fig. 12, the precision of each signal is specified by two digits. The first digit is the number of bits required to define each signal without overload and the second one is the number of bits for fractional points. The difference of these two digits is used for the sign and integer parts of a signal. In this implementation of GS-PAP algorithm, 28L+42N+78 bit memory is utilized. This figure also shows the maximum number of bits used at the output of GS algorithm. Although, in the middle frequencies, all the 22-bit will not be used, in frequencies near DC or Nyquist band, this number of bits is necessary. Because, in these cases, the approximation of the autocorrelation matrix needs more bits to suppress the overload in the calculation procedure. In Fig. 12, bis defined as an Nvector with only 1 in the first index and 0 in other indexes. Also, μis the update step size of the GS-PAP algorithm. Compared with the previous implemented or synthesized algorithms, the digital hardware cost comprising gate count and its overhead for power consumption could be approximately estimated in 90-nm digital CMOS technology. In this paper, the additional digital circuits are the 64-tap digital filter block for data prediction, the LMS machine to compute the error coefficients, and the blocks realizing thirdand fifth-order functions. On the other hand, a 122-tap filter is implemented in [6] for nonlinear interpolation where the gate-level synthesis of the logic for the combiner block, the nonlinear interpolation filter, and the calibration engine indicates a complexity of 17-K, 2.3-K, and 53-K gates, respectively. Also, the reported power consumption of the combiner block, interpolation filter, and calibration engine are 7.3, 1.15, and 1.8 mW, respectively, at 200 MHz. It is worth mentioning that the nonlinear interpolation algorithm utilized in [6] uses approximately the same digital hardware as used in the proposed approach. But, the digital engine in [6] is not used in every cycle. To reduce the digital hardware in the proposed calibration technique, the LMS algorithm can also be used instead of the GS-PAP one, but, with an increased convergence time and hence a degraded performance. VI. SIMULATION RESULTS The proposed background calibration method is evaluated in the context of a 1.5-bit/stage pipelined ADC with ZEINALI et al.: DIGITAL BACKGROUND CALIBRATION TECHNIQUE FOR PIPELINED ADCs 329 Corr. 14,13 14,13 μ14,14 Shift Register (N sample) 18,16 18,16 14,13 18,16 24,14 14,13 14,13 18,16 Dout UTShift Register (L sample) Shift Register (N sample) z-1 z-1 UT UT 18,16 Shift Register (N sample) z-L UT 18,16 z-1 20,16 b=[1,0,0,…,0]T 14,14 Gauss -Seidel Algorithm 22,10 z-1 } (N-1) Stage #1 Stage #4 Stage #5 Stage #6 Stage #7 Stage #12 2-bit Flash Calibration Mode 0 1 Vin Calibration Mode 0 1 Corr.Corr.Corr. Calibration Mode 0 1 Calibrated with the proposed method Calibrated with the ECS method Without Calibration 14,13 0.5 0.5 UTTranspose operator z-1 Delay unit Fig. 12. Digital implementation of the predictor with fixed-point elements. 12-bit resolution. The ADC has been simulated in a standard 90-nm CMOS technology with 1.2-V power supply and 100-MS/s sampling rate. It has twelve 1.5-bit stages with a 2-bit back-end flash ADC. To have a view on the value of error parameters, they are obtained for ADC’s first stage from the transistor-level simulations as α1=−0.04, α3=−0.11, and α5=−0.22. In this paper, in order to further relax the required analog circuits’ specifications and to better show the ability of the proposed calibration algorithm, the simulation results are reported by considering a fifth-order nonlinearity in the operational amplifiers. In practical implementations, the calibration can be also performed by considering a third-order nonlinearity and the proper design of amplifiers as well. As mentioned before, the calibration algorithm is applied only to the first six stages. In fact, the proposed error estimation method with nonprecision calibration signals is applied to the first four stages, and the other two stages use the ECS algorithm. The calibration procedure is commenced from the sixth stage and goes back to the first stage. This is because the proposed calibration algorithm is performed by assuming an ideal back-end ADC in the calibration of the ith stage. The accuracy of the calibration signals is limited to 7-bit where they can be easily implemented by the conventional resistive ladder. The analog circuits are simulated in HSPICE where the calibration process is implemented with MATLAB platform. It is worth mentioning that the design example is intended for 12-bit resolution while the accuracy of the calibration signals is limited to 7-bit. By considering the fact that 1-bit lower resolution is needed in every later stage, so, in the fifth stage, 7-bit resolution is needed and this can be achieved with the ECS technique. Therefore, instead of the proposed technique, the ECS approach is employed in the fifth and sixth stages in order not to use the extra DAC which is used in the proposed calibration technique. The output power spectral density (PSD) of the simulated ADC without calibration and with ECS calibration method is shown in Fig. 13(a) and (b), respectively. The simulated PSD using the proposed calibration algorithm is depicted in Fig. 14. The SNDR and SFDR are 40 and 42 dB, respectively, in noncalibrated ADC, and they are improved to 56 and 58 dB, respectively, by using the ECS calibration method in the first six stages. The SNDR and SFDR values are improved to 68 330 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 2, FEBRUARY 2014 0 1020304050 -120 -100 -80 -60 -40 -20 0 Frequency (MHz) Normalized PSD (dB) SNDR = 40.4 dB SFDR = 42.2 dB 0 1020304050 -120 -100 -80 -60 -40 -20 0 Frequency (MHz) Normalized PSD (dB) SNDR = 56.7 dB SFDR = 58.8 dB Accuracy of calibration signals > 7 bit (b) (a) Fig. 13. PSD of ADC’s digital output (a) before calibration and (b) with ECS calibration technique in the first six stages. and 83 dB, respectively, by applying the proposed calibration method. Figs. 15 and 16 plot the simulated DNL and INL before and after the calibration, respectively, at a sampling frequency of 100 MHz. The noncalibrated ADC has a maximum INL of ±50 LSB, while after calibration, the maximum INL is ±2.2 LSB. Also, the maximum DNL falls into +0.9LSBafter the calibration while before the calibration there are several missing codes. The ADC performance in the Nyquist band is evaluated by plotting the SNDR and SFDR for several input signal frequencies in Figs. 17 and 18, respectively. As seen, by using the proposed calibration algorithm, the values of SNDR and SFDR are considerably improved in whole of the input signal frequency band compared with the noncalibrated or calibrated ADCs by using the ECS method. It is worth to mention that because the equalization-based algorithms estimate the error coefficients independent of the input signal, the values of both SNDR and SFDR decrease when the input signal frequency is increased. Figs. 19 and 20 show the convergence behavior of the linear error coefficient (α1) and error in ADC’s first stage corrected by the ECS method and the proposed error estimation with nonprecision calibration signals algorithm, respectively. As seen, due to large errors in calibration signals, the convergence process in the ECS method has no proper situation, and the accuracy of estimation is limited to 7-bit. However, the proposed method has considerably better convergence behavior, and the accuracy of estimation is improved to 12 bits while the accuracy of calibration signals is only 7-bit. This means that 0 1020304050 -120 -100 -80 -60 -40 -20 0 Frequency (MHz) Normalized PSD (dB) SNDR = 68 dB SFDR = 83 dB fin = 9.86328125 MHz Input amplitude = -1 dBFS # of FFT points = 1024 Accuracy of calibration signals > 7 bit Fig. 14. PSD of ADC’s digital output with the proposed calibration technique. 500 1000 1500 2000 2500 3000 3500 4000 -1 0 1 DNL [LSB] 500 1000 1500 2000 2500 3000 3500 4000 -50 0 50 INL[LSB] Fig. 15. Simulated INL and DNL before the calibration. 500 1000 1500 2000 2500 3000 3500 4000 -1 0 1 DNL [LSB] 500 1000 1500 2000 2500 3000 3500 400 0 -2 0 2 Code INL[LSB] Fig. 16. Simulated INL and DNL after using the proposed calibration. the accuracy of calibration in the ECS technique is limited by the calibration signals, while the proposed calibration method improves that beyond the accuracy of calibration signals. For the calibration of each stage in the background structure, one frame with 213 samples is defined where 210 of them are only utilized for the estimation of the error coefficients, and the other frame samples are not skipped but are used in the normal conversion process. In fact, the foreground calibration process also need only upto 210 samples (with μ1=1/128, μ3= 1/4096, and μ5=1/8192). Hence, the total calibration time for background calibrated ADC or the start-up delay is equal to 491.52 μs with 100-MHz sampling rate. Also, it should be regarded that after the calibration of all stages, the calibration process is restarted from the sixth stage. Beside the simulation results, a quantitative analysis is provided to estimate the convergence time for different types