Using CAD tools for shortening the design cycle of high-performance sigma–delta modulators: A 16·4 bit, 9·6 kHz, 1·71 mW ΣΔM in CMOS 0·7 μm technology

Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 1 Using CAD Tools for Shortening the Design Cycle of HighPerformance ΣΔM: A 16.4bit 9.6kHz 1.71mW ΣΔM in CMOS 0.7μm Technology Fernando Medeiro, Belén Pérez-Verdú, José M. de la Rosa and Ángel Rodríguez-Vázquez Instituto de Microelectrónica de Sevilla-Centro Nacional de Microelectrónica Edificio CICA, C/Tarfia sn, 41012-Sevilla, SPAIN Phone #34 5 4239923, FAX #34 5 4231832 Abstract This paper uses a CAD methodology proposed by the authors to design a low-power 2ndorder ΣΔM. This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy metering mixed-signal ASIC and features 16.4bit at a digital output rate of 9.6kHz with a power consumption of 1.71mW. It yields a value of the figure which is the smallest reported to now, thus demonstrating the possibility to design high-performance embeddable ΣΔMs using CAD methodologies. I. INTRODUCTION Because of their reduced analog content and high tolerance to hardware imperfections, ΣΔ modulators are well suited to design high-resolution conversion front-ends in mixed-signal ASICs. This is illustrated by the ample variety of their already demonstrated applications, which span from instrumentation to video [1][2][3][4][5][6][7] based on the clever usage of a wide catalogue of modulator architectures: from simple low-order single-bit single-loop architectures with high oversampling ratio (M) [8], to elaborate high-order multi-bit, single-loop or multi-stage modulators with low M [9][10][11][12][13][14]. Low-power consumption is one of the basic design targets for embeddable analog-to-digital converters. Because reducing the power may compromise the bandwidth, we may resort to the classical figure-of-merit to classify different ADC ICs. However, by using this figure only converters with the same resolution can be compared among them. Recently, an alternative FigureOf-Merit (FOM) has been proposed which combines power, speed and resolution, to provide a more global view of the universe of ADC ICs [15]. For better fitting to the features of ΣΔMs, the original formula in [15] has been slightly modified here as follows: Power W () 2resolution bit()Output Rate(Hz)× ----------------------------------------------------------------------------- Power W () Output Rate(Hz) ---------------------------------------- © John Wiley & Sons. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 2 (1) where Output Rate is the sampling frequency divided by M (usually called DOR). For a given circuit, (1) gives the energy needed per conversion measured in picojoules, and allow us to classify the different low-power ΣΔM ICs reported in literature. Obviously, this classification is neither an absolute ranking, nor attempts to serve as an indicative of the quality of the analog design behind each modulator. It is only useful for illustration purposes. Actually, this is in the very nature of [15] where this FOM is used to quantify the yearly advances on ADCs reported at the International Solid-State Circuits Conference (ISSCC). During the last six years a number of ΣΔM ICs with FOM smaller than 10pJ have been reported − summarized in Table 1. We see that the smallest reported FOM is 2.1pJ − featured by a 4th-order ΣΔΜ in a BiCMOS technology [5]. For 2nd-order single-bit modulators, the smallest FOM corresponds to circuit in [16], which operates with only 1.5V supply to provide 12bit@6kHz using a 0.7μm CMOS technology. Larger resolutions in the audio range have been reported for this 2nd-order modulator at the price of larger power consumption and larger FOM values; namely, 16bit@[email protected] in 1μm CMOS technology with 5V supply voltage [17], and 15.3bit@[email protected] in 0.6μm CMOS technology with 1.8V supply voltage [18]. To design ΣΔM ICs for specifications at the state-of-the-art performance edges (i.e. with low values of the FOM) is a complicated and time-consuming task. Because at these performance edges TABLE 1. Summary of reported ΣΔ Modulators with FOM < 10 Resolution (bits) DOR (kHz) Power (mW) Process / Supply Architecture FOM (pJ) Yin and Sansen 94 [5] 15.8 1500 180 2μm BiCMOS / 5V Cascade 2-1-1 2.1 Medeiro et al. 95 [25] 14.8 160 10 1.2μm CMOS / 5V Cascade 2-2 2.2 Nys and Henderson 96 [28] 19 0.8 1.35*2 μm CMOS / 5V 2nd-Order, 3bit 3.2 Rabii and Wooley 96 [11] 15 50 5.4 1.2 μm CMOS / 1.8V Cascade 2-1 3.3 Yin et al. 93 [4] 15.7 320 65 1.2μm CMOS / 5V Cascade 2-1 3.9 Peluso et al. 96 [16] 12 6 0.1 0.7μm CMOS / 1.5V 2nd-Order 4.1 Brandt et al. 91 [17] 16 50 13.8 1μm CMOS /5V 2nd-Order 4.3 Baird and Fiez 96 [7] 13.7 1000 58 1.2μm CMOS / 5V 4th-Order, 4bit 4.5 Brandt and Wooley,91 [6] 12 2100 41 1μm CMOS / 5V Cascade 2-1, 3bit 4.8 Williams and Wooley 94 [14] 17 50 47 1μm CMOS /5V Cascade 2-1 7.2 Dedic 94 [29] 14.7 200 40 1.2μm CMOS /5V Cascade 2-2-2 (tri-level) 7.7 FOM Power W () 2resolution bit() Output Rate(Hz)× ---------------------------------------------------------------------------- 1 0 12 ×= Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 3 the operation is limited by non-idealities other than quantization (thermal noise, incomplete settling, finite opamp-gain, opamp nonlinearities, mismatches, jitter, etc. [19]) a large wealth of knowledge is required to understand the impact of these non-idealities on the modulator performance [4][8][19][20][21]. In addition, intensive optimization is needed to map the high-level specifications of ΣΔMs into working ICs. These difficulties result in the necessity to complete large design cycles, thus compromising the timely marketing of mixed-signal ASICs with embedded ΣΔMs and, hence, their economic success. To alleviate this problem a number of CAD tools and methodologies have been proposed during the last few years [22][23][24][25][26][27]. Unfortunately, only a few of these methodologies have been demonstrated through real working state-of-the-art prototypes. This paper uses the methodology proposed by the authors in [25] to design a 2nd-order ΣΔM whose measurements featured [email protected] with a FOM of only 2pJ. This modulator has been fabricated in a 0.7μm CMOS technology to be used as the front-end of an energy metering mixed-signal ASIC requiring to accomplish these specifications for a maximum input of 1V and with minimum possible power consumption. Architecture selection, modulator sizing and cell sizing were supported by CAD tools and completed in only one week by one engineer, while the full-custom layout, which was done manually, took about three weeks. II. A CAD METHODOLOGY FOR ΣΔM DESIGN Fig.1 shows the flowgraph of operations involved in the design of ΣΔM ICs. It comprises three different synthesis levels: (a) Modulator level: architecture selection and modulator sizing; (b) Cell level: topology selection and cell sizing; and (c) Layout level: full-custom layout of the modulator. In addition, supervisory simulations should be performed between each couple of levels − usually behavioural simulation between the modulator and cell levels; electrical simulations between the cell and layout levels and electrical simulation of the complete modulator including the extracted layout parasitics in the end of the design cycle. The CAD methodology presented by the authors in [25] uses a set of dedicated tools to support the most time consuming activities related to the design of switched-capacitor ΣΔM ICs, namely: 1. Modulator Architecture Selection: Depending on the modulator specifications, high-order and Grilo et al. 96 [18] 15.3 6 2 0.6 μm CMOS / 1.8V 2nd-Order 8.1 *. Although this ΣΔ converter includes digital filtering, the power computed here consumption corresponds only to the modulator. TABLE 1. Summary of reported ΣΔ Modulators with FOM < 10 Resolution (bits) DOR (kHz) Power (mW) Process / Supply Architecture FOM (pJ) Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 4 or multibit modulators with small value of M, or simpler architectures with larger M can be selected to minimize the power dissipation. This is realized with the help of a tool called SDOPT. 2. Modulator Sizing: The same tool is used to automatically obtain specifications for the building blocks in accordance to the modulator specifications. This is done by combining detailed equations relating the circuit imperfections and the noise they introduce at the modulator output, and a statistical optimization algorithm based on simulated annealing. 3. Behavioural Simulation: An advanced sigma-delta simulator (ASIDES) is used to validate the modulator sizing. This program incorporates a large number of building blocks (integrators, comparators, multibit quantizers, D/A converters, etc.) that can be combined in a netlist to define arbitrary modulator topologies. Each block can be considered ideal or defined by a detailed behavioural model that contemplates many of the non-idealities due to the circuit imperfections. Some distinctive features of the tool are: inclusion of thermal noise for the integrators, slew-limited two-pole model for their transient response; non-linearity of capacitors; opamp DC-gain and multibit ADCs and DACs; Monte-Carlo simulations to take into account Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 5 the mismatch in capacitor ratios, etc. 4. Cell Sizing: A cell level optimizer (FRIDGE) enables the automatic sizing of the building blocks to fulfil their terminal specifications with minimum power dissipation and occupation area. This tool is based on electrical simulation and optimization (either statistical - a set of heuristic has been introduced to accelerate the convergence of simulated annealing algorithms, or a guided algorithm based on the Powell‘s Method). In what follows we illustrate the use of this methodology and its related tools to achieve [email protected] using a switched-capacitor ΣΔM with the minimum possible value of the FOM, i.e. with the minimum possible power consumption. Such a design objective must be kept in mind at whatever level of the design flow. Particularly, a critical evaluation has to be performed regarding the trade-off between oversampling ratio and hardware complexity. Also, special effort has to be put in reducing the dynamic specifications of the amplifiers which often consume the 80% of the power. III. ARCHITECTURE SELECTION. At this level, some simplified equations are used to evaluate the power consumption of available single-bit modulator architectures. The possible benefit [28] of multi-bit quantization regarding Fig. 1. Operation flow in ΣΔ modulator design. System Simulation ok? LAYOUT CELL SIZING MODULATOR SIZING MODULATOR SELECTION CELL SELECTION Modulator Specifications Cell Specifications Cell Simulation ok? CELL LEVEL MODULATOR LEVEL Ci Co vivo - + S1 S1 S2 S2 Cl IQ v−v+vo+vo− Y I2 XE g2 −g2' g1 −g1' D/A I1 Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 6 power consumption is difficult to quantify in a general case due to the diversity of the techniques used to attenuate the influence of the DAC non-linearity [7][10][28][30][31]. Thus, such architectures will not be considered in this study. Let us assume that for whatever modulator the dominant error sources are quantization, thermal noise and incomplete settling noise. Other error sources like integrator leakage, capacitor mismatch and non-linearity, etc. are difficult to include in this simplified analysis and will be considered afterwards. For given resolution, b (bit), the dynamic range (DR) is evaluated as (2) where represents the reference voltage (full-scale input) of the modulator; and are the in-band power of quantization, thermal and incomplete settling noise, respectively. Let us consider that is controlled to be well below the other error sources. In such a case, (3) The two noise powers in (3) can be approximated as functions of only three design parameters: modulator order , oversampling ratio , and integrator sampling capacitor , as follows: (4) where is the Boltzman constant and is the absolute temperature. Note that in (4) quantization noise has been supposed to be an additive white noise and that the contribution of the first integrator to the in-band thermal noise has been considered dominant as compared to that of other integrators in the modulator loop. Using (3) and (4) it is possible to calculate a lower bound for the sampling capacitor for given 1. Once is known, the equivalent load of the first integrator opamp is evaluated as (5) 1. An absolute lower bound must be imposed regarding layout requirements. DR 32 2b1– ⋅Vr 22⁄ PQPTh PSt ++ ------------------------------------== Vr PQPTh and PSt ,, PSt DR Vr 22⁄ PQPTh + ----------------------≅ L M Ci PQ 2Vr () 2 12 ----------------π2L 2L1+()M2L1+ --------------------------------------≅ PTh kT MCi ----------≅ k T DR M and L,, Ci Ceq CiCpCl1CiCp + Co ------------------+ ⎝⎠ ⎛⎞ ++≅ Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 7 where an integrator like that of Fig.2 with single-stage opamp has been assumed. The opamp input and the integrator output parasitics, and , respectively, can be estimated as a fraction, , of the sampling capacitor. The feedback capacitor, , is also related to the sampling capacitor by the integrator gain. Assuming an integrator gain of 0.5, (5) is rewritten as (6) where and have been estimated as . To accomplish the previous assumption that , the unity gain frequency of the opamp, given by , should be large enough to render the settling error of the integrator negligible. A conservative choice is to make, (7) where represents the sampling frequency. This expression allows us to make an estimation of the transconductance needed in the opamps. At this point, in order to estimate the power consumption, one more assumption has to be made regarding the topology of the opamp used for the integrators: Let be the opamp a folded-cascode OTA with the same current, , flowing through the differential pair and the output branches. Assume also that the same current is used in the biasing stage. Thus, the total current spent by one opamp is . The current depends on the required as , where is the transconductance parameter of the input transistors. Once the tail current of the opamps has been estimated, the static power can be calculated as (8) where is the supply voltage. Note that L identical opamps have been considered for simplicity. On the other hand the dynamic power dissipated to commute a capacitor between the reference voltages can be approximated by . Using fully-differential circuitry there are Ci Co vo - +Cl Cp Fig. 2. SC integrator during the integration phase Cp Cl ζ Co Ceq 1ζ+()CiζCi1Ci1ζ+() 2Ci -----------------------++ 1 2,5ζζ2 2 -----++ ⎝⎠ ⎛⎞ Ci == Cp Cl ζCi PSt PQPTh ,« gm2πCeq ()⁄ gm2πCeq ()⁄5fS = fS IB 4IB IB gm IBgm 22β()⁄= β PWS 4IBVsupplyL= Vsupply Ci Pw2Vr () 2CifS = Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 8 6 commuting per integrator (assuming ). Thus, the dynamic power of the analog part of a LTh-order modulator can be approximated by, (9) In addition the dynamic power of the modulator digital part (quantizer, flip-flop and gates) has to be taken into account. However that power strongly depends on the number of quantizers in the modulator as well as the specific circuitry used to implement them. As a gross approximation we shall use the following expression: (10) where denotes the number of quantizers (latch + flip-flop + small logic), each of them with 10 equivalent inverters commuting with a power peak of 5mW within 1ns. The value of depends on the modulator architecture: It is one for single loop modulators and larger for cascade modulators. We will suppose a value . The above equations have been included into the modulator sizing tool, SDOPT, and used to estimated the FOM of several single-bit modulators architectures, from L = 2 to L = 6. Each architecture showed different suitability degrees for different regions of the resolution-bandwidth plane. We have found that for resolution around 17bit and above the lowest FOM corresponds to the 2nd-order modulator. This is because for those resolution levels the modulator output spectrum is thermal noise dominated. Thus, although the quantization noise can be reduced by using higher order modulators, the sampling capacitor cannot due to the thermal noise restriction, resulting in the same current per opamp. Fig.3 shows the estimated FOM as a function of the oversampling ratio to obtain 17bit@10kHz with several modulator architectures. The lowest FOM is featured by the 2nd-order modulator with oversampling ratio close to 300. According to these results, the 2nd-order single-loop ΣΔ modulator of Fig.4 with oversampling ratio equal to 256 was selected. IV. SWITCHED-CAPACITOR IMPLEMENTATION The modulator has been implemented using fully-differential switched-capacitor (SC) circuits. Ci Co2Ci = PWD analog,6L2Vr () 2CifS = PWD digital,10N5mW 1ns()fS ⋅= N N NL2⁄= Y I2 XE g2 −g2' g1 −g1' D/A I1 Fig. 4. Block diagram of the second-order modulator Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 9 Besides its robustness, this technique provides good suppression of common-mode interference. The integrator weights have been selected to minimize the required output-swing (OS) and speed of the two integrators. By using g1 = g1, = g2 = 0.25 and g2, = 0.5, the voltage swing at the integrator output is reduced so that the OS can be clipped at only the reference voltage, instead at twice the reference voltage as required using the classical choice g1 = g1, = g2 = g2, = 0.5. Fig.5 shows the SC fully-differential second-order ΣΔ modulator. Note that the opamp of the first integrator includes a chopper compensation technique to attenuate its offset and low-frequency noise. The second integrator has two branches to implement two different weights g2 and g2,. This is not necessary in the first integrator where the weights of the input and feed-back paths are the same. Modulator timing consists of two non-overlapping phases and two delayed versions of them used to avoid signal-dependent feed-through errors. A chopper phase is also needed. Switches with large voltage swing, identified as “sc” in the schematic, are complementary to get maximum linearity. Each clock phase and its complementary will be routed together in the layout to minimize the substrate noise. A. Modulator sizing The specifications for the building blocks and other design parameters at the modulator level have been optimized using SDOPT to obtain the values shown in Table 2. This optimization is based on a set of equations relating the non-idealities of the building blocks to the power of noise and/or distortion that they introduce in the modulator base band [8][19][21][25]. For instance, the opamp 10 100 1000 Oversampling ratio (M) 1 10 FOM (pJ/conversion) L=4 L=5 5 Fig. 3. Estimated FOM to obtain 17-bit resolution and 10-kHz DOR with several modulator architectures, as a function of the oversampling ratio. L=2 L=3 Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 16 B. Complete modulator Fig.11 shows a microphotograph of the modulator chip in 0.7μm CMOS single-poly technology which presents an active area of 0.42mm2 and consumes 1.71mW from a 5-V power supply. A twolayer board was fabricated to measure the performance of the modulator [33] with separated analog and digital ground planes, decoupling capacitors and signal filtering to attenuate the switching noise in the analog signal and biasing traces. The modulator was evaluated using a high-quality fully-differential programmable input signal source (THD < -100dB). A digital data acquisition system was used to generate the clock signal and to acquire the serial modulator output at the clock rate. Data were acquired automatically by controlling the test set-up with proprietary C routines and transferred to a Fig. 10. Measured transfer curve of the latched comparator Fig. 11. Microphotograph of the second-order ΣΔ modulator. Clock phase generator is also shown. CLOCK 1st INT. 2nd INT. COMP Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 17 workstation to perform the decimation filtering using MATLAB. Fig.12(a), (b) and (c) show the modulator output spectrum with chopper not activated for different input amplitudes and 1.25-kHz frequency. Note that the noise floor in the base band is flat (around -115dBV) and no large noise patterns are observed. On the other hand, total harmonic distortion for 1-V amplitude is below -90dB. Fig.12(d) shows the output spectrum for no input with chopper enabled and disabled. Note that, when chopper is active, the offset is significantly reduced. Measurements of the signal-to-noise ratio (SNR) and SNDR figures were obtained processing the modulator output bit stream with a digital filter implemented by software. Fig.13 shows both ratios for an input tone at 1.25kHz and oversampling ratios of 128 and 256 as a function of the input level. The dynamic range measured for M = 256 is over 100dB with a SNR-peak of 94.2dB corresponding to 1.2-V input and a SNDR-peak of 91.8dB for 0.8-V input. Respect to the case M= 128, the dynamic range is 92dB with SNR and SNDR peaks of 84.4dB for 1-V input. Measurements of the dynamic range versus the oversampling ratio for given clock rate, see 1 10 100 1000 10000 Frequency (Hz) -125 -100 -75 -50 -25 0 Amplitude (dBV) 1 10 100 1000 10000 Frequency (Hz) -125 -100 -75 -50 -25 0 Amplitude (dBV) 1 10 100 1000 10000 Frequency (Hz) -125 -100 -75 -50 -25 0 Amplitude (dBV) Fig. 12. Measured output spectrum of the modulator for (a) -32, (b) -2 and (c) 0-dBV amplitude and 1.25kHz input tone. (d) Effect of the chopper compensation. (a) (b) (c) 100 1000 10000 Frequency (Hz) -150 -130 -110 -90 -70 -50 -30 -10 Amplitude (dBV) CHOPPER ON CHOPPER OFF (d) Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 18 Fig.14, show that for M = 256 the modulator is just on the limit between the quantization noise limited region (slope=15dB/octave) and the white noise limited region (3dB/octave) − a consequence of the dominance of the incomplete settling noise. The modulator performance is summarized in Table 9 for three oversampling ratios M=128, 256 and 512. Note that, for the nominal value of M = 256, the FOM of the modulator is only 2pJ/conversion which is lower than those in Table 1. However the FOM increases for the two other values of M. This shows that the modulator has been optimized for the nominal oversampling ratio -100 -80 -60 -40 -20 0 Input Level (dBV) 0 10 20 30 40 50 60 70 80 90 100 dB SNR SNDR DR >100dB -100 -80 -60 -40 -20 0 Input Level (dBV) 0 10 20 30 40 50 60 70 80 90 100 SNR (dB) M=128 M=256 Fig. 13. Measured SNR and SNDR for an input tone of 1.25kHz and amplitude variable, (a) for M=256 and (b) for M=256 and M=128. In all cases the clock frequency was set to 2.56MHz. (a) (b) 5678910 log2(M) 60 65 70 75 80 85 90 95 100 105 110 DR (dB) 11 12 13 14 15 16 17 18 10 Effective resolution (bit) Quantization limited White noise M = 256 Fig. 14. Measured dynamic range versus oversampling ratio. limited Using CAD Tools for Shortening the Design Cycle High-Performance ΣΔM:... 19 and, although it is possible to obtain better resolution with higher values of M, the FOM increases as well. REFERENCES 1. B. P. Del Signore D. A. Kerth, N. S. Sooch and E. J. Swanson, “A Monolithic 20-b Delta-Sigma A/D Converter”. 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