Study, Design and Implementation of Neuromorphic Systems through a Spiking Boolean Computing Paradigm

UNIVERSIDAD DE SEVILLA DOCTORAL THESIS Study, Design and Implementation of Neuromorphic Systems through a Spiking Boolean Computing Paradigm Author: Álvaro Ayuso Martínez Supervisors: Dr. Gabriel Jiménez Moreno and Dr. Juan P. Domínguez Morales A thesis submitted in fulfillment of the requirements for the degree of Doctor of Philosophy in the Robotics and Computer Technology Lab. Departamento de Arquitectura y Tecnología de Computadores October, 2024 iii Declaration of Authorship I, Álvaro Ayuso Martínez, declare that this thesis, entitled “Study, Design and Implementation of Neuromorphic Systems through a Spiking Boolean Computing Paradigm”, and the work presented in it are my own. I confirm that: • This work was done wholly or mainly while in candidature for a research degree at this University. • Where any part of this thesis has been previously submitted for a degree or any other qualification at this University or any other institution, this has been clearly stated. • Where I have consulted the published work of others, this is always clearly attributed. • Where I have quoted from the work of others, the source is always given. With the exception of such quotations, this thesis is entirely my own work. • I have acknowledged all main sources of help. • Where the thesis is based on work done by myself jointly with others, I have made it clear exactly what was done by others and what I have contributed myself. v UNIVERSIDAD DE SEVILLA Abstract Escuela Técnica Superior de Ingeniería Informática Departamento de Arquitectura y Tecnología de Computadores Doctor of Philosophy Study, Design and Implementation of Neuromorphic Systems through a Spiking Boolean Computing Paradigm by Álvaro Ayuso Martínez In recent years, advances in transistor integration within digital computers have enabled them to be reduced to near-atomic scales, pushing this technology to its physical and thermal limits. This trend, which has also significantly increased production costs, reinforces the belief that Moore’s law is going to become obsolete in the coming years. However, although doubts may arise about the possibility of further improving the efficiency of digital computers, these disappear when considering the brain, which is the most powerful and efficient system known. It is not based on transistors but on neurons and achieves high performance with minimal power consumption, both characteristics emerging mainly from the massive parallelism inherent to the nervous system. Inspired by the principles of neuromorphic engineering, this work proposes replacing transistors in digital circuits with neurons to harness these benefits. By abstracting neuronal function, it is possible to apply Boolean algebra to the design of Spiking Neural Networks under specific conditions, in a similar way to how it is applied to the design of digital circuits. Thus, this work lays the foundation for spiking Boolean computation through the spiking implementation of basic logic gates, providing a systematic approach for designing these networks, which could be valuable for researchers in the field. It also explores the development of complex spiking blocks for specialized applications, in which the development of the spiking computer is highlighted, and presents an extensive set of experiments whose results demonstrate their correct functionality mainly on two different neuromorphic platforms, SpiNNaker and Dynap-SE. The final implementations have been shown to behave as expected in challenging environments and under conditions comparable to those found in biology. vii Acknowledgements “Don’t walk behind me; I may not lead. Don’t walk in front of me; I may not follow. Just walk beside me and be my friend.” – Albert Camus This doctoral thesis is the result of several years of hard work, during which my life has undergone many changes and during which I have had both good and difficult moments. I would like to leave a personal reflection for my future self: when you read these words, you will remember everything you never thought you were capable of doing but managed to do, who you were and what your dream was. Overcoming all the barriers I have encountered during these years would not have been possible without the indispensable support of all those who have accompanied me on this path, and I would like to take advantage of this special moment to be honest and dedicate a few words to some of them. First, I would like to thank my family for the support they have given me, especially during the last year and a half, as well as remembering two people who would surely feel very proud of this work, my grandparents Joaquín and Sebastiana, who passed away during its development. I will always remember you with affection. Throughout my life I have had many teachers who have instilled in me values that, together, have led me to be who I am today. I would especially like to thank one of them, Carmen Pinto Álvarez, for showing me music not as just another academic or professional career, but as a philosophy of life. For all the love and understanding you offered me for so many years, even when I had to say goodbye. Thank you very much. To my supervisors Gabriel Jiménez Moreno and Juan Pedro Domínguez Morales: thanks for your guidance and patience. Gabriel, your great interest in research, your vast knowledge and your personality totally transformed me as a student and made me born as a researcher. Juanpe, before I knew you, I already admired you for being the promise of the department. Inspired by the effort you put into your work, which gives it an exceptional quality, you have reminded me that there is no remarkable success without great effort. Thank you for teaching me everything you learned and for always looking out for the best for me. I will always be grateful for everything you have done for me in the last few years. Finally, I also would like to thank Ángel Jiménez Fernández, whose support has also been very important throughout these years, especially at the beginning, the most difficult moment for any PhD student. Thanks also to the rest of my colleagues of the Department of Computer Architecture and Technology and the Robotics and Computer Technology Lab., who support me and have been part of my daily life since I arrived more than three years ago. Special mention is given to Alejandro Linares Barranco for viii promoting research activity in the department and to Saturnino Vicente Díaz and Fernando Díaz del Río for their great work as its director and secretary, respectively. I am deeply grateful to all the amazing people I have had the opportunity to meet outside of Sevilla through my research activities. Thanks to Thorben Schoepe and Hugh Greatorex, who visited our department in 2021 and with whom I had the pleasure of working for a short period of time. Special thanks to Fernando Pérez Peña for the warm welcome at the Escuela Superior de Ingeniería of the University of Cádiz during my research visit in 2022, even though we had never met before. Thanks to everyone I connected with at the CapoCaccia Neuromorphic Workshop in 2023, including Luna Gava, Natasa Samardzic, Saray Soldado, Antony N’dri, Thomas Tiotto, Jules Lecomte and Luca Peres, among many others. Finally, I cannot forget here to mention some of the people with whom I had the privilege of spending months during my research visit to the Institute of Neuroinformatics at the University of Zurich and ETH Zurich also in 2023: Melika Payvand, Arianna Rubino, Farah Baracat, Héctor Ramírez, Ata Atabek, Katarina Vujic, Arianna Alonso, Josephine Loehle, Chiara de Luca and Saptarshi Ghosh. Thank you all for your support and company during times when I felt alone and far from home. This visit would not have been possible without the support of Giacomo Indiveri and the Neuromorphic Cognitive Systems group, which kindly hosted me. Thanks also to Kathrin Aguilar, for her kindness and effort in facilitating my visit to the institute. Now, it is the turn for very, very special people for me. First, I would like to mention three people with whom I share a common history. Pablo Sánchez Cuevas, Antonio Pérez Peña and Daniel Casanueva Morato, thanks for accompanying me since we started studying computer engineering. We have gone through all kinds of situations, including the pandemic, a year of adventures in Granada, and the return to Sevilla to start a new life. I must also mention Lourdes Durán López and Juan Pedro Domínguez Morales, my indispensable office partners, with whom I have shared an enormous amount of time since I arrived to the department. Thanks to all five of you for making my daily life at the university much easier, for your trust and for the incredible moments we experience every week. Here is a special mention to a very special person for me, Pablo Romero Sánchez. Thanks for offering me one of the most real and beautiful friendships that the university gave me, full of great moments and unwavering loyalty even in the most difficult situations. Your presence in my life has completely changed it during these last eight years. This work is dedicated to you. To all my people from Valverde del Camino: Pablo R., Irene, Gloria, Pablo Z., Guille, María, Luisa, Iuliana, Inma, Javi, Víctor and Viktor, among many others, thank you for welcoming me as one of your own for so many years. Valverde will always be in my heart. ix I also would like to thank the families, old and new. To the Romero Sánchez and Cote Llamas families for giving me a love that very few people have given me throughout my life and for treating me like another member of them. To the Romero Marín and Cote Pérez families... I wish you all the happiness and that your children grow up surrounded by love and health. Gael and Lia, your birth represents an important moment in your parents’ lives and I am very proud to have the opportunity to watch you grow up so close. Thank you all, those I have mentioned and those I have not, for being part of my life or having been part of it at some point during these last three years. This work has been supported by Spanish grants from the national research projects MINDROB (PID2019-105556GB-C33) and SANEVEC (TED2021-130825BI00), which have been used to cover some publication costs and also costs associated with the research visits. xvi 3.22 Example of an ECG data file’s MLII signal while using the delta modulator algorithm to extract on and off spikes. . . . . . . . . . . 54 3.23 Example of a 2-bit spiking counter processing an input spike train built from ECG data using the delta modulator algorithm. CO indicates when the counter overflows, while FO indicates when the filtering neuron fires. . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.24 Appearance of the application developed to interact with the realtime simulated spiking memory on SpiNNaker. . . . . . . . . . . . 56 3.25 Robotic platform used for the experiments carried out. A) Romeo BLE board. B) Adafruit HUZZAH32. C) HC-SR04 ultrasonic sensor. 56 3.26 Response of the system to the variation of distances at which the object is placed from the ultrasonic sensor. Output spikes are marked with red points and vertical lines. . . . . . . . . . . . . . . . 57 3.27 Experiment conducted on SpiNNaker to study the subthreshold dynamics of a LIF neuron by injecting input spike trains at frequencies of 1 Hz, 2 Hz, and 10 Hz. . . . . . . . . . . . . . . . . . . 58 3.28 Diagram of the implemented 3-state FSM. . . . . . . . . . . . . . . . 59 3.29 Spiking implementation of the 3-state FSM. The states are represented by the SR latches shown in green. Blue and red synapses are excitatory and inhibitory, respectively. Elements represented in orange are related to the forward transitions and triggered by SG1, while elements shown in pink are related to the backward transition from S3to S1and triggered by SG2. ...... 59 3.30 Results of an experiment conducted on the implemented FSM, operating at discrete times. The input spike trains are shown below the dotted line. Stop is used to reset the states, and start to set the state S1.OP contains the spikes required to operate, SG1indicates to advance to the next state and SG2indicates to return back to the previous state. The spikes fired by each of the states and transitions are shown above the dotted line. . . . . . . . . . . . . . . . . . . . . 61 xvii List of Tables 3.1 Overview of the implemented blocks, indicating where to find more detailed information on each of them. . . . . . . . . . . . . . . 24 3.2 Set of neuron parameters used on SpiNNaker. . . . . . . . . . . . . 26 3.3 Set of neuron and synaptic parameters used on Dynap-SE. . . . . . 26 3.4 Boolean behavior of 3-input OR, AND, and NOR gates. A "1" indicates that a spike is transmitted through the respective synapse (A,B, and C) or fired by the respective output neuron (OR, AND, and NOR). In the case of the NOR gate, it will fire only if a spike is transmitted through OP and there is no activity through A,Band C. 27 3.5 Results of the experiments carried out on the inhibition-based OR gate for different numbers of inputs (n) and different operating frequencies (f) on Dynap-SE. The ticks indicate that the expected behavior is obtained in any repetition, while the crosses indicate that the SNN is not able to operate correctly. . . . . . . . . . . . . . 33 3.6 Results of the experiments carried out on the inhibition-based AND gate for different numbers of inputs (n) and different operating frequencies (f) on Dynap-SE. The ticks indicate that the expected behavior is obtained in any repetition, while the crosses indicate that the SNN is not able to operate correctly. . . . . . . . . 34 3.7 Analysis of the resources used and the latency of each of the spiking logic gates. nrefers to the number of inputs and τto the time it takes for a spike to propagate through the union of a synapseandaneuron. .......................... 34 3.8 Abbreviation, description and value for each of the energy variables. 35 3.9 Analysis of the resources used and the latency of each of the designs related to the spiking memory which were implemented on SpiNNaker. nrefers to the number of inputs of the decoder, c refers to the columns of the matrix of D latches, i.e., the number of bits employed for each of the registers, and τrefers to the time it takes for a spike to propagate through the union of a synapse and aneuron................................... 43 xviii 3.10 Results of the experiments carried out on spiking ripple-carry adders for different numbers of bits (n) and different operating frequencies (f). The ticks indicate that the expected behavior is obtained, while the crosses indicate that the SNN is not able to operatecorrectly. ............................. 49 3.11 Analysis of the resources used and the latency of the high-level designs proposed related to the implementation of the spiking ALU. nrefers to the number of inputs, bto the number of bits and τto the time it takes for a spike to propagate through the union of a synapse and a neuron according to the parameters used. . . . . . 49 3.12 Analysis of the resources used and the latency of the high-level designs proposed related to the implementation of the spiking counter. brefers to the number of bits and τto the time it takes for a spike to propagate through the union of a synapse and a neuron according to the parameters used. . . . . . . . . . . . . . . . . . . . 53 xix List of Abbreviations EPSP Excitatory Post-Synaptic Potential IPSP Inhibitory Post-Synaptic Potential STDP Spike-Timing-Dependent Plasticity LTP Long-Term Potentiation LTD Long-Term Depression SNN Spiking Neural Network ANN Artificial Neural Network LIF Leaky Integrate-and-Fire ISI InterSpike Interval AEIF Adaptative-Exponential Integrate-and-Fire SNP Spiking Neural P CSS Constant Spike Source ECG ElectroCardioGram CPU Central Processing Unit ALU Arithmetic Logic Unit CU Control Unit FSM Finite-State Machine 1 Part I Thesis 3 Chapter 1 Introduction “The neurochemistry of the brain is astonishingly busy, the circuitry of a machine more wonderful than any devised by humans.” – Carl Sagan Over the past century, computers have evolved at an exponential rate, driving unprecedented technological advancements. These systems have become increasingly powerful and efficient, enabling vast amounts of mathematical calculations to be performed in ever-shorter times, thereby accelerating progress across all scientific fields. However, recent predictions suggest that this rapid progress could slow down considerably as technology approaches physical limits that may seem impossible to overcome. However, nature offers a solution that demonstrates that alternative paradigms, such as those seen in the brain, the most sophisticated computing system, can be used to overcome these challenges. This chapter explains the principles of brain functioning and its inherent properties, what neuromorphic engineering is, and how these engineers have designed new technologies inspired by the brain and the nervous system to bring the power and efficiency of the brain to artificial systems. Finally, an analogy is drawn between the fundamentals of digital circuits and the functioning of biological neural networks in an attempt to improve the understanding of the functions they perform, as well as to facilitate the design of new bioinspired systems by using a spiking computing approach, which could benefit from the inherent properties of the brain and whose exploration is the main focus of this work, thus being the main contribution of this thesis. 1.1 The brain and the nervous system Human beings, curious by nature, have tried throughout history to solve some of the most difficult questions regarding their own existence: Who are we? What are we? Why are we? These questions are a sample of the evolution of human thought and the precedents of modern science. Archaeological and 4Chapter 1. Introduction anthropological findings, such as cave paintings, symbolic figures, and burial practices, indicate that humans already asked these kinds of questions tens of thousands of years ago in prehistoric times. With the advent of ancient science, greater emphasis was placed on finding answers to these questions. In ancient Greece, Hippocrates (c. 460-370 BC) first postulated that the brain was the main cause of human thought and emotions. Moreover, in the Roman Empire, Galen (c. 129-200 AD) argued that the brain controlled the body through nerves. Although Aristotle (c. 384-322 BC) asserted that thought and emotions were caused by the heart, something that prevailed until the Renaissance, the emergence of the scientific method in the 15th and 16th centuries allowed science to greatly evolve, giving us a better understanding of the brain and its crucial role in biology. Today we know that Hippocrates and Galen were right. The brain is a complex organ that serves as the center of the nervous system. It is responsible for processing sensory information, regulating bodily functions, and facilitating thought, memory, and emotion. Structurally, the brain is divided into three major parts: the cerebrum, the cerebellum and the brainstem. The cerebrum, the largest part, is involved in higher brain functions such as decision making, problem solving, and planning. It is split into two hemispheres, each of which can be divided into different sections which specialize in different functions, as shown in Figure 1.1. The cerebellum controls coordination and balance, while the brainstem regulates essential functions such as heartbeat and breathing. Thanks to the Spanish scientist Santiago Ramón y Cajal, who is considered the father of modern neuroscience and received the Nobel Prize in Physiology or Medicine in 1906, we know that neurons, or nerve cells, are the basic building blocks of the brain and the nervous system (Cajal, 1906). They are in charge of receiving and transmitting information through electrical and chemical signals to facilitate communication within the brain and throughout the nervous system, and, although there are many different types of neurons, all of them have a common structure that consists of three parts: the dendrites, the soma and the axon, as shown in Figure 1.2. In addition, the whole neuron is surrounded by a plasma membrane that separates it from the external environment. At rest, i.e., when a neuron has not received any signals, this separation allows its internal medium to be approximately 10 times richer in potassium (K+)than the external medium, and the external medium to be approximately 10 times richer in sodium (Na+)than the internal medium. Calcium (Ca2+)and chlorine (Cl−)are also present in both mediums, but play a minor role in the resting state (Stevens, 1979). The constant exchange of these chemicals through pores in the neuron membrane, i.e., ion channels, allows an ionic charge balance to be reached between both mediums, producing a membrane potential of approximately -70 mV (Gerstner et al., 2014), known as the resting potential. 1.1. The brain and the nervous system 5 FIGURE 1.1: Brain functions by lobe, extracted from the Shirley Ryan AbilityLab, 2023 The soma, or cell body, contains the nucleus and various organelles that maintain cellular function and meet its metabolic needs. The dendrites are tree-like extensions of the soma that are sensitive to the appearance of neurotransmitters and are a key element in the rupture of the resting state. These neurotransmitters bind to specific receptors located in the dendrites, causing an Excitatory Post-Synaptic Potential (EPSP, positive) or Inhibitory Post-Synaptic Potential (IPSP, negative) per branch, depending on the type of neurotransmitter and receptor. Then, the dendrites perform the integration of these potentials, summing all EPSPs and IPSPs at the beginning of the axon, which is a long, slender projection of the neuron. If the resulting sum causes the membrane potential to reach a certain threshold, about -55 mV (Gerstner et al., 2014), an action potential, commonly called a "spike", is generated. Reaching this threshold potential causes voltage-gated sodium channels to open, allowing a rapid influx of Na+ions into the neuron, further increasing the membrane potential (depolarization) and opening adjacent voltage-gated sodium channels along the axon. In this way, the axon conducts the resulting electrical impulses away from the cell body toward other neurons or muscles in the form of a wave. This propagation typically occurs in only one direction due to the inactivation of voltage-dependent sodium channels as a consequence of membrane depolarization (Bear et al., 2020), which prevents backward 12 Chapter 1. Introduction proximity to biology in exchange for a greater or lesser computational cost, respectively, it is usually associated with an electrical circuit consisting of a resistor and a capacitor placed in parallel, i.e., an RC circuit (Abbott, 1999), which is shown in Figure 1.6. From this circuit, an equation can be derived that describes how the membrane potential of LIF neurons changes over time, as is shown in Equation 1.1 (Gerstner et al., 2014), where: •τmis the membrane time constant. •V(t)is the membrane potential at time t. •Vrest is the resting potential. •Rmis the membrane resistance. •I(t)is the input current at time t. In this equation, the input current, I(t), includes the currents generated in response to the integration of input spikes, which contribute to the changes in the membrane potential. In biological neurons, an action potential is generated once the membrane potential reaches a threshold potential (Vth), followed by the refractory period. However, this behavior is not represented in the basic RC circuit model, and therefore an additional mechanism should be introduced in the circuit to account for the threshold crossing and subsequent resetting of the membrane potential to its resting value. This leads to Equation 1.2, which must be considered in the simulation of LIF neurons. FIGURE 1.6: Representation of the LIF model as an RC circuit, inspired by Gerstner et al., 2014 τmdV(t) dt =−(V(t)−Vrest) + RmI(t)(1.1) V(t) = Vrest, if V(t)≥Vth (1.2) 1.2. Neuromorphic engineering and Spiking Neural Networks 13 There are several possibilities for the implementation of SNNs, which can be classified into three categories: software for simulation, dedicated hardware for simulation, and dedicated hardware for emulation. Popular simulation software libraries include PyNN (Davison et al., 2009), NEST (Gewaltig and Diesmann, 2007), Brian (Goodman and Brette, 2008), NEURON (Hines and Carnevale, 1997) and Nengo (Bekolay et al., 2014). For dedicated hardware simulation platforms, SpiNNaker (Furber et al., 2014), Loihi (Davies et al., 2018) and TrueNorth (Akopyan et al., 2015), which are fully digital, and BrainScaleS (Pehle et al., 2022), which is mixed-signal, are among the most widely used. These software libraries and hardware platforms support the implementation of various neuron models and simulate SNNs by performing mathematical computations based on the governing equations of these models, although both categories differ in the way in which resources are employed to perform these computations. While software libraries rely on general-purpose hardware, dedicated hardware platforms are specifically designed to optimize SNN simulation, allowing for larger networks and improved real-time performance. Finally, emulation platforms use the physical properties of electronic components to directly reproduce the neuron’s biophysics. The Dynap-SE chip (Moradi et al., 2017), also considered mixedsignal, is an example of such an emulation platform. This work focuses primarily on PyNN, SpiNNaker and Dynap-SE, which are further described below. NEST and Brian have also been used occasionally to verify the results of specific experiments. • PyNN (Davison et al., 2009) is a Python package designed to provide a standardized interface to build and simulate SNNs in different simulation environments. It aims to make it easier for neuroscientists and engineers to develop and share models by allowing them to write code that can be run on multiple backends, such as NEST, Brian, NEURON, SpiNNaker and BrainScaleS without any modifications. Thus, PyNN simplifies the process of switching between simulators, facilitating the comparison and validation of models and results across different platforms. • SpiNNaker (Furber et al., 2014), developed by the University of Manchester, is defined as a massively parallel multicore computing system that was designed to allow modeling very large SNNs in real time and whose interconnected architecture is inspired by the connectivity characteristics of the mammalian brain. In this work, the SpiNN-3 and SpiNN-5 versions (Rowley et al., 2019) were used, which consist of 4 chips and 48 chips, respectively, each one made up of 18 ARM968E-S cores operating at 200 MHz. Moreover, the SpiNN-5 version additionally has 3 FPGAs, allowing it to be connected to 6 other boards to make up a larger SpiNNaker machine. Regardless of the version, a 100 Mbps Ethernet connection is used as an I/O interface and to send scripts and commands to the SpiNNaker boards. While the SpiNN-3 board allows for faster simulations of small SNNs, the SpiNN-5 board has generally been used to simulate SNNs that required 14 Chapter 1. Introduction more resources than those available on the SpiNN-3 board with a higher computational and time cost. SpiNNaker initially supports five PyNN neuron models, one of which is an Izhikevich model and the other are different variations of the LIF model, although it also supports the implementation of up to 13 extra models and the definition of new custom models by the user (Rhodes et al., 2018; sPyNNaker, 2015). • Dynap-SE (Moradi et al., 2017) is a neuromorphic platform for realtime spike processing developed by SynSense, a technology company from Switzerland specializing in neuromorphic computing that closely collaborates with the University of Zürich and ETH Zürich. In this work, a Dynap-SE1 board consisting of 4 chips was used. Each chip can accommodate up to 256 DPI neurons (Indiveri et al., 2011), which are equivalent to Adaptative-Exponential Integrate-and-Fire (AEIF) neurons (Qiao et al., 2015; Brette and Gerstner, 2005) configurable to behave like LIF neurons. It also supports four different types of synapses, which are totally inspired by the two major types of excitatory synapses, AMPA and NMDA, and the two major types of inhibitory synapses in the nervous system, GABA A and GABA B (Gerstner et al., 2014). The differences between these synapses involve not only their excitatory or inhibitory nature but also the speed at which their ion channels open in response to specific neurotransmitters. For instance, AMPA synapses have fast ion channel speed, while NMDA channels are slower. Similarly, the ion channel speed of GABA A is much higher than that of GABA B. Figure 1.7 shows how, in biology, the postsynaptic currents would change after a spike arrives at a postsynaptic neuron depending on the type of synapse. FIGURE 1.7: Dynamics of postsynaptic currents that appear after a single spike arrives at the postsynaptic neuron at t = 0 depending on the type of synapse, extracted from Gerstner et al., 2014 1.3. Spiking Boolean computation 15 1.3 Spiking Boolean computation The definition of what a computer is may give rise to a long philosophical discussion; let it be defined as a machine that can be programmed to automatically carry out sequences of arithmetic or logical operations. Although a large number of instruments designed throughout our history before the 20th century could be considered computers, it seems clear that there was a turning point in its evolution: the appearance of the mechanical computer, with Babbage’s analytical engine in the early 19th century (Bromley, 1982). Thus, computers were primarily analog until the advent of transistors, i.e., semiconductor devices which were particularly effective at switching electrical signals, in the mid-20th century (Riordan, 2004). Shortly before, Claude Shannon had demonstrated that it was possible to systematically apply Boolean algebra to electrical circuits (Boole, 1847; Shannon, 1938), which allowed for the design of electrical circuits whose behavior was defined by complex truth functions based on three basic elements such as OR (conjunction), AND (disjunction) and NOT (negation). Shannon’s work and the advent of transistors, in combination, led to a great improvement in logic gates, devices used to perform Boolean functions which were already being used in analog computers. Figure 1.8 shows an example of a transistor-based AND gate built using BJTs (Bipolar Junction Transistors). These improved logic gates led to the emergence of the digital computer, which was characterized by higher accuracy and lower error, size and cost than the analog computers that had preceded it. From this point, there is no doubt that digital computers have not only brought about an unprecedented technological revolution throughout the 20th century, but also that their impact, not only technological but at all levels, has grown exponentially up to the present day. This is mainly thanks to the significant increase in the computational power of digital computers over the last 50 years, driven by the exponential growth in the number of transistors they contain, which followed the predictions of Moore’s law (Moore et al., 2006). However, despite being called a "law", Moore’s law may soon no longer apply. This is largely due to the challenges associated with the continued miniaturization of transistors in electronics. Advances have pushed transistors to near-atomic scales, thus approaching physical and thermal limits, resulting in significantly higher production costs (Shalf, 2020). However, the industry increasingly needs more powerful computers without significantly increasing their power consumption. How could these limits then be addressed? Science is searching for new alternatives to prevent the imminent stagnation in the evolution of digital computers. Currently, many of them are being studied and are the focus of great research efforts by engineers, such as the three-dimensional integration of transistors, the search for new materials that can replace silicon and provide new advantages in the manufacture of these transistors, or even the replacement of the transistors themselves as 16 Chapter 1. Introduction FIGURE 1.8: General design of an AND gate using BJTs the basic element of computing, as occurs in quantum computing or optical computing, where information processing is carried out by qubits and photons, respectively. One of the most promising fields in this regard is neuromorphic engineering, introduced in Section 1.2, which has seen how doubts about the power consumption of digital computers could disappear considering the main element of study in this field: the brain. It only needs about 20 watts to operate (Balasubramanian, 2021), which is much less than the power consumption of today’s computers, i.e., typically between 30 and 500 watts; however, the brain is clearly more powerful than any of them when navigating complex problems that require high levels of cognition. On the other hand, while the human brain contains approximately 86 billion neurons (Herculano-Houzel, 2009; Azevedo et al., 2009), the number of transistors in a CPU is generally less than 100 billion, according to Lundstrom and Alam, 2022. Therefore, the number of basic computing elements is similar in both systems, so... where does efficiency come from? Carver Mead stated that the main factor that makes the brain much more efficient than digital computers is the parallelism inherent to the nervous system, the essence of which lies in the large number of synapses that can be found in it (Mead, 1990). Taking this as inspiration, it can be deduced that a great increase in the degree of parallelism of digital systems could be another great solution to the search for reducing the power consumption of the transistors contained in them, which, in fact, would make it possible to reduce operating voltages and frequencies without losing computational power (Kim et al., 2003). In these systems, parallelism is often significantly improved by directly replicating hardware resources. For example, in multicore processors, multiple identical cores are integrated into a single chip, each 1.3. Spiking Boolean computation 17 capable of executing instructions independently. Similarly, in multiprocessor systems, entire processors are duplicated, enabling multiple processors to work in parallel. This replication increases the number of elements that can be used to execute instructions simultaneously, thus improving the system’s overall parallel processing capability. However, this differs from the nervous system, where its high connectivity allows neurons to participate in multiple operations simultaneously. Thus, neurons are not simply replicated, but are reused to engage in different functions at the same time. It would be similar to reusing existing logic gates in digital systems to build many different complex circuits instead of replicating them, which would be challenging, since transistors are limited by their fan-in and fan-out capabilities, i.e., the maximum number of inputs and outputs they can handle, respectively. Neurons, however, are not so limited, so... What if a paradigm shift was applied to increase the parallelism of current systems? Ideally, this paradigm shift would involve redefining the fundamentals of computing by transitioning from transistors and logic gates to biological neural networks built to perform specific functions. Thus, implementing these changes would present two major challenges. First, it would be necessary to find a way to maintain the optimal functioning of neurons that could easily die in inappropriate environments. Second, there are still many unknowns regarding the architectures of the neural networks found in the nervous system and the specific functions they perform. One possible solution to the latter problem would be not to eliminate the logic gates, but only to replace the transistors that form them with neurons. This would require a high-level abstraction of the functioning of neurons, such that the membrane potential would not be taken into account, but only whether or not they generate spikes. Thus, the information would be summarized in the existence or absence of spikes that would propagate, or not, to each of the postsynaptic neurons. This abstraction would make it feasible to implement Boolean logic using neurons, so that any digital component with a specific truth function could also be implemented using this new paradigm. Taking advantage of the fan-in and fan-out capabilities of neurons, these new architectures could greatly optimize the number of resources used to perform many different operations, thus benefiting from improved parallelism. In this way, each neuron would provide the result of a Boolean operation that could be forwarded to another neuron, thereby performing complex Boolean functions. This work focuses on the implementation of these new spiking Boolean architectures, which are based on SNNs to achieve closer proximity to the functioning of the nervous system. The most basic logic gates (OR, AND and NOT), which form the base of Boolean algebra, will be presented first. Following Boolean algebra, the combination of these basic spiking logic gates makes it possible to build blocks that perform any complex Boolean function. Some of these complex blocks will also be presented in the following sections. Although 18 Chapter 1. Introduction the implementation of spiking logic gates has already been studied in other works, the approach applied in each of them differs from the approach of this work. For example, in Song et al., 2016, the implementation of spiking logic gates based on Spiking Neural P (SNP) systems is carried out. However, the rules these systems apply to compute are usually far from the complex equations used in the neuron models presented in Section 1.1, and thus they are not that close to biology as SNNs. In other works, SNNs were employed to implement spiking logic gates but using different methods. In Reljan-Delaney and Wall, 2017, the AND and XOR gates were implemented by assigning specific firing rates to Boolean values one and zero and building a fully connected SNN with synapses that had to be fine-tuned to perform Boolean operations. This network did not always operate correctly, as in the case of the AND gate. Moreover, since firing rates are used, combining these blocks to perform complex Boolean functions could be challenging. The output firing rates should be precisely adjusted to match the expected input rates of the subsequent blocks to ensure the correct representation of ones and zeros. Furthermore, fine-tuning the weights of the synapses in the SNNs to achieve the desired behaviors introduces uncertainty and makes it more difficult to understand the network’s functioning. Finally, in Mo and Wang, 2021, the STDP learning mechanism was used to implement a fully connected SNN that was trained once per specific logical operation and which was taken as a building block that could be combined to perform more complex functionalities. However, the number of neurons and the number of synapses required to implement this building block are large, which could pose a problem in terms of scalability, since these are very limited in neuromorphic software and hardware. In conclusion, the approach chosen for the development of these networks aims to facilitate the spiking implementation of Boolean logic, especially in terms of determinism and scalability, and also to help neuromorphic engineers lay a knowledge base to facilitate the understanding of how to optimally build function-specific SNNs. The development of this doctoral thesis is framed within the Robotics and Computer Technology research group (RTC), to which I belong, and which has been and is strongly linked to the field of neuromorphic engineering thanks to its great scientific production, which includes a great amount of articles published in high impact factor journals, the development of other doctoral theses, national and international collaborations, and a series of research projects that have served to finance the research activity that has enabled the development of this doctoral thesis, such as: • MINDROB: Percepción y cognición neuromórfica para actuación robótica de alta velocidad (PID2019-105556GB-C33). • SANEVEC: Un enfoque basado en simulación para determinar el despliegue de una red urbana de estaciones de recarga de vehículos eléctricos con beneficios medioambientales y sociales (TED2021-130825BI00). 1.3. Spiking Boolean computation 19 which have not only paid for the publication costs of the published articles, but also for the research visits without which it would not have been possible to achieve the results obtained. 21 Chapter 2 Objectives This doctoral thesis is mainly focused on the design and implementation of SNNs that are capable of performing Boolean functions, starting with the spiking logic gates and, subsequently, implementing more complex spiking blocks that are analogous to several digital components by combining previous designs. In order to achieve this main objective, a series of tasks had to be carried out, which are detailed below: 1. Previous study of the elements involved in the development of the work (a) Study of the biological mechanisms and behaviors existing in the nervous system based on neuroscientific knowledge. (b) Exploration and comparison of the different existing paradigms for the development of bioinspired systems. (c) Study of Spiking Neural Networks and the different neuron models that can be used for their implementations. (d) Exploration and comparison of neuromorphic software and hardware for the design and implementation of Spiking Neural Networks. 2. Design and implementation of blocks capable of performing Boolean functions based on Spiking Neural Networks. (a) Design of each of the blocks using free software tools, justifying each of the resources used. (b) Optimization of each of the designs, reducing the number of resources needed for their implementation. (c) Implementation of the blocks on SpiNNaker, testing their functioning in constrained environments and under ideal conditions. (d) Implementation of the blocks on Dynap-SE, thus testing their functioning in conditions closer to those found in the nervous system. (e) Analysis of results and verification of expected behaviors. 28 Chapter 3. Summary of results FIGURE 3.1: a) Design of a 3-input OR gate implemented on SpiNNaker. b) Design of the OR gate modified for its implementation on Dynap-SE. The yellow neuron is used to add a delay in the propagation of the spikes, the red neuron is the NOR neuron, and the green neurons are the output neurons. precisely configure the synaptic weights and delays on SpiNNaker to achieve this behavior. In this way, it consisted of only two neurons, where the first neuron was an OR gate that would fire whenever an input spike was received, generating an inhibition of weight n−1 on the second neuron, where nis the number of input synapses. These synapses also reached the output neuron, but with an added delay to allow the input spikes to arrive at the same time as the inhibition generated by the OR gate. Thus, it would only fire if the excitation was greater than the inhibition, i.e., only if nspikes were received. Finally, the NOT gate consists of a single neuron that must be inhibited when the input to be negated transmits a spike, for which an inhibitory synapse is used, thus preventing the neuron from firing. However, the opposite case implies the generation of an output spike when no input spike is received, which gives rise to one of the biggest problems found in the design of spiking blocks. Does it make sense to generate spikes without them being received in any way? Where does this energy come from? Originally, to solve this problem, a block called "Constant Spike Source" (CSS) was designed, which was in charge of generating a spike in each simulation time step in SpiNNaker. This was achieved by initially injecting a spike using a spike generator into a neuron that was connected to another recurrently so that each caused the other to fire. There is biological evidence of the presence and functionality of these recurrent neural networks in the human brain, which underlie memory formation (Casanueva-Morato et al., 2022), as they 3.2. Spiking implementation of OR, AND and NOT gates 29 FIGURE 3.2: a) Design of a 3-input AND gate implemented on SpiNNaker. b) Design of the AND gate modified for its implementation on Dynap-SE. The blue neuron is the OR gate, the yellow neuron is used to add a delay in the propagation of the spikes, the red neurons are the NOT neurons, and the green neurons are the output neurons. allow energy to be retained cyclically in the form of spikes. The design of the CSS block is presented in Figure 3.3, which also shows the usual way it was connected to a NOT gate to obtain the desired behavior. This block was also exploited to create a new design of the AND gate, which operated faster. These designs were implemented and tested on SpiNNaker. Although only a limited number of experiments were conducted, this is justified by the expectation that identical results would be obtained under identical conditions, since all the experiments were based on a strict simulation of the equations mentioned in Section 3.1. The correct operation of these blocks on the platform was successfully verified. Figure 3.4 presents an extract of a trace of an experiment carried out on the implementation of a 4-input AND gate. It shows how input spikes transmitted through synapses A,B,C, and Dcaused the OR gate to fire one time step later due to the propagation delay. Whenever spikes were transmitted simultaneously through all input synapses, the AND gate fired after two time steps. Similarly, Figure 3.5 presents an extract of a trace of an experiment carried out on the implementation of a NOT gate connected to a CSS block. In this figure, it can be seen how both the CSS block and the NOT gate fired at each time step of the simulation until input spikes were transmitted through the input synapse A. When this occurred, the NOT gate was prevented from firing in the subsequent time step due to the inhibition applied to the output neuron. 30 Chapter 3. Summary of results FIGURE 3.3: Design of a NOT gate, provided with input spikes by means of a CSS block to operate, whose neurons are represented in yellow. The neuron with the SG label is a spike generator which only fires once. The green neuron is the output neuron, i.e., the NOT gate. These traces were generated using some functions defined in "sPyBlocks", which is a Python package that was developed to make it easier for researchers to work with the implemented spiking logic gates and can currently be found in the first of the public repositories mentioned above. This package defines a custom Python class for each block, using PyNN functions to implement the design on object initialization. These classes include connection functions that relieve the user from working at the neuron level when interconnecting blocks, and which are also used for building more complex blocks. Thus, more complex classes were created by combining the simplest spiking logic gates. Although the implementations behaved as expected on SpiNNaker, these spiking blocks did not work well at all when implemented on Dynap-SE, as some limitations that might occur in a more realistic environment had not been considered. First, it was observed that, when neurons received more than one spike at the same time from multiple excitatory synapses, they stopped firing, which could find its biological counterpart in neuronal death due to overexcitation (Dodd, 2002). In other cases, the implementations performed as expected. Then it was decided to look for a way to avoid the use of multiple excitatory synapses to prevent overexcitation. In this way, new designs were developed that were not based primarily on excitatory synapses, but on inhibitory synapses, for which De Morgan’s laws were used to reach Equation 3.1 and Equation 3.2. In these equations, the negation of each of the logic values involved can be achieved by using NOT gates. 3.2. Spiking implementation of OR, AND and NOT gates 31 FIGURE 3.4: Extract of a trace of an experiment conducted on a 4-input AND gate on SpiNNaker. A "1" indicates that a spike is transmitted or fired. Spikes from the input excitatory synapses are shown in blue, those from the OR gate, which inhibit the output neuron, are represented in red, and spikes from the output neuron are shown in green. FIGURE 3.5: Extract of a trace of an experiment conducted on a NOT gate on SpiNNaker. A "1" indicates that a spike is transmitted or fired. Spikes from the input inhibitory synapse are shown in red, those from the CSS block are represented in blue, and spikes from the output neuron are shown in green. A+B+C=A+B+C=A·B·C(3.1) A·B·C=A·B·C=A+B+C(3.2) After that, another observation was made. By connecting a postsynaptic neuron to multiple presynaptic neurons via inhibitory synapses and to another presynaptic neuron via an excitatory synapse, the postsynaptic neuron fired only when no spikes were transmitted through the inhibitory synapses and there was activity through the excitatory synapse. This behavior is equivalent to the NOR operation, whose truth table is included in Table 3.4. This finding was one of the key points of the progress made while using Dynap-SE, as it improved the robustness and bioplausibility of the implementations. Moreover, NOR gates are an essential alternative to OR, AND and NOT gates in Boolean logic. Since they could be implemented using only one neuron, this also highlighted a clearer path for resource optimization. Finally, a general modification was also introduced in which the CSS block was eliminated, following a suggestion received in one of the review processes 32 Chapter 3. Summary of results of the currently published papers. From this point on, the spiking blocks no longer operated discretely at a fixed frequency as occurred on SpiNNaker, but only when expected to do so, which was consistent with the asynchronous nature of SNNs. This directly affected NOT gates, which were the main reason why this CSS block was initially implemented. Thus, NOT gates required a new source of events that indicated when to operate, for which different possibilities would arise depending on each design and the conditions under which they had to operate. This will be reflected especially later on, when the construction of complex spiking blocks is discussed in more detail. Taking into account Equation 3.1, Equation 3.2 and the latter considerations, inhibition-based designs were developed for the OR and AND gates. These new designs, which are shown on the right (b) of Figure 3.1 and Figure 3.2, respectively, also introduced the concept of using additional neurons to generate delays in spike propagation, which is often used in the design of SNNs. This approach was used to control the timing of the spikes and to achieve the desired behavior of each of the blocks without relying on the delays of the synapses on Dynap-SE, which, as was previously mentioned, are neither adjustable nor fixed. The implementations of these designs were rigorously tested through an extensive series of experiments to verify the correct behavior of both gates by varying the number of inputs and the operating frequency. These mainly examined inhibition-based OR and AND gates with 2, 3, 5, 10, 15, 20, 25, 30, 40, 50, and 60 inputs, while operating at maximum frequencies of 0.5, 1, 2, 5, and 10 kHz on Dynap-SE, although some tests were previously carried out on SpiNNaker. Since such experiments on Dynap-SE depended on external conditions, unlike SpiNNaker, all of these experiments were repeated three times to ensure that consistent conclusions could be drawn. Figure 3.6 shows the results of an experiment carried out with a 5-input OR gate, and Figure 3.7 shows the results of an experiment carried out with a 3-input AND gate, both operating at a maximum frequency of 5 KHz. FIGURE 3.6: Test of a 5-input inhibition-based OR gate operating at a maximum frequency of 5 KHz on Dynap-SE. δrefers to the delay added by neurons and synapses while propagating spikes in the output path. 3.2. Spiking implementation of OR, AND and NOT gates 33 FIGURE 3.7: Test of a 3-input inhibition-based AND gate operating at a maximum frequency of 5KHz on Dynap-SE. δrefers to the delay added by neurons and synapses while propagating spikes in the output path. TABLE 3.5: Results of the experiments carried out on the inhibitionbased OR gate for different numbers of inputs (n) and different operating frequencies (f) on Dynap-SE. The ticks indicate that the expected behavior is obtained in any repetition, while the crosses indicate that the SNN is not able to operate correctly. f (KHz) / n 2 3 5 10 15 20 25 30 40 50 60 0.5 ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ 1✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ 2✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ 5✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ 10 ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ The results of all the experiments are summarized in Table 3.5 and Table 3.6. In the case of the experiments performed with the inhibition-based OR gate, their results demonstrated its proper functioning, except while operating at a frequency of 10 KHz. This was similar for the inhibition-based AND gate, in which one of the experiments performed with 3 inputs also failed while operating at 5 KHz. It was concluded that this was most likely due to the fact that, because the operating frequency was quite high, the spikes arrived when the neurons were in the refractory period, which prevented the Boolean behavior of the block. Furthermore, the experiments indicated how inhibition-based AND gates with 40, 50 and 60 inputs were not able to operate correctly, even when operating at frequencies that were not considered high, which was due to limitations in the use of spike generators on Dynap-SE. Once the implementations were performed and tested, an analysis of the resources used and the latencies obtained for each of them was carried out, which is shown in Table 3.7. In this analysis, two key considerations must be discussed. First, it is assumed that only one synapse is used to provide the spikes that indicate to NOT and inhibition-based OR and AND gates when to operate. However, multiple synapses could be employed for this purpose depending on the neural network’s design requirements, thus increasing the number of 34 Chapter 3. Summary of results TABLE 3.6: Results of the experiments carried out on the inhibition-based AND gate for different numbers of inputs (n) and different operating frequencies (f) on Dynap-SE. The ticks indicate that the expected behavior is obtained in any repetition, while the crosses indicate that the SNN is not able to operate correctly. f (KHz) / n 2 3 5 10 15 20 25 30 40 50 60 0.5 ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✗ ✗ ✗ 1✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✗ ✗ ✗ 2✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✗ ✗ ✗ 5✓ ✗ ✓ ✓ ✓ ✓ ✓ ✓ ✗ ✗ ✗ 10 ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ ✗ TABLE 3.7: Analysis of the resources used and the latency of each of the spiking logic gates. nrefers to the number of inputs and τto the time it takes for a spike to propagate through the union of a synapse and a neuron. Block Neurons Synapses Latency OR 1 nτ AND 2 2n+1 2τ NOT 1 2 τ Inh.-based OR 3 n+4 2τ Inh.-based AND n+2 3n+2 2τ resources used. Second, the values shown in this table apply if no optimizations are considered. However, some blocks, particularly the inhibition-based OR and AND gates, are highly optimizable. For example, reusing the delay neurons in both cases, or the NOT gates within the inhibition-based AND gate, could significantly reduce the number of neurons and synapses used. A detailed discussion of power consumption is now required. First, it is important to highlight existing drawbacks when measuring the power consumption of simulated SNNs, whether on general-purpose systems or specific-purpose platforms, such as SpiNNaker. Power consumption in these cases should be determined not only taking into account the computations performed for each simulation, but also the static power consumption of the system on which this simulation is running and the power consumption associated with other activities. In this way, using a different system could result in a different measure of power consumption, which makes it an unreliable metric when comparing simulated SNNs with other technologies. However, the implementations on Dynap-SE are physical and it makes more sense to measure their power consumption, since it does not depend on other activities. In Risi, 2022, Equation 3.3 is provided to measure the dynamic power consumption of SNNs implemented on Dynap-SE, where rnis the firing rate of the neuron n, Ncores counts the number of target cores and Ncam−match is the total number of 3.2. Spiking implementation of OR, AND and NOT gates 35 TABLE 3.8: Abbreviation, description and value for each of the energy variables. Abbr. Description Value (pJ) Espike Energy to generate one spike 883 Een Energy to encode one spike and append destination 883 Ebr Energy to broadcast events to the same core 6840 Ert Energy to route events to a different core 360 Epulse Energy of the pulse extender circuit 324 neurons that receive the spikes. The descriptions and values of each of the energy variables that appear in the equation were presented in Moradi et al., 2017, and are shown in Table 3.8. Since in our case Ncores =1, it would probably not make sense to consider Ert, although it was considered not to modify the original equation, which would require a better understanding of the circuits involved. This equation does not include the static power consumption of the platform, but it can be useful to provide an analysis of the power consumption of the inhibitionbased OR and AND gates. Pdyn = N ∑ n=1 rn(Espike +Een +Ncores(Ebr +Ert) + Ncam−matchEpulse)(3.3) In the inhibition-based OR gate presented in Figure 3.1, at most three neurons are involved without optimizations. Let nout be from now on the number of synapses extending from an output neuron to other neurons outside the block, the delay neuron be neuron 1, the NOR gate be neuron 2 and the NOT gate be neuron 3. Considering the worst case at the energy level, which is the case in which the NOR gate receives one spike through each input synapse, and also considering that each of the neurons of the block which are not inhibited fires at the same frequency (r)as a result of the parameters used, the application of the equations would be as follows: •P1=r·(883 +883 +1·(6840 +360) + 1·324)·10−12 W=r·9.290 pW •P2=0. This neuron does not fire, since it is inhibited. •P3=r·(883 +883 +1·(6840 +360) + nout ·324)·10−12 W=r·(8.966 + nout ·0.324)pW In this way, Pdyn =∑3 n=1Pn=r·(18.256 +nout ·0.324)pW. Considering that the output neuron is only connected to another neuron and that it operates at a frequency of 1 KHz, the total dynamic power consumption would be 18.580 µW. For the case in which no input spikes are provided to neuron 2, the power consumption of this gate would also be the latter, since the output neuron would 36 Chapter 3. Summary of results not fire but neurons 1 and 2 would. Note that, in this equation, the power consumption of the spike generators is not considered. In the inhibition-based AND gate presented in Figure 3.2, at most five neurons are involved without optimizations. Let the delay neuron be neuron 1, the NOT gates be neurons 2, 3 and 4 and the NOR gate be neuron 5. In this case, the worst case at the energy level would be the case in which no input spikes are provided to the NOT gates, and the application of the equations would be as follows: •P1=P2=P3=P4=r·(883 +883 +1·(6840 +360) + 1·324)·10−12 W =r·9.290 pW •P5=0. This neuron does not fire, since it is inhibited. Therefore, Pdyn =∑5 n=1Pn=r·37.160 pW, which translates into a total dynamic power consumption of 37.160 µWfor the inhibition-based AND gate operating at 1 KHz. It is important to note that all scenarios in this gate can be generalized into two main cases: 1) varying the number of inhibited NOT gates without inhibiting all of them, and 2) inhibiting all NOT gates. In the first case, the total dynamic power consumption would be r·(nNOT +1)·9.290 pW, where nNOT is the number of NOT gates that fire. In the second case, the total dynamic power consumption would be r·(18.256 +nout ·0.324)pW. The latter scenario is similar to the one described for the inhibition-based OR gate. In Chapter 1, it was mentioned that some works in the state of the art had already implemented spiking logic gates using different approaches. In Song et al., 2016, SN P systems were used for this purpose. These systems are purely theoretical computational models and not physically implementable, since, unlike LIF neurons, for example, which can be represented by electrical circuits for physical implementation, they lack a clear physical implementation and therefore can only be simulated. This is probably why no mentions have been found in terms of power consumption. In terms of latency, the developed SN P systems require a similar number of time steps to these designs, except for the OR gate, for which their design requires one more time step than that of the inhibition-based OR gate. However, their computations would probably be much faster due to the simplicity of the rules involved, with smaller time steps. SN P systems would also be better in terms of scalability, since the computations performed on these rules are simpler than those required to solve differential equations, and thus it would be possible to simulate a larger number of elements. Nevertheless, it must be taken into account that the main reason why neuromorphic engineers use SNNs is their bioplausibility, an aspect in which they clearly outperform SN P systems. In Reljan-Delaney and Wall, 2017, the implementation of AND gates based on firing rates using SNNs is performed on MatLab. However, this implementation was not totally deterministic, and therefore it could hardly be 3.3. Applications 37 used for the construction of complex Boolean blocks, as any system dependent on a non-deterministic component would behave chaotically. In fact, the authors admitted that their AND gate was not properly operating in all cases. In Mo and Wang, 2021, functional OR and AND gates were implemented using a trained fully-connected SNN. Regarding latency, each time one of these blocks is placed in series, it takes two additional time steps (2τ)to compute the results. In contrast, Table 3.7 includes some blocks with a latency of τ. Moreover, various optimizations could be applied to these designs while implementing complex blocks to reduce not only the number of resources used but also the latency of the resulting blocks, an approach that does not appear to be feasible with these trained blocks. In terms of scalability, they also require more neurons than any of the designs listed in Table 3.7. As a result, any complex design created by combining them would require a larger number of resources than any complex design built from the combination of the designs presented in this section. 3.3 Applications Once the spiking OR, AND, and NOT gates were implemented, their combination allowed implementing spiking blocks that perform any complex Boolean function, i.e., it was possible to implement any spiking combinational logic, enabling an infinite range of applications for these logic gates and making it crucial to determine which of them could most significantly advance scientific knowledge. In this doctoral thesis, three different applications are proposed that could represent three different scientific fields. These are the following: • Design and implementation of the main components of the spiking computer (Neuromorphic computing and electronics). • Filtering QRS complexes in electrocardiograms using a spiking counter (Biomedical engineering). • Development of an obstacle detection system based on SNNs (Autonomous robotics). This section discusses the progress made in the development of the first two applications, the results of which are currently published. The progress made on the last of the three applications is discussed in Section 3.4.3. 3.3.1 Main components of the spiking computer Digital computers are complex systems capable of performing computations and are composed of both software and hardware elements. At the hardware level, there are two main types of digital elements: those that execute operations and those that store information. The greatest exponent of the former is the processor, or Central Processing Unit (CPU), while the greatest exponent of the latter is the 44 Chapter 3. Summary of results may seem the most logical, but it also turned out to be a much more expensive OR gate in terms of resources. This alternative OR gate was designed by assigning a separate neuron to each input that needed to be integrated, with each input synapse connecting to a different neuron. To ensure that only one neuron could fire at a time, some simple rules were introduced to make them fire with priority. Let nbe the number of inputs of the decoder, ibe the index of an input neuron, and OPibe the input synapse associated with neuron i. Initially, set i=n−1. These rules are the following: • If OPitransmits a spike, neuron ifires, and all neurons jwith 0 ≤j<iare inhibited. • Otherwise, decrement iby 1 and repeat the process for the next neuron until i=0. These priority rules allowed these neurons to be connected to an output spiking block without causing overexcitation. However, it was also observed that the number of resources used was nneurons and (n2+n)/2 synapses. Most of these synapses are inhibitory for high values of n. This results in an exponential increase in the number of synapses required for this implementation, which is the reason why this OR implementation was only used for this purpose. This implementation of the decoder solved the problem encountered in its original implementation with respect to case "00" by eliminating the CSS block, which was responsible for producing the constant triggering of the corresponding AND gate. In this implementation, this case does not even have a place, since it is the no-operation case, which is totally in line with the spiking philosophy. Finally, taking into account this alternative OR gate, the inhibition-based AND gates and the introduction of delay neurons, the implementation of the decoder was achieved following the design shown in Figure 3.13. With respect to each of the operations performed by this ALU, it is necessary to delve into the implementation of the blocks that enable two of them: the XOR and ADD operations. The XOR gate was also implemented in Ayuso-Martinez et al., 2022 (Appendix A) together with the original implementation of OR, AND and NOT gates, and its design has remained the same since then. This network consists of a fully-connected SNN with two layers of neurons, in which each neuron in the input layer is connected one-to-one with a corresponding neuron in the output layer through excitatory synapses and also connected to the rest of the neurons of this layer through inhibitory synapses. In this way, only one neuron fires if the rest are inhibited. To correctly introduce the XOR operation into the spiking ALU, a slight modification was required, which consisted of replacing each neuron of the input layer with a NOT gate. To allow ADD operations, it was necessary to implement a new component: the adder. There are several variants of digital adders; however, for the sake of simplicity, in this work, the ripple-carry adder was used, even though it is not the most optimal of them all. In these adders, half adders and full adders are 3.3. Applications 45 FIGURE 3.13: Design of the implemented simple ALU for performing logical and arithmetic operations with two 3-bit numbers. A and B have a delay of 3τ, indicated as +3 in the scheme. digital circuits used to add two bits. A half adder performs the addition operation without accounting for a carry-in, while a full adder includes a carry-in for more complex addition. The digital circuit of a full adder is shown in Figure 3.14, which also includes a half adder. Each of the gates within both circuits is translated into its spiking form using the blocks presented in this doctoral thesis, finally reaching the spiking implementation of the ripple-carry adder, whose design is shown in Figure 3.15. In this design, some purple neurons have two input excitatory synapses, which could raise concerns about potential overexcitation. However, due to the behavior of the neurons in the network, overexcitation should not be possible, as a spike will never be received simultaneously through both input synapses. This optimization allowed using original OR gates instead of inhibition-based OR gates, which would slightly increase the number of resources used. 46 Chapter 3. Summary of results FIGURE 3.14: Digital circuit of a full adder based on AND, OR and XOR gates. The area represented in green corresponds to the digital circuit of a half adder, which does not take into account the value Cin.SHA and CHA represent the sum and carry outputs of the half adder, respectively, while SFA and CFA denote the sum and carry outputs of the full adder. As also occurred with the rest of experiments conducted on Dynap-SE for previous blocks, an extensive series of experiments were performed to validate the spiking implementations of, first, the ripple-carry adder, and second, the ALU. In the case of the ripple-carry adder, each experiment consisted in the addition of two numbers of 2, 3, 4, 5 or 6 bits performed at operating frequencies of 0.5, 1, 2, 5 or 10 KHz. There were two different sets of experiments depending on whether random numbers or specific numbers were used for the addition operations. In the latter case, these numbers were A=3 and B=2n+1−1, where nis the number of bits considered in each experiment. This set of experiments enabled the verification of the correct propagation of partial results. To correctly interpret the results of these experiments, it was essential to consider the delay introduced by neurons and synapses in the propagation of the spikes, which caused each neuron Sito fire after the neuron Si−1for i≥1, leading to overlaps between the output spikes corresponding to different operations at high frequencies. Thus, the spikes fired by these neurons had to be read diagonally, where the slope of the resulting line was proportional to the value of τ. Figure 3.16 shows the results of a test in which two 5-bit random numbers were added at an operating frequency of 2 KHz. The results of the experiments carried out on the spiking ripple-carry adder are summarized in Table 3.10. Similar to the inhibition-based gates, some experiments failed when operating at high frequencies, as the neurons were unable to maintain the expected Boolean behavior. A final experiment was performed to validate the correct operation of the spiking ALU. This consisted in using a pattern of nine pairs of numbers, which were used to perform each of the allowed operations nine times. The results are shown in Figure 3.17. Finally, an analysis was performed to quantify the number of resources used and the latency of each of the blocks designed for the implementation of the 3.3. Applications 47 FIGURE 3.15: Design of a 3-bit, 2-input spiking adder using SNNs and inspired by the digital ripple-carry adder circuit. The green areas inside the full adders represent a SNN equivalent to a half adder circuit. The purple neurons represent where partial or total results can be obtained in the addition operation, thus Siand Cirepresent one digit of the final result and a partial carry to the next digit, respectively. C2represents the final carry, indicating whether there is overflow during the count. The red neurons perform NOT or NOR operations. Delays are represented as (+n), where nis the value of the corresponding added delay. 48 Chapter 3. Summary of results FIGURE 3.16: Test of adding two 5-bit random numbers at an operating frequency of 2 KHz with the implemented spiking ripple-carry adder. SOP is shown in blue, the spike trains related to A and B are represented in yellow and red, respectively, and the output spike train is shown in green. The spikes colored purple are related to the final carry, indicating whether the addition operation overflows. All spikes contained between two red lines represent a single addition operation. 3.3. Applications 49 TABLE 3.10: Results of the experiments carried out on spiking ripple-carry adders for different numbers of bits (n) and different operating frequencies (f). The ticks indicate that the expected behavior is obtained, while the crosses indicate that the SNN is not able to operate correctly. f (KHz) / n 2 3 4 5 6 0.5 ✓ ✓ ✓ ✓ ✓ 1✓ ✓ ✓ ✓ ✓ 2✓ ✓ ✓ ✗ ✓ 5✓ ✓ ✓ ✗ ✗ 10 ✗✗✗✗✗ TABLE 3.11: Analysis of the resources used and the latency of the highlevel designs proposed related to the implementation of the spiking ALU. nrefers to the number of inputs, bto the number of bits and τto the time it takes for a spike to propagate through the union of a synapse and a neuron according to the parameters used. Block Total neurons Total synapses Latency Alternative OR n(n2+n)/2 τ Decoder 2n+4n(n+1)·2n+3/2 ·n2+7/2 ·n−1 3τ Ripple-carry adder 5b2+12b−11 5b2+28b−20 ... ALU 5b2+23b+12 5b2+48b+29 ... spiking ALU, which is shown in Table 3.11. The latency of the ripple-carry adder depends on the neuron Siand can be calculated using the following formula: (5i+2)·τ,∀i∈ {1, 2, . . . , b−1}, where iis the bit index and bis the total number of bits. For S0, the latency is equal to 3τ. Thus, the latency of the ALU depends on the operation to be performed, since each block in charge of performing each operation has its own latency. For example, in the case of performing the addition operation, this latency also depends on the number of bits, as occurs with the ripple-carry adder. 3.3.2 Filtering QRS complexes in electrocardiograms using a spiking counter An implementation of a spiking counter was presented (Appendix D), aiming not only to leverage the inherent advantages of SNNs but also to serve as a valuable component for processing spiking information based on spike trains. A comparison was then made between LIF neurons, which generally act as highpass filters by requiring a minimum frequency of the input spike train to generate an output spike train, and this spiking counter, whose count action was not affected by the frequency with which it was performed. In this way, spiking counters can not be considered filters, although they are also useful to generate an output spike train with a frequency lower than that of the input spike train. 50 Chapter 3. Summary of results FIGURE 3.17: Test of the implemented spiking ALU operating at 1 KHz. The spike trains fired by the decoder, OPOR, OPXOR,OPAND and OPADD are represented in blue. The spike trains related to A and B, which were delayed by 3τto match the decoder output, are shown in yellow and red, respectively. The output spike trains fired by each of the OR, XOR, AND or adder blocks inside the ALU are represented in green. Note that each type of operation is performed only when the corresponding spike train OP contains spikes. 3.3. Applications 51 This is due to the fact that, unlike in the case of a LIF neuron, whose frequency division relies on complex variables and differential equations, the frequency division caused by the use of this spiking counter depends solely on the number of bits it contains and the parameters used. As a result, the behavior of the spiking counter is independent of the subthreshold dynamics of the neurons that compose it, making it easier to understand and more predictable. To implement this spiking counter, it was first necessary to design a spiking register. To this end, double-neuron SR latches were used, with an additional neuron added to each latch to prevent spikes from being introduced if it was already in the active state, thereby avoiding the overexcitation of the neurons. In this way, this new design of the SR latch could be implemented on Dynap-SE, which would not be the case for the original design presented in Section 3.3.1.1. An additional neuron was introduced to allow the reset of all the latches simultaneously, resulting in the design shown in Figure 3.18. FIGURE 3.18: Design of a spiking register of 4 bits. Biindicates the synapses which are used to set each of the SR latches, independently. Reset is used to perform the reset of all of them. Finally, the design of the spiking counter, shown in Figure 3.19, was mainly based on this spiking register. While the register was used to store the count, a count signal was used to indicate when to increase this count by one. Consequently, each of the latches was not expected to be set or reset through external spike trains, but through the spike trains generated by an intermediate combinational logic based on the use of NOT gates, which made it possible to perform the binary combinations necessary to represent the number of spikes 52 Chapter 3. Summary of results that had been received through the synapse representing the count signal. This combinational logic allowed SR latches to behave as switches, changing their state every time a spike was fired from the NOT gate to which they were connected. An analysis of the resources used and the performance of the block is shown in Table 3.12. FIGURE 3.19: Design of a spiking counter of 4 bits. Count is the input synapse through which spikes increase the count by one. Although it was theoretically possible to implement this design on DynapSE, SpiNNaker was chosen to accelerate the experiments due to time constraints. Initially, a theoretical study of the expected results was conducted using a spike train with a firing rate of 1 KHz as the count signal for a 4-bit spiking counter, which increased the count value by one every 1 ms, as shown in Figure 3.20. Subsequently, this counter was implemented on SpiNNaker. In this second experiment, the expected behavior of the block was validated. Its results are presented in Figure 3.21, showing two main differences with respect to the theoretical study. First, the neurons in the double-neuron latches fired alternately. In addition, synaptic delays were reflected in the timing of the spikes. FIGURE 3.20: Ideal behavior of a 4-bit spiking up-counter when receiving an input spike train with a constant frequency of 1 KHz. 3.3. Applications 53 TABLE 3.12: Analysis of the resources used and the latency of the highlevel designs proposed related to the implementation of the spiking counter. brefers to the number of bits and τto the time it takes for a spike to propagate through the union of a synapse and a neuron according to the parameters used. Block Total neurons Total synapses Latency Improved SR latch 3 9 τ Register 3b+1 9b+1τ Counter 6b−6 17b−8τ FIGURE 3.21: Real behavior of the proposed implementation for a 4-bit spiking up-counter when receiving an input spike train with a constant frequency of 1 KHz. Once implemented, it was proposed to use the spiking counter in the development of a spiking system to filter QRS complexes. SNNs are especially useful for working with time-dependent patterns, especially when there is plasticity. The aim was to find out whether a static structure, in which no plasticity existed, could somehow work reliably with more realistic spike trains. Thus, experimenting with the electrical signals generated by the heart was the perfect case, as they contain a characteristic pattern of variations which, although may be slightly different for each individual, is well defined. The QRS complex is one of the essential components of this pattern, as its duration and amplitude are particularly useful for the detection of cardiac abnormalities (Christov, 2004; Corradi et al., 2019). An experiment was designed to show that a spiking counter can be used as a frequency divider to preprocess a spike train and then filter QRS complexes using a LIF neuron. For this purpose, the PhysioNet Arrhythmia Database from the Massachusetts Institute of Technology and Beth Israel Hospital (MIT-BIH)1 was used. First, it was essential to encode the electrical signals contained in a data file into spikes, for which the delta modulator algorithm (Corradi et al., 2019) was used, in which the spikes represent a change in the potential of the signal that exceeds a certain threshold, positively or negatively (on and off spikes, respectively). In this work, only MLII (Modified Limb Lead II) signals were 1https://www.physionet.org/content/mitdb/1.0.0/ 60 Chapter 3. Summary of results This implementation was tested through an extensive series of experiments, which mainly varied the operating frequency in a way similar to the experiments conducted for the inhibition-based OR and AND gates. These experiments proved that the FSM behaved as expected while operating at 0.5 KHz, 1 KHz and 2 KHz, but they did not totally work as expected when working at 5 KHz. It should be studied to what extent the improved SR latches, which have an additional neuron to avoid overexcitation in the latches, could have improved the results obtained. Figure 3.30 shows the results of an experiment in which the FSM was tested with discrete operation spikes. Note that, when OP and SG1 transmitted a spike simultaneously, the FSM always moved to the next state, but when OP and SG2coincided, it only returned to the previous state if state S3was active at that time. Another important detail is that, if SG1or SG2transmitted a spike but OP did not, the latches did not change their state, as none of the transitions was activated. 3.4. Work pending publication 61 FIGURE 3.30: Results of an experiment conducted on the implemented FSM, operating at discrete times. The input spike trains are shown below the dotted line. Stop is used to reset the states, and start to set the state S1.OP contains the spikes required to operate, SG1indicates to advance to the next state and SG2indicates to return back to the previous state. The spikes fired by each of the states and transitions are shown above the dotted line. 63 Chapter 4 Discussion This chapter discusses some general aspects of the paradigm introduced for the implementation of spiking blocks that have not yet been explored in detail, and it also describes some possible lines of future work which arise from the work presented in this doctoral thesis. In Section 3.1, it was mentioned that the firing times of the spike generators in Dynap-SE may vary slightly from the expected values. In fact, this variance can occur not only in the spike generators but also in the neurons of an implemented SNN, as they share a common analog nature, which could lead to unexpected behaviors of these neurons. Suppose the scenario in which the parameters of a single LIF neuron have been adjusted so that the accumulated current induced by two spikes which arrive simultaneously is sufficient to bring the membrane potential to the threshold potential, thus causing the neuron to fire. Considering that one of the two spikes could arrive earlier and taking into account that LIF neurons tend to bring their membrane potential to their resting potential, it is clear that a drop in its membrane potential would occur between the arrival of both spikes. In this way, the impact of this drop on the neuron’s behavior would depend on its specific parameters. If the drop is large enough, this would cause the neuron not to reach the threshold potential after the arrival of both spikes, thus preventing the expected behavior from being achieved. This effect has not been observed in the implementations on Dynap-SE of the spiking blocks designed in this doctoral thesis, probably because these drops were insufficient to cause unexpected behaviors in SNNs with few layers of neurons using the parameters presented in Chapter 3. However, in SNNs with many layers of neurons, the cumulative effect of these temporal variations could eventually become significant enough to affect their functionality. Therefore, an in-depth study of this aspect would be required during the implementation of SNNs of much greater complexity than those presented. In App. Band App. C, two solutions were proposed to solve this possible problem in the future while maintaining the spiking Boolean paradigm. The first of these two solutions, which would require the least effort, would consist in adjusting the neuron parameters to minimize the drop in membrane potential, which could be 64 Chapter 4. Discussion done by extending the time it takes for this potential to decay. However, this could significantly limit the maximum operating frequency of the implemented blocks, as overlapping operations may occur. The second solution would be the ideal solution, but also the most complex to achieve, since it would consist in implementing a mechanism for the synchronization of spikes coming from different synapses. There is biological evidence of the existence of spike synchronization mechanisms in the nervous system (MacLeod et al., 1998; Riehle et al., 1997). A potential synchronization mechanism could leverage the latches used to implement the spiking counter. This would involve using a SR latch for each input synapse, which would be activated upon the arrival of the first spike at the corresponding synapse. An AND gate would then generate an output spike only when all SR latches were active, at which point the latches would also be reset. The output synapse would have a weight equal to the sum of the weights of all input synapses, mimicking the effect of spike integration on a postsynaptic neuron. This mechanism would introduce a delay equal to the delay of the last input spike. Although this would increase the latency of the implemented blocks, it would ensure their correct operation. However, in cases where input spike trains have high firing rates, this mechanism could produce fewer output spikes than expected. In Chapter 3, many experiments were presented that aimed to test the behavior of the spiking blocks implemented on Dynap-SE under several operating frequencies. However, it has been mentioned that they may fail when these frequencies are particularly high, which could be associated with the rapid arrival of spikes to neurons that are still within their refractory period, thus preventing their Boolean behavior. What should be the operating frequency then? The results showed that, operating at 1 KHz, the behavior of all the implemented blocks was as expected in all cases. Therefore, it is proposed to make these blocks operate at that frequency whenever possible to avoid unexpected behaviors. Reducing the refractory period of the neurons inside the blocks would help their maximum operating frequencies to increase. In terms of power consumption, an analysis of the consumption of inhibition-based OR and AND gates on Dynap-SE was carried out together with a comparison with other works of the state of the art in Section 3.2. However, a comparison should also be made between these dynamic power consumptions and the dynamic power consumption of transistors, e.g., CMOS transistors, which can be calculated using the formula presented in Equation 4.1, extracted from Beloglazov et al., 2011, where ais the switching activity, Cis the physical capacitance, Vis the supply voltage and fis the clock frequency. Note that this clock frequency is equivalent to a constant operating frequency in the spiking designs presented. Chapter 4. Discussion 65 Pdyn =aCV2f(4.1) To ensure a fair comparison, it must be considered that in the dynamic power consumption studies presented in this doctoral thesis the neurons fired one spike every 1 ms, corresponding to a frequency of 1 KHz, thus having a=1 and f=1 KHz, meaning that the transistor switches at every clock cycle (1 ms). The supply voltage, as reported in Moradi et al., 2017, was V=1.3 V. Assuming a capacitance of C=0.5 fF, which is a quite small but typical value for current transistors, the dynamic power consumption of a CMOS transistor can be calculated as shown in Equation 4.2. Pdyn =1·0.5 ·10−15 ·1.32·103=0.845 pW (4.2) The calculated value is significantly lower than the 9.29 µWobtained for a single neuron in the spiking designs, assuming a firing rate of 1 KHz and a single output synapse. It should also be taken into account that the parameters used in Equation 4.2 correspond to transistors with dimensions of only a few nanometers, whereas, in Dynap-SE, a 0.18 µmtechnology is used. However, as discussed in Moradi et al., 2017, the real reason why the SNNs implemented on this platform could benefit from very low power consumption would be, as is the case of the nervous system and the brain, the ability of these networks to implement massively parallel architectures, thus reducing the amount of resources used and therefore their overall power consumption. This could be demonstrated in the future by implementing designs that reuse a large number of neurons to carry out the different partial operations needed to perform specific functions. Finally, there is another aspect that also needs to be taken into account. The electrical circuits used in Dynap-SE to implement DPI neurons are made up of many of these transistors, so comparing the power consumption of a CMOS transistor versus the power consumption of many of them together would be trivial if parallelism were not considered. However, since the designs presented in this thesis are biologically plausible, they could be physically implemented using not only electrical circuits but also real neurons, in a hypothetical future where neurons could be manipulated and interconnected at will. Experiments would then be carried out to verify whether it would be possible to maintain the Boolean behavior of the neurons even in the most complex possible environment. This, on the other hand, could also serve to discover whether there are structures similar to the designs of the most basic combinational blocks in the nervous system, which could implicitly suggest the existence of Boolean function calculations in biology. 67 Chapter 5 Summary and conclusions This chapter presents a summary of the main conclusions that can be drawn from the work described in this document, highlighting the key points covered in the previous sections: • An in-depth study of the biological foundations of the nervous system and the brain was carried out, describing the features that biological neural networks exploit to make the brain the most efficient computer currently in existence. • This work is closely related to the field of neuromorphic engineering, whose aims and advances are detailed in this thesis, as well as one of the main working tools of these engineers, the Spiking Neural Networks (SNNs). Thus, the functioning of these bioinspired networks, the main neuron models and the neuromorphic alternatives used for their implementation were explored in depth. • Based on the use of SNNs, this work initially proposed to adopt a spiking Boolean computing paradigm that would allow implementing combinational blocks exhibiting the main advantages of SNNs, which are low-power consumption and high real-time capacity, both related to their massive capacity for parallelism. In addition, this paradigm would allow neuromorphic engineers to implement any spiking combinational logic in a systematic way, which could be very useful in their research. • This thesis demonstrates the ability of SNNs to exhibit Boolean behaviors under a particular set of neuron parameters through the spiking implementation of the most basic blocks, i.e., the logic gates, from which any other combinational block can also be implemented. • These new spiking architectures were validated in both digital and analog environments using the SpiNNaker and Dynap-SE neuromorphic platforms and under an extensive series of experiments, which demonstrated their bioplausibility by overcoming certain difficulties that 68 Chapter 5. Summary and conclusions a biological neural network could also be subject to, such as overexcitation or spike synchronization. • During the design of inhibition-based OR and AND gates, it was possible to implement NOR gates using only one neuron. Since NOR gates are also universal gates, i.e., any Boolean function can be constructed from them, blocks implemented using such gates could be quite optimal. • The performance and scalability of the implemented blocks on SpiNNaker and Dynap-SE were analyzed. For inhibition-based OR and AND gates, an analysis of dynamic power consumption was also carried out. This analysis was used to make a comparison with the works found in the state of the art, thus obtaining better results than other implementations based on SNNs and the use of different paradigms. • No comparable spiking implementations were found for many of the presented blocks, which highlights their novelty and the potential of the proposed paradigm for building spiking implementations. As a result, it was not possible to include direct comparisons in terms of performance, scalability or power consumption. • A series of applications were carried out that seek to demonstrate the usefulness of the spiking Boolean computing paradigm and thus exploit the main advantages of SNNs when performing known tasks encompassed within different branches of science. Among them, the advances made in the implementation of a spiking computer stand out due to the complexity of the SNNs involved, whose behaviors were also validated through an extensive series of experiments. • Finally, some issues to be taken into account in the future were discussed, such as the possibility of problems arising from differences in the arrival times of spikes to the neurons of a network and some possible solutions that could be attempted to be applied if this occurs in networks of much greater complexity than those presented in this thesis. Thus, all the objectives proposed in Chapter 2were met. 69 Chapter 6 Bibliography Abbott, Larry F (1999). “Lapicque’s introduction of the integrate-and-fire model neuron (1907)”. In: Brain research bulletin 50.5-6, pp. 303–304. Akopyan, Filipp, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John Arthur, Paul Merolla, Nabil Imam, Yutaka Nakamura, Pallab Datta, GiJoon Nam, et al. (2015). “Truenorth: Design and tool flow of a 65 mw 1 million neuron programmable neurosynaptic chip”. In: IEEE transactions on computer-aided design of integrated circuits and systems 34.10, pp. 1537–1557. Anderson, James A (1972). “A simple neural network generating an interactive memory”. In: Mathematical biosciences 14.3-4, pp. 197–220. Aslam, Abdul Rehman and Muhammad Awais Bin Altaf (2019). “An 8 channel patient specific neuromorphic processor for the early screening of autistic children through emotion detection”. In: 2019 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, pp. 1–5. Auge, Daniel, Julian Hille, Etienne Mueller, and Alois Knoll (2021). “A survey of encoding techniques for signal processing in spiking neural networks”. In: Neural Processing Letters 53.6, pp. 4693–4710. Ayuso-Martinez, Alvaro, Daniel Casanueva-Morato, Juan P Dominguez-Morales, Angel Jimenez-Fernandez, and Gabriel Jimenez-Moreno (2022). “Spikebased building blocks for performing logic operations using Spiking Neural Networks on SpiNNaker”. In: 2022 International Joint Conference on Neural Networks (IJCNN). IEEE, pp. 1–9. Ayuso-Martinez, Alvaro, Daniel Casanueva-Morato, Juan P Dominguez-Morales, Angel Jimenez-Fernandez, and Gabriel Jimenez-Moreno (2023a). “A SNNBased Implementation of a Spiking Counter for Filtering and Processing Spike Trains in Real Time”. In: X Workshop in R&D+ i & International Workshop on STEM of EPS. Springer, pp. 340–349. Ayuso-Martinez, Alvaro, Daniel Casanueva-Morato, Juan Pedro DominguezMorales, Angel Jimenez-Fernandez, and Gabriel Jimenez-Moreno (2023b). “Construction of a spike-based memory using neural-like logic gates based on Spiking Neural Networks on SpiNNaker”. In: IEEE Transactions on Emerging Topics in Computing 11.4, pp. 868–881. 77 Part II Set of papers 79 Appendix A Spike-based building blocks for performing logic operations using Spiking Neural Networks on SpiNNaker Authors • Alvaro Ayuso-Martinez • Daniel Casanueva-Morato • Juan P. Dominguez-Morales • Angel Jimenez-Fernandez • Gabriel Jimenez-Moreno Publication State: Accepted and published Type: Conference Paper Conference Name 2022 International Joint Conference on Neural Networks (IJCNN) Place: Padova, Italy. Date: July 2022 Publisher: IEEE Number of pages: 9 ISSN: 2161-4407. ISBN: 978-1-7281-8671-9 DOI: https://doi.org/10.1109/IJCNN55064.2022.9892479 89 Appendix B Construction of a spike-based memory using neural-like logic gates based on Spiking Neural Networks on SpiNNaker Authors • Alvaro Ayuso-Martinez • Daniel Casanueva-Morato • Juan P. Dominguez-Morales • Angel Jimenez-Fernandez • Gabriel Jimenez-Moreno Publication State: Accepted and published Type: Regular Paper Journal Name: IEEE Transactions on Emerging Topics in Computing Publisher: IEEE Date: June 2023 Number of pages: 13 ISSN: 2168-6750 DOI: https://doi.org/10.1109/TETC.2023.3281063 103 Appendix C Analog Implementation of a Spiking System for Performing Arithmetic Logic Operations on Mixed-Signal Neuromorphic Processors Authors • Alvaro Ayuso-Martinez • Daniel Casanueva-Morato • Juan P. Dominguez-Morales • Giacomo Indiveri • Angel Jimenez-Fernandez • Gabriel Jimenez-Moreno Publication State: Accepted for publication Type: Regular Paper Journal Name: Advanced Intelligent Systems Publisher: Wiley Number of pages: 20 ISSN: 2640-4567 125 Appendix D A SNN-Based Implementation of a Spiking Counter for Filtering and Processing Spike Trains in Real Time Authors • Alvaro Ayuso-Martinez • Daniel Casanueva-Morato • Juan P. Dominguez-Morales • Angel Jimenez-Fernandez • Gabriel Jimenez-Moreno Publication State: Accepted and published Type: Book Chapter Book Name: Recent Advances and Emerging Challenges in STEM Publisher: Springer Date: August 2024 Number of pages: 11 ISSN: 2662-3161. ISBN: 978-3-031-64105-3 DOI: https://doi.org/10.1007/978-3-031-64106-0_38 137 Appendix E Live Demonstration: Construction of a spike-based memory using neural-like logic gates based on Spiking Neural Networks on SpiNNaker Authors • Alvaro Ayuso-Martinez • Daniel Casanueva-Morato • Juan P. Dominguez-Morales • Angel Jimenez-Fernandez • Gabriel Jimenez-Moreno Publication State: Published on arXiv Type: Conference Paper Number of pages: 1 DOI: ... 139 Appendix F A Low-Cost Real-Time Spiking System for Obstacle Detection based on Ultrasonic Sensors and Rate Coding Authors • Alvaro Ayuso-Martinez • Daniel Casanueva-Morato • Juan P. Dominguez-Morales • Angel Jimenez-Fernandez • Gabriel Jimenez-Moreno Publication State: Published on arXiv Type: Journal Paper Number of pages: 22 DOI: https://doi.org/10.48550/arXiv.2409.02680