A general translinear principle for subthreshold MOS transistors

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 5, MAY 1999 607 A General Translinear Principle for Subthreshold MOS Transistors Teresa Serrano-Gotarredona, Bernab´e Linares-Barranco, and Andreas G. Andreou Abstract—This paper revises the conditions under which the translinear principle can be fully exploited for MOS transistors operating in subthreshold. Due to the exponential nature of subthreshold MOS transistors, the translinear principle applies immediately as long as the source-to-bulk voltages are made equal to zero (or constant). This paper addresses the conditions under which subthreshold MOS transistors still satisfy a translinear principle, but without imposing this constraint on all V BS voltages. It is found that the translinear principle results in a more general formulation than the originally found for BJT’s since now multiple translinear loops can be involved. The constraint of an even number of transistors is no longer necessary. Some corollaries are stated as well and, finally, it is shown how to use the theorem for subthreshold MOS transistors operated in the ohmic regime. Index Terms—CMOS analog integrated circuits, current mode circuits, low-power circuits, nonlinear circuits, subthreshold circuits, translinear circuits, very large scale integration. I. INTRODUCTION THE translinear principle, introduced by Gilbert in 1975 [1], is one of the most important circuit theory contributions in the electronics era. In its original formulation, the translinear principle provides a simple and efficient way to analyze and synthesize nonlinear circuits based on bipolar junction transistors (BJT’s). Due to their exponential characteristics, the translinear principle can be extended to MOS transistors operating in weak inversion [2], [3] without or with floating-gate devices [4]. For MOS transistors operating above threshold there has also been found a similar way to analyze and synthesize nonlinear circuits [5]. For bipolar transistors one practical problem that may require some attention when applying the translinear principle is the nonzero base current [6]. In contrast, the translinear principle holds for MOS subthreshold transistors in an exact manner if source and bulk are short circuited. However, it has been found that the principle holds as well in an exact manner under different circumstances [2]–[3], although a general subthreshold MOS translinear theorem has not been devised until now. In this paper we provide this general theorem and outline the conditions under which subthreshold Manuscript received October 8, 1997; revised May 11, 1999. This work was supported in part by the ONR under Grant N00014-95-1-0409. This paper was recommended by Associate Editor V. P. Villar. T. Serrano-Gotarredona and B. Linares-Barranco are with the National Microelectronics Center (CNM), 41012 Sevilla, Spain. A. G. Andreou is with The Johns Hopkins University, Baltimore, MD 21218 USA. Publisher Item Identifier S 1057-7122(99)03883-0. MOS transistors, viewed as four terminal devices, satisfy a general translinear principle. The operation of a subthreshold MOS can be described by the following equation [2], [7]–[9]: (1) where is the thermal voltage, is a positive constant current, is the transistor size factor ( where is transistor width and is its length), and is a technology-dependent positive parameter. This equation holds true as long as (2) where is the device’s flat-band voltage [10]. Voltage can take either positive or negative values as long as the parallel PN diode junction is biased below its forward conduction threshold voltage. Parameter is known to have a slight dependency on voltage [2]. However, in this paper we will assume to be constant, which is a reasonable assumption if care is taken to make the voltages similar for all transistors. For operation in saturation, (1) can be simplified to (3) and can be rewritten as (4) where (a normalized current) is transistor current normalized with respect to transistor size factor and are dimensionless numbers called pseudo-currents and equal to (5) II. ORIGINAL TRANSLINEAR THEOREM APPLIED TO SUBTHRESHOLD MOS TRANSISTORS Let us use the symbol in Fig. 1 to represent a weak-inversion MOS in saturation. Let us call the path that goes from the gate terminal to the source terminal the branch (or gate branch), and the path that goes from the bulk terminal to terminal the branch (or bulk branch). We are using a diode-like symbol to represent the exponential relationship between the voltage of the branch and the current flowing out of the device and a capacitive-like termination to each diode symbol to represent the capacitive coupling nature of the gate 1057–7122/99$10.00 1999 IEEE 608 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 5, MAY 1999 Fig. 1. Translinear symbol representation for subthreshold MOS transistor in saturation. and bulk terminals. If (or constant) there is an exact exponential relationship between and [see (3)] and the original BJT translinear formulation can be directly and exactly applied (see Fig. 2): Theorem 1: In a closed loop containing an equal number of oppositely connected translinear elements, the product of the normalized currents in the elements connected in the clockwise (CW) direction is equal to the corresponding product for elements connected in the counterclockwise (CCW) direction. Proof: In a loop, the sum of branch voltages adds to zero. Since voltages of CW-oriented junctions have opposite sign than those of CCW-oriented junctions, the following holds: (6) Since for all subthreshold MOS transistors, using (3) in (6) yields (7) Since tthe number of CW-oriented devices is equal to the CCW-oriented ones, the coefficients in (7) cancel out, thus resulting in (8) Fig. 2 illustrates this Theorem. In Fig. 2(a) a loop with six -branches is represented. The -branches are not shown because their terminals are short circuited together and, consequently, have no effect on the circuit behavior. Fig. 2(b) shows the same circuit, but using the MOS transistor symbol to represent the devices. III. GENERALIZED TRANSLINEAR THEOREM FOR SUBTHRESHOLD MOS TRANSISTORS In this section, we will consider the conditions under which translinear principles can be applied to circuits with subthreshold MOS transistors, but without imposing the constraint of making We will introduce first some preliminary theorems and definitions and then state and prove the generalized translinear theorem for subthreshold MOS devices. Afterwards, a few examples will illustrate the theorem. The first concepts to be introduced are loop and loop. Aloop (or gate loop) is a closed loop of branches, and aloop (or bulk loop) is a closed loop of branches. For these loops we can state translinear theorems for their pseudocurrents. Theorem 2: In a loop containing an arbitrary number of branches, the product of pseudocurrents of branches connected in the CW direction is equal to the corresponding product for branches connected in the CCW direction. Proof: the branch voltages of a loop satisfy (9) Applying the first equation of (5) in (9) yields (10) Note that since pseudocurrents are dimensionless entities, we can have an arbitrary number of branches oriented CW and another arbitrary number of branches oriented CCW [as opposed to the case of (7)]. A completely equivalent theorem holds directly for loops. Up to now, things are similar to classical translinear loops, except that an arbitrary number of branches are allowed. However, the presence of two exponential branch voltages in (3) is what makes subthreshold MOS translinear loops more general and complicated than the classical ones. A first consequence of this fact is the following concept of coupled loops. Definition 1: Two loops are said to be coupled if at least one MOS device of the first loop and at least one other different device of the second loop share their respective branches in a common loop. This is illustrated in Fig. 3. Devices 1-3-5 form a loop and devices 2-4-6 form another loop. However, devices 12-3-4 form a loop, thus causing the previous two loops to be coupled through the branches of devices 1-2-3-4. An equivalent definition applies for coupled loops. Note that two loops may have a common branch without being necessarily coupled loops. SERRANO-GOTARREDONA et al.: A GENERAL TRANSLINEAR PRINCIPLE FOR SUBTHRESHOLD MOS TRANSISTORS 609 (a) (b) Fig. 2. Subthreshold MOS transistors translinear loop where for all transistors V BS =0 : (a) Translinear symbol representation. (b) Circuit schematic representation. Fig. 3. Example of coupled G loops using translinear symbol representation. In the example of Fig. 3, we can write for the two loops (11) where all pseudocurrents have cancelled out by applying Theorem 2. However, due to loop 1-2-3-4, (12) which introduces a coupling between the two equations in (11), and makes loops 1-3-5 and 2-4-6 to be coupled loops. When devices form multiple touching loops it is not clear which ones to choose or how many to choose. For example, in Fig. 4 one can choose loops 1-2-3-6, 6-7, and 2-4-5. But why not consider 1-3-4-5-6, 6-7, and 2-4-5 or 1-3-4-5-7 and 12-3-6. One can try all possible options as long as one chooses a set of nonredundant (NR) loops: Definition 2: A set of loops is said to be NR if the sum of branch voltages of any loop cannot be expressed as a linear combination of the sum of branch voltages of other loops in the set. For example, in Fig. 4, for loops 1-2-3-6, 2-4-5, and 1-3-4-5-6 their respective sums of branch voltages are (13) Fig. 4. Illustration of the G -order concept. Devices 1-2-3-6 form a G loop which is coupled to the G loop formed by devices 2-4-5 because devices 1-2-3-4 form a B loop. Devices 1-2-3-4-5-6 form a closed translinear set and so do devices 6 and 7. Device 2 has a G order of n G 2 =2 because its G branch belongs to two G loops of the same closed translinear set. All other devices have G order one. Fig. 5. Example of CTS’s. MOS devices 7 and 8 form a CTS and so do MOS devices 1–7. Any of these three equations can be expressed as a linear combination of the other two. Thus, the three loops do not form an NR set of loops. However, any two of these three loops do form an NR set of loops. The fact that subthreshold MOS transistors can form coupled loops, yields naturally to the following concept of the closed translinear set (CTS). Definition 3: Given a set of MOS devices, and once an NR set of loops has been chosen, a CTS is a set of devices such that all loops they form are only coupled among themselves, but are not coupled to loops where branches of other devices (not belonging to the CTS) are present. This is illustrated in Fig. 5. Let us select the NR set of loops 1-2-3-7, 4-5-6, and 7-8 and the NR set of loops 12-3-4-5-6, 7, and 8. loops 1-2-3-7 and 4-5-6 are coupled because there are branches of devices of both loops that are shared in the common loop 1-2-3-4-5-6. The two loops, 1-2-3-7 and 4-5-6, and the two loops, 1-2-3-4-5-6 and 7, are not coupled to other loops (neither are loop 7-8 nor loop 8), thus, (for the chosen NR set of loops) devices 1- 610 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 5, MAY 1999 2-3-4-5-6-7 form a CTS. On the other hand, neither loop 7-8 nor -loops 7 and 8 are coupled to any other loop. Therefore, devices 7-8 form another CTS. When working with multiple loops and loops, with some of them being coupled, it is not very convenient to classify each branch as being CW or CCW oriented, as will become apparent later. Let us instead classify all branches into two orientation groups, the wise oriented branches and the wise oriented branches. Two branches are classified into the same group (either the wise or the wise) if they appear in the same loop with the same orientation. On the contrary, two branches are classified, each into a different group (one into the wise, the other into the wise) if they appear in the same loop with opposite orientation. Note that, now, a CW branch in one loop and a CCW branch in another loop can be classified into the same wise or wise group. If a branch is short circuited, it forms a one-branch loop and can be classified as either wise or wise. Another concept that is useful for stating the generalized translinear subthreshold MOS theorem is that of order and order of a MOS device in a CTS. Definition 4: Once an NR set of loops has been chosen, a subthreshold MOS transistor which is part of a CTS is said to have a order of value if its branch belongs to loops of the given CTS. An equivalent definition of the order can be stated for loops. The concept is illustrated in Fig. 4. Let us choose the NR set of loops 1-2-3-6, 2-4-5, and 6-7 and of loops 1-2-3-4, 5, 6, and 7. loops 1-2-3-6 and 2-4-5 are coupled because devices 1-2-3-4 form a loop. There are no other couplings among the chosen loops. Consequently, devices 12-3-4-5-6 form a CTS which consists of loops 1-2-3-6 and 2-4-5 and loops 1-2-3-4, 5, and 6. Devices 6 and 7 form one loop (6-7) and two loops (6 and 7) which are not coupled to any other loop. Therefore, devices 6 and 7 form another CTS. MOS device 2 has order because its branch appears in two loops of the same CTS. MOS device 6 does not have order two because, although its branch belongs to two different loops, these two loops do not belong to the same CTS. All MOS devices have order one because their branches appear only in one loop. When a branch has order greater than one, it belongs to more than one loop of the same CTS. In such cases it is possible that the branch be classified as wise in some loops and as wise in other loops. Under these circumstances, it is convenient to divide its order into two parts (14) where (let us call it - order) denotes the number of times this branch is classified as wise in a CTS and (let us call it - order) denotes the times it is classified as wise in the CTS. Similarly, for branches, the order can be separated into the - order and the - order Using the concepts and preliminary theorems introduced until now, it is possible to state and prove the generalized translinear theorem for subthreshold MOS transistors1: Theorem 3: Given a set of subthreshold MOS devices and choosing for them a set of NR loops and loops, for each CTS the following can be stated. If it is possible to find an and wise classification of their loops and loops such that the following pertains. a) The sum of - orders equals the sum of - orders (15) b) Every time a device’s branch is classified as wise in a loop, its branch can be classified as wise in some loop, and every time a device’s branch is classified as wise in a loop, its branch can be classified as wise in some loop. Then, the product of normalized currents raised to the power of their - order of all transistors in the CTS whose branches have been classified wise equals the product of normalized currents raised to the power of their - order of all transistors whose branches have been classified wise. Proof: For each loop in the CTS, the following holds (as we know from Theorem 2): (16) Since this is true for every single loop we can multiply these equations for the chosen set of NR loops and their product will still be equal to unity (17) Furthermore, we can raise it to the power of and it still will be equal to unity (18) 1The theorem will be stated using G branches as primary branches and making B branches depend on them. However, because of the symmetry between G branches and B branches [due to the symmetry between V GS and V BS voltages as (3)], the theorem can be stated, as well, by interchanging G branches and B branches. SERRANO-GOTARREDONA et al.: A GENERAL TRANSLINEAR PRINCIPLE FOR SUBTHRESHOLD MOS TRANSISTORS 611 Note that, since the devices form a CTS, all branches will be present and no branch of another CTS appears. Consequently, (18) includes all branches of the CTS and only the branches of this CTS. Equivalently, the same can be stated for all loops (19) but raising now to the power of for convenience. Note that, due to statement b) in Theorem 3, every time a device has its pseudocurrent in the numerator of (18), its pseudocurrent will also appear in the numerator of (19) and both will appear times. And the same holds for pseudocurrents in the denominators of (18) and (19). Therefore, let us define and such that (20) Also, since the devices form a CTS, (18) includes all devices of the CTS, and so does (19). Consequently, we can multiply (18) and (19) and index the and pseudocurrents of the same device with the same subscript and use this subscript to index the MOS device (21) On the other hand, due to statement a) in the theorem, the following is satisfied: (22) By multiplying (21) and (22) and using (4) we obtain (23) which concludes the proof of the generalized subthreshold MOS translinear theorem. In the remaining of this section this theorem will be illustrated with a few examples. Consider the circuit of Fig. 6, where we can choose the two NR loops 1-2-3 and 4-56 and the two NR loops 2-6 and 1-3-4-5. The two loops are coupled through each of the two loops. Hence, all devices in Fig. 6 form a unique CTS. Table I shows a possible or wise classification of the branches. Column - denotes MOS devices whose branch has been classified wise, column - those whose branch has been classified wise. Similarly, columns - and - do the same for branches. The dashed lines in Table I encircle those devices in a common loop. In Table I, the classification is such that when a device appears under - , it also appears under - and if it appears under - , it also appears under - , therefore, satisfying the requirement of condition b) in Theorem 3. Since each or branch has order one (it appears only in one loop), Table I reveals that the sum of - orders is equal to the sum of - orders (and the sum of - orders is equal to the sum of - orders). Consequently, condition a) of Theorem 3 is also satisfied. Therefore, applying Theorem 3 results in (24) For illustration purposes, let us now write the current equation for each transistor as follows. If a branch is connected wise, we write its equation as in (4), but if its branch is connected wise we invert both sides of the equation (25) Pseudocurrents and are in the same loop. Consequently, by Theorem 2 (26) 612 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 5, MAY 1999 (a) (b) Fig. 6. Example of subthreshold MOS translinear circuit with V BS 6 =0 : (a) Translinear symbol representation. (b) Circuit schematic representation. TABLE I The same applies for pseudocurrents and Similarly, for pseudocurrents the following is satisfied: (27) Consequently, by multiplying all equations in (25), (24) is obtained. Note that the generalized theorem imposes a topological constraint in the way the loops and loops are formed. This topological constraint is visualized in Table I, where devices under - must also be under - and devices under - must also be under - A particular bias arrangement for the circuit in Fig. 6 is shown in Fig. 7, which applies the following constraints to (24) for equally sized transistors: (28) Fig. 7. Particular bias arrangement for the circuit configuration of Fig. 6. resulting in (29) In this example, all branches have order and order equal to one because device branches were not present in more than one loop. The example in Fig. 8 illustrates Theorem 3 for the case in which one of the devices has and order greater than one. Let us choose the NR set of loops 1-3-4-5 and 1-2. On the other hand, devices 2-3 form a loop,2while the branches of devices 1, 4, and 5 form three single-branch loops. Consequently, branches of devices 1, 4, and 5 can be classified as wise or wise as many times as needed.3 2This will force V BS 2 = 0 V BS 3 so that one of them must be positive. In such a case, it needs to be insured that the positive V BS voltage is kept below the threshold voltage of the diode PN junction between source and bulk. 3Note that the pseudocurrent of such a branch is equal to unity and can be SERRANO-GOTARREDONA et al.: A GENERAL TRANSLINEAR PRINCIPLE FOR SUBTHRESHOLD MOS TRANSISTORS 613 (a) (b) (c) Fig. 8. Example of subthreshold MOS translinear circuit with one device having order-a higher than one. (a) Translinear symbol representation. (b) Circuit schematic representation. (c) Particular bias arrangement. TABLE II Table II shows how and branches of the topology in Fig. 8(a) can be classified as wise and wise. In loop 2-3 branches of devices 2 and 3 are oriented in the same direction, therefore they must appear under the same column in Table II. Let us put them under - Then, for loop 13-4-5, device 3 should appear under - and for loop 1-2, device 2 should appear under - as well. Devices 1, 4, and 5 fill the spaces needed in Table II under column to fulfill the conditions of Theorem 3. Consequently, the following equality arbitrarily added to the numerator or denominator of (23) as many times as desired. will be satisfied: (30) A possible bias arrangement for this circuit is shown in Fig. 8(c) where, for equally sized transistors, the following constraints are applied: (31) This together with (30) forces to solve the following second-order polynomial: (32) Note that, with the generalized subthreshold MOS translinear theorem, the number of devices does not have to be an even number, as opposed to the traditional translinear theorem. In Fig. 7 there is an even number of transistors, while in Fig. 8 there is an odd number. IV. COROLLARIES FOR THE GENERALIZED SUBTHRESHOLD MOS TRANSLINEAR THEOREM A set of immediate corollaries follow from the generalized subthreshold MOS translinear theorem: Corollary 1: It is possible to have an exact translinear subthreshold behavior in a single loop with all transistor bulks connected to the same terminal if the transistors share their sources pairwise and the branches form loops of even numbers, half of them connected CW and the other half CCW. This was anticipated by Vittoz [3] and is illustrated in Fig. 9(a). Devices 1-2-3-4-5-6 form a CTS and so do devices 6-7. For each CTS their branches and branches can be classified and wise, as is shown, respectively, in Tables III and IV. Applying Theorem 3 results in (33) A particular bias arrangement is shown in Fig. 9(b), which imposes the following constraints for equally sized transistors: (34) which, together with (33), make current solve the following second-order polynomial 614 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 46, NO. 5, MAY 1999 (a) (b) Fig. 9. Arrangement for translinear subthreshold MOS devices with common bulk and sources shared pairwise. (a) Translinear symbol representation. (b) Schematic representation of a particular bias arrangement. TABLE III TABLE IV (35) Corollary 2: There is a need to distinguish among loops and loops as long as and are different. If a technology is available for which , there would be no need to distinguish between branches and branches, and they could be mixed in common loops. Corollary 3: If different subthreshold MOS devices are available (for example, NMOS and PMOS), such that they have equal , they could be mixed to form translinear loops. Corollary 4: If two different subthreshold devices are available, such that their parameters add to one , then branches of the first type of device can be mixed with branches of the second type, and vice versa, to form translinear loops. Fig. 10. Translinear symbol representation for subthreshold MOS in ohmic regime. (a) (b) Fig. 11. Subthreshold MOS circuit with one transistor operating in ohmic region. (a) Circuit schematic. (b) Translinear symbol representation. V. EXTENSION TO OHMIC OPERATION As suggested in [2], the translinear principle for subthreshold MOS in saturation is directly extendable to the ohmic region by noting that, from (1), one can obtain the following: (36) Under these circumstances, the symbol in Fig. 10 can be used to build (or analyze) circuit diagrams. The symbol indicates that the fictitious current flowing out of terminal is exponentially controlled by and , while fictitious current flowing out of terminal is exponentially controlled by voltages and , as given by (36). In this case, however, fictitious currents and need to be eliminated by using and another circuit constraint where is the physical current (normalized to size factor ) that flows from the drain terminal to the source terminal. Now the device has two branches, which will be called the branch and branch, and two branches, which will be called the branch and branch. The new and branches can be treated like the previous branches, and the new and branches as the previous branches. As an example, consider the circuit in Fig. 11(a), which was introduced by Delbr¨ uck in 1991 [11]. All transistors operate in saturation except Consequently, all transistors can be represented by the symbol in Fig. 1 except for , which SERRANO-GOTARREDONA et al.: A GENERAL TRANSLINEAR PRINCIPLE FOR SUBTHRESHOLD MOS TRANSISTORS 615 TABLE V TABLE VI has to be represented by the symbol in Fig. 10. The resulting translinear symbol representation is shown in Fig. 11(b). In this figure, the branches of devices 1, 4 and are not shown because both their terminals are connected to ground. In Fig. 11(b) we can choose the two NR loops 1-2f and 4-32r-2f, and loop 3-2r, which form two CTS’s (4-3-2r-2f and 1-2f). For each of them, a possible and wise classification table can be filled out, as shown in Tables V and VI. Since in the loop formed by 4-3-2r-2f branches 3 and 2r are in opposite directions, and so are branches 3 and 2r in the loop, Theorem 3 is fulfilled and, hence, the following translinear relations are satisfied: (37) On the other hand, by (36) (38) Solving (37)–(38) yields (39) Since the output of the circuit is (40) VI. CONCLUSIONS A general translinear principle for analyzing and searching new circuit topologies for subthreshold MOS transistors is provided. This principle takes into account the presence of the bulk terminal and provides the topological conditions under which subthreshold MOS devices satisfy translinear relations in an exact manner, without having to short circuit bulk and source terminals of all transistors. Several corollaries are derived from the generalized subthreshold MOS translinear theorem. Finally, it is also shown how the principle can be extended to subthreshold MOS transistors operating in ohmic region. REFERENCES [1] B. Gilbert, “Translinear circuits: A proposed classification,” Electron. Lett., vol. 11, no. 1, pp. 14–16, 1975. [2] A. G. Andreou and K. A. Boahen, “Translinear circuits in subthreshold MOS,” J. Analog Integr. Circuits Signal Processing, vol. 9, pp. 141–166, 1996. [3] E. A. Vittoz, “Analog VLSI implementation of neural networks,” in Handbook of Neural Computation. Cambridge: Institute of Physics and Oxford Univ. Press. [4] B. A. Minch, C. Diorio, P. Hasler, and C. Mead, “Translinear circuits using subthreshold floating-gate MOS transistors,” J. Analog Integr. Circuits Signal Processing, vol. 9, pp. 167–179, 1996. [5] E. Seevinck and R. J. Wiegerink, “Generalized translinear circuit principle,” IEEE J. Solid-State Circuits, vol. 26, pp. 1198–1102, Aug. 1991. [6] D. R. Frey, “Log-domain filtering: An approach to current-mode filtering,” Proc. Inst. Elec. Eng., vol. 140, pt. G, pp. 406–416, Dec. 1993. [7] E. A. Vittoz and J. Fellrath, “CMOS analog integrated circuits based on weak inversion operation,” IEEE J. Solid-State Circuits, vol. 12, pp. 224–231, Jun. 1977. [8] E. A. Vittoz, “Micropower techniques,” in VLSI Circuits for Telecommunications, Y. P. Tsividis and P. Antognetti, Eds. Englewood Cliffs, NJ: Prentice-Hall, 1985. [9] C. A. Mead, Analog VLSI and Neural Systems. Reading, MA: Addison–Wesley, 1989. [10] Y. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1988. [11] T. Delbr¨ uck, “Bump’ circuits for computing similarity and dissimilarity of analog voltages,” in Proc. Int. Joint Conf. Neural Networks, Seattle WA, 1991, pp. 475–479. Teresa Serrano-Gotarredona received the B.S. degree in electronic physics and the Ph.D. degree in VLSI neural categorizers from the University of Seville, Sevilla, Spain, in 1992 and 1996, respectively, and the M.S. degree in electrical and computer engineering from the Johns Hopkins University, Baltimore, MD, in 1997, where she was sponsored by a Fulbright Fellowship. She is now a Research Staff Member at the Analog Design Department, National Microelectronics Cente, Sevilla, Spain. Her research interests include analog circuit design of linear and nonlinear circuits, VLSI neural-based pattern recognition systems, VLSI implementations of neural computing and sensory systems, and VLSI electrical parameter characterization. She is coauthor of the book Adaptive Resonance Theory Microchips. Dr. Serrano-Gotarredona was corecipient of the 1995–1996 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS Best Paper Award and the recipient of a Fulbright Fellowship. Bernab´e Linares-Barranco received the B.S. degree in electronic physics, the M.S. degree in microelectronics, and the Ph.D. degree in high-frequency OTA-C oscillator design from the University of Seville, Sevilla, Spain, in 1986, 1987, and 1990, respectively, and the Ph.D. degree in analog neural network design from Texas A&M University, College-Station, TX, in 1991. Since September 1991 he has been a Senior Researcher with the Analog Design Department, National Microelectronics Center, Sevilla, Spain. From September 1996 to August 1997, he was on sabbatical at the Department of Electrical and Computer Engineering, the Johns Hopkins University, Baltimore, MD. He has been involved with circuit design for telecommunication circuits, VLSI emulators of biological neurons, VLSI neural-based pattern recognition systems, hearing aids, precision circuit design for instrumentation equipment, bio-inspired VLSI vision processing systems, and VLSI electrical parameters characterization. He is coauthor of the book Adaptive Resonance Theory Microchips. Dr. Linares-Barranco was corecipient of the 1995–1996 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS Best Paper Award. He organized the 1994 Nips Post-Conference Workshop on neural hardware engineering. Since July 1997, he has been Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II and, since January 1998, he has been Associate Editor for the IEEE TRANSACTIONS ON NEURAL NETWORKS.