TCAD simulations on CMOS propagation induced pulse broadening effect: Dependence analysis on the threshold voltage

Depósito de investigación de la Universidad de Sevilla https://idus.us.es/ This is an Accepted Manuscript of an article published by IEEE Transactions on Nuclear Science on 2010/08, available at: https://doi.org/ 10.1109/TNS.2010.2043685 © 2010 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other Works” 1 TCAD simulations on CMOS Propagation Induced Pulse Broadening Effect: Dependence analysis on the Threshold Voltage J. M. Mogoll´ on*, F.R. Palomo, M. A. Aguirre, J. N´ apoles, H. Guzm´ an-Miranda, and E. Garc´ ıa-S´ anchez Abstract—Propagation Induced Pulse Broadening (PIPB) effect is becoming a major concern for electronic designers since new technologies are fast enough to propagate and capture Single Event Transients (SET). In this paper, we explore the influence of the MOSFET threshold voltage (VT) on PIPB effect by TCAD simulating the propagation of an SET after an ion strike, showing up this dependence by the modification of some CMOS technology parameters affecting VT. For this work, the test vehicle used to measure PIPB effect is a self-feedback chain of CMOS inverters. The conclusions outlined can be useful when designing with Multi-Vt nano-metric CMOS technologies. Our results suggest that the |VT|/VDD ratio could be a figure of merit for SET propagation broadening. I. INTRODUCTION SET (Single Event Transient) propagation in an Integrated Circuit has been already studied from different points of view. In [1] an analysis of a chain of inverters considering different gate output load is done. Another approach considering fluctuations of the power supply voltage is made in [2], among many others. As technology shrinks, logic gate speed increases and SET can propagate and even get broader easily through circuitry if transient pulse width is broader than a critical minimum which depends on the technology [3]. As a consequence, the initially very fast transients are broadened enough through the propagation gates to become pulses that have more probability of being stored by edge triggered registers or other digital blocks giving place to data corruption. These transients can also affect analog circuits such as operational amplifiers, voltage regulators [4], etc... In this work we have performed several different Sentaurus TCAD mixed-mode simulations (SPICE-2D) to show the PIPB (Propagation Induced Pulse Broadening) effect dependence on the VTvoltage [5]. We have studied this dependence on the VT voltage by TCAD simulations of different implanted channel doping profiles since it is well known that ion implantation is used mainly to set this threshold value [6]. In this way, we can increase or decrease VTin a realistic manner and observe the correlation between pulse distortion and VTshifts. All simulations are carried out using the test vehicles in fig. 2 and 3. We focus on nodes A, B, C since these nodes are balanced with respect to each other, and PIPB effect is not attributable to unbalance within them. Department of Electronics Engineering, School of Engineering, University of Sevilla, Spain, ∗e-mail: [email protected]. W0W1 tHLtL HtL HtHL Fig. 1. Expected behavior of a transient pulse passing through two identical inverters. The effect of different tLH and tHL delay times on the pulse width is compensated and PIPB should never appear. W0and W1should be identical. Today Multi-Vt nano-metric CMOS technologies offer the possibility to design choosing the VTthreshold for each transistor in the design. With this work we try to compare the response to SET broadening of a simple circuit made up with 2D transistor models for different values of VTafter the strike of a heavy ion. This paper is structured as follows. Section II is a brief revision of the theoretical background of the paper. In Section III the circuit simulated is described. Section IV is devoted to a light introduction to the ion implantation process exploited in this work to adjust the VTvoltage. In section V we performed several simulations varying the doping profile parameters given in section IV. Finally, in section VI, the main conclusions of this work are outlined. II. THEORETICAL BACKGROUND The expected behavior for a transient pulse traveling through two inverters is shown in fig. 1. This behavior can be figured out from the inverter Vo-Vi DC characteristic curve. In the example depicted, the tLH (Low-to-High) delay is shorter than the tHL (High-to-Low) delay due to an inverter switching point voltage (Vsp) over V DD/2. As can be seen, after the first inverter the transient pulse width is broadened. However, when passing through the second inverter the effect is reverted and the initial transient pulse width is recovered. This is the expected behavior in balanced circuits where all the inverters are identical and hence, all of them share the same Vsp. SPICE transient simulation of the circuit in fig. 1 (replacing 2D models for SPICE models from the foundry) agrees with the theoretical prediction showing neither broadening nor narrowing of the transient pulse (see V). However, many experiments carried out by Cavrois et al. [7],[8], have shown that PIPB effect occurs in chains of SOI and bulk CMOS inverters. To reproduce these phenomena, HSPICE models 2 415 SPICESPICE SPICESPICESPIC E IBM8RF-2DIB M8RF-2DIBM8RF-2D Node A SPICE IBM8RF-2D Node CNode B Fig. 2. Test Vehicle A is composed of four mixed inverters (2D-HSPICE) and 12 full-HSPICE models. 2D models are placed to produce the distortion of the transient pulse. The pulse is generated by an ion strike in the first 2D NMOS. The rapid propagation of the pulse through the chain makes necessary to introduce several HSPICE models to delay the return of the transient to the first inverter avoiding pulse superposition. As can be seen, nodes A, B and C share the same boundary conditions, so there exists no unbalance between any of them. 415 SPICESPICE IBM8RF-2DIB M8RF-2DIBM8RF-2D Node A IBM8RF-2D Node CNode B Fig. 3. Test Vehicle B is composed of four 2D inverters and 12 full-HSPICE models. 2D models are placed to produce the distortion of the transient pulse. The pulse is generated by an ion strike in the first 2D NMOS. The rapid propagation of the pulse through the chain makes necessary to introduce several HSPICE models to delay the return of the transient to the first inverter avoiding pulse superposition. As can be seen, nodes A, B and C share the same boundary conditions, so there exists no unbalance between any of them. delivered by the foundries in their process design kits (PDK) are not valid if used without including external parasitic elements [9]. The connection between the Vsp and the device physics can be done through the equation relating Vsp and VT[10]: Vsp =qβn βp·VT n + (V DD −VT p) 1 + qβn βp (1) where βnand βpare the trans-conductance parameters for the NMOS and PMOS transistors respectively, VT n and VT p are the corresponding threshold voltages, and VDD the bias voltage. We can change linearly Vsp by changing VT n or VT p. The voltage threshold for an NMOS and PMOS transistors is given by [6]: VT n =VT0n+γ(pφ0+VSB −pφ0)(2) VT p =VT0p−γ(pφ0−VSB −pφ0)(3) where VT0is the voltage threshold for VSB = 0,φand γare constants depending on different technology parameters, and VSB is the source-bulk voltage. For short-channel transistors, the term VT0depends also on VSB , nevertheless, for the work done in this paper this dependence is no longer relevant since no quantitative effects are measured. From eq. (2) and (3), when VSB is fixed, VTis a constant. However if VSB can fluctuate, then VTis no longer a constant, so, from eq. (1), Vsp will be different among the inverters and the PIPB effect probably will appear as was demonstrated in [7]. In [7] this effect is simulated on SPICE models by selectively adding +50 mV to the NMOS bulk contact (-50 mV to the n-well contact for PMOS transistors) to achieve a negative VSB voltage in NMOS transistors (positive for the PMOS) placed at specific positions in a chain of inverters. This gives place to a staggered bias voltage for the bulk contact along the chain of inverters. This condition of asymmetry in VTis enough to give place to PIPB effect as described in [5]. For bulk CMOS devices, capacitive coupling between the gate and the body surface near the MOS channel (a.k.a. “back gate”) is probably the main factor causing staggered body bias in symmetrically loaded inverters [11]. To take account of this effect, a parasitic gate-to-body capacitance can be placed between the gate and bulk contacts in the PDK models [9], 3 giving place to the expected pulse broadening. Our approach deals with 2D TCAD models that include no external elements. The use of these models allows us to face the problem from the process technology perspective. This approach is justified since, in advanced CMOS processes, technology parameters have become a major constraint for “back gate” surface potential, less and less controllable by layout designers considerations [9]. TCAD simulations make it possible to “look inside” the device during the transients and some physical variables such as the electrostatic potential in the bulk mesh can be analyzed. Such a study is performed at the end of section V to throw some light on the commonly accepted theory of staggered body bias mentioned above in this section to explain PIPB effect. By selectively changing VTthrough technology parameters, we will observe the behavior of the transient pulse for the circuit under test. III. TEST VEHICLE The circuit under test is a self-feedback CMOS inverter chain. It has been simulated the impact of a heavy ion and the later propagation of the fast voltage transient pulse through it. Fig. 4 is the schematic of both test vehicles with the situation of the 2D models in the chain and the initial logic state. By using feedback, we reduce the computational task minimizing the number of 2D-models. Consequently, the number of Poisson and electron-hole equations to solve. ‘0’ SPIC E 2D -0 ‘0’‘1’‘1’ ‘0’‘1’ 2D -12D -22D -3 Fig. 4. Schematic of the test vehicles A and B showing the 2D-inverters in positions 0,1,2 and 3. Even inverters correspond to positions 0 and 2, and odd inverters correspond to positions 1 and 3 (see section V). The initial logic state of the chain (previous to ion strike) is showed. The technology simulated in this work is based on the IBM 8RF twin well 130 nm CMOS process and the TCAD calibration described in [12]. To reduce computational overload, the inverter chain is composed of two types of inverters. In test vehicle A, four of them are mixed models, with a 2D model of the NMOS and an HSPICE model for the PMOS. In test vehicle B, four of the inverters are full 2D models with 2D models for the NMOS and PMOS devices. The remaining inverters are full HSPICE models. The W/L aspect ratios for the PMOS and NMOS transistors are not considered relevant, since unequal NMOS/PMOS drive does not cause pulse broadening as stated in [11]. The mixed model inverters have two purposes: it is possible to simulate a heavy ion strike and it is also possible to change technology parameters in the implanted channel doping profiles of the transistors and other technology parameters. HSPICE inverters increase the time it takes to the pulse to pass through the whole chain to simplify the visualization of the transient simulations. The ion LET (Linear Energy Transfer) is set to induce a voltage transient width over a critical minimum [3]. Test vehicles A and B are balanced if looking to the nodes A to C. We are interested in pulse FWHM (Full Width at Half Maximum) broadening due to the intrinsic device physics and not attributable to circuital asymmetries. Test Vehicle A will be used to study pulse broadening within nodes A, B, C (see fig.2) when only the NMOS transistor in the inverter is a 2D model. This way we compute the contribution of the NMOS transistor trying with different values for the characteristic parameters of the implanted channel (see IV). Test Vehicle B will be also used within the sub-chain composed by the first four inverters, observing pulse broadening between nodes A and C. Comparing with Test vehicle A, we can take account of the PMOS transistor contribution to PIPB effect. Transient simulations have been performed where the 2D TCAD NMOS model in the first inverter of the chain is affected by an ion-strike. After the strike, the pulse propagates freely along the chain. IV. IMPLANTED CHANNEL Ion implantation is the preferred method in modern CMOS technology to introduce dopants in shallow regions of silicon wafers like the channel region. Sentaurus TCAD can model ion implantation so it is possible to reproduce technological effects. By mean of the Vt implant, fine tuning of the transistor threshold voltage is achievable, and also the Id-Vg characteristic can be changed in a drastic manner [6]. A first-order model for an implant doping profile is mathematically described by a gaussian distribution [10], N(x) = Npexp[−(x−Rp)2 2∆R2 p ](4) where Npis the peak dopant concentration, Rpis the depth of the peak and ∆Rpis the standard deviation of the profile. To try different approaches to change VTwe have taken into account little variations in the ion-implantation process and we have performed some simulations on the parameters of eq. (4). So, we have divided simulations in three types each of one considering different values for the parameters Np,Rp and ∆Rpfor the NMOS transistor and variations on Npfor the PMOS transistor. Rpand ∆Rpfor PMOS are fixed parameters with values 16.5 nm and 5.76 nm., respectively. A. Doping Peak Concentration The beam fluence of the ion implantation process affects the doping peak concentration Npin eq. (4). The nominal peak concentration for this technology is 6e+18 cm−3for the NMOS and 5e+18 cm−3for PMOS as can be seen by previous calibration against the HSPICE models. NMOS Id-Vg curves are plotted in fig. 5-a. The changes on the absolute value of VTwhen decreasing or increasing Npin the PMOS device is the same as that in the NMOS device (Rpand ∆Rpfor NMOS with values 16.5 nm and 5.76 nm., respectively). 4 3e+18 cm−3 4e+18 cm−3 5e+18 cm−3 6e+18 cm−3 Vg (V) 0.5 1 Id (A) 0.0e+00 2.0e−04 4.0e−04 6.0e−04 (a) VTshifting by Npvariation. Rp= 16.5 nm. and ∆Rp= 5.76 nm. 60.0 nm 25.0 nm 16.5 nm 8.2 nm Vg (V) 0.5 1 Id (A) 0.0e+00 2.0e−04 4.0e−04 6.0e−04 (b) VTshifting by Rpvariation. Np= 6e+18 cm−3and ∆Rp= 5.76 nm. 2.79 nm 3.49 nm 4.89 nm 5.76 nm Vg (V) 0.5 1 Id (A) 0.0e+00 2.0e−04 4.0e−04 6.0e−04 (c) VTshifting by ∆Rpvariation. Np= 6e+18 cm−3and Rp= 16.5 nm. Fig. 5. 2D NMOS model Id-Vg DC curves. Vt is shifted by variation of technological parameters in eq. (4) within the nominal values for this technology. The shift is similar for the absolute value of Vtin the PMOS transistor. B. Doping Peak Depth The energy of the implantation ion beam determines the depth Rpwhere the peak of the doping profile is allocated. We also have simulated the impact in pulse distortion of changing this value within the nominal value of 16.5 nm under the gate oxide for the NMOS device. VTshifting for the NMOS is showed in fig. 5-b (Npand ∆Rpfor NMOS with values 6e+18 cm−3and 5.76 nm., respectively). C. Doping Standard Deviation This parameter is associated with range straggling during ion implantation, and several different values has been simulated to complete this work. The nominal value for the standard deviation of the gaussian profile is 5.76 nm. In this case we have simulated 2.79 nm, 3.49 nm, 4.89 nm and 5.76 nm (See fig.5-c) for the NMOS device. (Npand Rpfor NMOS with values 6e+18 cm−3and 16.5 nm., respectively) V. ION-STRIKE AND PIPB SIMULATIONS We have carried out different simulations to test the PIPB dependence on Vt shifts for the NMOS and PMOS devices. In a first step, the peak dopant concentration Npis increased gradually to study its effect in pulse broadening. The second step is to increase the doping peak depth Rp. The final step consists of changing the doping standard deviation ∆Rpof the gaussian implantation profile. All the parametric variations are made around the nominal or constant values obtained for the calibrated model used by [12] for the implanted channel doping profile. A. Test Vehicle A In this subsection, we describe the set of simulations carried out on the circuit shown in fig.2 considering only the transient pulse distortion from node A to node C, this way taking into account the distortion in the 0 to 1 and 1 to 0 transitions. As can be seen, the three nodes (A, B, C) are identical and share the same boundaries. In this case, unbalance does not exist so the broadening is intrinsically due to the device and the solid state physics involving its response to a fast pulse. Tables I, II and III show the pulse broadening (or PIPB factor) measured between nodes A and C for several round trips after the ion strike (see fig.2). The behavior observed is the same for all groups of simulations. The broadening (or PIPB factor) decrease monotonically with increasing number of round trips, this can be explained if we consider that before the first pulse arrives, the system is in a quiescent state. After pulse train establishes, PIPB factor decays to 0 due to the high repetition rate (2.5 Ghz approx.). This result agrees to that in [11] for SOI devices, where PIPB factor decrease by increasing switching frequency and approaches 0 for frequencies over several Mhz. This behavior is related to the time the body potential needs to stabilize [7]. We have observed how, for lower values of VT, the PIPB factor tends rapidly to zero, keeping the pulse width with minor variations. The PIPB effect is more significant for higher VT. This result is clear if we observe fig. 6. It shows graphically the content of Table I. The Y-axis shows the observed broadening after two inverters, from node A to node C. If we replace 2D models for HSPICE models (as-delivered by the foundry) we have the full-SPICE curve in fig. 6 showing no PIPB effect. B. Test Vehicle B In this case we introduce a 2D model for PMOS transistors in the first four inverters of Test Vehicle A, this way we have the circuit depicted in fig. 3. We will try to observe the contribution of PMOS transistor to PIPB effect by trying different peak concentrations (Np) in the implanted channel doping profile of the PMOS. In other words, we will expand some of the curves in fig.6 by trying different Npvalues in the PMOS 2D model. 5 0 2 4 6 8 10 −1 0 1 2 3 4x 10 −12 Round Trips Broadening (s / trip) 6e+18 cm−3 3e+18 cm−3 4e+18 cm−3 5e+18 cm−3 full−SPICE Fig. 6. Differential pulse broadening per trip (node A to C in test vehicle A, fig. 2) as a function of the total number of trips for different VTvalues for the 2D NMOS transistor. For the full-SPICE case, the PIPB effect does not exist. As can be seen in fig. 7, PMOS device contributes increasing PIPB factor. It is also noticeable how the decreasing rate in the PIPB factor after the first pulse is higher when considering the PMOS 2D model. Another remarkable effect is observed when looking fig.7. If one compares fig.7.a with fig.7.b and fig.7.c, it can be stated that the effect of PMOS variations in Npis less and less appreciable when decreasing Npin the NMOS transistor. C. Shallow Bulk Voltage Analysis To better understand the parasitic coupling effects affecting bulk biasing near the transistor channel, we exploited the possibilities of TCAD simulations to extract information about voltage inside the bulk region of the 2D models. In the chain of inverters under study, the accepted theory to explain PIPB effect is the staggered bias in the substrate near the channel due to capacitive coupling mainly [9],[11]. We have plotted the bulk voltage (VB) along an orthogonal cut 100 nm under the gate oxide as depicted in figure 8 for both the NMOS and PMOS transistors. As a visual reference, Fig. 8 shows the 100 nm cut in the NMOS transistor 2D-model used in this paper. We have focused on the bulk biasing for the NMOS and PMOS transistors in the chain before the ion strike. When plotting the voltage across the transistor 2D-model at 100 nm from the surface we encountered a dependence on bias state of the corresponding inverter along the chain. The bias state is different for even or odd inverters due to different gate voltages. Fig. 9 shows the bulk bias voltage in the steady state before the ion strike. The left side corresponding to the source side and the right side corresponding to the drain side of the NMOS (reversely for the PMOS). As can be observed, in the steady state exists a shift in the voltage in the region under the channel (around the center at X= 0 µm and 100 nm in-depth). This shifts is about +200 mV approximately for the even NMOS respect to the odd NMOS and somewhat less than -200 mV for the odd PMOS respect to the even PMOS. We have also observed the bulk voltage after the ion strike in PMOS and NMOS transistors in both even and odd inverters 0 2 4 6 8 10 1 2 3 4 5 6x 10 −12 Round Trips Broadening (s / trip) SPICE 6e+18 cm−3 5e+18 cm−3 4e+18 cm−3 (a) NMOS Np= 6e+18 cm3 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 3.5 4x 10 −12 Round Trips Broadening (s / trip) SPICE 6e+18 cm−3 5e+18 cm−3 4e+18 cm−3 (b) NMOS Np= 5e+18 cm3 0 2 4 6 8 10 0.5 1 1.5 2 2.5 3x 10 −12 Round Trips Broadening (s / trip) SPICE 6e+18 cm−3 5e+18 cm−3 4e+18 cm−3 (c) NMOS Np= 4e+18 cm3. All the curves are exactly the same, no dependence exists on Np. Fig. 7. Differential pulse broadening per trip (node A to C in test vehicle B, fig. 3) as a function of the total number of trips for different VTvalues for the 2D PMOS transistor (SPICE model is also included), given a fix value for the NMOS Np. Subfigure (a) corresponds to Np= 6e+18 cm3for the NMOS, (b) corresponds to Np= 5e+18 cm3for the NMOS and (c) corresponds to Np= 4e+18 cm3for the NMOS. to find an explanation to the decreasing broadening as the pulse travel along the chain again and again. In the period between pulses, the bias voltage experiences a shift that is remarkable in the PMOS placed at odd positions. In fig. 10 we can observe a detail of the peak voltage in odd and even PMOS transistors (the detailed fig. 10 correspond to the top of the PMOS curves in fig. 9). It is interesting to realize how 6 Broadening (ps) Doping Peak Concentration higher VT→ Round Trip 3e+18 cm-3 4e+18 cm-3 5e+18 cm-3 6e+18 cm-3 1 1.088 2.104 3.219 3.639 2 0.269 1.035 1.865 2.332 3 0.065 0.676 1.475 1.895 4 0.039 0.614 1.337 1.788 5 -0.014 0.577 1.263 1.680 6 0.005 0.576 1.161 1.554 7 -0.022 0.544 1.117 1.421 8 0.000 0.574 1.063 1.390 9 0.000 0.515 1.006 - TABLE I PULSE BROADENING MEASURED BETWEEN NODES AAND CIN TEST VEHICLE AAFTER SEVERAL ROUND TRIPS FOR DIFFERENT NMOS NpVALUES (Rp= 16.5 nm AND ∆Rp= 5.76 nm). Broadening (ps) Doping Peak Depth higher VT→ Round Trip 60 nm 25 nm 16.5 nm 8.2 nm 1 0.415 0.118 3.639 8.140 2 0.062 -0.491 2.332 4.076 3 -0.175 -0.540 1.895 2.881 4 -0.133 -0.476 1.788 2.331 5 -0.147 -0.518 1.680 1.978 6 -0.172 -0.499 1.554 1.682 7 -0.189 -0.514 1.421 1.401 8 -0.214 -0.424 1.390 1.256 TABLE II PULSE BROADENING MEASURED BETWEEN NODES AAND CIN TEST VEHICLE AAFTER SEVERAL ROUND TRIPS FOR DIFFERENT NMOS RpVALUES (Np= 6E+18 cm−3AND ∆Rp= 5.76 nm). Broadening (ps) Doping Standard Deviation higher VT→ Round Trip 2.79 nm 3.49 nm 4.89 nm 5.76 nm 1 1.016 1.715 3.342 3.639 2 0.232 0.735 2.025 2.332 3 0.078 0.502 1.623 1.895 4 0.015 0.399 1.500 1.788 5 0.009 0.354 1.399 1.68 6 -0.011 0.351 1.332 1.554 7 -0.045 0.330 1.278 1.421 8 -0.043 0.307 1.248 1.390 9 -0.014 0.284 1.16 - 10 -0.022 0.289 1.133 - TABLE III PULSE BROADENING MEASURED BETWEEN NODES AAND CIN TEST VEHICLE AAFTER SEVERAL ROUND TRIPS FOR DIFFERENT NMOS ∆RpVALUES (Np= 6E+18 cm−3AND Rp= 16.5 nm). the shift in even PMOS is negligible as round trips increase but in odd PMOS the final shift due to the pulse repetition rate is near 50mV. The bulk bias tends to stabilize gradually as expected [7]. In the case of NMOS the effect is much less noticeable, probably due to the difference in the lifetime of charge carriers in the PMOS and NMOS transistors. VI. CONCLUSIONS Variations in the implanted channel doping profile are critical in the threshold voltage (VT) final value of an NMOS transistor (the same is valid for the PMOS transistor). This variations in VThave shown to be a relevant factor in the appearance of the PIPB effect and in general in the distortion of the transient pulse. Simulations show a clear cause-effect relation between the VTthreshold and the transient pulse distortion through logic gates in CMOS technology. The lookinginside capability of TCAD, by showing the bulk voltage level curves, also demonstrate the staggered bias hypothesis as the responsible of the PIPB effect. For the simulations performed over Test Vehicle A, we have shown how for higher VTthe PIPB effect is more significant. The PIPB values are in accordance to that in [7] for the PIPB factor in 130 nm bulk CMOS technologies. The effect of pulse repetition rate is also noticed, agreeing with previous works, showing a bigger PIPB factor for the first pulse arriving (quiescent state) and a tendency to zero for successive pulses. 7 100 nm Fig. 8. Detail of the upper side of the NMOS model with the dashed line showing the 1D-region where voltage is analyzed at 100 nm from the surface. The same region has been analyzed in PMOS transistors. −0.5 −0.25 0 0.25 0.5 0 0.5 1 X (um) Voltage (V) PMOS−even PMOS−odd NMOS−even NMOS−odd Fig. 9. NMOS and PMOS bulk bias voltage at 100 nm from the surface. The effective bulk voltage is slightly different from even to odd inverters. Parasitic capacitive coupling gives place to staggered bias along the chain of inverters in the region under the channel −0.02 −0.01 0 0.01 0.02 0.03 0.04 0.05 1.25 1.3 1.35 1.4 X (um) Voltage (V) round trips increase EVEN PMOS CURVES ODD PMOS CURVES Fig. 10. Detail of the PMOS bulk voltage at 100 nm from the surface after several round trips. The odd bulk voltage shifts considerably reducing the difference between even and odd transistors. The shifting from one round trip to the next is shorter as round trips increase. After stabilization, the total shift is about 50 mV. In the case of the NMOS this shift is less significant. Test Vehicle B includes PMOS transistor to observe the contribution to PIPB of this device related to NMOS. As supposed, the PIPB factor is increased, and the increase is higher for higher |VT|values (as in the NMOS case). This effect is not appreciable when lowering VTin the NMOS transistor. It is also noticeable that the PIPB factor decreasing rate is high when considering the 2D models for the PMOS devices. Previous works on PIPB effect, report a similar tendency in PIPB factor when changing VDD [11],[7]. Decreasing bias voltage has the same effect on PIPB that increasing VTas is shown in this paper. These results suggest that the |VT|/VDD ratio can be a figure of merit to have in mind when considering propagation of SET, higher values mean higher PIPB factors. Multi-Vt CMOS technologies offer designers the possibility to use transistors choosing usually among several values of VTfor each single transistor. Our simulation work shows that it must be taken into account the probable appearance of PIPB effect depending on the faster low-VTor slower high-VT transistors choice. As an example, for critical combinational logic blocks in digital circuits, the designer can consider the use of low-VT transistors in order to harden the circuit against pulse broadening in the propagation of SETs. In this work, electrodes are modeled as ohmic or gate contacts as defined in the Electrical Boundary Conditions for Sentaurus Device simulator [13]. Hence, the metal stack-up structure at drain and gate electrodes are not considered even though probably affects the results in the dynamic capacitive coupling to the shallow bulk region. This issue will be approached in future works. Finally, we conclude that any other VT-shift phenomena like those associated to TID (Total Ionizing Dose) can give place to transient distortion in circuits where normally it would never occur. It must be taken into account by circuit designers and hardened technologies conceived to operate in harsh radiation environments. Furthermore, the increase in the speed of electric signals in today commercial technologies implies that some care must be taken with jitter in clock signals over hundreds of Megahertz. REFERENCES [1] G. Wirth, F. L. Kastensmidt, and I. Ribeiro. Single event transients in logic circuitsload and propagation induced pulse broadening. IEEE Transactions on Nuclear Science, 55:2928–2935, dec 2008. [2] M. J. Gadlage, R. D. Schrimpf, B. Narasimham, B. L. Bhuva, P. H. Eaton, and J. M. Benedetto. Effect of voltage fluctuations on the single event transient response of deep submicron digital circuits. IEEE Transactions on Nuclear Science, 54:2495–2499, dec 2007. [3] P. E. Dodd, M. R. Shaneyfelt, J. A. Felix, and J. R. Schwank. Production and propagation of single-event transients in high-speed digital logic ICs. IEEE Transactions on Nuclear Science, 51:3278–3284, dec 2004. [4] A. T. Kelly, P. C. Adell, A. F. Witulski, W. T. Holman, R. D. Schrimpf, and V. Pouget. Total dose and single event transients in linear voltage regulators. IEEE Transactions on Nuclear Science, 54:1327–1334, aug 2007. [5] A. Wei, D. A. Antoniadis, and L. A. Bair. Minimizing floating-bodyinduced threshold voltage variation in partially depleted SOI CMOS. IEEE Electron Device Letters, 17(8):391–394, aug 1996. [6] Yannis Tsividis. Operation and Modeling of the MOS Transistor. Oxford University Press, 2003. 8 [7] V. F. Cavrois, V. Pouget, D. McMorrow, J. R. Schwank, N. Fel, F. Essely, R. S. Flores, P. Paillet, M. Gaillardin, D. Kobayashi, J. S. Melinger, O. Duhamel, P. E. Dodd, and M. R. Shaneyfelt. Investigation of the propagation induced pulse broadening (PIPB) effect on single event transients in SOI and bulk inverter chains. IEEE Transactions on Nuclear Science, 55:2842–2853, dec 2008. [8] V. Ferlet-Cavrois, P. Paillet, D. McMorrow, N. Fel, J. Baggio, S. Girard, O. Duhamel, J. S. Melinger, M. Gaillardin, J. R. Schwank, P. E. Dodd, M. R. Shaneyfelt, and J. A. Felix. New insights into single event transient propagation in chains of invertersevidence for propagationinduced pulse broadening. IEEE Transactions on Nuclear Science, 54:2338–2346, dec 2007. [9] P. Tuinenga and Ll. Massengill. Circuit modeling of single-event transient pulse stretching in digital CMOS. In Nuclear and Space Radiation Effects Conference, 2009, Quebec (Canada), July 2009. [10] R. Jacob Baker. CMOS Circuit Design, Layout, and Simulation. IEEE Press, 2008. [11] L. W. Massengill and P. W. Tuinenga. Single-event transient pulse propagation in digital CMOS. IEEE Transactions on Nuclear Science, 55:2861–2871, dec 2008. [12] O. A. Amusan, L. W. Massengill, M. P. Baze, A. L. Sternberg, A. F. Witulski, B. L. Bhuva, and J. D. Black. Single event upsets in deepsubmicrometer technologies due to charge sharing. IEEE Transactions on Device and Materials Reliability, 8(3):582–589, sep 2008. [13] Sentaurus TCAD Tools. Synopsys, Inc., 2007. View publication stats