Efficient cache architectures for reliable hybrid voltage operation using EDC codes

E icien Cache A chi ec u es o Reliable Hyb id Vol age Ope a ion Using EDC Codes Bojan Ma ic1,2Jaume Abella2Ma eo Vale o1,2 1Ba celona Supe compu ing Cen e (BSC-CNS) 2Uni e si a Poli ecnica de Ca alunya (UPC) {bojan.ma ic, jaume.abella, ma eo. ale o}@bsc.es Abs ac —Semiconduc o echnology e olu ion enables he de- sign o senso -based ba e y-powe ed ul a-low-cos chips (e.g., below 1 C) equi ed o new ma ke segmen s such as body, u ban li e and en i onmen moni o ing. Caches ha e been shown o be he highes ene gy and a ea consume in hose chips. This pape p oposes a no el, hyb id-ope a ion (high Vcc, ul a- low Vcc), single-Vcc domain cache a chi ec u e based on eplac- ing ene gy-hung y bi cells (e.g., 10T) by mo e ene gy-e icien and smalle cells (e.g., 8T) enhanced wi h E o De ec ion and Co ec ion (EDC) ea u es o high eliabili y and pe o mance p edic abili y. Ou a chi ec u e is p o en o la gely ou pe o m exis ing solu ions in e ms o ene gy and a ea. Index Te ms—Caches, Low Ene gy, Reliabili y, Real-Time I. INTRODUCTION Highe semiconduc o echnology in eg a ion due o geome y scaling opens he doo o new ma ke segmen s. In pa icula , echnology e olu ion enables adding some deg ee o in elligence o any con ol o measu ing engine such as biomedical senso applica ions o moni o he body, en i onmen senso applica- ions o moni o wind, empe a u e, sunamis, e c., by means o ba e y-powe ed ul a-low-cos (e.g., below 1 C) compu ing de ices. The main equi emen s o his new ma ke segmen a e: (i) ul a-low ene gy consump ion in o de o ex end ba e y li e ime, (ii) e y simple sys em design o inc eased yield and educed cos and (iii) s ong unc ional and iming gua an ees equi ed o he wo s -case execu ion ime (WCET) es ima ion, as needed o unning c i ical applica ions on op. Typically, hose compu ing sys ems ha e wo ope a ion modes and di e en op imal supply ol ages (Vcc): (i) high-pe o mance and low- powe ope a ion mode unde high o mode a e ol age (HP mode o sho ) du ing ela i ely sho pe iods o ime o eac o some in equen pa icula e en s (e.g., 0.01% - 1% o he ime [19]) and (ii) low pe o mance, ul a-low ene gy and eliable ope a ion mode unde nea -/sub- h eshold (NST) ol age (ULE mode o sho ) du ing mos o he ime un il in equen e en s a ise (e.g., 99% - 99.99% o he ime [19]). Cache memo ies a e used in hose sys ems o educe he numbe o slow and ene gy-hung y memo y accesses, hus inc easing he e iciency o he sys em. Howe e , caches become he main ene gy consume on he chip. Cheap solu ions based on a single-Vcc domain ha e been demons a ed ecen ly [14], [15]. Those caches use la ge memo y cells o achie e high le els o eliabili y e en a ULE mode, as needed by c i ical applica ions un on op. Dec easing he size o he memo y cells o highe ene gy e iciency a he expense o highe ailu e a es is unaccep able in his en i onmen . Faul y en ies should be hen disabled and s ong pe o mance gua an ees equi ed by c i ical applica ions would no be achie able [20]. 978-3-9815370-0-0/DATE13/©2013 EDAA This pape p oposes a no el single-Vcc domain cache a - chi ec u e whose main cha ac e is ics a e: (i) low ene gy con- sump ion, (ii) simple design and (iii) high eliabili y le els, ou pe o ming exis ing solu ions [14]. In pa icula , ou cache design elies on eplacing ene gy-hung y bi cells (e.g., 10T) by mo e ene gy-e icien and smalle cells (e.g., 8T) enhanced wi h e o de ec ion and co ec ion (EDC) ea u es. We illus a e ou cache a chi ec u e wi h wo scena ios, depending on he eliabili y le el o he baseline (no coding o single e o co ec ion double e o de ec ion (SECDED)), whe e 10T cells a e eplaced by smalle 8T cells (a) by keeping no coding a HP mode and by adding SECDED a ULE mode, whene e no coding is in place o (b) by keeping SECDED a HP mode and by eplacing SECDED by double e o co ec ion iple e o de ec ion (DECTED) a ULE mode, whene e SECDED is in place. Ou cache a chi ec u e achie es signi ican ene gy sa ings (up o 14% and up o 42% on a e age a HP and ULE mode espec i ely) and small a e age pe o mance deg ada ion (up o 3%) wi h espec o exis ing solu ions [14] while keeping he same gua an eed pe o mance and eliabili y le els. II. RELATED WORK The e is an abundance o li e a u e on low-powe echniques o caches. Double-ended 6T (6 ansis o s) SRAM cells ha e been widely deployed o high ol age ope a ion. Nume ous SRAM cell designs such as 8T [16], Schmi -T igge 10T (10T) [12], e c. a ge di e en ol age and obus ness sce- na ios. Howe e , hose SRAM cells in oduce signi ican a ea and ene gy o e heads w. . . 6T cells a high ol age, which is una o dable in embedded cache design i used ex ensi ely. Some au ho s p esen echniques o sa e ene gy by econ igu - ing cache cha ac e is ics such as cache size and associa i i y [3] o lowe ing cache Vcc [9] (o e en ga ing i [18]) o some cache sec ions o he whole cache. O he au ho s p opose spli ing he cache in o di e en modules [11]. Zhou e al. [23] p opose downsizing 6T cells o la ge on-chip caches combined wi h EDC echniques and ex a cells o gua an ee a a ge yield. In gene al, hose echniques a e unsui able o ou ma ke since hey ail o ope a e eliably a ULE mode. Techniques based on ha ing mul iple Vcc domains a e un- a o dable o ou a ge ul a-low-cos (e.g., below 1 C) ma - ke [8]. Likewise, echniques based on disabling aul y cache en ies [21], [1], [7] ail o p o ide s ong iming gua an ees equi ed o he wo s -case execu ion ime (WCET) es ima ion, as needed o c i ical applica ions in ou a ge ma ke [20]. A ailu e o pe o m an ope a ion co ec ly and wi hin a gi en ime may ha e ca as ophic consequences in hese en i onmen s. Ma ic e al. [14] p opose hyb id-ope a ion, single-Vcc domain cache a chi ec u es, sui able o ou a ge ma ke . Ne e heless, au ho s nai ely achie e obus ness a ul a-low Vcc by simply Fig. 1. P oposed cache a chi ec u e o scena io A. inc easing bi cells size, which ansla es in o la ge a ea and ene gy o e heads. Ou app oach builds upon he solu ion by Ma ic e al. educing ene gy and a ea o e heads while keeping obus ness, simplici y and pe o mance p edic abili y. III. PROPOSED HYBRID CACHE ARCHITECTURE In his sec ion, we i s desc ibe he cache a chi ec u e ha we use as he baseline. Nex , we p esen ou p oposal as well as he design me hodology o he p oposed a chi ec u e. A. Baseline A chi ec u e Based on he ac ha mos L1 caches in exis ing chips a e se -associa i e, we ha e chosen such o ganiza ion as he a ge o ou s udy, al hough signi ican pa s o ou s udy can be easily eused o di ec -mapped and ully-associa i e caches. We use a hyb id-ope a ion, single-Vcc domain cache design pa icula ly sui ed o ou a ge ma ke [14] as a s a ing poin . The cache is designed in such a way ha some o he cache ways a e op imized o sa is y high pe o mance equi emen s du ing high Vcc ope a ion (HP ways) whe eas he es o he ways p o ide ul a-low ene gy consump ion and eliabili y du ing NST Vcc ope a ion (ULE ways). In pa icula , we use a 6T+10T hyb id cache as he baseline [14]. In his design, HP ways a e implemen ed wi h di e en ial 6T bi cells whe eas he ULE ways consis o 10T bi cells, al hough ou p oposal is no limi ed o his design. Du ing ULE mode, da a p ocessing is expec ed o be minimal and wo kloads a e much smalle han du ing HP mode [19]. Wo kload disc epancy ac oss HP and ULE mode jus i ies educing he ha dwa e esou ces a ULE mode. Since HP ways would expe ience many aul s a NST Vcc and hus would no p o ide eliable ope a ion, hey a e u ned o a ULE mode. Howe e , all cache ways a e enabled a HP mode o i la ge wo kloads and p o ide high pe o mance. ULE ways a e eused a HP mode, in spi e o hei ine iciency a high Vcc, because hey educe he numbe o slow and ene gy-hung y memo y accesses [15]. The main d awback o his design is using la ge 10T cells o gua an ee obus aul - ee NST ope a ion. Simply dec easing he size o hese la ge memo y cells o eplacing hem by cheape cells (e.g., 8T) o highe ene gy e iciency would inc ease ailu e a es. Faul y en ies should be hen disabled and s ong pe o mance gua an ees equi ed by c i ical applica ions would no be achie able [20]. In o de o o e come he ine iciency o he la ge memo y cells (e.g., 10T) in e ms o a ea and ene gy, we p opose a new, simple, ene gy-e icien cache design wi hou jeopa dizing eliabili y le els o s ill p o ide p edic able pe o mance. B. Ou P oposal We illus a e ou p oposed cache a chi ec u e wi h wo scena - ios depending on he eliabili y le el o he baseline cache. In he i s scena io, we conside a 6T+10T baseline cache whe e no coding is in place. In he second scena io, he baseline cache has highe eliabili y and all ways a e SECDED p o ec ed o deal wi h so e o s (6T+SECDED+10T+SECDED). Ou cache design elies on eplacing ene gy-hung y bi cells (e.g., 10T) in ULE ways by mo e ene gy-e icien and smalle cells (e.g., 8T) enhanced wi h e o de ec ion and co ec ion ea u es o keep he same eliabili y le els, which a e pa icula ly c i ical a ULE mode. Figu e 1 depic s ou p oposed cache a chi ec u e o he i s scena io. Reliabili y o ULE ways a HP mode in bo h scena ios is no an issue, because bo h 8T and 10T cells a e mo e eliable (by some o de s o magni ude) han 6T ones a high ol age, hus he same coding (none o SECDED) as ha used o he baseline cache su ices. Howe e , a ULE mode, s onge codes (SECDED, i none in baseline o DECTED, i SECDED in baseline) mus be used, because smalle 8T cells a e less eliable han 10T a NST Vcc. The e o e, we ha e: Scena io A. The baseline is a 6T+10T cache and no coding is in place. 10T cells a e eplaced by smalle and less eliable 8T cells by adding SECDED whene e no coding is in place (6T+10T s. 6T+8T+SECDED). SECDED is only equi ed o deal wi h ha d aul s in 8T cells a ULE mode. A HP mode, SECDED is simply u ned o (6T+10T s. 6T+8T). Scena io B. The baseline has highe eliabili y han ha o scena io A since all cache ways a e SECDED p o ec ed o deal wi h so e o s (6T+SECDED+10T+SECDED). 10T cells a e eplaced by smalle and less eliable 8T cells by eplacing SECDED (only o ULE ways) by DECTED whene e SECDED is in place o deal wi h so e o s (6T+SECDED+10T+SECDED s. 6T+ SECDED+8T+DECTED). DECTED is only equi ed o deal wi h ha d aul s in 8T cells a ULE mode. A HP mode, DECTED is simply u ned o since SECDED p o ec ion o 8T cells is su icien o deal wi h so e o s a high Vcc (6T+ SECDED+10T+SECDED s. 6T+SECDED+8T+SECDED). Using EDC in oduces delay, ene gy and a ea o e heads. As desc ibed la e in Sec ion IV, we conside hose o e heads in ou calcula ions. Tu ning o HP ways a ULE mode is done by using he ga ed-Vdd echnique [18]. The p ocesso i sel is esponsible o ga ing o unga ing he co esponding cache ways (o co esponding EDC block) on a Vcc change. O e heads a e negligible, as explained in [18]. In he es o he pape , we use di e en ial 6T o HP ways, 8T o ULE ways, Hsiao SECDED and DECTED codes [5] and 32nm echnology node. Howe e , ou a chi ec u e is no limi ed o any pa icula Vcc le el, SRAM cell ype, echnology node, ype o p o ec ion o eliabili y le el as long as pe o mance p edic abili y is achie able. The ype o p o ec ion used depends on he gi en baseline cache and i s eliabili y le el. Since we main ain he same le el o obus ness as in he baseline cache, pe o mance p edic abili y ea u es emain he same. C. Design Me hodology HP ways a e designed wi h di e en ial 6T bi cells. Depending on he cache size and a ge cache yield, he ha d aul y bi a e (P ) is ob ained using elemen a y p obabili y calcula ions. Fo example, o ha e a 99% yield o an 8KB cache, aul y bi a e P mus be 1.22x10−6. Then, using he analysis based on impo ance sampling p oposed by Chen e al. [6] and calcula ed P , 6T bi cells size is de e mined. 10T bi cells sizing: 1. Fo chosen NST Vcc and educed equency a ULE mode, size 10T bi cell o ma ch he same ha d bi ailu e a e (P ) as 6T bi cells a HP mode, using he analysis based on impo ance sampling p oposed by Chen e al. [6] 2. Calcula e cache yield (Y10T) based on he gi en cache size and P Replacing 10T bi cells wi h 8T bi cells and EDC: 1. Se minimal anzis o sizes possible o a ge ed echnology node 2. Calcula e 8T bi cell’s ha d bi ailu e p obabili y P 8Tusing Chen’s analysis [6] 3. Calcula e ailu e p obabili y (P o al) o EDC-p o ec ed cache 4. Calcula e cache yield (Y) 5. I (Y <Y10T) 5a. Inc ease ansis o sizes by minimal amoun possible o a ge ed echnology 5b. Go o s ep 2 6. Else 6a. Op imal cell size is ob ained Fig. 2. Design me hodology o scena io A. The design me hodology o he ULE ways o scena io A is shown in Figu e 2. Remembe ha only ULE ways a e ac i e a ULE mode. Fo he chosen NST Vcc and educed ope a ing equency a ULE mode, we i s size 10T cells o ma ch he same ha d aul y bi a e as 6T cells a HP mode (P ) using Chen’s analysis [6]. Then, depending on he cache size and gi en P , cache yield (Y10T) can be easily calcula ed. No e ha in scena io B he 10T cells a e SECDED p o ec ed o deal wi h so e o s, and cache yield in ha case (Y10T+SECDED) can be calcula ed analogously o scena io A. Nex , we de e mine he size o 8T bi cells p o ec ed wi h EDC in o de o eplace 10T bi cells in ULE ways as shown in Figu e 2. We i s se minimal ansis o s sizes o 8T bi cells and hen calcula e he ha d bi ailu e p obabili y (P 8T) o he chosen NST Vcc by using Chen’s analysis [6]. Then, we de ine da a and ag wo ds o ha e 32 and 26 bi s espec i ely, and p o ec hem a such g anula i y. The p obabili y o ha ing aul - ee ag/da a wo ds and he cache yield (Y) a e: P( ag/da a) = 1 X i=0 (1 −P 8T)n+k−iPi 8Tn+k i(1) Y=P(da a)DW P( ag)T W ,(2) whe e DW and TW a e he o al numbe o da a and ag wo ds in cache espec i ely, nis numbe o bi s o ag o da a wo ds, kis numbe o added check bi s (i.e. 7 bi s o SECDED, 13 bi s o DECTED) o each ag/da a wo d and iis numbe o ha d aul s in a ag o da a wo d. No e ha in case o no coding (scena io A), SECDED su ices o co ec a ha d aul y bi in a wo d (8T+SECDED), whe eas in scena io B, DECTED can co ec bo h a so e o and a ha d aul y bi in he same wo d (8T+ DECTED). I he yield ob ained (Y) is lowe han equi ed (e.g., Y10T o scena io A o Y10T+SECDED o scena io B), ansis o s sizes mus be inc eased by he smalles amoun possible o he a ge echnology node and yield mus be calcula ed again. Once yield is high enough, we ha e an op imal SRAM bi cell size. IV. EVALUATION This sec ion p esen s he e alua ion me hodology and pe o - mance/ene gy esul s o e i y he e iciency o he p oposed cache a chi ec u e. A. Me hodology We ha e chosen a e y simple p ocesso a chi ec u e wi h one co e and in-o de execu ion, esembling a ecen ly ab ica ed In el p ocesso o hyb id Vcc ope a ion al hough no sui ed o he ul a-low-cos ma ke [10]. Bo h on-chip L1 da a (DL1) and ins uc ion (IL1) caches implemen he p oposed design. 8KB 8-way caches a e used, whe e 7 ways a e implemen ed wi h 6T cells and 1 way wi h 10T cells (7+1 o sho ). We ha e conside ed o he designs (e.g., 6+2), bu hey did no p o ide u he insigh s. The ela i e memo y la ency is low (in he o de o 20 cycles) gi en he simplici y equi ed in hose sys ems, i s small size ( ypically ew MBs) and i s high in eg a ion wi h he p ocesso i sel . Gi en ha all compa isons in ol e caches wi h he same cha ac e is ics in e ms o cache size and associa i i y, o he memo y la encies do no change he ends epo ed la e hus, we did no include memo y ene gy in ou esul s. 1) Benchma ks: To he bes o ou knowledge, a se o benchma ks speci ic o he domain ha we a ge does no exis . We ha e chosen MediaBench [13], because hey i e y well he expec ed needs o he ul a-low-cos segmen : an abundan da a p ocessing du ing HP mode and ela i ely small wo kloads a ULE mode. We classi y benchma ks in o wo ca ego ies, depending on he cache equi emen s: (i) SmallBench - wo k- loads i in o e y small cache sizes (e.g., 1KB) due o small da a olume (adpcm c, adpcm d, epic c and epic d) and (ii) BigBench - la ge cache space is equi ed o i he wo kload due o la ge da a olume (g721 c, g721 d, gsm c, gsm d, mpeg2 c and mpeg2 d). SmallBench benchma ks a e used du ing ULE ope a ion whe eas BigBench ones a e used du ing HP ope a ion. 2) Ope a ing Modes: Ou sys em has wo dis inc ope a ing modes: HP and ULE. We ha e se Vcc o 1V and 350mV o HP and ULE mode espec i ely. Ope a ing equencies a e se o 1GHz o HP mode, and 5MHz o ULE mode, which is in line wi h he In el p ocesso o hyb id Vcc ope a ions [10]. 3) Sys em Modeling: The echnology node conside ed is 32nm. L1 cache memo ies ha e been modeled using CACTI 6.5, which is a lexible and accu a e cache delay, ene gy, powe and a ea simula o [17]. To suppo wo di e en ope a ing modes, we ha e ex ended CACTI ool in o de o implemen accu a e ene gy models o 8T and 10T SRAM cells when ope a ing a high and NST Vcc by adap ing capaci ances, esis ances and geome y. All SRAM cells ha e been sized as desc ibed in Sec ion III. Se e al hyb id cache mic oa chi ec u es ha e been implemen ed using he e ogeneous SRAM cell ypes a a coa se g anula i y as explained in Sec ion III. Mo eo e , we ha e ex ended ag and da a wo ds (26 and 32 bi s espec i ely in ou case) wi h check bi s (7 bi s o SECDED, 13 bi s o DECTED) and aken in o accoun ene gy and a ea o e heads in oduced due o hose check bi s. In o de o unde s and he impac o di e en cache designs on he whole chip, we ha e inco po a ed ou cus om-modi ied CACTI ool in o he MPSim [2] ull-chip simula o . We ha e ex ended MPSim wi h powe models analogous o hose o Wa ch [4], bu using ou enhanced CACTI e sion o model all SRAM a ay-like s uc u es (Caches, TLB, e c.). All SRAM a ays excep L1 caches ha e been implemen ed using 10T cells so hey ope a e p ope ly a any ol age le el conside ed. In ou simula ions, we accoun an addi ional la ency o one clock cycle o SECDED/DECTED encoding and decoding as well as he ene gy consumed by he ex a EDC ci cui s a ULE mode. Ene gy consump ion o EDC encode s and decode s is ob ained by pe o ming HSPICE simula ions. Fo ha pu pose, we used he 32nm P edic i e Technology Model ansis o model and 10% a ia ion in h eshold ol age (V )[22]. B. Resul s and Discussion In his subsec ion, we p esen ene gy pe ins uc ion (EPI) and a ea esul s a HP and ULE modes compa ing he p oposed Fig. 3. No malized a e age EPI b eakdowns a HP mode o scena ios A and B. Fig. 4. No malized EPI b eakdowns a ULE mode o scena ios A and B. cache a chi ec u e wi h he baseline designs o bo h scena ios desc ibed in Sec ion III. Execu ion ime and ene gy a y ac oss scena ios. Thus, o he sake o cla i y, esul s ha e been no malized wi h espec o he baseline con igu a ion in bo h scena ios. 1) HP mode: Figu e 3 shows he no malized a e age EPI o bo h scena ios a HP mode. All benchma ks show mino di e ences o he a e age. The main eason is ha he ac ion o cache memo y accesses (ins uc ion and da a) and execu ion beha io o he di e en benchma ks is qui e simila gi en ha hei wo kloads i p e y well in cache, which will be he case in eal sys ems. Since caches a e he main ene gy con ibu o in hese ex emely simple p ocesso s, cache beha io domina es ull p ocesso beha io . Ou a chi ec u e shows ene gy sa ings o 14% and 12% on a e age o scena io A and scena io B espec i ely. This is due o he smalle ansis o sizes o 8T cells wi h espec o he 10T cells and hus, educed dynamic ene gy (which is he dominan ene gy ac o a high ol age). Ou a chi ec u e does no expe ience any pe o mance deg ada ion (no la ency o e head) since 8T cells a e as eliable as 6T a high ol age, so hey use exac ly he same coding as in baseline. 2) ULE mode: HP ways a e u ned o a his mode, so only ULE ways keep ope a ing. Leakage inc eases a ULE mode whe eas dynamic ene gy is s ill a signi ican ene gy ac o . Figu e 4 shows he no malized EPI b eakdowns ac oss all benchma ks o scena io A and B a ULE mode. Caches emain o be he main ene gy con ibu o and access equency is no d as ically di e en ac oss benchma ks, so e ec s on di e en sou ces o ene gy on each benchma k a e ela i ely simila , because dynamic and leakage cache ene gy is impac ed in a e y simila way. Thus, all benchma ks obse e simila ends. When EDC codes a e used, smalle ansis o s a e needed o 8T cells and hus, ela i e dynamic and leakage ene gy consump ion is lowe han o 10T cells. Smalle ansis o s keep capaci ances lowe and educe dynamic ene gy, which scales linea ly wi h capaci ance, whe eas delay and hus, leakage scales exponen ially. Hence, he ela i e leakage ene gy sa ings a e la ge han hose o dynamic ene gy. Taken all oge he , he no malized a e age EPI educ ions a e 42% and 39% o scena io A and B espec i ely. Pe o mance a ia ion due o he ex a cycle o EDC encoding/decoding is negligible (a ound 3% inc ease in execu ion ime in all cases). V. CONCLUSIONS We p opose a new, e icien and simple, single-Vcc domain cache a chi ec u e o hyb id Vcc ope a ions in ul a-low-cos (e.g., below 1 C) ba e y-powe ed sys ems. The cache design elies on eplacing ene gy-hung y bi cells (e.g., 10T) by mo e ene gy-e icien and smalle cells (e.g., 8T) enhanced wi h e o de ec ion and co ec ion ea u es o imp o e ene gy and a ea e iciency wi hou jeopa dizing eliabili y le els o s ill p o ide p edic able pe o mance, as needed o c i ical applica ions. Ou cache a chi ec u e achie es signi ican sa ings in ene gy (up o 14% and up o 42% on a e age a HP and ULE mode espec i ely) and negligible a e age pe o mance deg ada ion (up o 3%) wi h espec o exis ing solu ions while keeping he same gua an eed pe o mance and eliabili y le els. ACKNOWLEDGEMENTS This wo k has been pa ially suppo ed by he Spanish Min- is y o Science and Inno a ion unde g an TIN2012-34557, HiPEAC and he UPC unde g an FPI-UPC. REFERENCES [1] J. Abella e al. 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