Electronic Systems : Noteboook of Lab Activities

Electronic Systems Noteboook of Lab Activities José Antonio Soria Pérez Departament d’Enginyeria Electrònica Escola Politècnica Superior d’Enginyeria de Vilanova i la Geltrú José Antonio Soria Pérez 1 Contents: Lab Activity 1. Lab Instrumentation…....................................................................2 Lab Activity 2. Time and Frequency domains……...............................................24 Lab Activity 3. Linear DC Power Supplies............................................................50 Lab Activity 4. Switching Electronics: The Bipolar Junction Transistor (BJT)....70 Lab Activity 5. Analog Electronics: The Operational Amplifier….....................100 José Antonio Soria Pérez 2 Lab Activity nº 1: Lab Instrumentation Main Goal: To learn how to use the different instruments of the lab for measuring electrical signal parameters, both in continuous (DC) and alternate current (AC), and to get used to the basics of bread-board prototyping. These skills are considered CRUCIAL for the forthcoming lab activities of this course and development of technical skills during your current degree program. As such, students are encouraged to observe and experiment with the different buttons and controls that instruments have, and to follow mounting instructions carefully. The machines of the lab can be grouped in the following two main groups: • Stimulus (or Signal) generation: The Power supply for generating continuous (or DC) current and Waveform Function Generators for generating time-varying signals. • Measurement Instrumentation: The Multi-meter, which contains an ohmmeter, a voltmeter and an ammeter, all of which are aimed for measuring steady-state electrical variables; and the Oscilloscope for visualizing and measuring parameters in time-varying signals. . 1 DC Power Supply This device fixes its output to a constant voltage and delivers energy to the circuit in the form of DC current. Two models are available in the labs: 1) The IPS2303DD from ISO-TECH (Fig. 1a) at L-104; and 2) The E3631A from Agilent (Fig.1b) at L-106. Both consist of two identical outputs (red boxes) with adjustable voltage from 0 to 30V/3A and from 0 to 25V/2A, respectively. Another auxiliary high-power output (orange boxes) provides a fixed voltage of 5V for a maximum 5A DC current (The auxiliary output of the E3631A is variable and of 6V/5A). When the outputs are connected, the display shows both fixed voltage and injected current to the user’s circuit. The maximum voltage and current admitted to the circuit is programmed through the control functions in the front panel (rollers and buttons inside the blue boxes). However, the procedure varies depending on the machine model. (a) (b) Figure 1. Power supplies at the labs: a) IPS 2303DD from ISOTECH (L-104); b) E3631from Agilent (L-106). José Antonio Soria Pérez 3 Task LAB1: Configure one of the outputs from the DC power supply to operate at 5V with a maximum current of 0.25A. Proceed as indicated depending on the machine model available at your workstation (see below). DC current limiter: • IPS2303DD: With the device turned OFF, 1) Connect a cord between the positive and negative terminal at the output you’re going to use; 2) Turn the power ON and observe the current value in the display; 3) Use the roller labelled as CURRENT to set the limit to 0.25A; 4) Disconnect the output cord. • E3631A: In this model you can configure the current limiter without connecting a cord at the output terminals. 1) Turn the power ON; 2) Select the CURRENT option from the ADJUST menu in the front panel on the right (a digit from the display blinks); 3) Use the ‘<’ and’ >’ buttons to move along the digits and set the value with the roller until the value 0.25A is shown on the display. DC Voltage configuration: • IPS2303DD: 1) Turn the instrument ON leaving output terminals unconnected; 2) Use the VOLTAGE roller to set the output to 5V. • E3631A: 1) Select VOLTAGE from the ADJUST button (the display shows the current voltage and one digit blinks); 3) Use the buttons to move along the digits and set 10V. At this point, the machine is ready to operate with the configured options. However, for safety reasons, it is preferable to develop connections with unpowered outputs. In the E3631A model, an OUTPUT ON/OFF button allows these operations to be made while the machine is turned ON. In this case, a message appears indicating whether the output is deactivated; then, the user can connect the cords safety and push the button again to reactivate the output. In the IPS2303DD model, however, these operations may be made with the machine turned OFF. REMARK: You must WRITE DOWN your answers in the form provided at the end of this document (See Annex 1) and deliver it to the lab teacher at the end of the session. 2 The Digital Multi-meter A digital multi-meter (Fig. 2) integrates an ohmmeter, a voltmeter and an ammeter in one device and, as such, it can measure electric resistance, voltage and electric current; as well as other auxiliary parameters of stationary behavior. From the different terminals on the right of the front panel (red box), the VΩ terminal is intended for measuring electric voltage and resistance, whereas the terminal labelled as ‘Fuse on Rear Pannel’ is the point of electric current measurement. The red color (as well as the ‘HI’ label) indicates the POSITIVE connection (+), and the black terminal in the middle (also labelled as LO) is the NEGATIVE (-) one, which is “common” to all three measure variables. José Antonio Soria Pérez 4 Figure 2. Digital multi-meter 34401A at the L-104 and L-106, courtesy from Agilent Technologies The device function is configured through the keypad in the front panel (green box). The blue function above is selected by means of the SHIFT button. As such, for measuring resistance, DC voltage and electric current; the options are Ω, DC V or DC I (SHIFT > DC V) respectively. Generally, the multi-meter is intended for viewing stationary parameters, which are refreshed over the time, as information can only be provided through the display. Nevertheless when timevarying signals are sensed through the output terminals, in DC mode (DC V as well as DC I) the display shows the average value, whereas in AC mode (AC V and AC I) it shows the true1 root-mean-square value (or rms). Strictly speaking, the average value of any signal x(t) is obtained as ( ) ∫ = T dttx T x, 1 (1) where T corresponds to the measuring interval2 used by the device, and the true rms value is obtained as ( ) . 12 ∫ =T rms dttx T x (2) 1 Some multi-meters only provide the ‘rms’ value of sinusoids, since this value is easily obtained correcting the output peak by a factor of 0.707, which requires less resources. Hence, manufactures refer to the “true rms” implementation when their instrument contains the required circuitry to develop (2). It has to be mentioned, however, that the usefulness of this value relies on the basis of repetitive signals, which is a necessary condition in order to give a steady value of this measure through the display. 2 T is automatically fixed by the device. In DC mode, this value corresponds to a time interval of fixed width along which the average value is estimated. As such, it can be seen as the refreshment time of the display. In AC mode, the multi-meter uses a sophisticated system to detect the periodicity of signals and, then, it configures T accordingly. See the manufacturer user’s guide for more information on this topic. José Antonio Soria Pérez 5 Task LAB2: Get acquainted with the multi-meter functions by carrying out the following measurements: Electric resistance: • 1) Identify each one of the five different resistors included in the kit. 2) Use the ohmmeter to measure the resistors. 3) Turn the multi-meter ON and select Ω in the control panel button (the digital display shows the message MOHM). 4) Finally connect the cords and the resistor as shown in Fig. 3. • Determine the deviation of each resistor from its nominal value according to the following equation. Check whether the values are within tolerances. () 100% min min × − = alNo alNo Óhmetre R RR ERROR (3) REMARK: The TERMINALS button must be turned OFF in order to activate the front panel. Electric DC voltage: • Measure the 5V DC voltage configured in task LAB1 with the voltmeter. Configure the instrument by following these steps: 1) Turn both devices OFF; 2) Connect them as indicated in Fig. 4a; 3) Turn the multi-meter ON and press DC V in order to configure it as DC voltmeter (the display shows the message “VDC”); 4) Finally, turn the DC power supply ON. • Repeat measurements by reversing output connections at the voltmeter (Fig. 4b) Electric DC current: • Keep this 5V DC voltage and connect a 1 Kohm resistor to measure the electric DC current flow with the ammeter. As previously, 1) Turn both devices OFF. Make the connections of Fig. 5a; 2) Turn the multi-meter ON and select DC I (SHIFT > DC V) to configure it as an ammeter (the display shows the “ADC” message); and 3) Turn the DC power supply ON. • Repeat measurements by reversing output connections at the ammeter (Fig. 5b) Figure 3. Output connection and multi-meter configuration for measurement of electric resistance. José Antonio Soria Pérez 6 (a) (b) Figure 4. Measuring electric DC voltage from the supply with the voltmeter; a) Forward; b) Reverse. (a) (b) Figure 5. Measuring electric DC current flow. Arrows indicate flow direction a) Forward; b) Reverse. 3 From the electric diagram to the Bread-board prototype At this point, it becomes necessary to define symbols for representing the instruments, electronic components and their electrical connections. This will not only be used jut to drawing the schematics of electronic systems but also for understanding their behavior, which is essential in signal analysis and electronic design. Fig. 6 shows basic symbology and common standard conventions used in wire connectivity. In general, each element is a dipole and its terminals are connected to other dipoles. The positive pole of instruments is represented by “+” (Fig. 6a and 6b), and the resistor symbol is depicted in Fig. 6c. More than three connections between wires and/or terminals are indicated by a “point”, whereas a “bridge” (or the omission of points) means a crossing of unconnected wires (NC). Finally, the GROUND terminal (Fig. 6e) is a common reference used in electrical variables. José Antonio Soria Pérez 7 (a) (b) (c) (d) (e) Figure 6. Basic symbols of the elements shown in this document. In this sense, a schematic diagram for the current measurement layout of Fig. 5 is depicted in Fig. 7. An arrow represents the direction of I1, which flows from the positive to the negative pole of the power supply. By convention, the entrance point at the resistor sets the positive sign of its voltage drop (V1). Finally, the supply VCC, the ammeter (A) and the resistor (R1) form a closed path (or mesh), whereas a node is any connecting point between two (or more) terminals. This convention is similar to that used by the multi-meter. By default, electric currents ENTERING the red terminal are read positive3 by the multi-meter. So in the first situation of Fig. 7a, the value showed in the display matches to I1, both in value and sign, whereas in the second one the sign is reversed -I1. Another element, not considered an instrument, but essential when experimenting with electronics, is the test board (Fig.8). This board is known as the bread-board and it is where an electronic design is previously mounted and tested before their commercial implementation on a printed circuit board (PCB). The breadboard have five unconnected terminals, two columns, each vertically connected (left and right); and two rows, each horizontally connected (top and bottom). In addition, the central part have six groups of cells (from A to F), each with 47 x 5 holes horizontally connected but vertically unconnected. Knowing this layout is important to develop the circuit connections previously designed on a schematic. Mainly, it is important to place the components according to the schematic and ensure that terminals and wires are connected properly. Using terminals for common connections, such as the GROUND, developing as fewer connections as possible in the breadboard and using colors for assigning groups of connections (i.e: black for ground connection, red for + or grey for -); is important to avoid possible problems and to allow errors to be detected quickly and easily. 3 A similar criterion applies to the voltmeter, which takes as positive all drops caused by electric currents ENTERING the red terminal, and negative otherwise. José Antonio Soria Pérez 8 (a) (b) Figure 7 Electric diagrams and variable conventions using the DC current measurement layout in Fig. 5. (a) (b) Figure 8. Overview of the breadboard: a) Aerial view; b) Internal connections of holes. Task LAB3: Build the simple circuits of Fig. 9 on the breadboard and obtain experimentally their electric resistance: • In the first schematic; 1) Follow the breadboard distribution in Fig. 10; 2) Determine the theoretical value between A and B; and finally; 3) compare with experimental results. • In the remaining circuits (Fig. 9b and 9c), 1) Use the information in Fig. 8 to guess the connections you need to make and; 2) Proceed with the calculations and measurements. REMARK: The electric resistance between two points, A and B, is measured by DISCONNETING ALL SOURCES and connecting the ohmmeter IN PARALEL. NEVER touch the terminals with your own hands while carrying out this measurement. José Antonio Soria Pérez 15 Basic configuration: • 1) Turn the waveform generator ON and configure the previous settings (5V-peak sinusoid and 100Hz-frequency) if they are not set already. 2) Connect a BNC-BNC probe between the 50Ω generator’s output and the channel CH1 (Fig. 18). 3) Turn the oscilloscope ON and, follow these steps to observe the signal, once the grid appears (Fig. 17a): A) Vertical Panel > “1-knob” > Coupling > GND: The input signal disappear from the screen and a horizontal line shows the zero-voltage reference of CH1. Use the yellow roller to place this line at the center of the screen. B) Vertical panel > “1-knob” > Coupling > DC: The screen shows the waveform trace again. C) Vertical panel > VOLTS/ (yellow selector): Change the voltage resolution to 2V/ D) Horizontal panel > TIME/ (left selector from the horizontal menu): Set the time resolution to 1mseg/ REMARK: At this point, you should see a sinus of 10 grid positions (or squares) wide in the horizontal axis, due to the fact that T = 1/FREQ = 10mseg. Likewise, the vertical range is 5 grid positions wide (2.5 band-to-band beyond the zero-reference voltage) in the vertical axis. • 2) Access the TRIGGER menu by pressing the “Mode/Coupling” knob at the right in the control panel (orange box). Configure the following options: Mode (1) = “Edge”. Source = “CH1”. Slope = “Ascending”. Mode (2) = “Auto”. Coupling = “DC”. 3) Move the LEVEL roller (a discontinuous line appears and the text shows the activation threshold DC level on screen. 3) Move this line up to “2V” and observe how the signal shifts slightly along the time axis to set the 2V-level reference at the center of the screen. Coupling configuration: • 1) In the waveform generator, change the offset settings of the sinusoid to OFF = 2V. 2) Use the Trigger to fix the signal on screen. 3) Adapt the vertical axis to enclose the signal as LARGE as possible on the screen, and the horizontal axis to observe 4 CYCLES. • Configure the oscilloscope in AC mode (Vertical Panel > “1-knob” > Coupling > AC). Comment both results: José Antonio Soria Pérez 16 Figure 18. Oscilloscope connection for visualizing time-varying signals from the waveform generator. 1st. REMARK: The coupling mechanism is generally used to HIDE (NOT TO REMOVE) the average (or DC) input component from a signal. As such, the signal is forced to have a symmetric representation on screen, despite the 2V-level offset. This is done when the AC mode is selected. This mechanism is extremely useful to observe small AC components overlapped in very high DC components, which sometimes are of interest in order to understand the behavior of certain electronic systems. 2nd. REMARK: All configurations explained in this task are considered ESSENTIAL for correct instrument usage so, most probably, you’ll need to repeat them again during this course. Procedures also apply to CH2, which can be viewed with CH1 simultaneously. As the waveform generator, instrument configuration may be altered severely over students by the lab. In these situations, it may be wiser to upload the manufacturer initial configurations:  In the menu: Save/Recall > Storage > Set-up > Manuf. Other device utilities (optional): • Take the time to review other interesting configuration options from the oscilloscope which could be of interest for you, such as 1) the Measure button for displaying time and voltage measures automatically; 2) the Cursor menu to narrow the measures; 3) or the Math menu for developing mathematical operations with both channels. Task LAB8: Now connect the waveform generator at the input of the series circuit of Fig. 11, and the CH1 input channel in parallel. Represent the voltage waveform in each resistor (Fig. 19). • 1) Mount the circuit of Fig. 11a. if it’s not mounted already. 2) Use a “T” connector at the CH1 input of the oscilloscope and connect the generator output, vGen(t), by means of a BNC-BNC probe (Thus, you’ll to use an additional prove connected at the breadboard (Fig. 19b). Keep the previous sinusoid configuration (5V-peak; f = 100Hz and OFF = 2. 3) Connect the other cannel, CH2, in parallel with the second resistor to measure vR2(t) and represent its waveform shape. Do not forget coupling both channels in DC mode. José Antonio Soria Pérez 17 (a) (b) Figure 19. Oscilloscope and waveform generator connection for measuring the voltage drop at vGen(t), and, vR2(t). a) Connection diagram) Breadboard connection. Differential mode (floating-point voltaje): • Now, disconnect CH2 and connect this channel in parallel with the first resistor (all positive terminals from the generator, CH1 and CH2 must be TOGETHER. The negative pole of CH2 must be connected between R1 and R2). 3) What is the problem? • 1) Undo the last change and connect back channel CH2 in R2. 2) Now configure the oscilloscope in differential mode (MATH button > Operation > 1 – 2). This action will generate a new purple trace on screen corresponding to the point wise subtraction CH1CH2, which is in fact vR1(t) = vGen(t) - vR2(t) REMARK: Both negative poles of CH1 and CH2 are INTERNALLY CONNECTED. As such, connecting them at different circuit points causes short-circuit and unpredicted circuit behavior may be of severe consequences. José Antonio Soria Pérez 18 Annex 1 – Results form REMARK: Students must PRINT OUT THIS FORM and BRING it the day of the lab session. Escola Politècnica Superior d’Enginyeria de Vilanova i la Geltrú EEL Electronic Systems (SIEK) Lab Activity 1 Students: Date: 1 DC Power Supply • Task LAB1: ILIMIT = ________ VFONT = _________ 2 Multi-meter • Task LAB2: 2.1 Electric resistance measurement R1 R2 R3 R4 R5 Rnominal (Ω) RÓhmetre (Ω) Error (%) 2.2 DC voltage measurement VSUPPLY(Multi-meter) = ________ -VSUPPLY(Multi-meter) = _________ José Antonio Soria Pérez 19 2.3 DC current measurement IR(1kΩ) = ________ -IR(1kΩ) = ________ 3 From the electric diagram to bread-board prototyping • Task LAB3: 3.1 Series/parallel resistor association Series Circuit Parallel Circuit Series-parallel Circuit RTeòrica (Ω) RÓhmetre (Ω) • Task LAB4: 3.2 Electric DC measures in the series circuit I V1 V2 Theoretical Multi-meter 4 Waveform generator 4.1 AC voltage measurement from the generator (rms value) • Task LAB5: VAC(Multi-meter) = ________ 4.2 Electric AC measures in the series circuit • Task LAB6: V1(AC) V2(AC) Theoretical Multi-meter José Antonio Soria Pérez 20 5 The Oscilloscope • Task LAB7: Basic oscilloscope configuration CH1 VOLT/: 2V/ CH2 VOLT/: ----- TIME/: 1msec/ Coup: DC Zero POS: 0V Coupling setting with OFF = 2V and DC mode CH1 VOLT/: CH2 VOLT/: ----- TIME/: Acob: DC Zero POS: José Antonio Soria Pérez 21 Coupling setting with OFF = 2V and AC mode CH1 VOLT/: CH2 VOLT/: ----- TIME/: Acob: AC Zero POS: • Task LAB8: Representation of vGen(t) and vR2(t) in the series circuit CH1 VOLT/: CH2 VOLT/: TIME/: Acob: DC Zero POS: José Antonio Soria Pérez 22 Representation of vGen(t) and vR1(t) with CH2 and R1 in parallel CH1 VOLT/: CH2 VOLT/: TIME/: Acob: DC Zero POS: Explain the problem ____________________________________________________________ _____________________________________________________________ Representation of vGen(t), vR1(t) and vR2(t) using the MATH option CH1 VOLT/: CH2 VOLT/: TIME/: Acob: DC Zero POS: Explain the configurations in the MATH menu here to view vR1(t) correctly __________________________________________________________________ José Antonio Soria Pérez 23 Annex 2 – Resistor value coding 24 24 Lab Activity nº 2. Time and Frequency domains Main Goal: Learning how to determine the transient and frequency response of any Linear Time invariant system (LTI) in the form of a passive circuit, by means of the transfer function. This goal is not only restricted to a theoretical level but also considers technical development and extends to measurements in order to know such information in real electronic systems. 1. Capacitors and inductors A capacitor consists of two electrodes separated by an insulating medium called the dielectric. The electric charge q on the electrodes is proportional to the voltage vc across the capacitor, ()( ) t Cvt q c = (1) where C is the capacitance. The unit is given in farads (abbreviated F): 1 farad equals 1 coulomb/volt, and habitual values are in the order of microfarads (1μF=10-6F) or picofarads (1pF=10-12F). On the other hand, its electric current is given by the rate of change of the electric charge, so its voltage/current relationship is, ( ) () ( ) dt tdv C dt Cd dt d ti c c=== c v q . (2) Table 1 represents the mathematical model of this component both in time and frequency domain. More precisely, using the Laplace Transform allows time transitions to be expressed as, ( ) ( ) sxs dt tdx L×→ −1 (3) where s ≡ d(·)/dt is the laplacian operator containing the angular frequency ω, ω j s= (4) also related to the oscillation frequency f = ω/2 π which is expressed in Hz. As such, and with the use of basic theoretical rules (Ohm’s law, Kirchoff law, etc) it is easy to handle the behavior of reactive components, since knowing its electric impedance Xc is, most of the times, enough for carrying out calculations. This principle is also equivalent in the inductor, whose voltage drop varies with the magnetic field ϕ as, ( ) ( ) ( ) dt tdi L dt Ld dt d tv L L=== L i φ , (5) where now L is the inductance, in henris (H). For this reason both components are considered duals (that is replacing i by v and v by i in one equation leads to the other) since their impedances are Xc and XL, respectively. Task PRELAB0: Search through the Internet, or any manufacturer catalog (such as RS Amidata, Farnell in One, Digi-key, Google, etc) a 10nF and a 10μF capacitor. 31 31 Figure 6. Sinusoid of the form: x(t) = Acos(ωt) These two parameters are crucial since they specify circuit behavior at any frequency. In fact, there is a method by which calculations can be extended easily to ANY LTI system provided that the focus is on knowing only the steady state of the circuit. This methodology is even valid regardless of the number of resistors, capacitors and inductors included in the network. 3.2 Frequency response in steady-state LTI systems In general, given a LTI-system expressed in terms of its transfer function H(s) (Fig. 7), its module |H(s)| is obtained as, ( ) ( ) ( ) 22 RI Hj H j H j ω ωω = + (19) where “R” i “I” denote respectively the “real” and “imaginary” (complex) terms of H(s), whereas the phase ∠H(jω) is calculated as, ( ) ( ) ( ) ( ) ( ) ( ) ( ) 1 1 tan , si 0 tan , si 0 IR R IR R Hj Hj Hj Hj Hj Hj Hj ωω ω ωω πω ω − −  ≥    ∠=  +<     (20) where the units of ∠H(jω) are in radians. However, most of the times H(s) has a numerator and a denominator, both containing real and complex terms. In this situations, one can use, ( ) ( ) ( ) ( ) ( ) 22 22 RI RI num H j num H j Hj den H j den H j ωω ωωω    +    =   +    (21) to evaluate the numerical value |H(s)|, where “num” and “den” denote numerator and denominator of H(s), respectively. On the other hand, for evaluating ∠H(jω) we use, 32 32 Figure 7. General overview of the frequency response in a LTI-system. Figure 8. Voltage and time parameters used in the experimental estimation of |H(s)| and ∠H(s). ( ) ( ) ( ) ( ) ( ) 11 tan tan II RR num H j den H j Hj num H j den H j ωω ωωω −−        ∠= −              . (22) The reader can prove that using (21) and (22) in (8) leads to (18): the module and phase response of the series RC circuit. Furthermore, if we denote Vi(ω) and θi(ω) as the input magnitude and phase, respectively, at frequency ω, the output response is given by, ( ) ( ) ( ) oi V Hj V ω ωω = × and ( ) ( ) oi Hj θω ω θ =∠+ . (23) Fig. 8 shows the most representative points of both input and output signals of the LTI system. In other words, the module |H(jω)| is just their output-input peak relation, ( ) o i V Hj V ω = . (24) whereas the phase delay ∠H(jω) is evaluated by measuring the reference points t0, t1 and t2. Then, assuming that θi = 0, and therefore ∠H(jω) = θo, the phase is obtained from the signals as, 33 33 ( ) 21 12 112 2 , if 2 , if tt tt T Hj ttt T π ω π − ≥   ∠=  −<   (25) Task PRELAB2: Using the capacitor value C = 10nF, represent the waveform signals of the RC series circuit (Fig. 5b) that would be observed on screen if, instead of the square signal input, we use a sinusoid with amplitude Vi = 5V, zero offset, and frequency f = 1 kHz (ω = 2πf) • Use (18) to obtain module and phase response, and then determine the reference points of Fig. 8 by means of (24) and (25) to carry out this task. Use θi = 0 and fix on screen a random point for t0 on the horizontal axis. Specify oscilloscope configuration in order to observe on screen an entire cycle of both signals in detail. Task LAB2: Obtain the frequency response of the series RC circuit in the lab. • 1) Use a C = 10nF and connect the probe to the 50Ω of the waveform function generator (instead of the TTL output) and configure an input sinusoid of amplitude Vi = 5V, zero offset, and frequency f=1 kHz. 2) Draw the signals in the grip provided and annotate the parameters: Vi, Vo, t0, t1 i t2. 3) Use (24) and (25) to evaluate module and phase; and compare with (18). • Repeat the previous steps for f = 200Hz. 4. 2nd. Order systems. 4.1 LTI system response to a step function The standard notation of the 2nd. order LTI system is written as ()( ) ( ) 2 22 2 on i nn vs Hs K vs s s ω ξω ω = = ++ ; o bé ( ) ( ) ( ) ( ) 2 1 12 o inn Vj Hj K Vj j ω ωωω ω ξω ω = = −+ . (26) The output of such a system to a step function vi(s)=Vi/s is, () 12 212 1 121 pt pt oi ee vt KV pp V −−   =×+ −   −    (27) where, 2 1,2 1 nn p ξω ω ξ =±− (28) are the roots of the 2nd. order polynomial in the denominator of H(s), known as the system poles. 34 34 Generally speaking, the behavior of H(s) is best characterized by two parameters: the damping factor ξ and the natural frequency ωn, respectively. Depending on the damping factor, there are three cases: • Underdamped behavior: 0 < ξ < 1 When 0 < ξ < 1, p1 and p2 are complex conjugate. In this case, (27) can be rewritten as, ( ) 2 1 2 1 1 sin tan 1 nt oi d e vt KV t ξω ξ ωξ ξ −−    −    =×− +    −     . (29) and we obtain and underdamped behavior, which means that the output is characterized by an initial oscillating transient before it reaches its forced response (Fig. 9a). The parameter ωd = ωn(1ξ 2)1/2 is called the natural-damped frequency and is the frequency during the initial transient. The relevant points of this signal can be evaluated using the expressions in Table 1. • Critical damping: ξ = 1 Here, the poles are real and equal (p1 = p2 = ωn), and the output has the fastest possible response without overshot, ( ) ( ) 11 n t oi n vt KV e t ω ω −  =×− +  (30) • Over-damped: ξ > 1 When ξ >1, the poles are real but different. The output (27), which responds to an exponential law, increases slowly until it settles to its steady state. However, in this case we may distinguish two situations: one in which both poles are close each other and another where p2 gets over p1 ( ξ >> 1→ p1 >> p2). In the last case, H(s) can be approximated to a 1st. order system of the form, ( ) ( ) ( ) 1 2 2 ˆlim o pi vs p Hs K vs s p →∞ =+ � (31) where, 2 2 11 ˆ1 nn p τξω ω ξ = = −− (32) would correspond to the new time constant resulting from this estimation. In general, the order of H(s) depends on the degree in the denominator. Since the laplacian operator s = d(·)/dt also represents the derivative in the differential equation, the order is also established by the number of capacitors and inductors, provided that elements of the same type do not form series or parallel associations. 35 35 (a) (b) Figure 9. Underdamped behavior in a 2nd. Order LTI system (K=1). a) Output waveform; b) Defining σ. Parameter Expression Observations 1. Delay time (td) ------ It can only by evaluated by using (27) and imposing vo(t) = 0.5Vi 2. Rise time (tr) 1 1tan d r dd t ωπβ ω σω − −  = =  −  See Fig. 9b 3. Overshot time (tp) tp = π /ωd 3. Overshoot (SIP) ( ) ( ) ( ) 2 1 op o o vt v SIP e v ξπ ξ −− −∞ = = ∞ v o (t p ), v o (∞) output value at t=tp and steady state, respectively 4. Settling time (t s ) (* approximated value) ts = 3/(ξωn) Error 5% of Vi ts = 4/(ξωn) Error 3% of Vi Table 1. Important parameters of the underdamped response to a step function. 36 36 4.2 Response of the series RLC circuit to a step input One very popular and didactical example of a 2nd order LTI system is the series RLC circuit (Fig. 10) which consists of a resistor, a capacitor and an inductor. Using a voltage divider, the capacitor voltage (in s domain) is expressed as, ( ) ( ) ( ) ( ) ( ) c ci Lc Xs vs vs RXs Xs =++ (33) where, Xc(s) = 1/(Cs) and XL(s) = Ls are the impedances of the capacitor and the inductor, respectively. After rearranging (33), the standard expression becomes, ( ) ( ) ( ) ( ) 2 11 11 c i vs Cs LC Hs R vs R Ls ss Cs L LC = = = ++ ++ (34) and, therefore, the gain factor, the natural frequency and the damping factor are, K = 1; 1 n LC ω = and 2 RC L ξ = . (35) Task PRELAB3: On the Bread-board template, represent the necessary component and instrument connections from Fig.11 you’ll need to develop in order to measure the response to an input step of the series RLC circuit. Task LAB3: Obtain the true response of the series RLC circuit and compare measurements with the theoretical values. • 1) Evaluate the theoretical value of ξ and ωn by means of (35) and then evaluate the overshot (SIP) and the peak time (tp) using the information in Table 1. 2) Mount the RLC circuit. 3) Connect the TTL output of the waveform generator and set a frequency f = 100Hz. Use the “T” connector. 4) Configure the oscilloscope in order to observe the initial transient of CH2, in one of the ascending steps of CH1, in much detail. Draw the waveforms on the grid. 5) Annotate the peak and rise time, tp and tr ; the damping factor ξ and the overshot SIP, and compare with the theoretical ones. • 1) For R=100k, evaluate the new values of ξ and ωn by means of (35) and estimate the theoretical time constant τ using (32). 2) Change the resistor in the circuit and draw the new signals. 3) Measure the settling time (ts → 5τ in half a cycle) and establish the experimental τ of the circuit. Compare the values. 37 37 Figure 10. Schematics of the series RLC circuit and its equivalence in s domain. Figure 11. Circuit and instrument connections for Task LAB3. REMARK: The oscilloscope has a resistor RCH2 = 1MΩ and a capacitor CCH2 = 13pF in CH2 which connect in parallel with the circuit output (Fig. 12) when probes are plugged in. This connection has consequences in the true value of the parameters in (35). In fact, one can prove that the new transfer function considering these internal components becomes ( ) ( ) ( ) 2 2 2 1 EQ c iCH EQ EQ CH EQ KLC vs Hs vs K L RR C K ss LC LR C = =  + ++    (36) where 2 1 CH R KR  = +   ; n EQ K LC ω = ; 2 2 2 CH EQ CH EQ L RR C KR LC ξ + = per 2EQ CH C CC= + . (37) For the same reason, when R = 100k the settling value vc(∞) decreases to Vi/K = 4.5V. This analysis could be even more complex if the internal components of CH1 are also considered. 4.3 The electric resonance phenomenon (the series RLC circuit case) When RLC circuits are powered by sinusoids of the form vi(t) = Visin(ωt) (Fig. 6) there is an interesting phenomenon called electric resonance which occurs at a certain frequency. In the series RLC circuit, for example, let us define ZT as the global impedance of the passive network. When XL(jω) = -Xc(jω) = +j/Cω, the resistor voltage is maximum. That is, when the 38 38 (a) (b) Figure 12. Effect of connecting CH2 at the output of the RLC circuit. a) Detail of CH1 and CH2 showing the input resistance RCH2 and the capacitor CCH2 which is added to the circuit when the probe is connected. b) Resulting schematics considering these two components. Figure 13.Multi-meter connection for measuring the electric resonance. ( ) ( ) ( ) T Lc Z j RX j Xj ω ωω =++ , (38) 1 rr r j jL CLC ωω ω =  → = , (39) network produces its minimum impedance ZT(jωr) = R, so that the maximum resistor current becomes vR(jωr) = Vi/R. To this frequency ω = ωr we refer to as the resonant frequency. Task LAB4: Using the multi-meter, determine the experimental resonant frequency ωr of the RLC circuit (Fig. 13). • 1) Configure the waveform generator to the same sinus signal in task LAB2 (5V-peak, zero offset) but use a frequency f = 100Hz instead. 2) Connect the voltmeter with the resistor R in parallel. Use the AC measurement option (ACV). 3) In the waveform generator, increase the frequency f until the resistor voltage vR reaches its maximum value. 4) Annotate the frequency fr the peak VR and the rms value VRrms. 39 39 Annex 1 – Results form PRELAB REMARK: You MUST do these activities BEFORE THE LAB SESSION CORRESPONDING TO PRT2 Escola Politècnica Superior d’Enginyeria de Vilanova i la Geltrú EEL Electronic Systems (SIEK) Activity 2: Time and Frequency domain PRELAB Students: Date: PRELAB 0: Draw the contour package of a 10nF and a 10μF capacitor How is the polarity indicated? 10nF: _____________________________________________________________________________ _____________________________________________________________________________ 10μF: _____________________________________________________________________________ _____________________________________________________________________________ 40 40 PRELAB1. Series RC circuit – Response to a step function. Waveform function generator configuration, mounting diagram, and waveform traces to be observed on the screen Check the options you believe you need for the specified configuration - OUTPUT: TTL 50Ω. - FUNTION: Default SQUARE SINUS TRIANGULAR - OFFSET: Default Value: _____________ - AMPLITUDE: Defecte Vaue: _____________ - FREQUENCY: ________________ Representation of vi(t) and vc(t) CH1 VOLT/: 1V/ Zero POS: -2V CH2 VOLT/: 1V/ Zero POS: -2V TIME/: 500mseg/ Coupling: DC 47 47 Annex 3 –Basic Laplace Transformations f(t) F(s) Unit impulse 1 Step function u(t) 1s t 2 1s () 1 1! n t n − − n = 1, 2, 3, ... 1n s tn-1 n = 1, 2, 3, ... 1 ! n ns + e-at 1 sa+ te-at ( ) 2 1 sa+ ( ) 1 1 1! n at te n −− − n = 1, 2, 3, ... ( ) 1 n sa+ tne-at n = 1, 2, 3, ... ( ) 1 ! n n sa + + sin(ωt) 22 s ω ω + cos(ωt) 22 s s ω + sinh(ωt) 22 s ω ω − cosh(ωt) 22 s s ω − ( ) 11at e a − − ( ) 1 ss a+ ( ) 1 at bt ee ba −− − − ( )( ) 1 sasb++ ( ) 1 bt at be ae ba −− − − ( )( ) s sasb++ ( ) 11 1 at bt be ae ab a b −−  +−  −  ( )( ) 1 ss a s b++ 48 48 f(t) F(s) () 2 11at at e ate a −− −− ( ) 2 1 ss a+ ( ) 2 11at at e a − −+ ( ) 2 1 ssa+ ( ) sin at et ω − ( ) 22 sa ω ω ++ ( ) cos at et ω − ( ) 22 sa sa ω + ++ () 2 2sin 1 1 n t nn et ξω ωωξ ξ −− − 2 22 2 n nn ss ω ξω ω ++ () 2 2sin 1 1 nt nn et ξω ωω ξφ ξ − − −− − 2 1 1 tan ξ φξ −  −  =  22 2 nn s ss ξω ω ++ () 2 2 1 sin 1 1 nt nn et ξω ωω ξφ ξ − − −+ − ( ) 2 22 2 n nn ss s ω ξω ω ++ 1-cos(ωt) ( ) 2 22 ss ω ω + ωt-sin(ωt) () 3 22 2 ss ω ω + sin(ωt)- ωt-cos(ωt) ( ) 3 2 22 2 s ω ω + ( ) 1sin 2tt ω ω ( ) 2 22 s s ω + tcos(ωt) ( ) 22 2 22 s s ω ω − + ( ) ( ) 12 22 21 1cos costt ωω ωω  −  − (ω1 ≠ ω2) ( )( ) 2222 12 s ss ωω ++ ( ) ( ) 1sin cos 2tt ωω ω ω  +  ( ) 2 2 22 s s ω + 49 49 Properties of the Laplace Transformation 1 ℒ[A·F(t)] = A·F(s) 2 ℒ[f1(t)±f2(t)] = F1(s)± F2(s) 3 ( ) ( ) ( ) 1 1 0 nnk n nk nk df t sF s s f dt − − ± =  =−±   ∑ L on ( ) ( ) 1 1 1 k k k d ft ft dt − − − = 4 ()( ) ( ) ( )( ) 10 1 1 n nk n nk t k Fs f t dt f t dt ss ±−+ = ± =   = +   ∑ ∫∫ ∫∫ L 5 ( ) ( ) 0 tFs f t dt s  =   ∫ L 6 ( ) ( ) 0 0 lim s f t dt F s ∞ →  =   ∫ L ; si ( ) 0 f t dt ∞ ∫ existeix 7 () ( ) at e ft Fs a −  = +  L 8 ( ) ( ) ( ) 1as fta ta eFs −  − −=  L per a ≥ 0 9 ( ) ( ) ( ) 1n n n n d tft Fs ds  = −  L n = 1, 2, 3, ... 10 ( ) ( ) 1 s ft Fs t ∞  =   ∫ L ; si ( ) 0 1 lim s ft t → existeix 11 ( ) t f aF as a   =     L 12 ( ) ( ) ( ) ( ) 1 2 12 0 tf t f dt F s F s ττ  −=   ∫ L 13 ( ) ( ) ( ) ( ) 1 2 cj cj f t g t F p G s p dp j π +∞ −∞  = − ∫ L José Antonio Soria Pérez 50 Lab Activity 3. Linear DC Power Supplies Main goal: Knowing the basic stages that make up a low-power DC supply (line transformation, voltage rectification, filtering and stabilization) and learn the function that basic semiconductors (diodes, bridge rectifiers, Zener and integrated circuits) develop within this electronic system. 1 Introduction A DC power source provides a continuous DC voltage to a circuit. To make this possible, it is necessary to transform the high-power line voltage, which is in the form of a sinusoid of 220 · 2 311V= V peak and 50Hz, by means of several operations implemented in stages (Fig. 1): • The transformer generates another voltage (vS) of the same type as in the power line (vAC) at the second winding, but of a much lower amplitude. This value depends on the number of turns of both windings (N1 - primary and N2 – secondary, where N1 >> N2) and is calculated as: 2 1 S AC N vv N = (1) • The rectifier is implemented by means of diodes and converts the output from the transformer into a unipolar voltage of considerable ripple. • The ripple at the rectifier output is reduced even more with a filtering stage, which is responsible of removing the components of higher frequency. The ripple obtained with this operation, however, depends on other factors belonging to the output load (such as impedance and load current), and cannot be removed completely. • This is precisely the function of the last stage, the voltage regulator, which makes the DC output independent from the input line. 2 Rectifier circuits (rectifier diodes) We’ll start with the rectifier diode, the most common nonlinear semiconductor in electronics (Fig. 2a) which acts as a semi-controlled switch (Fig. 2c and 2d): • When a negative voltage is applied to both terminals (according to the reference in Fig. 1b, v < 0), this device behaves as an open circuit (Fig. 2c). In this situation, its electric current, from anode to cathode,is zero and it is said that the diode is reverse biased, or it works in OFF mode. • On the other hand, if the electric current is positive (i > 0) the device act as shortcircuit (Fig. 2d) and it is said that the diode is forward biased. It works in ON mode. The true behavior, however, varies slightly. In ON mode, it turns out that the voltage from anode to cathode (v) is not quite zero, but has a small value close to 0.7V (the true value depends on diode the material used by the manufacturer). One way of representing this threshold consists in adding an additional source (VD = 0.7V) in series with the ideal model (Fig. 3). José Antonio Soria Pérez 51 Figure 1. Block diagram corresponding to the different stages of the DC power supply. These are the necessary steps for the AC-DC energy conversion of the power line vAC. (a) (b) (c) (d) Figure 2. The ideal diode model: a) Symbol; b) i-v characteristics; c) OFF operation; d) ON operation. (a) (b) Figure 3. a) True and linealized i-v characteristics; b) Equivalent linealized model. One basic application which makes use of the diode characteristics is the rectifier (Fig. 4). This circuit consists of a diode D and a resistor R connected in series. When a sinusoid voltage vI = VPsin(2πft) is introduced as input, the diode will be in ON mode whenever vI(t) ≥ VD, and in OFF mode otherwise. Since in this mode iD becomes zero, the output voltage in the resistor R is also zero. José Antonio Soria Pérez 52 (a) (b) Figure 4. a) Single-phase half-wave rectifier circuit. B) Voltage waveforms vI(t) – blue; and vO(t) - red. Figure 5. vO – vI transfer characteristics of the half-wave rectifier in Fig. 3a. Thus, the circuit “rectifies” the negative cycle from the unique (or single-phased) input. During the positive cycle, the output will be the same as the input but removing the threshold VD corresponding to the voltage drop on the diode (Fig. 5). Hence, the name of the circuit: the single-phase half-wave rectifier. In practice, the average output voltage VO(av) is determined over an entire cycle as, ( ) ( ) ( ) ( ) 00 11 sin 22 TPD ID P D O av VV V v t v t dt V t d t V T π ωω ππ  = − −−  ∫∫ �� , (2) where VP corresponds to the input amplitude and depends on the transformer windings vI = vS. As for the diode, the average and maximum value of electric current, ID(av) and IDmax , respectively is obtained as ( ) ( ) O av D av V IR = and Omax max PD D VVV IRR − = = , (3) whereas the maximum repetitive voltage drop in OFF mode , VRRM1 is, VRRM = max{-vD(t)} = VP. (4) This information regarding the half-wave rectifier is important in practice, as it specifies which is the correct diode to use on one hand, and then it permits a first glance of the main DC power source parameters, such as the DC output or the power transferred by the source. 1 VRRM stands for Maximum Repetitive Reverse Voltage and is the maximum voltage the diode can take, from cathode to anode, when it is reverse biased. That is ID = 0A. José Antonio Soria Pérez 53 (a) (b) Figure 6. (a) Two-phae haf-wave rectifier. (b) Single-phase full-wave rectifier (or bridge rtectifier). Electrical variables Single-phase Rectifier (half-wave) Two-phase Rectifier (half-wave) Single-phase Rectifier (full-wave) VO(av) 2 PD VV π − 2PD VV π − 22 PD VV π − V RMM V P 2V P V P - V D IDmax PD VV R − PD VV R − 2 PD VV R − ID(av) ( ) O av V R Table 1. Summary of specifications corresponding to the different rectifier circuits. The rectifier circuits in Fig. 6, improve the features of the half-wave rectifier. On one hand, the two-phase half-wave rectifier increases the capacity of output power transferred to the load because using two phases doubles the average DC value on the resistor vO. On the contrary, however, the diodes must stand twice the input voltage when operating in OFF mode (VRRM ≈2VP). The benefits of the single-phase full-wave rectifier (or bridge rectifier), on the other hand, are similar to the two-phase rectifier but with a reverse voltage VRRM ≈VP (see Table 1). Task PRELAB1: In the Bread-Board template provided at the end of the document, draw the connections corresponding to the two rectifiers shown in Fig. 7, to be implemented in the lab on the 3rd. session. Include the connections from the transformer, components and oscilloscope. Task LAB1: In each circuit in Fig. 7, obtain the waveform at the second winding in the transformer vI(t), the output vO(t) and the voltage in one diode vD(t). • 1) Mount the circuit in Fig. 7a. 2) Turning both transformer and oscilloscope OFF, connect the probes and wires. When you finish, turn both devices ON. 3) Configure CH1 and CH2 as indicated in order to observe both signals in detail. 4) Select the MATH option and activate the SUBSTRACTION operation (purple trace: CH1 – CH2). 5) Obtain the values of VRRM and VO(av) by means of the MEASURE option of both channels. José Antonio Soria Pérez 54 (a) (b) Figure 7. Diagram connections the two rectifiers necessary to obtain vI(t), vD(t) i vO(t) in the lab. a) Single-phase half-wave rectifier. b) Two-phase half-wave rectifier. • Similarly, proceed with the second circuit (Fig. 7b) to obtain the waveform signals corresponding to the two-phase half-wave rectifier. REMARK: It is very important NOT MANIPULATING OR NOT MODIFYING PROBE CONNECTIONS while the transformer is on, in order to prevent the internal protection fuses of 0.5A from breaking. For the same reason, remember NOT TO CONNECT the negative terminal of the probes at different points in the circuit. As the benefits of the single-phase full-wave rectifier are quite acceptable, its use is extended as part of many commercial DC low-power supplies2. Because of the four diodes, this circuit increases in complexity and volume. Fortunately, today there are many integrated circuits including the four diodes in a single package, such as the bridge rectifiers (Fig. 8), which eases connectivity and implementation. 3 Filtering stage The subsequent step to the rectification of the negative cycle in the input line consists in reducing the ripple. The easiest way consists in connecting a capacitor in parallel with the load (Fig. 9a) in order to cause a smooth transition between cycles (Fig. 9b), thus “filtering out” the high-frequency components of the input line. The full sequence of Fig. 9b develops as follows: 2 In general, the low-power DC supplies are those providing a maximum output current IO = ID(av) < 2A. José Antonio Soria Pérez 55 (a) (b) (c) Figure 8. Three bridge rectifiers commonly used in DC power supplies: a) the W10G-E4 from Vishay; b) the KBPC5010 from Fairchild Semiconductor; c) the DF06 from International Rectifier (a) (b) José Antonio Soria Pérez 56 Figure. 9. Single-phase half-wave rectifier with filter. a) Schematics. b) Waveforms corresponding to voltages in vO, vI; and electric currents iD, iL. We assume RC >> T. • The diode allows the electric current to flow for small period of time (say ∆t = t2 – t1). The ON mode begins at t = t1, at this moment the input reaches the output value, which was decaying as a result of the capacitor discharge during the previous interval. • When vI has just reached the maximum value (we use the approximation VP – VD ≈ VP to simplify our comments), and assuming that the output transition is much slower in relation to that of the input because R and C are designed so that τ = RC >> T, the diode stops conducting at t2 and turns OFF. • When the diode is OFF (in almost all the full cycle T), the capacitor C transfer its charge to the resistor R. The evolution of vO(t) is given by (5) where t2 = 0 is assumed in order to simplify our comments: ( ) ( ) ( ) ( ) 2 tt RC RC OO O O P vt v vt v e Ve −− = ∞+ − ∞ =   . (5) Here, v(∞) = 0 is the hypothetical voltage the capacitor would reach in an event of permanent discharge, t = ∞, and v(t2) ≈ VP correspond to the initial value of this interval. Assuming that RC >> T, a good approximation is: 1 tRC t eRC − −� (6) • Since ( ) ( ) 11 tRC O Pr P P t v t V V Ve V RC − =−−�� , equating (6) and (5) allows the ripple to be estimated as: PL rP VI T VV RC fRC fC = =� (7) Knowing this parameter, the average value of the output voltage VO(av) is determined as () 2 r P O av V VV−� . (8) Finally, we obtain the average and maximum value of the electric current flowing through the diode, ID(av) and ID(màx) respectively. Once again, these parameters are crucial for selecting one diode from the different suppliers. Taking into account that the diode stops conducting when vI(t) ≈ VP, the conduction interval ∆t can be estimated by means of VP – Vr = VP cos(ω∆t), where ω = 2πf. = 2π/T corresponds to the angular frequency of the input line. Assuming that ω∆t is too small, the term cos(ω∆t) can be approximated as ( )( ) 2 1 cos 1 2 tt ωω ∆=− ∆ . So, the conduction angle α becomes 2 rP t VV αω = ∆= . (9) José Antonio Soria Pérez 63 b) Connections corresponding to the two-phase half-wave rectifier (Fig. 7b) PRELAB 2. Voltage filter Connections corresponding to the single-phase half-wave rectifier using filter (Fig. 10) José Antonio Soria Pérez 64 PRELAB 3. Estabilitzador de tensió Zener Connexions de la font d’alimentació DC completa amb regulador Zener (Fig. 14) PRELAB 4. Regulador de tensió integrat Connexions de la font d’alimentació DC completa amb regulador integrat L7805 (Fig. 16) José Antonio Soria Pérez 65 Annex 2 –Lab activities REMARK: You MUST PRINT OUT this form and TAKE IT WITH YOU the day of the lab session Escola Politècnica Superior d’Enginyeria de Vilanova i la Geltrú EEL Electronic Systems (SIEK) Activity 3: Introduction to DC supplies FULL DE RESULTATS Estudiants: Data: LAB 1: Voltage rectifiers Waveforms vI(t); vO(t) and vD(t) = vI(t) - vO(t) observed in the single-phase half-wave rectifier (Fig. 7a). CH1 VOLT/: 5V/ Zero POS1: 0V CH2 VOLT/: 5V/ Zero POS2: 0V MATH VOLT/: 5V/ TIME/: 5mseg/ Acob: DC VRRM: ____________ VO(av): _____________ José Antonio Soria Pérez 66 Waveforms vI(t); vO(t) and vD(t) = vI(t) - vO(t) observed in the two-phase half-wave rectifier (Fig. 7b). CH1 VOLT/: 5V/ Zero POS1: 0V CH2 VOLT/: 5V/ Zero POS2: 0V MATH VOLT/: 10V/ TIME/: 5mseg/ Acob: DC VRRM: ____________ VO(av): _____________ LAB 2: Voltage filter Waveform corresponding to vO(t) using C = 100nF. CH1 VOLT/: 5V/ Zero POS1: -5V TIME/: 2mseg/ Acob: DC VOmax: ________ VOmin: ________ Vr: ________ VO(av):_______ José Antonio Soria Pérez 67 Waveform corresponding to vO(t) using C = 10µF. CH1 VOLT/: 5V/ Zero POS1: -5V TIME/: 2mseg/ Acob: DC VOmax: ________ VOmin: ________ Vr: ________ VO(av):_______ Waveform corresponding to vO(t) using C = 100µF. CH1 VOLT/: 5V/ Zero POS1: -5V TIME/: 2mseg/ Acob: DC and AC VOmax: ________ VOmin: ________ Vr: ________ VO(av):_______ Explain the results: ____________________________________________________________ ____________________________________________________________ ____________________________________________________________ José Antonio Soria Pérez 68 ____________________________________________________________ ____________________________________________________________ LAB 3: Voltage regulator Waveforms corresponding tovc(t) and vO(t) CH1 VOLT/: 5V/ Zero POS1: -5V CH2 VOLT/: 5V/ Zero POS1: -5V TIME/: 2mseg/ Acob: DC Variable R L = 560Ω R L = 1kΩ R L = 10kΩ Vr VO IL Table 3. Electric variables corresponding to the Zener regulator Is Vr independent from VO? Explain why ____________________________________________________________ ____________________________________________________________ ____________________________________________________________ ____________________________________________________________ LAB 4: Voltage regulator using integrated circuit Variable R L = 390Ω R L = 1kΩ R L = 10kΩ Vr José Antonio Soria Pérez 69 VO IL Taula 4. Electric variables corresponding to the IC regulator L7805 Explain the difference of results regarding to the Zener configuration of section LAB3. What are the improvements and drawbacks of this configuration? ____________________________________________________________ ____________________________________________________________ ____________________________________________________________ ____________________________________________________________ ____________________________________________________________ José Antonio Soria Pérez 70 Lab Activity 4. Switching Electronics: the Bipolar Junction Transistor (BJT) Main goal: To understand the performance of the bipolar transistors (aka BJT)1 and knowing its main application in the field of switching electronics (analog, digital and mixed). 1 Introduction In this lab activity you’ll get introduced to the most common three-terminal electronic device: the bipolar junction transistor (BJT). Its operation principle is quite similar to a two-terminal current source which is controlled from another terminal. That is, the electric current at the base terminal (B) sets (or controls) the amount of current flowing from the collector terminal (C) to the emitter (E). Both electric symbols and current/voltage conventions are shown in Fig. 1. In general, we find two types of BJT: the npn (Fig. 1a) and the pnp (Fig. 1b). Their main difference lie on the sign convention used in all variables, which is opposite in relation to the other. As for the electric currents in each of the terminals, it holds that: E BC iii= + . (1) On the other hand, vBE corresponds to the voltage drop between base and emitter terminals, whereas vCE is the collector-emitter voltage. Unlike the diode, the BJT is able to operate up to three regions depending on the different conditions that may be given in the electrical variables when the three terminals are connected to other components (see Table 1): • When the base current iB is zero, there is no current flow at the collector terminal iC=0. In this case, we say that the BJT operates in the CUTOFF mode. This happens whenever the vBE voltage is under the threshold level VBEγ (typically VBEγ = 0.7V), specified by the manufacturer’s datasheet. • When the electric power at the base is significantly enough so as to make the base current iB greater than zero, the BJT leaves the cutoff region and enters in ACTIVE mode. The BJT will remain in this region as long as iB is significantly enough to keep the vCE voltage above the threshold level VCE(sat) (also specified in the datasheet). In this situation, vBE=VBEγ and iC is proportional to iB. The gain in current that is obtained between this to variables is denoted as hFE and is also provided by the manufacturer in the datasheet. 1 From now on we will use these terms to refer to this type of electronic semiconductor José Antonio Soria Pérez 71 (a) (b) Figure 1. The BJT. Symbols and electric current/voltage sign conventions. a) npn, b) pnp. Operating zone Electrical conditions Electrical behavior Cutoff (OFF) vBE < VBEγ , vCE > VCE(sat) iB = 0, iC = 0 Active iB > 0, vCE > VCE(sat) vBE = VBEγ, iC = hFEiB Saturation (ON) iB > 0, iB > iC/hFE vBE = VBEγ, vCE = VCE(sat) Table 1 Operating modes in the npn BJT: electric conditions and device behavior are specified. The same considerations apply to the pnp type when changing the variable index, i.e. vCE → vEC. • When iB is very large, the relation iC = hFEiB is not fulfilled anymore and the BJT enters the SATURATION mode. The voltage vCE takes its minimum value (vCE(sat)), and vBE is the same as in the active region, VBEγ. Fig. 2 summarizes the BJT i-v characteristics. In fact, the base-emitter junction acts as a diode: in both active and saturation regions this BE junction is in ON mode (vBE = VBEγ i iB > 0), whereas in the cutoff region this junction is in OFF mode (vBE < v VBEγ i iB = 0). In order to understand these three operating regions, consider the BJT circuit of Fig. 3, where Vin is some variable input voltage. Applying both KVLs at the input and output meshes (left and right, respectively) we obtain: 0 in B B BE V Ri v− −= (2) 2 0 C C CE v Ri v− −= (3) • CUTOFF operation: The boundary of Vin between the cutoff and active mode is obtained by using the condition vBE < VBEγ and setting iB = 0 in (2) (see Table 1). So the condition of Vin in the cutoff region is, in BE VV γ ≤ . (4) Since iC = 0, the condition vCE > VCEsat must hold, so, ( ) 2CE CE sat v VV= > (5) José Antonio Soria Pérez 72 (a) (b) Figure 2. The BJT i-v transfer characteristics. a) Input: iB – vBE. b) Output: iC – vCE. Figure 3. Schematics of the basic BJT configuration: npn type. • ACTIVE operation: It is clear that the input condition must be opposite to (4) if the BJT is to operate in this region. Indeed, expressing iB from (2) and using the equality vBE = VBEγ we obtain, 0 in BE B in BE B Vv i VV R γ − = ≥→ ≥ . (6) However, this is not the only condition for the active region because, on the other hand, when iB is large enough the BJT may enter the saturation region. The other boundary is determined using the condition vCE > VCE(sat). In addition, since we have iC = hFEiB in active mode, using (6) in (3) leads to the condition, 2 ()CE sat in B BE C FE vV VR V Rh γ − ≤+ , (7) Therefore, the active region is obtained within the input range, José Antonio Soria Pérez 79 Figure. 8. Enabling System of a 7-segment BCD display to be implemented in Task LAB2. (a) (b) Figure. 9. Other mechanical and passive elements of the circuit in Fig. 9. a) DIP8-switch3 used in the activation of all leds from the 7-segments BCD display; b) Integrated circuit 9A102G. It contains eight 1kΩ resistors with one terminal Connected to a common pin. Task PRELAB2. Identify the new components in the circuit of Fig. 8. Then, use the Board template to draw the connections you need to develop in order to make the enabling circuit of Fig. 8 work. • Use the web for looking for information on the 9A102G and LSD5355 integrated circuits. In the case of the 9A102G specify the meaning and the way 3 DIP – Dual In-line Package José Antonio Soria Pérez 80 of specifying the common pin. Which type of BCD display is necessary for in Fig. 8: common cathode or common anode? Task LAB2. Mount the circuit of Fig. 8 and check its behavior • 1) Mount the circuit on the Bread-Board. Place the components so as to minimize wire connections. 2) With the selector switch at position S = A, connect the power supply VCC = 5V. 3) With all switches in the DIP8-switch turned on, change the selector position (S = B). Mark the leds corresponding to the number represented in the display. • Change the position of switches in order to represent other decimal numbers and characters. Develop three examples, and indicate your selection in the results form specifying the configuration of switches in the table. • How would you use the waveform generator in order to show the number 8 (including decimal point) with a blinking pattern of 1-second interval? Specify the configuration of the waveform generator. 4. Latch SET/RESET (Optional section) In the digital functions introduced in section 3, the logic output is updated by the inputs at the same instant time t. That is, the inputs, and solely the inputs, specify the output of the system. This performance is known as a “memory-less” system. Digital circuits become interesting when they have memory. That is, they recall their last previous states. This allows, among different things, digital counters, arithmetical accumulators and all forms of circuits that work in a sequential fashion (one function executed after the other) to be implemented. Hence, it is said that this sort of digital systems use “sequential logic”. The most basic memory unit in digital circuits is known as the latch (or two-shot multivibrator). One type is the SET/RESET multivibrator (Fig. 9). Its output can be SET {Q = 1} or RESET {Q = 0}. In general, the output is modified using the 2nd and 3rd combination in Table 4 but, if S = 0 and R = 0, it remains unchanged, remembering the value updated in the previous state (see Fig. 10). Fig. 11 shows the electric diagram of a SET/REST multivibrator implemented with discrete components, including two bipolar transistors. As the NOT gate, both BJT can operate either at cutoff (IC = 0) or saturation (VCE ≈ 0) mode. This is the circuit performance: • When the power supply VCC is connected, both BJTs (T1 and T2) start their conduction cycle, since both base terminals are driven by positive voltages: T1 through resistors R2 – R6 – R7; and T2 through R1 – R5 – R8. However, not both transistors are identical (because of the tolerances within their manufacturing process caused by different level of impurities in the silicon material), so one transistor will conduct before the other. José Antonio Soria Pérez 81 (a) (b) Figure 9.SET/RESET multivibrator. a) Symbol; b) Implementation using 2-input NOR gates. Cases S R Q !Q 1 0 0 Q * !Q * 2 0 1 0 1 3 1 0 1 0 4 1 1 X X Table 4. Truth table of the SET/RESET multivibrator. Q* and !Q* denote previous output (before a ner update of the SET/RESET terminals is reached. !Q means inversion of Q. The combination S=R=1 is not valid in the SET/RESET multivabrator and is denoted with X. Figura 10. Behavior example of the SET/RESET multivibrator by means of a time diagram. Note that the output can be either Q = 0, or Q = 1 with S = R = OFF, depending on the previous state. José Antonio Soria Pérez 82 Figure 11.Schematics of the SET/RESET multivibrator implemented by means BJTs. At start up, assume that T1 is the first BJT conducting when S = R = OFF. Then, T2 = OFF and iC2 = 0. In this case, V!Q > VD2 = Vγ and the led D2 will be turned ON. The current flow at the base of T1, iB1 is then expressed as: !11 167 26 7 Q BE BE BRR VV V iii RR R γγ − =−= − + (20) where V!Q can be obtained from the KCL applied at the collector terminal of T2, ! ! 1! 26 2 2 62 CC Q Q BE Q R R RL L V V VV VV iii R RR γγ −− − =+→ = + → 62 122 26 ! 62 22 26 CC L BE L Q LL V RR V RR VRR VRR RR RR γγ ++ →= ++ (21) Thus, iB1 will be large enough to cause the saturation of T1 (T1 = ON) and, therefore, its collector-emitter voltage will decrease drastically (vQ = VCE1 (sat) ≈ 0.2V). Since this potential is not enough to drive the base of T2, vBE2 = VCE1(sat)R8/( R8 + R5) < VBE2γ, this transistor will work on cutoff mode. These will be the initial conditions of the circuit, the RESET state (Q = 0 and !Q = 1). • Now, assume that the switch S is activated (S = ON) for a small time period. Then, iB2 is momentary fixed by R3 (green path of Fig. 12a). The value of this variable during this interval is expressed as: José Antonio Soria Pérez 83 (a) (b) Figure 12. Idea del funcionament de la bàscula RS. a) Condició de SET. b) Condició de RESET. El camí marcat en verd indica el camí que causa la la saturació del BJT, mentre que el vermell indica el camí de circulació de corrent per activar els Leds. 22 2 35858 // // CC BE BE B VV V iRRRRR γγ − = − + (22) and is large enough to cause the saturation of (T2 = ON). Since vCE2 = VCE2(sat) ≈ 0.2V, this potential will not only be enough to maintain led D2 on but will also cutoff T1 (T1 = OFF). That is, both transistors change their behavior (SET: Q =1 i !Q = 0) and now the led that glows is D1. José Antonio Soria Pérez 84 The reader can note that this new situation is guaranteed even after the fading of vS(t) as iB2 will be given with an expression similar to (20) but with resistors R1, R5 and R8, 22 2 58 15 8 Q BE BE B RR VV V iii RR R γγ − =−= − + (23) when S=R=OFF, so the voltage VQ is also analogous to (21). In other words, the new outputs are, 5 1 2 1 1 15 ! 2( ) 511115 0 CC L BE L Q Q CE sat LL V RR V RR VRR V vV RR RR RR γγ ++ = = ++ ; � (24) • For returning to the RESET state, the user must activate the switch R (R = ON). Both BJTs will exchange again their operation (T2 = OFF and T1 = ON) and Q = 0; !Q = 1 (Fig. 12b). The procedure by which T1 is set to ON is analogous to that just explained above for T2 and the outputs will be given again by (21). Task PRELAB 3. Draw the component connections of the SET/RESET multivibrator from Fig. 11 in the Board template provided. Task LAB 3. Check the correct operation of the SET/RESET multivibrator. • 1) Mount the circuit. Use the following components: T1 = T2 = BC547C, R1 = R2 = 1k, R3 = R4 = 1k2, R5 = R6 = 10k, R7 =R8 =100k, RLED1 = RLED2 = 1k8, D1 = D2 of threshold voltage: Vγ=1.2V. • 2) Connect the power VCC = 5V and check which led is turned on. 3) Push the RESET button (R) if D1=ON, or push SET (S) if D2 = ON). Both leds should change operation mode. 4) Check that pushing again the same button (R or S depending on the initial case) does not alter the operation of leds. 5) Push the other button to return to the initial case. REMARK: Use wires for implementing the push buttons by connecting one end to VCC and emulate the effect of setting vS(t) and vR(t) to “1” by connecting momentarily the other end of the wire to R3 and R4, respectively. • Explain a possible utility of the SET/RESET circuit in digital electronics. José Antonio Soria Pérez 85 Annex 1.- BJT applications operating in the active region This section considers two typical applications of BJTs operating in the active region. No activities are proposed, since the main goal here is just to show the advantages and the utility of this operating region. The signal amplifier and the current source constitute two of the main general purpose applications of the BJT operating in this mode. A1.1 Signal amplifier using BJT One basic application where the BJT is “always” assumed to operate in active mode is called the voltage amplifier (or the signal amplifier). This electronic system is used very often to improve the power of audio and sensor signals. Strictly speaking, its functionality consists in “increasing” the input voltage magnitude in order to provide more power to the output. The following expression represents the mathematical function corresponding to this operation ( ) ( ) out in v t kv t= (1) where k > 1 is the gain factor of the electronic system, vout is the output and vin the input to be amplified. Figure A1 shows the block diagram corresponding to this operation. The slope of the input/output transfer characteristics vout – vin (Fig. A2) gives an idea of the gain that is obtained at the output. One way of implementing the amplifier by means of a BJT consists in changing the source vin in Fig. 3 by the same signal source vin(t) and modifying RB to so as to operate in the active region. Unfortunately, the npn BJT can only operate in active mode when vin > VBEγ, so the circuit admits only positive values of vin. This problem can be solved adding a DC voltage in series with vin so that an offset voltage level and all values from the input vin can be positive, but this would increase the implementation cost of the amplifier because another DC power supply (or battery) is required. The BJT amplifier in Fig. 3 develops its functionality and circumvents the offset problem using one single DC voltage source. This basic amplifier is know as the Common Emitter (CE) amplifier. In order to design its components, the analytical process consists of the following three steps: A. Offset estimation (VOUT) (or transistor biasing): The output offset is estimated by just considering the DC voltage supply (VCC) and disconnecting the remaining independent sources (the AC input, vin(t) = 0, in this case). If capacitors exists they are considered as open circuits because when s = 0, their impedance becomes infinite (ZC(s) → ∞). In fact, the goal of C1 is to permit the biasing of the BJT through resistor R2 and connect the AC input source to the base junction so that the input signal can be amplified. José Antonio Soria Pérez 86 Figure A1. Block diagram of the BJT voltage amplifier. The input magnitude vin is increased by a factor k at the output vout. Figura A2. Input/output transfer characteristics: vout – vin of the voltage amplifier Figure A3 Common Emitter voltage amplifier using BJT. When only the DC source is considered the circuit can be simplified to that of Fig. 4a (just use the Thevenin equivalent observed at the base terminal). Assume that the BJT is operating in the active region. The current IB is obtain by means of the KVL expression, () 12 / / 0. B B BE E E V R R I V RI γ − −− = (2) José Antonio Soria Pérez 87 (a) (b) Figure A4. Analytical diagrams of the BJT voltage amplifier. a) DC analysis. b) AC analysis where VB = R2VCC/(R1 + R2). Since IE = IB + IC = IB(hFE + 1), equating IB leads to: () ( ) ( ) 212 12 // 1 CC BE B E FE V RRR V IR R Rh γ +− =++ (3) where the term RE(hFE +1) the input resistance (Rin(BJT)) the BJT has in this circuit. If we design the resistors so as to obtain Rin(BJT) >> R1//R2 (10 times: Rin(BJT) ≈ 10 R1//R2), then IC can be approximated and estimated as B BE C FE B E VV I hI R γ − =� . (4) In other words, the base DC voltage VB and the resistor RE controls the amount of electric DC current flow in the the collector terminal IC . With this approximation, the base current can be underestimated (IB ≈ 0) and the output offset VOUT is expressed as B BE OUTCCCCCCC E VV V VRIVRR γ − =−=− (5) B. Voltage gain estimation (k): The gain factor is obtained by considering just the AC sources (AC) from the circuit and setting the DC supply to zero (VCC = 0). In this case, electrolytic capacitors are considered short-circuits at relatively higher frequencies (s = jω = j2πf where f > 1kHz) an their impedances can be underestimated, |ZC(s)| → 0. The capacitor C1 will then connect the AC source to the base junction of the BJT and the input AC resistance of the amplifier, Rin becomes ( ) 12 ()12 // // // // 1 in in BJT E FE R RRR RRRh= = + (6) José Antonio Soria Pérez 88 Since, vb(t) = vin(t) and the base-emitter junction can be considered a biased diode during the full input range, the swing of the base-emitter voltage will be negligible vbe(t) = 0, so in practical terms it can be assumed that the input voltage falls on vRE(t). For this reason, the collector current ic(t) is obtained as ()( ) ( ) RE in c EE v t vt it RR = = (7) and the output AC voltage expression, vo(t) = -vRC(t) = -RCic(t) is obtained as: ( ) ( ) in out C E vt vt RR = − (8) Thus, the voltage gain (k) of the circuit is () () out C in E vt R kvt R = = − (9) Finally, we can use (5) and (9) to obtain the full DC and AC output, vOUT(t), by means of the superposition principle ( ) ( ) ( ) ( ) C OUT OUT out CC B BE in E R v tV vtV VV vt R γ = + =− −+ (10) C. Estimation of the output swing (∆vout): We define as the output swing to the limitation in dynamic range ∆vout existing at the output of the voltage amplifier when the BJT leaves the active region, and which is normally expressed in terms of the maximum peak value that can be obtained at the output without causing signal distortion. Theoretically, the input vin(t) there is no limit for both the input and output amplitude. In practice, however, this assumption is not true because the BJT could leave the active region. When this happens, the result at the output is a pulsating signal of considerable distortion in relation to that of the input. Figure A5 illustrates the root of this problem. At vin(t) = 0, the zero reference at the output is fixed by the BJT operating point Q = {IC, VCE}. When the input varies, this point moves along a straight line which depends on the design of resistors RC and RE. To this line we refer to as the load line. The expression representing this line can be determined if both DC and AC analysis are overlapped when obtaining the collector-emitter voltage. On one hand, the contribution of input variations to this variable (Fig. A4b) is obtained by the KVL, José Antonio Soria Pérez 95 PRELAB 1. The logic inverter (The NOT gate) using BJT. Represent the waveforms you expect to see of vB(t) and vCE(t) CH1 VOLT/: Zero POS: CH2 VOLT/: Zero POS: TIME/: Acob: PRELAB 2: Electronic switch with 7-segment BCD Display. Draw the internal connections of the integrated circuit 9A102G and LSD5355 José Antonio Soria Pérez 96 Specify the meaning of the reference 9A102G: Specify common terminal at the 9A102G IC:__________________________________ Configuration used in the 7-segment BCD display:______________________________ PRELAB 3 (Opcional). SET/RESET multivibrator José Antonio Soria Pérez 97 Annex 3 –Lab activities REMARK: You MUST PRINT OUT this form and TAKE IT WITH YOU the day of the lab session Escola Politècnica Superior d’Enginyeria de Vilanova i la Geltrú EEL Electronic Systems (SIEK) Activity 4: Switching Electronics: The Bipolar Transistor (BJT) RESULTS FORM Students: Date: LAB 1. The inverter logic (NOT Gate) using BJT. Represent the waveforms of vB(t) and vCE(t) from the oscilloscope CH1 VOLT/: Zero POS: CH2 VOLT/: Zero POS: TIME/: Acob: José Antonio Soria Pérez 98 Specify the values of vB and vCE both at cutoff and saturation regions VB (cutoff) : ___________ VB(saturation) : ___________ VCE (cutoff) : ___________ VCE(saturation) : ___________ LAB 2. Electronic switch with 7-segment BCD display • Display visualization with S = B and S1=...=S8 = ON4 • Visualization with S = B and three random examples 1) 2) 3) Exemple S 1 S 2 S 3 S 4 S 5 S 6 S 7 S 8 1 2 3 Table A3.1 Specify switch positions in each example. Use ON and OFF to specify whether the switches are OPEN or CLOSED, respectively. 4 Mark the segments you believe will glow after setting the specified configuration. José Antonio Soria Pérez 99 • Specify the waveform generator configuration for observing the number “8” (decimal point included) with a blinking pattern of ONE SECOND. - SORTIDA: TTL 50Ω. - FUNCIÓ: Defecte SQUARE SINUS TRIANGULAR - OFFSET: Defecte Valor: _____________ - AMPLITUD: Defecte Valor: _____________ - FREQÜÈNCIA: ________________ LAB 3 (Optional). SET/RESET multivibrator Explain the behavior observed in the SET/RESET multivibrator and specify some use of this circuit in digital electronics: ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ ______________________________________________________________________ José Antonio Soria Pérez 100 Lab Activity 5. Analog electronics: The Operational Amplifier (OPAMP) Main Goal: Knowing the operation principle of the operational amplifier and to understand its utility in analog electronic applications, such as audio amplifiers and signal synthetization systems. 1 Introduction The operational amplifier (OPAMP) is a voltage amplifier with “extremely” high gain. For example, the popular 741 has a typical gain k = 200,000, whereas the gain of more expensive integrated circuits with advanced features, such as the reference OP-77 is k = 12,000,000. Due to such high values, the gain is often expressed in V/mV (or V/μV) and decibels. In the later case, the scale transformation used is ( ) 10 20log dB kk= . (1) Thus, the OP-77 has a voltage gain of 12V/μV, which is also equivalent to 141.6 dBs. Figure 1 shows the symbol of the OPAMP and the DC power-supply connection to make it work (though most of the times the power-supply is not represented in the diagram in order to minimize schematic cluttering). The inputs, identified by the “-” and “+” symbols are designated inverting and non-inverting, respectively. Their voltages with respect to ground are denoted vN and vP, and the output voltage as vO. The arrowhead form pointing to the right specifies the signal transmission direction from the input to the output. Figure 1b shows the equivalent circuit of a properly powered OPAMP. Though the integrated circuit itself does not have ground pin, the ground symbol represents the common point of the symmetric power supply of Fig. 1a. The model includes a voltage source controlled by vD, of gain factor k, the differential input resistance rd and the output resistance ro, respectively. Figure 2 shows the input-output transfer characteristics (vO-vD) of this component. Taking into account that vD = vP – vN corresponds to the differential input voltage, this electronic device is mathematically modelled as , for ,for , for OH OH D OL OH OD D OL OL D V Vv k VV v kv v kk V Vv k >    = ≤≤   <   . (2) José Antonio Soria Pérez 101 (a) (b) Figure 1. The OPAMP: a) Symbol and power connection; b) Internal mathematical model. This integrated circuit operates as a voltage amplifier. The values in red indicate component pin for the reference LM741, which is most used in 8-pin integrated circuits. Figure 2. The OPAMP transfer characteristics vO – vD. The horizontal axis has been extended (μV scale) in order to show the linear region in more detail. The supply voltages set the upper and lower limits, and the output swing of the amplifier VOL < vO < VOH: VOH = v(7) - VDrop-out i VOL = v(4) + VDrop-out; with v(7) being the positive supply and v(4) the negative one. The voltage drop information can be obtained from the manufacturer’s datasheet, and for the 741 this value is about VDrop-out = 2V. Since the 741 is powered with v(7) = -v(4) = VCC = 15V and the output range is ΔvO = ±13V, the input voltage is bound to be very small (ΔvD = ΔvO /k = ±65μV). For For instance, to sustain vO = 6V and unloaded 741 requires vD = 6/200,000 = 30μV. By connecting external components around an OPAMP, we obtain what we shall henceforth refer to as an OPAMP circuit. Understanding the difference between an OPAMP circuit and the OPAMP itself containing all the circuitry for developing its function is crucial. One example is the noninverting amplifier. José Antonio Soria Pérez 102 Task PRELAB0. Identify the new components you are going to use in this lab activity: the power transistors and the OPAMP. • Search the important information regarding the LM741 (or UA741) integrated circuit, the power BJTs: the BD243 and BD244; Find the manufacturer’s datasheet of each device and represent their contour package in the box provided. Indicate pin name and distribution. • Read the electrical characteristics from the OPAMP and specify open-loop voltage gain (k) drop-out and maximum power supply. 2. The noninverting amplifier The circuit of Fig. 3a consists of an OPAMP and two external resistors: R1 and R2. To understand its function, finding the relation between vOUT and vIN is necessary. To this end, the circuit is redrawn as in Fig. 1b, where the OPAMP has been replaced by its equivalent model (Fig. 1a), the internal resistors have been removed (rD →∞ and ro→0) and the resistive network has been rearranged strategically to emphasize its role in the circuit (Fig. 3b). vOUT can be found by means of (2) but expressions for vP and vN must be obtained previously. By inspection, it holds that P IN vv= . (3) On the other hand, using the voltage divider at the output yields 1 12 N OUT R vv RR =+ . (3) In fact, the voltage vN represents the fraction (or “sample”) of vOUT that is being fed back to the inverting input in order to be compared with the system input. So the system error, characterized by vε is 1 12 D P N IN OUT R vv vv v v RR ε ==−= −+ . (4) Using the relation (2), vOUT = kvD allows the output to be expressed as, 1 12 O IN OUT R v kv v RR  = −  +  . (5) Collecting terms and solving the ratio vOUT / vIN leads to, José Antonio Soria Pérez 103 (a) (b) Figure 3. The noninverting voltage amplifier. a) Schematics; b) Block diagram of the noninverting configuration aimed at correcting the error signal vD = vIN – vN so ther the input can track the sample vP = vOUTR1/(R1+R2). 1 12 '11 OUT IN vAk kR vA kRR β = = = +++ (6) Where we shall designate k = A and β = R1 / (R1 + R2). This result reveals that the circuit of Fig. 3 consisting of an OPAMP and a resistor pair is itself another voltage amplifier with different gain. This is not surprising, as the two amplifiers, while sharing the same output vOUT, have different inputs, namely vD in the case of the OPAMP and vIN for the circuit. To understand this difference, k is referred to as the open-loop gain, and k’ as the closed-loop gain. • The ideal OPAMP Considering the simplicity of the analysis corresponding to the the noniverting configuration, and its ideal closed-loop results, we wonder whether there is not a simpler technique to derive similar results in other more complex OPAMP circuits, bypassing most of the tedious algebra. Such a technique exists and is based on the fact that when the OPAMP is operated with negative feedback, in the limit k →∞ its input voltage approaches zero (vD = vOUT / ∞ = 0). As such, since vD = vP – vN in the limit it holds that, lim NP k vv →∞ = . (7) This property, referred to as the input constraint makes the input terminals seem as if they were shorted together, though they are not. Additionally, an ideal OPAMP draws no current at its input terminals “+” “- since its differential input resistance is also very large. In other words for voltage purposes the input port seems to be shorted, but for current purposes it seems to be open. Hence the popular designation “virtual short”. José Antonio Soria Pérez 104 Definition 1: When operated with negative feedback, the ideal operational amplifier will output whatever voltage and electric current {vOUT ,iOUT} it takes to drive vD = 0 (or equivalently to force vN to track vP) but without drawing any current at either input terminal (iN = iP = 0). From Fig. 1b it can be seen that is the voltage vN which tracks vP and not the other way round. Otherwise, the OPAMP would be unable to control the system and (7) will never hold. Thus, the OPAMP controls vN via the external feedback network and the output is always within the linear región of Fig. 2, so ideally the voltage gain of the circuit is '2 1 1 lim 1 1 OUT ideal A IN vR A k v AR ββ →∞ = = = + +� (8) To understand better the functionality of the OPAMP, consider the electric diagram of Fig. 4, where, by inspection, we have vP = vN = vIN(t). Since the operational drives vOUT to whatever vN = vP it takes to cause iN = iP = 0, it holds that iR1 = iR2, () ( ) ( ) 2 0 1 IN IN OUT vt vtv t RR −− = . (9) Equating (9) in order top find the ratio vOUT(t)/vIN(t) leads to the gain factor, 2 1 1 OUT IN vR vR = + (10) which is equivalent to that of (8). In general, when operated with negative feedback the OPAMP obtains the output fraction trough the path connected from the output to vN (from vOUT to vN, and from vN to ground). On the other, with positive feedback (path towards vP instead of vN), or no feedback at all, the OPAMP act as a voltage comparator: positive saturation (VOH when vP > vN) or negative saturation (VOL when vP < vN; ). 3. Current driver Obviously, there are a wide range of applications with th OPAMP using negative feedback. The idea that the output value can be set regardless of the load connected to it makes the OPAMP a good candidate for developing complex electronic systems with multi-stage connection (one stage connected after the other). In Annex 1, the reader can find a summary of applications using a single or several OPAMPS. In practice, however, the definition of the ideal OPAMP is only valid within the limitations specified by the manufacturer and, consequently, they may be taken into account in design purposes. For instance, one may be tempted to connect a 8Ω-speaker at the output, and use the noninverting configuration as an audio amplifier. However, if VOUT = 10V the OPAMP must be able to draw 1.25A, far too much in relation to the maximum 10mA of the 741. José Antonio Soria Pérez 111 (a) (b) (c) Figure 10. The three multivibrator types and their operation principle: a) Free-running; b)One-shot c) Twoshot. • Free-running multivibrator with OPAMP In the free-running multivibrator with OPAMP of Fig. 11a, the capacitor C and the resistor R in the negative feedback, and the resistors R1 and R2 (positive feedback) form an inverting Trigger Schmitt. When v(7) = -v(4) = VCC = 15V and assuming symmetric output saturation, VSAT = +13V and –VSAT = -13V since the positive feedback is predominant in this circuit7, the thresholds at vP will also be symmetric with ±VT = ± VSATR1/( R1+ R2) and the signal to the inverting input, while the inverting input vN the voltage is determined by the RC network. At power turn-on (t = 0), vOUT will swing either to +VSAT or –VSAT. Assume iy swings to +VSAT, so that vP = +VT. This will cause the resistor R to charge C towards +VSAT, leading to an exponential rise in vN with time constant τ = RC. As son as vN catches up with vP = +VT < vN at t = t1, the output snaps to –VSAT. This will not only snap vP = -VT but it will reverse the sing of the capacitance current. As such, for t > t1 the capacitor voltage will decay exponentially towards –VSAT until it caches up with vP = - VT > vN at t = t2. At this point, the output will snap again to +VSAT thus repeating the cycle. It is evident that once powered, the circuit has the ability to start and sustain oscillations: with vO snapping back and forth between +VSAT and -VSAT; and vN slewing exponentially from +VT to -VT and vice versa; so the waveform signal becomes square and periodic (Fig. 11b). Thus, it is interesting knowing the oscillation frequency f0 which can be found from the period T as T = 1/f0. 7 One may think that this circuit uses negative feedback, because of the RC network, and that the concept of ideal OPAMP can be therefore applied. However, when another branch is present in the positive path, and in the absence of external input sources (as it is the case of this cexampl), the positive feedback prevails over the negative feedback and will force the OPAMP to operate in saturation mode, working as a voltage comparator. José Antonio Soria Pérez 112 (a) (b) Figure 11. Free-running multivibrator using OPAMP. a) Electric diagram. b) Time signals at the output vOUT and the inverting input vN (red trace). Thanks to the symmetry of the saturation levels, the output vO has a duty-cycle, D =TH/T of 50% (=0.5), so finding the interval range ∆t = t2 – t1 = T/2 is necessary. Using the standard expression corresponding to the capacitor charge/discharge8 in this range, ( ) ( ) ( ) ( ) ( ) 22 1 t C N C CC vt vt v vt v e t ∆ −  = = ∞+ − ∞  (18) where vC(∞) = -VSAT; it holds that for ∆t = T/2, vN(t1) = +VT, vN(t2) = -VT; and τ = RC we obtain, ln 2 SAT T SAT T VV TRC VV  + = −  . (19) Substituting VT = VSATR1/( R1+ R2) and equating f0 = 1/T it leads to, 0 1 2 11 2 ln 1 2 fTR RC R = =  +   , (20) It can be observed that f0 depends only on the external components. In particular, it is unaffected by VSAT, which is an ill-defined parameter which varies from one OPAMP to another: any variation in VSAT will cause VT to vary in proportion, thus ensuring the same transition time and, hence, the same oscillation frequency. On the other hand, the maximum operating frequency is determined by the OPAMP slew-rate of expression (15). 8 See the document of PRT2, where the step response of the RC network was considered, in order to understand expression (11) in the interval ∆t = t2 – t1 José Antonio Soria Pérez 113 Task PRELAB2 (Optional). In the Bread-board template represent the component distribution and wire connections corresponding to the OPAMP-based freerunning multivibrator of Fig. 12 to be implemented in the lab. Task LAB2 (Optional). Mount the circuit and check the performance of the OPAMP-based free-running multivibrator (Fig. 12). • 1) Mount the circuit. Connect the DC power-supply and oscilloscope probes as indicated in Fig. 12. Turn the power on and represent the capacitor voltage vC in CH1; and the output vOUT in CH2. 2) Obtain the threshold values: ±VSAT, ±VT; and measure the oscillation frequency f0. 3) Compare the experimental results with the theoretical values obtained by means of (16). Task PRELAB3 (Optional). How would you connect the two circuits of this activity (Fig’s. 9 and 12, respectively) in order to synthesize and to hear a low sound of 500Hz through the speaker? Represent the circuit in the box provided and specify component values. Task Lab3 (Optional). Mount the circuit from PRELAB3 and check its electric operation. • 1) Mount the circuit. 2) Using the oscilloscope and/or the multimeter represent the waveforms and obtain the data you believe it is important in order to understand circuit behavior. • Comment results regarding the sound synthesizer. Figure 12. Mounting diagram corresponding to the free-running multivibrator in the lab. José Antonio Soria Pérez 114 Annex 1 – OPAMP basic configurations (with negative feedback) The OPAMP circuits of this section are considered basic. Very often, these circuits are used as stages of very complex analog electronic systems. In here, all configurations use negative feedback operation. Only the connection diagram (without DC supply) and the transfer function of each circuit is specified in Table 1. The analytical process necessary to obtain these functions are left to the reader as an exercise. Circuit name Connection diagram Function Voltage Follower 1 O I v v= OI vv= Noninverting amplifier 2 1 1 O I vR vR = + Inverting Amplifier 2 1 O IN vR vR = − Inverting adder Amplifier 1 Ni OF ii v vR R = = − ∑ José Antonio Soria Pérez 115 Diferential Amplifier 24 2 134 21 1 1 O RR vv RRR Rv R  =+−  +  − * If R1 = R2 = R3 = R4 21O v vv= − I/V Converter (T network) OI v kRi= − where 22 1 1RR kRR =++ Howland’s current source 41 23 123 1 O I RR RR iRRR v R  − = +   + * if R4/R3 = R2/R1 1 I O v iR = Derivator ( ) ( ) I O dv t v t RC dt = − ( ) () O I vs RCs vs= − Integrator ( ) ( ) ( ) 0 0 1t OI c v t v t dt RC vt =−+ + ∫ ( ) ( ) ( ) 0 1 Oc I v s vt v s RCs s =−+ * Habitually t0 = 0 José Antonio Soria Pérez 116 Instrumentation Amplifier (2 OPAMPS) ( ) 21Od v Av v= − 22 11 12 d RR ARR  =++   Instrumentation Amplifier (3 OPAMPS) ( ) 21 Od v Av v = − 32 1 12 d G RR ARR  = +   Negative Impedance Converter (NIC) 1 2 EQ R RR R = − * If R1 = R2 EQ RR= − Taula 1. Diverses configuracions bàsiques amb un o varis operacionals, i la seva funció de transferència José Antonio Soria Pérez 117 Annex 2 – Results form PRELAB REMARK: You MUST these activities BEFORE THE LAB SESSION CORRESPONDING TO PRT5 Escola Politècnica Superior d’Enginyeria de Vilanova i la Geltrú EEL Electronic Systems (SIEK) Activity 5: Analog Electronics: The operational amplifier (OPAMP) PRELAB Students: Date: PRELAB 0: Draw the contour package packages corresponding to the LM741; the BD243 and BD244. Paràmetre LM741 Observacions: Coment manufacturer observations k ∆v O V CC SR Taula A2.1 Anoti la informació relativa al BC547C que ha trobat al full de característiques José Antonio Soria Pérez 118 PRELAB1. Audio amplifier with OPAMP Represente the contour package of the potentiometer and specify pin function Specify connection and configuration of the DC-power supply so as to obtain a symmetric power DC-voltage of ±15V Represent the component connections of the audio amplifier José Antonio Soria Pérez 119 PRELAB2(Optional): OPAMP free-running multivibrator Represent the component connections of the OPAMP-based free-running multivibrator PRELAB3 (Optional): Sound synthesizer Represent the electric diagram corresponding to the sound synthesizer José Antonio Soria Pérez 120 Annex 3 – Lab activities REMARK: You MUST PRINT OUT and TAKE IT WITH YOU the day of the lab session Escola Politècnica Superior d’Enginyeria de Vilanova i la Geltrú EEL Electronic Systems (SIEK) Activity 5: Analog Electronics: The operational amplifier (OPAMP) RESULTS FORM Students: Date: LAB1. Audio amplifier. Represent the waveforms vIN(t) and vOUT(t) (1V-peak vIN) CH1 VOLT/: Zero POS: CH2 VOLT/: Zero POS: TIME/: Acob: