Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem

FINAL DEGREE THESIS Bachelor’s Degree in Electric Engineering DEVELOPMENT OF A ROBUST THREE-PHASE INVERTER FOR MICROGRID (MG) AND ELECTRIC TRACTION EXPERIMENTATION: CONTROL SUBSYSTEM Report and Annex Authors: Pau Novoa Pérez Co-supervisors: Herminio Martínez García Xavier Jordà Saruny Department: Department of Electronics Engineering Call: 2025, January Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem i Abstract This thesis presents the approach, design, implementation and manufacture of the control of a threephase inverter, developed for experimentation in microgrids and traction of electrical machines. Throughout this work, the three-phase inverter and its design will be briefly explained to introduce some of the most widespread control strategies in the control and power electronics sector for these type of converters. Next, the development of the control subsystem of a three-phase inverter for laboratory experimentation will be shown, from the approach and design to the manufacture and testing of it. This section will aim to show the following design strategies, selection of components, systems and devices chosen and software implementation to carry out the control of the inverter theoretically described while meeting the specific requirements of the project. The aim of the work is to deepen the design aspects of the control of a three-phase inverter, presenting different alternatives, to finally implement the design of a robust control with specific requirements. Finally, the performance of the developed system will be tested along the power subsystem to meet the requirements and expectations set by both the bases of these converters and the objectives set by the project. Memory ii Resum Aquesta tesi presenta l'aproximació, disseny, implementació i fabricació del control d'un inversor trifàsic, desenvolupat per a l'experimentació en microxarxes i tracció de màquines elèctriques. Al llarg d'aquest treball s'explicarà breument l'inversor trifàsic i el seu disseny per introduir algunes de les estratègies de control més esteses en el sector de l'electrònica de control i potència per a aquest tipus de convertidors. A continuació, es mostrarà el desenvolupament del subsistema de control d'un inversor trifàsic per a l'experimentació en laboratori, des de l'aproximació i el disseny fins a la fabricació i prova d'aquest. En aquest apartat, es pretén mostrar les següents estratègies de disseny, selecció de components, sistemes i dispositius escollits i implementació de programari per dur a terme el control de l'inversor teòricament descrit complint els requisits específics del projecte. L'objectiu del treball és aprofundir en els aspectes de disseny del control d'un inversor trifàsic, presentant diferents alternatives, per finalment implementar el disseny d'un control robust amb requeriments específics. Finalment, el rendiment del sistema desenvolupat es provarà al llarg del subsistema de potència per complir els requisits i expectatives establerts tant per les bases d'aquests convertidors com pels objectius fixats pel projecte. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem iii Resumen Esta tesis presenta el enfoque, diseño, implementación y fabricación del control de un inversor trifásico, desarrollado para la experimentación en microrredes y la tracción de máquinas eléctricas. A lo largo de este trabajo, se explicará brevemente el inversor trifásico y su diseño, con el fin de introducir algunas de las estrategias de control más extendidas en el sector de la electrónica de potencia y control para este tipo de convertidores. A continuación, se mostrará el desarrollo del subsistema de control de un inversor trifásico para experimentación en laboratorio, desde el planteamiento y diseño hasta su fabricación y prueba. Esta sección tiene como objetivo mostrar las estrategias de diseño empleadas, la selección de componentes, los sistemas y dispositivos escogidos, así como la implementación del software necesario para llevar a cabo el control del inversor descrito teóricamente, cumpliendo con los requisitos específicos del proyecto. El propósito de este trabajo es profundizar en los aspectos del diseño del control de un inversor trifásico, presentando diferentes alternativas para, finalmente, implementar un diseño de control robusto que satisfaga los requisitos planteados. Por último, se evaluará el rendimiento del sistema desarrollado junto con el subsistema de potencia, verificando que cumpla con los requisitos y expectativas establecidos tanto por las bases de estos convertidores como por los objetivos definidos en el proyecto. Memory iv Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem v Appreciations I would like to express my sincere gratitude to my TFE co-coordinators, Xavier Jordà Saruny and Herminio Martinez Garcia, for their invaluable guidance and support throughout this work. I would also like to thank IMB-CNM(CSIC) for graciously allowing me to use their facilities and resources, which were crucial for the development of this thesis. My heartfelt thanks go to ePowered RACING, without my time in the association this would not have been possible as I could not have found my passion for engineering. To Adrià Aroca, my project colleague, with whom I have worked nail to toe to be able to develop this project. Finally, I would like to thank my family and friends for their support, encouragement, and patience during the course of this project. Memory vi Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem vii Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 5 2. Introduction 2.1. Objective As mentioned before, this document aims to be a guide on how to design the control of a three-phase inverter from scratch, defining the basics for the implementation of a robust circuit and algorithm that makes the power subsystem work with a high performance. First, context will be given on three-phase inverter’s design and the control of this type of converters will be deeply explained. This will include explaining the principles of DC-AC conversion of electric energy, main power switching control types used in most applications digging dip into PWM and space vector control, the used control method will be presented and explained in detail and finally the implementation of this control along the circuit designed for it will be explained. Next, it will be detailed how to design, develop, and validate a control of three-phase inverter system that regulates power delivery through Space Vector Pulse Width Modulation. The project details the complete process of designing an integrated circuit and implementing the required hardware and software to ensure correct functionality. The PCB design includes a microcontroller, level shifters, dead-time circuits, and signal conditioning circuits necessary for communicating with a power subsystem. In addition, it includes This system aims to provide precise switching signals for power transistors, ensuring reliable operation under different load conditions. The project also involves programming control algorithms, focusing on SVPWM, to maximize inverter performance and improving the overall efficiency of power conversion. To achieve this, real-time data acquisition from sensors through Analog-to-Digital Converters is incorporated, allowing the system to monitor parameters such as DC bus voltage used to adjust modulation and switching times. Testing and validation of the subsystem and the whole three-phase inverter will be carried, focusing on verifying the shape of the PWM signals, analyzing the inverter’s performance under load conditions, and efficient electric power conversion. The main objective is to make sure the control subsystem works along the power subsystem and adds up to a functional three-phase inverter. Memoria 6 2.2. Scope Scope of the project includes the following points: - Introduction to the three-phase inverter: Introduction of the converter’s operation and scheme / design. - Control strategies for three-phase inverters: Introduction to most used control strategies of the three-phase DC-AC converters and selection of desired strategy for the project. - Hardware design: Design of the different electrical circuits for the control subsystem and implementation in printed circuit board. - Control scheme design of a three-phase inverter: Review of the control scheme designed for the converter, software selection and code implementation. - Results and validation of final prototype: Presentation of final device, with results of different tests made in laboratory experimentation and validation of performance. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 7 3. Theoretical introduction In this section, theoretical introduction on three-phase inverters and control strategies will be explained and detailed to give a base for the developed work in this project. 3.1. DC-AC conversion An inverter is a converter that allows to make a DC-AC electric energy conversion, this is a conversion that transforms direct current (DC) in alternate current (AC) often referred as “inversion”, which derives in the name inverter for the device that realizes this operation. As shown in Figure 3.1.1, direct signals like DC voltages or currents, are signals whose mean value is constant and different to zero over time, while AC signals are known to have a mean value equal to zero over time. In electricity, direct current also has the characteristic of having a single flow direction, while alternate current can flow in both positive and negative directions depending on the instant. Figure 3.1.1. DC and AC signals. DC-AC conversion is used in a wide range of applications including renewable energy systems (solar photovoltaic generation), electric traction, electric vehicles, uninterruptible power sources, etc. So, being used in so many different fields and applications, there have been loads of efforts to evolve this type of converters and their performance. In addition, different types of these kind of converters have been developed to cover all these applications, they may need different types of control, power, frequencies… A basic DC-AC conversion structure, or inverter structure, that allows the DC voltage (u) and current (i) with reference in the source (points M and N) to flow in two directions to generate an alternating Memoria 8 current in the load (points O and O’), being u’ and I’ the corresponding AC voltage and current [1], is shown in Figure 3.1.2: Figure 3.1.2. Basic DC-AC converter structure [1]. K1 and K1’ are complementary switches, as K2 and K2’ also are. When K1 is closed K1’ is opened and vice versa, same happens with K2 and K2’. Dividing the time in small periods T, alternating current from the direct current source is generated with an easy algorithm to control the opening and closure of the 4 switches: - 0 < t < T/2 K1 and K2’ are closed while K1’ and K2 are opened, applying a positive DC voltage between O and O’ and making the direct current flow from O to O’ during T/2. - T/2 < t < T K1’ and K2 are closed while K1 and K2’ are opened, applying a negative DC voltage between O and O’ and making the direct current flow from O’ to O during T/2. This can be seen in a. Figure 3.1.3. Basic DC-AC conversion. From top to bottom, direct current u having a constant value U, alternate current u’ having a value of U during T/2 and -U during T/2 [1]. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 9 As it can be seen in Figure 3.1.3., voltage in the load is an alternating signal which will lead to an alternating current when a certain impedance is connected between O and O’. This alternating voltage was generated from a DC voltage from the source simply by applying a simple algorithm for the opening and closure of the 4 switches. Applying different algorithms, the AC voltage and current in the load can be formed in multiple ways, such as sinusoidal alternating signals, triangular signals… Just my modifying the times in which DC voltage is applied in positive / negative directions, mean values inside the switching period can be lower or higher to form an AC voltage and current, with lower frequency than the switching frequency but different shape and characteristics. 𝑓𝑠=1 𝑇 (1) Memoria 10 3.2. Three-phase inverters Having reviewed how DC-AC conversion is performed with the use of a circuit made with four switches and a simple control algorithm, a single-phase inverter, the structure of a three-phase inverter can be easily explained by just making three branches made up of a single-phase inverter each, all three connected to the DC source, and each one connected to each phase of the load, as illustrated in Figure 3.2.1. Figure 3.2.1. Three -phase inverter basic circuit, with delta and star connections [22]. As it can be depicted in the previous image, the DC source E is feeding three branches, with two complementary switches each QX, and every switch QX is placed with an antiparallel diode which allows return currents from the load. From the center point of each branch, each line of the three-phase load is connected and fed with positive or negative voltage from the DC source, depending on which switch of each branch is closed and which is open. A transistor with an antiparallel diode is the most used solution for this group of switches, and it allows the inverter to be a four-quadrant converter, which allows both voltage and current in both directions. It is important to account for return currents, as normally inductive loads are fed (electric motors or drives, coils…) with this type of converters, and these return high amounts of energy when negative currents are applied to them, which is the case for AC loads. The most common voltage and currents generated with inverters is three-phase sinusoidal alternating current. To be able to generate this type of current, switches must be controlled in order they generate three alternating currents from the DC source, with sinusoidal waveforms displaced 120º between each other. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 11 So, knowing one each pair of complementary switches will be conducting every 180º, and that a three AC currents displaced 120º between each other must be generated, it is obvious that three out of the six switches will be conducting at any moment. This leads to 6 different possibilities of connection of the three-phase inverter, seen in Figure 3.2.2. Figure 3.2.2. Six different connection possibilities [8]. Phase and line voltages will depend on the connection of the phases, hence they will depend on which switches are conducting. So, controlling the opening and closure of the switches, it will be possible to control the voltages applied on the three-phase side, always keeping a fixed reference in the DC source. Memoria 12 3.3. Three-phase inverter control The control of a three-phase inverter plays a pivotal role in ensuring the power efficiency of the converter itself. These methods control the commutation of the transistors based on different strategies with the objective of reducing losses, harmonic reduction, precise control, simplicity etc. The methods discussed in this chapter are based in pulse width modulation (PWM) an extended strategy. In specific sinusoidal PWM (SPWM) and space vector PWM (SVPWM) are reviewed. 3.3.1. Pulse Width Modulation (PWM) Pulse Width Modulation (PWM) is a technique used to control the electrical power delivered to some devices in which, in a fixed period, the width of the pulses from the original source is varied. This modulation technique is commonly used in power electronics in DC-DC, AC-DC, or DC-AC converters such as boosts, bucks, rectifiers or inverters. The idea is to connect the original source to the connected device through a controlled switch such as a transistor. This transistor is then gate-controlled by the PWM signal, so it will connect source and load when the PWM signal gives a logic high value (logic 1) and disconnect them when the signal has a logic low value (logic 0). This modulation technique allows in converters with a DC source to reduce the mean value over the period between 0 and Vdc. In inverters it allows reproducing different waveforms to get AC voltages in the load from a DC source. The two most important parameters in a PWM are the period (T), which dictates the frequency at which the amplitude of the signal will change and also the range in which the switch will operate, and the duty cycle that is the amplitude of the signal within the time period. The duty cycle is calculated as follows: 𝑑𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒(%)= 𝜏 𝑇∗100 (2) Where T is the total period and τ the semi period in which the pulse is in logic 1. Figure 3.3.1 illustrates three different PWM with 10%, 50% and 90% duty cycle. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 13 Figure 3.3.1. Three PWM with different duty cycles. So, in converters with DC sources such as inverters, the mean value over a period of the output voltage will be, considering the source voltage has a value of Vdc: 𝑉𝑚𝑒𝑎𝑛 =𝑉𝑑𝑐∗𝑑𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒 100 =𝑉𝑑𝑐∗𝜏 𝑇 (3) So, in a three-phase inverter, three PWM can be modified to have a duty cycle that creates three voltage wave forms from the DC source one that have a mean value of 0 over a bigger period than the PWM one, thus generating an AC voltage. Memoria 20 3.3.3.3. SVPWM: application of vectorial modulation As mentioned before, SVPWM is a practical application of vectorial modulation. As it is used to operate inverters usually in motor control, its main goal is to produce sinusoidal alternating voltages to produce stator currents that generate a rotating field. In three-phase inverters, three sinusoidal currents with a 120º offset in between them. To achieve this, a rotating voltage vector must be produced in α-𝛽 reference with the desired amplitude and frequency requested by the control. Knowing the reference amplitude (Vref) and reference frequency desired (fref), the three voltages desired in abc reference are: 𝑣𝑎(𝑡)=𝑉𝑟𝑒𝑓·sin(2𝜋𝑓𝑡) (11) 𝑣𝑏(𝑡)=𝑉𝑟𝑒𝑓·sin(2𝜋𝑓𝑡+𝜋 3) (12) 𝑣𝑐(𝑡)=𝑉𝑟𝑒𝑓·sin (2𝜋𝑓𝑡−𝜋 3) (13) Reference α-𝛽 voltages can be extracted from Clarke’s transformation: [𝑣𝛼 𝑣𝛽]=2 3 [ 1 −1 2−1 2 0√3 2−√3 2 ] [𝑣𝑎 𝑣𝑏 𝑣𝑐] (14) As explained in section 3.3.3.2, α-𝛽 voltages form a reference voltage vector, and this can be generated using the eight different discrete voltage vectors from the eight different switching states. This come from the opening and closure of the switches of the three branches of the inverter, being Q1, Q3 and Q5 the upper switches connected to Vdc and Q2, Q4 and Q6 the lower switches connected to ground. Knowing the switches of the same branch can’t be in the same state at the same time, there are 8 possible different voltage vectors that can be applied. The following table summarizes these vectors, the line-to-line voltages applied based on DC reference voltage Vdc and the α-𝛽 voltages produced. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 21 Table 3.3.1: Discrete voltage vectors, in function of the transistors combination, line-to-line voltages and alfa-beta components. 0: Open, 1: Closed. Vector name Q1 Q3 Q5 van vbn vcn vα vβ vref 𝒗𝟎 󰇍 󰇍 󰇍 󰇍 0 0 0 0 0 0 0 0 0 𝒗𝟏 󰇍 󰇍 󰇍 󰇍 1 0 0 2𝑉𝐷𝐶 3 −𝑉𝐷𝐶 3 −𝑉𝐷𝐶 3 𝑉𝐷𝐶 3 𝑉𝐷𝐶 √3 2 3𝑉𝑏𝑎𝑡 𝒗𝟐 󰇍 󰇍 󰇍 󰇍 1 1 0 𝑉𝐷𝐶 3 𝑉𝐷𝐶 3 −2𝑉𝐷𝐶 3 −𝑉𝐷𝐶 3 𝑉𝐷𝐶 √3 2 3𝑉𝑏𝑎𝑡𝑒𝑗1𝜋 3 𝒗𝟑 󰇍 󰇍 󰇍 󰇍 0 1 0 −𝑉𝐷𝐶 3 2𝑉𝐷𝐶 3 −𝑉𝐷𝐶 3 −2𝑉𝐷𝐶 3 0 2 3𝑉𝑏𝑎𝑡𝑒𝑗2𝜋 3 𝒗𝟒 󰇍 󰇍 󰇍 󰇍 0 1 1 −2𝑉𝐷𝐶 3 𝑉𝐷𝐶 3 𝑉𝐷𝐶 3 −𝑉𝐷𝐶 3 −𝑉𝐷𝐶 √3 2 3𝑉𝑏𝑎𝑡𝑒𝑗𝜋 𝒗𝟓 󰇍 󰇍 󰇍 󰇍 0 0 1 −𝑉𝐷𝐶 3 −𝑉𝐷𝐶 3 2𝑉𝐷𝐶 3 𝑉𝐷𝐶 3 −𝑉𝐷𝐶 √3 2 3𝑉𝑏𝑎𝑡𝑒𝑗4𝜋 3 𝒗𝟔 󰇍 󰇍 󰇍 󰇍 1 0 1 𝑉𝐷𝐶 3 −2𝑉𝐷𝐶 3 𝑉𝐷𝐶 3 2𝑉𝐷𝐶 3 0 2 3𝑉𝑏𝑎𝑡𝑒𝑗5𝜋 3 𝒗𝟕 󰇍 󰇍 󰇍 󰇍 1 1 1 0 0 0 0 0 0 It can be seen that there are six active vectors (1 to 6) with a 60º offset between them and two null vectors 𝑣0 󰇍 󰇍 󰇍 󰇍 , 𝑣7 󰇍 󰇍 󰇍 󰇍 which apply no voltage to the three phases. These 6 sectors separated 60º between them are delimited by two vectors each one which can be extracted from: 𝑣 𝑖=2 3𝑉𝑏𝑎𝑡𝑒𝑗(𝑖𝜋 3) (15) 𝑣 𝑖+1 =2 3𝑉𝑏𝑎𝑡𝑒𝑗(𝑖𝜋 3+𝜋 3) (16) These six vectors delimiting the six sectors form a hexagon shown in Figure 3.3.4, the rotating vector in α-𝛽 reference will be normally inside a circular trajectory, but it can reach the values outside this range if it respects the hexagon perimeter. Memoria 22 Figure 3.3.4. Voltage limit hexagon and reference vector in α𝛽 plane [13]. In this hexagon in the α-𝛽 plane, the distance between the centre of the axis and one of the hexagon vertices is 2 √3∗𝑉𝑑𝑐, while the distance between the axis centre and the centre of every side of the hexagon, which is the circle radius is Vdc. To generate a sinusoidal voltage, as in the ‘abc’ three-phase reference, a reference voltage vector in α𝛽 plane must be rotating along the axis and inside these delimited perimeters. The angular velocity and amplitude of this vector will reflect on the output voltage, which will have the same frequency and line-to-line amplitude. Every two vectors delimit a sector (i) numbered from 1 to 6, sectors are used in control to understand which vectors have to be applied in every point of rotation of the vector. In every sector, the two adjacent vectors and the null vectors (v0 and v7) can be used to increase the amplitude or modify the angle of the voltage vector. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 23 3.3.3.4. Opening and closing times calculation For this project, an open loop SVPWM is going to be designed in order to control the three-phase inverter’s energy processing subsystem for which the control is designed [7]. This means reference voltage amplitude and frequency will be given by the control, so Vref, vα and v𝛽 will be generated and calculated by the control itself instead of being given by any other type of control such as FOC or DTC. Every instant, according to the reference amplitude and frequency, the voltage vector magnitude and angle will be generated from these and applied as a reference for the control, having to generate three 120º offset PWM that will make for a sinusoidal output in the three-phase inverter. To implement this algorithm, it will just take to calculate for how much time each one of the two adjacent voltage vectors of every sector is applied in every moment depending on the reference vector given, and how much time the null vectors are applied inside every period. The period will be given by the commutation frequency (fcom), which will be 15.625 kH, hence the every period Tcom will be 64 μs. First, the reference vector is decomposed in a linear addition of alpha and beta axis vectors. This is made by simply representing the reference vector as a vectorial sum of both vectors, in which beta is represented as the imaginary part and alpha as the real part of the vector [23]. 𝑣 𝑠∗=𝑣𝑠𝛼 ∗+ 𝑗𝑣𝑠𝛽 ∗ (17) Then, the vector can be done easily decomposed as a sum of the two reference vectors adjacent to the sector in which it is at every instant. Taking a look at an example in which the vector is in sector one in Figure 3.3.5, it can be easily seen how the reference vector vs in α-𝛽 plane can be decomposed as a sum of the two unitary vectors v1 and v2 multiplied by the time in which they are applied. Memoria 24 Figure 3.3.5. Voltage vector decomposition in sector 1, α𝛽 plane. [23] Generalizing for every sector, the reference vector can be separated in the sum of the first vector of the sector vi and the second vi+1 multiplied by the semi periods in which they are applied (τi and τi+1) and added to the time the null vectors are applied also multiplied by their semi periods (τ0 and τ7). 𝑣 𝑠∗=𝑣𝑠𝛼 ∗+ 𝑗𝑣𝑠𝛽 ∗=𝜏0𝑣 0+ 𝜏7𝑣 7+𝜏𝑖𝑣 𝑖+ 𝜏𝑖+1𝑣 𝑖+1 (18) The reference vector will result in a linear combination of the unitary vectors, which directly represent a concrete switching state of the inverter, and the null vectors which also represent fixed switching states of the inverter. All the upper transistors Q1, Q3 and Q5 will receive a PWM that will change in every period Tcom based on the semi periods in which every unitary vector is applied, which can be seen in Table 3.3.1. Combining equations 17 and 18 the real times in which every non-null vector is applied are calculated [23]: 𝑇𝑖=(𝑠𝑖𝑛(𝑖𝜋 3)𝑣𝑠𝛼 ∗−𝑐𝑜𝑠(𝑖𝜋 3)𝑣𝑠𝛽 ∗)√3·𝑇𝑐𝑜𝑚 𝑉𝑏𝑎𝑡 (19) 𝑇𝑖+1=(−𝑠𝑖𝑛((𝑖−1)𝜋 3)𝑣𝑠𝛼 ∗+𝑐𝑜𝑠((𝑖−1)𝜋 3)𝑣𝑠𝛽 ∗)√3·𝑇𝑐𝑜𝑚 𝑉𝑏𝑎𝑡 (20) Substituting for every sector, these are the times in which every unitary vector is used depending on the reference alpha and beta voltages: Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 25 Table 3.3.2: Commutation times for each sector, for a star load [23]. 𝑖=1 𝑖=2 𝑖=3 𝑇1=√3 2𝑉𝑏𝑎𝑡(√3𝑣𝑠𝛼 ∗ −𝑣𝑠𝛽 ∗)𝑇𝑐𝑜𝑚 𝑇2=√3 𝑉𝑏𝑎𝑡(+𝑣𝑠𝛽 ∗)𝑇𝑐𝑜𝑚 𝑇2=√3 2𝑉𝑏𝑎𝑡(√3𝑣𝑠𝛼 ∗ +𝑣𝑠𝛽 ∗)𝑇𝑐𝑜𝑚 𝑇3=√3 2𝑉𝑏𝑎𝑡(−√3𝑣𝑠𝛼 ∗ +𝑣𝑠𝛽 ∗)𝑇𝑐𝑜𝑚 𝑇3=√3 𝑉𝑏𝑎𝑡(𝑣𝑠𝛽 ∗)𝑇𝑐𝑜𝑚 𝑇4=√3 2𝑉𝑏𝑎𝑡(−√3𝑣𝑠𝛼 ∗ −𝑣𝑠𝛽 ∗)𝑇𝑐𝑜𝑚 𝑖=4 𝑖=5 𝑖=6 𝑇4=√3 2𝑉𝑏𝑎𝑡(−√3𝑣𝑠𝛼 ∗ +𝑣𝑠𝛽 ∗)𝑇𝑐𝑜𝑚 𝑇5=√3 𝑉𝑏𝑎𝑡(−𝑣𝑠𝛽 ∗)𝑇𝑐𝑜𝑚 𝑇5=√3 2𝑉𝑏𝑎𝑡(−√3𝑣𝑠𝛼 ∗ −𝑣𝑠𝛽 ∗)𝑇𝑐𝑜𝑚 𝑇6=√3 2𝑉𝑏𝑎𝑡(√3𝑣𝑠𝛼 ∗ −𝑣𝑠𝛽 ∗)𝑇𝑐𝑜𝑚 𝑇6=√3 𝑉𝑏𝑎𝑡(−𝑣𝑠𝛽 ∗)𝑇𝑐𝑜𝑚 𝑇1=√3 2𝑉𝑏𝑎𝑡(√3𝑣𝑠𝛼 ∗ +𝑣𝑠𝛽 ∗)𝑇𝑐𝑜𝑚 With these times and Tcom, every other time as T0 and T7 can be calculated in order to give the instructions to the duty cycle of the PWM of every transistor. The three PWM will be centre aligned, which means the half of the period will also be the half of the semi periods in which every PWM is on high-level. Figure 3.3.6. Voltage vector decomposition in sector 1, α𝛽 plane. This will help reduce harmonic distortion as it minimizes low frequency harmonics in the output voltage making the waveforms smoother. It will also distribute switching losses as it distributes switching events evenly between the three branches; In addition it will give symmetric output wave forms and improve voltage utilization allowing better usage of the DC source. Memoria 26 So, to calculate the duty cycles of every transistor (TQ1, TQ3 and TQ5), it will just be needed to take a look at Table 3.3.1 and the vectors used in every sector. For example if reference vector is in sector 1 (between angles 0 and π/3), only v1 (1,0,0) and vector 2 (1,1,0) along with the null vectors will be used. Which means Q1 will be used in T1, T2 and T7, while Q3 will be used in T2 and T7 and Q5 will just be used in T7. In T0 all three PWM are in low state. Figure 3.3.7. Three centre aligned PWM in sector 2, including which vector v0, v1, v2, v7 is used to generate them (R=Q1, S=Q3, T=Q5). [6] So, having vector times T1 and T2, T0 is easily calculated as: 𝑇0=𝑇𝑐𝑜𝑚−𝑇1−𝑇2 (21) 𝑇7=𝑇0 2 (22) Duty cycles will be calculated as: 𝑇𝑄1=𝑇1+𝑇2+𝑇0 2 (23) 𝑇𝑄3=𝑇2+𝑇0 2 (24) 𝑇𝑄5=𝑇0 2 (25) T0 and T7 (T0/2) are always calculated in the same way, the only thing that will change for every sector is the vectors used and their times (Ti and Ti+1) and which transistor (Q1, Q3 and Q5) contributes to each vector. For example, looking at sector 3 which is between angles 2π/3 and π of the αβ plane and delimited by vectors v3 and v4: Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 27 So, having vector times T3 and T4, T0 is easily calculated as: 𝑇0=𝑇𝑐𝑜𝑚−𝑇3−𝑇4 (26) 𝑇7=𝑇0 2 (27) Duty cycles will be calculated as: 𝑇𝑄1=𝑇0 2 (28) 𝑇𝑄3=𝑇3+𝑇4+𝑇0 2 (29) 𝑇𝑄5=𝑇4+𝑇0 2 (30) Sector 2 between π/3 and 2π/3: 𝑇0=𝑇𝑐𝑜𝑚−𝑇2−𝑇3 (31) 𝑇7=𝑇0 2 (32) Duty cycles will be calculated as: 𝑇𝑄1=𝑇2+𝑇0 2 (33) 𝑇𝑄3=𝑇3+𝑇4+𝑇0 2 (34) 𝑇𝑄5=𝑇0 2 (35) Sector 4 between π and 4π/3: 𝑇0=𝑇𝑐𝑜𝑚−𝑇4−𝑇5 (36) 𝑇7=𝑇0 2 (37) Duty cycles will be calculated as: Memoria 28 𝑇𝑄1=𝑇0 2 (38) 𝑇𝑄3=𝑇4+𝑇0 2 (39) 𝑇𝑄5=𝑇4+𝑇5+𝑇0 2 (40) Sector 5 between 4π/3 and 5π/3: 𝑇0=𝑇𝑐𝑜𝑚−𝑇5−𝑇6 (41) 𝑇7=𝑇0 2 (42) Duty cycles will be calculated as: 𝑇𝑄1=𝑇6+𝑇0 2 (43) 𝑇𝑄3=𝑇0 2 (44) 𝑇𝑄5=𝑇5+𝑇6+𝑇0 2 (45) Sector 6 between 5π/3 and 2π: 𝑇0=𝑇𝑐𝑜𝑚−𝑇6−𝑇1 (46) 𝑇7=𝑇0 2 (47) Duty cycles will be calculated as: 𝑇𝑄1=𝑇6+𝑇1+𝑇0 2 (48) 𝑇𝑄3=𝑇0 2 (49) 𝑇𝑄5=𝑇6+𝑇0 2 (50) Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 29 3.4. Microcontroller To design a three-phase inverter control subsystem it is capital to choose a suitable option to manage all the computing, I/O signals and all the processes. There is a huge variety of different devices such as digital signal processors (DSPs), field-programmable gate arrays (FPGAs) and microcontrollers (MCU). For this project, an MCU has been chosen to play the role of controlling and computing all the orders and processes related to the inverter control. This choice has been made thinking in affordability, flexibility, and the facility MCU have because they have multiple peripherals integrated like PWM timers, analog-to-digital converters (ADCs) and communication interfaces which simplify real-time control tasks, for example SVPWM inverter control. Microcontrollers are chips designed as compact computing systems and they are used for specific tasks. They combine a Central Processing Unit (CPU), memory, and peripherals in a single device. They can be used in a wide range of applications such as automation, power electronics and inverter control. “Today, microcontroller production counts are in the billions per year, and the controllers are integrated into many appliances we have grown used to” [10]. Selecting a microcontroller depends on processing power, peripherals, cost, and energy efficiency. The option for this project was the STM32F767 microcontroller integrated in the STM32F767ZI learning board or ‘nucleo’ fabricated and distributed by STMicroelectronics® shown in Figure 3.4.1. The STM32 series was chosen for this project for its advanced timers, high-speed ADCs, easy and adaptable development system, and number of entries. In addition, the author had some experience with the STM32 series MCU and a lot of information about them available. Figure 3.4.1. STM32F767ZI board with STM32F767 MCU [19]. Memoria 36 4. Design Inside this chapter the design of the hardware of the three-phase inverter control system will be shown and explained in detail. It is a crucial part of the project as it materializes all the theoretical study that has been developed and it shows it in a real and particular application. First, the different electrical circuits of the system will be analysed and described in order to understand the different functionalities of the whole device. The different components used will be reviewed and their main functionalities and characteristics mentioned. Then, the physical materialization of the project will be reviewed, focusing on the fabrication of the electrical circuit as a printed circuit board (PCB). All steps, characteristics, restrictions, techniques, and considerations involved in the manufacturing process will be detailed, reflecting the complete system. 4.1. Electrical circuit The design of the electrical circuit of the three-phase inverter control system is critical to ensure functionality and optimal performance. It has to be conceptualized in a way all the different circuits comprising the system are correctly interconnected and their electrical specifications are consistently adhered to. For the optimal operation of the whole system, every component must have its own circuit in terms of power source, high frequency filtering and voltage ripple filtering. In addition, every in or out pin of the integrated circuit components has to be connected in a certain way whether it is connected or not. No short-circuits can be possible in any circuit configuration and all the necessary components and lines have to be designed in order to compel with the system’s purpose and specifications. Finally, all components that must be grounded have to be connected between them at the same voltage level (0). Finally, all the inputs to the system must be connected through an entry port to their destination and the output signals from the system must have a correct exit port to access other systems of the inverter such as the energy processing subsystem’s drivers that have to be connected to the output PWM of the control system. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 37 4.1.1. STM32F767ZI The microcontroller is the central part of the whole system, is the component that will output the raw signals from the SVPWM control and will receive the treated signals for the input reference control of the AC voltage and frequency and feedforward control of the DC voltage as well as the AC currents monitoring. In Figure 4.1.1 it is shown how the STM32F767ZI will be connected to the electrical circuit through four surface-mounted (SMD) 36 pin double row connectors with 2.54 mm spaced pins, the HLE-118-02-LDV-K model from SAMTEC, that will be connected to the 144 output pins of the MCU board. Figure 4.1.1: STM32F767ZI electrical circuit in inverter control system. As seen in Figure 4.1.1, the board will be fed at the common 5 V of the whole system through pin E5V (pin 6 in STM32F767ZI, pin 5 in left-side smd connector), with an internal regulator that reduces from 5 V to 3.3 V it will feed the microcontroller and all the features of the board. The voltage source will be given through two ceramic capacitors 10 μF and 100 nF that will filter high frequencies and voltage ripple of the source. Memoria 38 Figure 4.1.1 takes a look at the two sets of two potentiometers each: PTV09A-4020F-A503 with a 0-51 kΩ value range and PTV09A-4020F-A502 with a 0-5 kΩ range will be connected in series to control both reference AC voltage amplitude and frequency. Figure 4.1.2: Potentiometer electrical circuit for reference generation . Both potentiometers are fed with a 3.3 V source that comes from the voltage regulator of the STM32F767ZI, fed through two ceramic capacitors 10 μF and 100 nF that will filter high frequencies and voltage ripple of the source. The positive voltage will be connected to the positive pin of the 51 kΩ potentiometer, its regulated resistance pin (centre pin) will be connected to the positive pin of the 5 kΩ potentiometer and to the MCU’s ADC (pins 35 and 37 of STM32F767ZI) and its regulated resistance pin (centre pin) will be connected to ground. This way, a 0-55 kΩ regulated resistance will be made in which the voltage can be regulated from 3.3 V (0-51 kΩ potentiometer set to 0Ω) to 0 V (0-5 kΩ potentiometer set to 0Ω), which will be both minimum and maximum reference values for AC voltage amplitude (0-300 V) and frequency (0-100 Hz). Finally, six PWM (IGBT_Q1 to IGBT_Q6) will be outputted from the MCU’s board through the connectors to the following circuits (dead-time and conditioning 3.3 V to 5 V circuits); 3 AC currents Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 39 and DC voltage feedback will be inputted to the STM32F767ZI through their conditioning and filtering circuits detailed in section 4.1.4. 4.1.2. Dead time circuit As explained in section 3.5, the dead time consists in a short delay in the signal of each of the PWM signal, delaying the state switch. Six circuits have been designed like the one shown in Figure 4.1.3, one for each transistor’s control signals, all consisting in the same circuit model and components. Figure 4.1.3: Dead time circuit. The circuit is inputted the already level-shifted to 5 V PWM from the MCU (and through the levelshifter circuit). The circuit consists of a low-pass RC filter built with a fix 1 kΩ resistance and a variable 0-51 kΩ SMD potentiometer (PVG5A503C03R00 series) connected in series with a 100 pF capacitor and an antiparallel high frequency SMD diode (1N4148W-G series) that allows to rapidly discharge the capacitor. The SVPWM output from the MCU will have a frequency of 15.625 kHz., so the low-pass filter formed by the RC association must not filter the PWM output but be able to control the rising-up pulses of the signal in order to have dead-time in the closing of the switches. The range of frequencies filtered depending on the R and C values are: 𝑓𝑐=1 2𝜋(𝑅+𝑅𝑝𝑜𝑡)𝐶 (52) So, with potentiometer set to 0Ω, maximum frequency (fc) allowed will be: 𝑓𝑐=1 2𝜋∗1000∗100∗10−12=1.591 𝑀𝐻𝑧 (53) Memoria 40 So, with potentiometer set to 51 kΩ, maximum frequency allowed will be: 𝑓𝑐=1 2𝜋∗51000∗100∗10−12=31.2 𝑘𝐻𝑧 (54) With the biggest value of the potentiometer the PWM period frequencies would be filtered, so in order for the system to work correctly, a fixed value for the potentiometer will be set for the dead-time circuit to perform correctly and limit the minimum time in the closing of the transistors. After a theoretical first approach, the potentiometer value will be adjusted by hand in experimentation. 4.1.3. Buffers, level shifters and trigger Schmitt circuits The conditioning circuits for the SVPWM MCU’s outputs are critical for the performance of the whole system, including the energy processing system that treats the HV signals. The reason behind it is that the whole control system has been standardized to a 5 V common voltage for all logic circuits, and the optocoupler driver works with a current of 10 mA, which the MCU can not provide through the General Purpose Input/Output ports used for outputting the six PWM. Level-shifter As shown in chapter 3.6, the first circuit to interact with the output signals are the level-shifters that elevate the logic high value of the six PWM to 5 V instead of 3.3 V. The level-shifters used for this purpose are the SN74HCT125N, with four possible input/outputs that can lift the voltage of the high frequency digital signals as it can work with rise/falling times of 500 ns or less. Two level-shifters will be used for the six transistors’ PWM signals, three signals will be operated in each of the SN74HCT125N series chips. To be able to output the signals at a certain voltage value, the components must be fed at that exact same value. In this case, SN74HCT125N have to be given a supply voltage between 3.5 V and 3.5 V [14], for this project the supply voltage will be the common 5 V bus of the system. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 41 Figure 4.1.4: Level-shifter circuits. As seen in Figure 4.1.4, U1 and U2 are the corresponding level-shifter circuit symbols. The 5 V voltage source is fed through two capacitors of 1 μF and 100 nF as recommended by Texas Instruments in the component’s datasheet [14]. In addition, every pair input/output ports have also a logic nor port that activates/deactivates its output if it is grounded (1-OE for 1A/1Y pair of input/output pins). Any not used pair of pins must have input and logic gate grounded for the proper functionality of the chip. Figure 4.1.5: Level-shifter functional block diagram. [14] The U1 level-shifter receives 3.3 V transistor’s 1 to 3 outputs from the MCU (IGBT_Q1 to IGBT_Q3) and outputs the 5 V signal to the dead-time circuit (IGBT_1_5V to IGBT_3_5V), while U2 level-shifter receives 3.3 V transistor’s 4 to 6 outputs from the MCU (IGBT_Q4 to IGBT_Q6) and outputs the 5 V signal to the dead-time circuit (IGBT_4_5V to IGBT_6_5V), distributing this way the power and pins usage of both chips. Schmitt trigger The inverted trigger Schmitt used is the HEF40106BT-Q100J series from Nexperia, chosen because its wide range of supply voltage 3 V-15 V [15] and the number of pins available in each chip. At a 5 V supply Memoria 42 voltage it has got a minimum and maximum positive-going threshold voltage of 2 V and 3.5 V respectively and its perfect for correctly shaping and filtering the modified PWM outputted by the dead-time circuit, giving a 5 V correctly shaped PWM but already with the dead-time delays. Figure 4.1.6 shows the circuits of the two HEF40106BT-Q100J used in the control system circuit, which receive the signals from the dead-time circuit (already at 5 V as they have been outputted from the level-shifters) as an input at A pins, and output the filtered but inverted PWM at 5 V with dead-times: Figure 4.1.6: Trigger Schmitt’s electrical circuit. 5 V voltage supply is filtered by two ceramic capacitors of 10 μF and 100 nF as recommended by the datasheet [15], and the logic ground of the chips is connected to the ground reference of all the system. Delayed signals of IGBTs 1 and 2 are corrected and filtered with IC1 and outputted as inverted 5 V signals (IGBT_Q1_INV, IGBT_Q2_INV), while delayed signals of IGBTs 3 to 6 are corrected and filtered with IC2 and outputted as inverted 5 V signals (IGBT_Q3_INV to IGBT_Q6_INV). Pins have been selected for space and physical positioning of the chips as it will be shown in chapter 4.2. Buffer The inverted buffers used in the control system for the six output PWM that will feed the opto-drivers in the energy processing system are the MC14049UB hex buffers from Onsemi. These allow a supply voltage range (VDD) of 3 V-18 V, can output voltages up to VDD + 0.5 V being able to output a 45 mA current [16] which is more than enough for the 10 mA needed by the optocoupler drivers. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 43 Figure 4.1.7: Inverted buffers electrical circuit. As illustrated in Figure 4.1.7, IC3 and IC4 are the MC14049UB inverted buffers responsible for outputting the six 5 V, dead-time, filtered and buffered PWMs adapted for the opto-drivers used in the energy processing subsystem that will be responsible for the transistors switching. Inverted signals from Schmitt triggers (IGBT_QX_INV) are fed to the IN pins of the buffers while conditioned signals for the drivers (DI_IGBT_X) are outputted through OUT pins of both IC3 and IC4. As it happened with IC1 and IC2, transistors 1 and 2 signals are treated by IC3 and transistors 3 to 6 signals are treated by IC4 due to space and physical distribution in the PCB. Memoria 44 4.1.4. Analog-to-digital converters and filtering As mentioned in chapter 3.7, the three AC output currents and input DC voltage are sensed and their values sent in real time to the MCU’s ADC peripherals to be able to monitor and apply a feedforward control over the SVPWM output. For the correct processing of the signals, these have to be adapted to the 3.3 V voltage control that the ADCs make in order to be able to read them properly. Starting with the AC currents, these already are voltage signals regulated at 3.3 V, so they don’t have to be treated by any means in order for the ADC to read them correctly. However, a low-pass filter has been designed for each signal for them to avoid high-frequency noises that could disturb the signals, as illustrated in Figure 4.1.8: Figure 4.1.8: AC currents sensed signal filters. Every AC current RST sensed signal is filtered with a low-pass filter composed by a 1 kΩ resistance and a 100 nF ceramic capacitor that cut frequencies over 1.6 kHz. AC currents should not have a frequency over 100 Hz so this value will cut frequencies over 16 times their fundamental. In addition, the 1 kΩ resistance limits the current value outputted by the sensors to 3.3 mA. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 45 For the feedforward control of the DC voltage source of the inverter a voltage transducer LV 25-P is used to sense the DC input voltage value [7]. This voltage transducer, when receiving the nominal input current from the primary circuit of 10 mA will output 25 mA through the secondary winding [17]. With a 25 mA signal sent to the control subsystem, it must be adapted to be an analogue voltage signal from 0 V to 3.3 V. To make Vdc sensor output becomes a voltage signal a 133 Ω resistance has been placed in the circuit and the voltage of the ADC is measured in the resistance terminals, so the maximum voltage drop in the resistance will be: 𝑉=𝑅𝐼=133Ω∗0.025𝐴=3.325𝐴 (55) This way, the ADC will be able to read all the voltage in the range from 0-25 mA in the secondary of the voltage transducer, which corresponds to 10 mA in the primary that, considering it comes from a 55 kΩ resistance connected between DC power source and earth it can measure up to 550 V. This circuit will be suitable for the whole system as the maximum Vdc applied will be 300A. Figure 4.1.9: Circuit for Vdc sensing via ADC. As it can be seen in Figure 4.1.9, sensed signal comes from the energy processing subsystem and its current flows through R12 generating a voltage drop between the first terminal of R12 and ground. Then this voltage drop is sensed by the MCU’s ADC corresponding to the SENSOR_V_IN entry. Memoria 52 4.2.2. Distribution of the circuits and PCB design The distribution of the circuits has been thought taking into account that the most important traces are the ones corresponding to the 6 PWM and they can’t cross loads of power lines. Figure 4.2.3 shows the different circuits or components distributed along the PCB layout. It can be seen that the 6 PWM outputs from the MCU connectors (dark blue) are connected to the level-shifters (purple) which switch the logic high values from 3.3 V to 5 V. Then, outputs of the level-shifters go through the 6 dead-time circuits for each PWM (light yellow) that apply a dead time to the rising edges of the PWM and they are later corrected and filtered by the Schmitt triggers (light green). Then, signals are buffered at the inverted buffers circuits (light blue) to finally be outputted in the connectors (dark yellow). Upper right connectors input and output voltage source for all logic circuits of the board and the voltage sensor in the energy processing board. Potentiometers (dark green) are situated in the left top and down corners for adjusting reference inputs in the MCU and finally low-pass filters (grey) treat the current sensors signals that come from the connectors. Figure 4.2.3: PCB layout circuits distribution. This distribution of circuits allows for the six SVPWM outputs to be inputted from the MCU, treated by the different conditioning circuits and be outputted through the board connectors without being excessively crossed by power lines or other analogic or digital signals such as sensor signals. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 53 Due to space limitations, connectors have been distributed top and below the board for space optimization and to keep the output PWM traces as short as possible to avoid increasing line impedance, hence disturbing the output signal. As seen in Figure 4.2.4, the common +5 V power line for all logic circuits has been traced almost in its totality in the bottom face (blue) of the board to avoid it being near the analogic and digital signals and possibly perturbing them. Figure 4.2.3: +5 V power line in PCB layout. To feed the different circuits located in the top face, vias were used to bring the power line from one layer to the other, as it can be seen in Figure 4.2.4 in which one of the Schmitt triggers (IC2) is fed from a via that transports +5 V line. Figure 4.2.4: IC2 Schmitt trigger fed from +5 V net via. Memoria 54 All via holes used were 0.3 mm diameter drill holes to respect and provide margin from the manufacturer’s restriction in section 4.2.1. All vias are at least 0.7 mm diameter which results in a 0.2 mm minimum spacing between hole and end of the via, respecting the restriction of 0.1 mm minimum value and 0.15 mm recommended value. Minimum trace widths are 0.5 mm and trace-to-trace distances placed in the board are at least 0.6 mm, clearly respecting 0.1 mm limit and ensuring less line impedance. Clear example of this shown in Figure 4.2.5 are lines for MCU 3.3 V PWM output corresponding to transistors Q1 and Q3, which are 0.5 mm width each and have a 0.6 mm spacing. Figure 4.2.5: Minimum trace width and spacing in PCB layout. All the different circuits and components share the same reference 0 V point, corresponding to the ground of the voltage source, this net in the PCB layout is noted as Earth. All circuits must be connected to this same ground for the current to flow through them and return to the power source. The problem with the GND net is that loads of lines should be traced to all points of the board and it would be a mess to not cross them with other net traces. For this purpose and also trying to avoid high line impedances, a mass plane or ground plane is designed all over the two layers of the PCB. This way, every space not filled with any trace or via corresponding to other nets, is connected to the GND net. Figure 4.2.6 shows the PCB layout with the Earth net mass plane highlighted to show the design of it. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 55 Figure 4.2.6: Earth net, mass plane designed in the PCB. The clearance, minimum spacing between mass plane and other nets’ traces or vias, is 0.3 mm respecting the manufacturer’s restrictions. This design allows for the current to have a big path (low impedance) for it to return to the negative pole of the voltage source, and also saved time and effort in the PCB design. Taking a look into the different components powered at +5 V, most or all of them are fed the voltage from a capacitor filtering the voltage and maintaining it constant. This capacitor or capacitors must be connected between +5 V and Earth, and situated near the +5 V and GND pins of the different components. Some of the components don’t have their +5 V and GND pins near or are separated by another net’s trace, which doesn’t allow for the GND of the capacitors to be near the GND of the component. In Figure 4.2.7 it is shown how this problem has been solved for IC2 placing a via that allows for the current to flow out of the component through the capacitor GND, making sure electrons are flowing correctly through their path and avoiding noise in the source. Memoria 56 Figure 4.2.7: Earth via for IC2. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 57 4.2.3. Fabrication and component soldering Once the PCB is fabricated by the manufacturer, including traces, vias and insulation testing of all the board, all the components of the board have to be placed and welded in their specific position and pads for the system to work correctly and perform all its features. All components are tinned manually with a welding tool, tin and with the help of flux to ensure the tin is in contact with the copper pads of the board and the pins and pads of every component. As illustrated in Figure 4.2.8, first the MCU surface-mounted connectors were tinned to check the correct spacing and design of the board, the PCB is held in order to ease the soldering work. Figure 4.2.8: PCB with just two connectors tinned. Almost all components of the board are surface-mounted, which allows for the connection to be made in just one of the layers of the PCB, except for the reference setting potentiometers which are throughhole components that are connected to both layers. In Figure 4.2.9 it can be seen the PCB with all components hand-tinned except for the input/output connectors of the PCB, but with the MCU connectors placed. Memoria 58 Figure 4.2.9: PCB with just all components tinned except for I/O connectors. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 59 5. Software The implementation of the SVPWM algorithm in the MCU is a critical part of the project, as it sets the base for the system’s functionality and performance. This chapter provides a comprehensive review of the software design and programming, focusing on its integration within the inverter control system. The STM32F767ZI is programmed using STM32CubeIDE tool, which supports C development. The programming process involves writing code, compiling it into a binary file, and flashing it onto the MCU via SWD (Serial Wire Debug) interface, using the ST-Link debugger/programmer. Figure 5.0.1 shows the block diagram that explains the software operation and implemented SVPWM algorithm divided in the different sections of the program. First, the analog-to-digital converted signals are used as inputs for system key signals such as reference voltage (V*), reference frequency (f*) and DC bus voltage (VDC). Using the inputs from the ADC required for SVPWM parameters, the program calculates the voltage vector components (vα*, vβ*) in the αβ plane. This process is executed in a timer 2 (TIM2) interruption Moreover, the angle (θ) is depicted from the ADC inputs, and it is later used for sector interpretation, defining which sector (1 to 6) is the voltage vector in SVPWM algorithm. This sector will determine which switching states will be active. Based on the sector, the algorithm calculates the switching times (Ti, Ti+1) for the active vectors, hence determining how long each switching state is applied during the PWM cycle. Then, the switching times are converted into PWM duty cycles (TQ1, TQ3, TQ5), all this is performed in the main loop of the program. Finally, duty-cycles are applied in form of clock ticks (NQ1, NQ3, NQ5) in the timer 1 (TIM1) registers that will output them in form of PWM signals, together with their complementary channels (NQ2, NQ4, NQ6). This actualization of the TIM1 registers is also performed in the TIM2 interruption. Memoria 60 Figure 5.0.1: SVPWM programmed algorithm block diagram. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 61 5.1. Main code The main code or program main.c is where the SVPWM algorithm is executed, by calculating reference voltage vector and angle, selecting the sector of the SVPWM in which the vector is to apply the correct switching states. Then, times for the application of every vector are calculated to compute the duty cycle of the PWM of every transistor, finally these duty cycles are outputted to the TIM1 registers in charge if generating the PWM signals. This main program can be separated in two different parts, the main loop in charge of the calculations and the interruption that updates the different input and output values. 5.1.1. Main loop: Opening and closing times calculation The main loop is the part of the main program where, depending on the inputted values, the SVPWM sector is selected (1 to 6), to decide which voltage vectors are used and calculate the times in which they are applicated inside the PWM period (Ti, Ti+1). Finally, duty cycles of each transistor’s PWM (TQ1, TQ3, TQ5) are computed from these times. Figure 5.1.1 shows how this process is done for sector 1, between angles 0 and π/3, calculating T1, T2, T0 and the three duty cycles (TQ1, TQ3, TQ5), which are compared to the minimum switching time that the transistors have (Tmin). The sector selection is done with an IF instruction, and the calculations for each IF or sector are inside a main loop WHILE(1), which is repeated forever. Figure 5.1.1: Main loop, first sector (IF). Memoria 68 5.2.2. Analog-to-digital converters (ADC) To program the ADCs used for input information in the program, a similar procedure has been carried in order to configure them. Six ADC channels have been used for the three AC current measurement, voltage and frequency reference values potentiometers and one for DC voltage measurement. The procedure followed for programming the ADC is the following: First, all GPIO and ADC clocks are enabled using the Reset and Clock Control (RCC), then GPIO pins used (PA2, PA3, PB0, PC2, PC3, PF9) are configured in analog mode. When these are enabled, it is necessary to configure them using the sequence registers (SQR), setting the sampling time for each channel and then configuring the ADC pre-scaler and resolution (12-bit) in the common control register (CCR). Finally, the configuration of the different ADC channels is done, configuring their conversion mode in the status register (SR) to scan mode for every ADC to be able to check the values in different channels. The last step is to initialize the ADC conversion with the control register 2 (CR2) to set the channels to a working mode. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 69 6. Testing and validation of the inverter This thesis has reviewed in the previous chapters theoretical concepts about three-phase inverter control, the design and fabrication of the electrical circuit of the control system and the development of the software implementation of the SVPWM algorithm for the inverter control. This chapter will now show the results obtained when testing the developed inverter control system under different circumstances. First, the operation of the system alone will be tested, focusing in the different PWM outputs depending on the reference values inputted to the system and the signal treatment and conditioning performed in the different system’s circuits. The goal of the first part is to check if the outputs of the control system have the expected shape and functionalities. After that, the control system is incorporated to the whole three-phase inverter developed along the energy processing system developed in parallel [7]. These last tests will have the objective of demonstrating both the system’s performance in a real application and how the control affects the output under load conditions. One thing to consider is, during the tests, the ADC programming is not fully developed and implemented, so the reference values of VDC, V* and f* are manually set to the system by software. 6.1. SVPWM output testing As mentioned above, the first tests performed to the system are to check its operation stand alone, testing if the reference values change affects the output and to verify all the signal treatment is performed correctly by the different circuits integrated in the control board developed. First, the PWM outputs from the STM32F767ZI are measured under different input reference values of amplitude and frequency, the PWM output and filtered output (fundamental sinusoidal value) are captured to check that the different functionalities of the control algorithm are working. Then, the six different PWM outputs conditioned to the opto-drivers characteristics (5 V, filtering) and transistors necessities (dead-time) are captured, the objective of these measures is to check the correct design, manufacture, mounting and operation of all the different circuits that comprehend the control system. Memoria 70 6.1.1. MCU PWM output (3.3 V) As already mentioned, firstly the MCU PWM outputs are measured, checking the algorithm performance when different input reference values are applied. By measuring the output in the pins of the MCU, and also applying an RC filter to be able to observe the fundamental sinusoidal wave that is to be replied by the SVPWM the different characteristics can be observed when the reference is changed. The RC filter applied is a low-pass filter with a cut-off frequency lower than the PWM frequency so the pulses of the digital signal are not observed but the fundamental wave to be replicated by the signal is observed. The filter was designed to cut-off approximately at one tenth of the PWM frequency: 𝑓𝑅𝐶 =𝑓𝑃𝑊𝑀 10 =15.625𝑘𝐻𝑧 10 =1.562𝑘𝐻𝑧 (56) To choose the R and C values of the filter, first the resistance value is selected with a high enough value not to consume a big current for the 3.3 V of the output, then in the low-pass RC filter equation is solved for the C value. 𝐶= 1 2𝜋𝑓𝑅𝐶𝑅 (57) Common components values of 4.7 kΩ and 22 nF are selected to make a low-pass filter of 1.539 kHz. Figure 6.1.1 shows STM32F767ZI with output signals connected to the RC filters mounted in the protoboard to filter SVPWM outputs. Figure 6.1.2: STM32F767ZI and RC filters connected. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 71 In Figure 6.1.2 the output of the PWM which controls Q5 opto-driver (hence Q5 itself) out of the MCU is observed, with (blue) and without (red) RC filter to observe PWM amplitude and sinusoidal fundamental wave characteristics. The reference values used are VDC=300 V, V* (line-to-line, peak value) = 230 V and f*=50 Hz. So, the system is operating to output a 230 V peak value sinusoidal output at 50 Hz with a 300 V DC source. Figure 6.1.2: Q5 MCU PWM output. 5 ms/div, 1V/div. As observed in Figure 6.1.2, the raw PWM output (red) has an amplitude of 3.3 V, and the filtered signal is a pseudo sinusoidal signal with a period of 20 ms, which corresponds to a 50 Hz frequency. This measure serves the purpose to check the actual output of the MCU and the frequency of the fundamental sinusoidal signal being generated by the STMF767ZI SVPWM outputs. The following measure done is the filtered measure of PWM outputs for Q3 and Q5 filtered to check the offset of the two fundamental sinusoidal signals and their output frequency. As shown in Figure 6.1.3, both filtered signals are outputted with their fundamental sinusoidal components having a 6.39 ms offset corresponding almost to a 120º offset in the 20 ms period. In addition, their peak-to-peak value is 1.5 V. The reference values used are VDC=300 V, V* (line-to-line, peak value) = 100 V and f*=50 Hz. So the system is operating to output a 100 V peak value sinusoidal output at 50 Hz with a 300 V DC source. Memoria 72 Figure 6.1.3: Q3 and Q5 MCU SVPWM filtered output. 10 ms/div, 1 V/div. After that, the same measure is done but changing the reference frequency to double the one used in the test before, 100 Hz. In Figure 6.1.4 the same two signals are captured, but the period of the signals is now 10 ms corresponding to the 100 Hz reference frequency applied to the control system. The peakto-peak value is 1.5 V. The reference values used are VDC=300 V, V* (line-to-line, peak value) = 100 V and f*=100 Hz. So the system is operating to output a 100 V peak value sinusoidal output at 100 Hz with a 300 V DC source. Figure 6.1.4: Q3 and Q5 MCU SVPWM filtered output. 10 ms/div, 1 V/div. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 73 Finally, a last test is performed measuring these two signals, going back to the 50 Hz reference frequency value and increasing the reference peak voltage to 230 V. In Figure6.1.5, the signals period is 20 ms again corresponding to the 50 Hz, the peak-to-peak value is 2.7 V. The reference values used are VDC=300 V, V* (line-to-line, peak value) = 230 V and f*=50 Hz. So the system is operating to output a 100 V peak value sinusoidal output at 100 Hz with a 300 V DC source. Figure 6.1.5: Q3 and Q5 MCU SVPWM filtered output. 10 ms/div, 1 V/div. Table 6.1.1 shows comparative values between the MCU output signals depending on their input reference values. Table 6.1.1: Comparative values between output filtered signals depending on reference values. VDC VLL* (peak) f* Vpeak f Vpeak/V1peak f/f1 300 V 100 V 50 Hz 1.5 V 50 Hz 1 1 300 V 100 V 100 Hz 1.5 V 100 Hz 1 2 300 V 230 V 50 Hz 2.7 V 50 Hz 1.8 1 As illustrated in Table 6.1.1, frequency reference value is directly affecting the frequency output value being the same as the filtered sinusoidal value. Input reference voltage amplitude is also affecting the amplitude of the filtered signals, but its relation is not as direct as with the frequency. The output voltage of the sinusoidal filtered signals is related to the input reference value, but to see if the system Memoria 74 is correctly regulating the voltage, a measure with the complete inverter system is needed and it can be found in chapter 6.2. 6.1.2. Control system PWM output (5 V) After checking the different outputs from the MCU, the 5 V corrected signals out of the control system’s PCB are measured to ensure correct operation of the system and the different circuits. Figure 6.1.6 shows the whole control system with the STM32F767ZI connected to the PCB, and the system’s outputs connected to the RC filters mounted. Figure 6.1.6: Control system mounted and connected to the RC filters. In Figure 6.1.7 it is observed how the output PWM signal that controls the opening and closure of the Q1 transistor is measured with and without filter. The output raw PWM has a 5 V amplitude, and the filtered sinusoidal signal has a 20 ms period and 4.01 V peak-to-peak value. The reference values used are VDC=300 V, V* (line-to-line, peak value) = 230 V and f*=50 Hz. So the system is operating to output a 100 V peak value sinusoidal output at 100 Hz with a 300 V DC source. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 75 Figure 6.1.7: Q1 control system PWM non-filtered (blue) and filtered (red) output. 20 ms/div, 2 V/div. The signal treatment is in charge of the conditioning of the PWM signal, increasing the high logic value of the PWM to 5 V (3.5 V minimum), applying a dead time and correcting the signal to make it an almost perfect square signal with variable duty cycle. In Figure 6.1.5 it is observed how the signal is increased to 5 V maintaining the same characteristics in the fundamental sinusoidal component (frequency and amplitude variability). In Figure 6.1.8, Q1 and Q2 output 5 V signals are observed with detail on the rising/falling edges, to observe the dead-time circuit performance. In the test captured in Figure 6.1.6, dead-time is adjusted to 1.5 μs, it is observed how between the falling edge of Q2 PWM (red) and the rising edge of Q1 PWM (blue) there’s a 1.58 μs offset, confirming the correct performance of the dead-time and conditioning circuits designed. Memoria 76 Figure 6.1.8: Q1 PWM (blue) and Q2 PWM (red) offset measurement. 400 ns/div, 2.5 V/div. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 77 6.2. Load condition validation After testing the control system stand-alone, the whole three-phase inverter system is tested along with the energy processing system developed in parallel [7]. The whole system is wired and connected to every power source necessary to make it work. Figure 6.2.1 shows the complete three-phase inverter system connected to the power source, the control system in front is wired with the energy processing system and the power distribution board (back). Voltage probes are connected to an RC filter and measurement points in the transistors board [7]. These voltage probes are connected to an oscilloscope (right) used for capturing the signals. Output lines are connected to a transformer, which has a three-phase load connected in the secondary coil. Figure 6.2.1: Full inverter system in test laboratory. The transformer used has two star-connected windings, the characteristics of the windings are summed up in Table 6.2.1. Table 6.2.1: Transformer characteristics. Winding Nominal voltage Nominal current Primary 400 V 1.6 A Secondary 58 V 9.8 A With the inverter connected in the primary, and three 200W triangle-connected loads to the secondary the inverter output was measured in order to check the correct performance of the control system and Memoria 84 management of electronic waste. Such norms encourage proper disposal and recovery practices to minimize environmental harm. The resources used in this project, both material and energy, are detailed in the economic chapter. These include the PCB components, soldering devices, and measurement tools like oscilloscopes. The system itself is energy-efficient, consuming a maximum of only 2.11W during operation. It has been thoroughly tested for 20 hours to ensure reliability while maintaining low energy consumption. In conclusion, this project has been developed with a strong emphasis on sustainability, from ethical sourcing of materials to energy-efficient operation. While there are challenges in recycling certain materials like FR4 PCBs, efforts have been made to use components responsibly and minimize waste. The project’s focus on renewable energy and resource-conscious development underscores its contribution to a more sustainable future. To calculate the CO2 footprint, it is necessary to calculate the equivalent emissions of the different aspects of the project. According to the Ministerio para la Transición Ecológica (MITECO) [20], the equivalent emissions from electricity consumption are 0.166 kg of CO₂ per kWh. A computer was utilized throughout this project to carry out the necessary tasks. The equivalent emissions produced were estimated based on 600 hours of operation during the project and a power consumption of 58 W by the computer. 𝐶𝑂2𝑐𝑜𝑚𝑝𝑢𝑡𝑒𝑟 =600ℎ∗58𝑊∗0.166𝑘𝑔𝐶𝑂2 1𝑊ℎ =5.7 𝑘𝑔𝐶𝑂2 (58) In addition, the PCB was transported from Hong Kong to Barcelona by plane. Estimating a 0.2 kg of the package, a flying distance of 10301 km and a 0.6 kgCO2/t·km factor [21]. 𝐶𝑂2𝑃𝐶𝐵=10300𝑘𝑚·0.0002𝑡·0.6𝑘𝑔𝐶𝑂2 1𝑡·𝑘𝑚 =1.24 𝑘𝑔𝐶𝑂2 (59) The system’s consumption is about 2.11W, taking into account it was used for 20 H of testing, it consumed: 𝐶𝑂2𝑇𝑒𝑠𝑡 =20ℎ∗2.11𝑊∗0.166𝑘𝑔𝐶𝑂2 1𝑊ℎ =0.007 𝑘𝑔𝐶𝑂2 (60) Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 85 8.2. Social impact The development of a three-phase inverter control system has brought many benefits to different people and organizations. It has also made a positive impact on important projects related to renewable energy and sustainable technology. This project shows how engineering can help solve problems, create new tools, and contribute to a better future. First, the microelectronics institute of Barcelona now has an inverter to test their chips and transistors. This is very important for them because their research focuses on designing and improving microelectronic devices. With the three-phase inverter, they can connect their chips and transistors to a real system and see how they perform. This helps them develop better technology and push the limits of what is possible. The inverter gives them a practical tool to test their ideas and improve their work. Second, the university UPC now has an open-source inverter to test microgrids. Microgrids are small, independent energy systems that can use renewable energy like solar panels or wind turbines. By having an open-source inverter, students and researchers at UPC can experiment with new ideas for managing energy and improving microgrid performance. This makes the university a leader in renewable energy research and education. The open-source design also allows other people outside the university to use the inverter and learn from it, creating a wider impact. For the author of this thesis, working on this project has been a journey of personal and professional growth. Designing a complex system like a three-phase inverter required learning new skills, solving problems, and being very creative. It also required using teamwork and communication to make sure everything worked together. This experience has made the author a better engineer and prepared them for future challenges in their career. It has been a big step forward in their education and their life. All the materials and components used in this project were purchased from distributors that follow ethical codes. This means that the companies providing the materials care about doing business responsibly. They make sure their workers are treated fairly and that they respect the environment. This was an important decision for the project because it reflects the values of the people involved. Choosing ethical suppliers shows a commitment to doing what is right, not just what is easy. Three-phase inverter systems also play a very important role in renewable energy systems and grids. Renewable energy sources like solar panels and wind turbines produce electricity in a way that is not always steady. Inverters help convert this electricity into a stable form that can be used in homes, factories, or sent to the grid. This makes renewable energy more reliable and easier to use. By Memoria 86 improving inverter technology, we can make renewable energy systems more efficient and accessible to more people. This helps reduce pollution and supports the transition to cleaner energy for everyone. In summary, the development of the three-phase inverter control system has provided the microelectronics institute with a testing tool, the university with an open-source platform for innovation, and the author with valuable personal and professional growth. The project also showed the importance of using ethical materials and highlighted the role of inverter technology in renewable energy. It is a great example of how engineering can make a positive difference in many areas. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 87 9. Conclusions The development of a robust three-phase inverter control system for microgrid experimentation and electric traction applications has been a project that has reviewed all the aspects of developing a power electronics control system of these characteristics. This thesis has explained the design, implementation, and validation of a comprehensive control subsystem designed for laboratory use. The project adopted a holistic approach, explaining theoretical analysis, hardware design, software implementation, and rigorous testing, to deliver a versatile and high-performance inverter. The theoretical introduction provided a basis to understand the principles of DC-AC conversion, threephase inverter architectures, and advanced modulation techniques like Space Vector Pulse Width Modulation (SVPWM). The research explored efficient practices in control algorithms, focusing on minimizing harmonic distortion, optimizing switching sequences, and ensuring efficient energy conversion. These aspects were crucial for the design of a robust and adaptable control subsystem, being able to output the control signals for the transistors of the three-phase inverter ensuring a good control and performance of the converter. In terms of hardware design, the project achieved significant progress by carefully selecting and integrating essential components such as microcontrollers, level shifters, dead-time circuits, and signal conditioning elements. Complex electrical circuits have been designed to treat and adapt the SVPWM output signals from the microcontroller and make them compatible to work with the opto-drivers to which they were sent to control. A whole schematic has been designed in order to fulfil all the different functionalities of the system, making it able to receive different inputs from other systems or human interfaces such as potentiometers to regulate different aspects and critical elements in the control algorithm and system The PCB layout was meticulously crafted to ensure low noise levels, effective signal transmission, and scalability for future enhancements. The system’s modular design supports upgrades and adaptability for diverse experimental setups, reinforcing its utility in research and development contexts. The PCB was carefully designed to ensure efficient distribution and maintaining low impedance lines that could affect the signals forms. All the manufacturing and mounting process of the PCB was shown as the different parts of the system were developed, focusing on component soldering and the assembly of the different parts of the system. The software implementation relied on STM32CubeIDE, showing the flexibility and precision of modern microcontroller platforms. Real-time processing of feedback signals, including voltage and Memoria 88 current measurements, enabled adaptive control and ensured system reliability under varying load conditions. Peripherals programming and SVPWM algorithm were designed to optimize energy delivery and reduce power losses, demonstrating the project's potential for scalable industrial applications and ensuring good performance for the laboratory applications it was designed for. The software was designed thinking on adaptability and a potential future improvement in terms of implementation of different inputs, possibility of adding feedback control for the different electrical outputs such as AC currents, making it adaptable to add a motor control algorithm such as Field Oriented Control or Direct Torque Control. Testing and validation confirmed the inverter's ability to meet predefined performance standards, including stable PWM generation, accurate voltage control, and reliable operation under load conditions. These results underscore the robustness of the design and its readiness for integration into experimental microgrid setups and electric traction systems. Different tests were performed to the system, ones with the stand-alone operation, checking MCU outputs in front of different reference inputs, showcasing the good design of the software and control algorithm. Tests were performed where output waveforms from the PCB were observed to ensure correct functionality of the different circuits of the PCB and a correct manufacture and mounting process. In addition, measures were taken to check the correct operation of the dead-time circuit designed crucial for safety and good operation of the three-phase inverter. Finally, a test under load conditions was performed with the whole three-phase inverter system, which showed not only that the different developed systems could work together as a robust unit but that the control system was perfectly designed to meet the original expectations, measuring output waveforms from the inverter exactly as they were inputted as a reference in the control system. To conclude, this project has reached all the original expectations for the development of a control of three-phase inverter system for laboratory uses, adaptable to many circumstances, loads, components and different control strategies that are to be applied in the future to the developed system. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 89 10. References [1] SÉGUIER, Guy; LABRIQUE, Francis. Power electronic converters: DC-AC conversion. Springer Science & Business Media, 2012. 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Available: https://www.st.com/resource/en/datasheet/stm32f765bi.pdf. [19] STMicroelectronics, STM32F75xxx and STM32F74xxx advanced ARM-based 32-bit MCUs reference manual, RM0385, Rev. 7, Dec. 2022. [Online]. Available: https://www.st.com/resource/en/reference_manual/rm0385-stm32f75xxx-and-stm32f74xxxadvanced-armbased-32bit-mcus-stmicroelectronics.pdf. [20] Ministerio para la Transición Ecológica y el Reto Demográfico (MITECO), "Cálculo de emisiones." [Online]. Available: https://www.miteco.gob.es/content/dam/miteco/es/ceneam/programas-deeducacion-ambiental/hogares-verdes/2011%20-%2016%20Calculo%20de%20emisiones%20 HV2011_tcm30-171463.pdf [21] International Air Transport Association (IATA), "Environmental sustainability." [Online]. Available: https://www.iata.org. [22] Sunyer de Garizabal, Ignacio. Control's Optimization of a PMAC Motor for Motostudent Competition. May 2019. Universitat Politècnica de Catalunya. [23] JORDÀ I SANUY, Xavier. Conception et Réalisation d’une Commande Economique de Couple d’une Machine Asynchrone pour la Traction Electrique. Universitat Autònoma de Barcelona, 1995. Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 91 Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 93 Annex A: Electrical scheme (KiCad) Annexos 100 Tq1 = T0/2; Tq3 = T4+(T0/2); Tq5 = T4+T5+(T0/2); Tq1 = LT(Tq1 , Tmin) ? 0 : Tq1; Tq3 = LT(Tq3 , Tmin) ? 0 : Tq3; Tq5 = LT(Tq5 , Tmin) ? 0 : Tq5; } else if((GT(angle,PI*4/3) || EQ(angle,PI*4/3)) && LT(angle, PI*5/3))// (GT(angle,PI*4/3) || EQ(angle,PI*4/3)) && LT(angle, PI*5/3) { //Calculations of the application times of the non-null vectors T5 =SQRT3/(2*vbat)*(-SQRT3*valfa-vbeta)*Tcom; T6 = SQRT3/(2*vbat)*(SQRT3*valfa-vbeta)*Tcom; //Calculations of the opening times of the transistors T0 = Tcom-T5-T6; Tq1 = T6+(T0/2); Tq3 = T0/2; Tq5 = T5+T6+(T0/2); Tq1 = LT(Tq1 , Tmin) ? 0 : Tq1; Tq3 = LT(Tq3 , Tmin) ? 0 : Tq3; Tq5 = LT(Tq5 , Tmin) ? 0 : Tq5; } else{ //Calculations of the application times of the non-null vectors T6 = SQRT3/(vbat)*(-vbeta)*Tcom; T1 =SQRT3/(2*vbat)*(SQRT3*valfa+vbeta)*Tcom; //Calculations of the opening times of the transistors T0 = Tcom-T6-T1; Tq1 = T1+T6+(T0/2); Tq3 = T0/2; Tq5 = T6+(T0/2); Tq1 = LT(Tq1 , Tmin) ? 0 : Tq1; Tq3 = LT(Tq3 , Tmin) ? 0 : Tq3; Tq5 = LT(Tq5 , Tmin) ? 0 : Tq5; } // Nq1 = (Tq1/Tcom)*Ncom; // Nq3 = (Tq3/Tcom)*Ncom; // Nq5 = (Tq5/Tcom)*Ncom; } } static void tim2_callback(void){ Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 101 //Duty cycle assignation to corresponding PWM Nq1 = 256 - (Tq1/Tcom)*Ncom; Nq3 = 256 - (Tq3/Tcom)*Ncom; Nq5 = 256 - (Tq5/Tcom)*Ncom; if(++counter > 127)counter=0; TIM1->CCR1 = Nq1; TIM1->CCR2 = Nq3; TIM1->CCR3 = Nq5; //Speed discrete integration to obtain current angle, 0(tn)=0(tn1)+w*dt angle = angle+w*Tcom; //if(angle>= PI2) angle =0; angle = fmodf(angle, PI2); // this normalizes the angle between 0 and 2PI correctly (circularly) //dq to alfa beta with voltage and angle //The index of the look up tables is computed from the calculation of the angle and escalated with Ntot/PI2 valfa = cos_table[(int)(angle*Ntot/PI2)]*voltage; vbeta = sin_table[(int)(angle*Ntot/PI2)]*voltage; } void TIM2_IRQHandler(void){ //Clear the update interrupt flag TIM2->SR &= ~SR_UIF; //Execute control orders tim2_callback(); } Annexos 102 TIMER_CONFIG.C #include "stm32f767xx.h" #define DIER_UIE (1U<<0) void tim1_PWM_output(void){ //Config pins for alternate function as TIM1 channels// //Clock access to AHB1 (GPIOA, GPIOE) RCC->AHB1ENR |= (1U<<0); RCC->AHB1ENR |= (1U<<4); //PA8 TIM1/1 Q1 AF GPIOA->MODER &=~ (1U<<16); GPIOA->MODER |= (1U<<17); //PA9 TIM1/2 Q3 AF GPIOA->MODER &=~ (1U<<18); GPIOA->MODER |= (1U<<19); //PA10 TIM1/3 Q5 AF GPIOA->MODER &=~ (1U<<20); GPIOA->MODER |= (1U<<21); //PE14 TIM1/4 Q7 AF GPIOE->MODER &=~ (1U<<28); GPIOE->MODER |= (1U<<29); //PA7 TIM1/1N Q2 AF GPIOA->MODER &=~ (1U<<14); GPIOA->MODER |= (1U<<15); //PE10 TIM1/2N Q4 AF GPIOE->MODER &=~ (1U<<20); GPIOE->MODER |= (1U<<21); //PE12 TIM1/3N Q6 AF GPIOE->MODER &=~ (1U<<24); GPIOE->MODER |= (1U<<25); //Set pins to corresponding AF type (TIMX_CHX(N))--> they are all AF1 //PA8 --> AFR8 --> AF1 GPIOA->AFR[1] |= (1U<<0); GPIOA->AFR[1] &=~ (1U<<1); GPIOA->AFR[1] &=~ (1U<<2); GPIOA->AFR[1] &=~ (1U<<3); //PA9 --> AFR9 --> AF1 GPIOA->AFR[1] |= (1U<<4); GPIOA->AFR[1] &=~ (1U<<5); GPIOA->AFR[1] &=~ (1U<<6); GPIOA->AFR[1] &=~ (1U<<7); //PA10 --> AFR10 --> AF1 GPIOA->AFR[1] |= (1U<<8); GPIOA->AFR[1] &=~ (1U<<9); GPIOA->AFR[1] &=~ (1U<<10); GPIOA->AFR[1] &=~ (1U<<11); Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 103 //PE14 --> AFR14 --> AF1 GPIOE->AFR[1] |= (1U<<24); GPIOE->AFR[1] &=~ (1U<<25); GPIOE->AFR[1] &=~ (1U<<26); GPIOE->AFR[1] &=~ (1U<<27); //PA7 --> AFR7 --> AF1 GPIOA->AFR[0] |= (1U<<28); GPIOA->AFR[0] &=~ (1U<<29); GPIOA->AFR[0] &=~ (1U<<30); GPIOA->AFR[0] &=~ (1U<<31); //PE10 --> AFR10 --> AF1 GPIOE->AFR[1] |= (1U<<8); GPIOE->AFR[1] &=~ (1U<<9); GPIOE->AFR[1] &=~ (1U<<10); GPIOE->AFR[1] &=~ (1U<<11); //PE12 --> AFR12 --> AF1 GPIOE->AFR[1] |= (1U<<16); GPIOE->AFR[1] &=~ (1U<<17); GPIOE->AFR[1] &=~ (1U<<18); GPIOE->AFR[1] &=~ (1U<<19); //Clock access enable APB2 (TIM1) RCC->APB2ENR |= (1U<<0); //Set pre-scaler value TIM1->PSC = 2 - 1; // 16.000.000 / 2 = 8.000.000 Hz //Set auto-reload value TIM1->ARR = 256 - 1; // 8.000.000 / 256 = 31.250 Hz = 31.25 kH TIM1->CCR1 = 255; TIM1->CCR2 = 255; TIM1->CCR3 = 255; TIM1->CCR4 = 255; //Enable centre-aligned mode 1 TIM1->CR1 |= (1U<<5); TIM1->CR1 &=~ (1U<<6); //Enable MOE TIM1->BDTR |= (1U<<15); //Enable TIM1_CH1 output compare TIM1->CCMR1 &=~(1U<<0); TIM1->CCMR1 &=~(1U<<1); //Enable TIM1_CH2 output compare TIM1->CCMR1 &=~(1U<<8); TIM1->CCMR1 &=~(1U<<9); //Enable TIM1_CH3 output compare TIM1->CCMR2 &=~(1U<<0); TIM1->CCMR2 &=~(1U<<1); //Enable TIM1_CH4 output compare TIM1->CCMR2 &=~(1U<<8); Annexos 104 TIM1->CCMR2 &=~(1U<<9); //We set the Output compare mode to PWM Mode 2 //TIM1_CH1 Q1 TIM1->CCMR1 |= (1U<<5) | (1U<<6)|(1U<<4); TIM1->CCMR1 &= ~(1U<<16); //TIM1_CH2 Q3 TIM1->CCMR1 |= (1U<<12) | (1U<<13) | (1U<<14); TIM1->CCMR1 &= ~(1U<<24); //TIM1_CH3 Q5 TIM1->CCMR2 |= (1U<<5) | (1U<<6)|(1U<<4); TIM1->CCMR2 &= ~(1U<<16); //TIM1_CH4 Q7 TIM1->CCMR2 |= (1U<<12) | (1U<<13) | (1U<<14); TIM1->CCMR2 &= ~(1U<<24); //Capture/Compare enable works for both functions since they are used with the same bits //We enable the capture/compare channels //CH1 (Q1) & CH1_N (Q2) TIM1->CCER |= (1U<<0); TIM1->CCER |= (1U<<2); //CH2 (Q3) & CH2_N (Q4) TIM1->CCER |= (1U<<4); TIM1->CCER |= (1U<<6); //CH3 (Q5) & CH3_N (Q6) TIM1->CCER |= (1U<<8); TIM1->CCER |= (1U<<10); //CH4 (Q7) TIM1->CCER |= (1U<<12); //Clear counter TIM1->CNT = 0; // Enable timer 1 as slave, trigger by Timer 2 //Slave mode selection, We can try either Trigger mode (0110) or Combined reset + trigger mode (1000) TIM1->SMCR |= (1U<<16); // Slave mode selection: Trigger Mode (reset on rising edge) TIM1->SMCR &= ~(1U<<0); TIM1->SMCR &= ~(1U<<1); TIM1->SMCR &= ~(1U<<2); //TS, trigger selection, 001 Internal Trigger 1 (ITR1), which following the table, corresponds to TIM2 TIM1->SMCR |= (1U<<4); // Trigger selection: TI1FP1 (TI1 Edge Detector) TIM1->SMCR &= ~(1U<<5); TIM1->SMCR &= ~(1U<<6); } void tim2_interrupt_init(void){ Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 105 //Enable clock access to TIM2 RCC->APB1ENR |= (1U<<0); //Set prescaler value TIM2->PSC = 4-1; // 16 000 000 Hz/ 4 = 4 000 000 Hz //Set auto-reload value TIM2->ARR = 256 - 1; // 4 000 000/256 = 15625 Hz //Clear counter TIM2->CNT = 0; //Enable TIM interrupt, configuring the interrupt enable register TIM2->DIER |= DIER_UIE; //Enable TIM interrupt in NVIC, TIM2_IRQn is equivalent to 28 NVIC_EnableIRQ(TIM2_IRQn); //Master Mode selection for TIM2, Update, the update event is selected as trigger output TIM2->CR2 |= (1U<<5); TIM2->CR2 &= ~(1U<<4); TIM2->CR2 &= ~(1U<<6); } Annexos 106 MAIN.H #ifndef MAIN_H_ #define MAIN_H_ #define EPSILON 1e-6 #define EQ(x, y) (fabs((x) - (y)) < EPSILON) #define LT(x, y) (((x) - (y)) < -EPSILON) #define GT(x, y) (((x) - (y)) > EPSILON) #define SR_UIF (1U<<0) //Constant definitions #define SQRT3 1.73205080757f #define PI 3.14159265358f #define PI2 6.283185307f #define VOLTAGE_STEP 0.01 // Increment of voltage for every interruption int counter = 0; int i = 0; //Variables definition //Configurable variables by the user, in the current program freq and Tcom are computed in main float freq; int voltage_ll =230; float voltage = 230/SQRT3; float Tcom; //Computed variables related to configurable variables float w; //int angle=0; float angle = 0.0f; float valfa, vbeta; //Transistor commutation times, periods, and integers float T1, T2, T3, T4, T5, T6, T0; float Tq1, Tq3, Tq5; int Nq1, Nq3, Nq5; int Ncom; //Subdivisions of the SVPWM period (power of 2) int Ntot = 256; //2^8 subdivisions, same as length of look up tables float vref, vbat = 300, fref = 50; //Measured values, not in the current version //Minimum T IGBTs can handle (rising / falling edges...) float Tmin = 0; //Look-up tables of sin and cos of 256 values (2^8) const float sin_table[256] = { 0.0000000000, 0.0245412285, 0.0490676743, 0.0735645636, 0.0980171403, 0.1224106752, 0.1467304745, 0.1709618888, 0.1950903220, 0.2191012402, 0.2429801799, 0.2667127575, 0.2902846773, 0.3136817404, 0.3368898534, 0.3598950365, Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 107 0.3826834324, 0.4052413140, 0.4275550934, 0.4496113297, 0.4713967368, 0.4928981922, 0.5141027442, 0.5349976199, 0.5555702330, 0.5758081914, 0.5956993045, 0.6152315906, 0.6343932842, 0.6531728430, 0.6715589548, 0.6895405447, 0.7071067812, 0.7242470830, 0.7409511254, 0.7572088465, 0.7730104534, 0.7883464276, 0.8032075315, 0.8175848132, 0.8314696123, 0.8448535652, 0.8577286100, 0.8700869911, 0.8819212643, 0.8932243012, 0.9039892931, 0.9142097557, 0.9238795325, 0.9329927988, 0.9415440652, 0.9495281806, 0.9569403357, 0.9637760658, 0.9700312532, 0.9757021300, 0.9807852804, 0.9852776424, 0.9891765100, 0.9924795346, 0.9951847267, 0.9972904567, 0.9987954562, 0.9996988187, 1.0000000000, 0.9996988187, 0.9987954562, 0.9972904567, 0.9951847267, 0.9924795346, 0.9891765100, 0.9852776424, 0.9807852804, 0.9757021300, 0.9700312532, 0.9637760658, 0.9569403357, 0.9495281806, 0.9415440652, 0.9329927988, 0.9238795325, 0.9142097557, 0.9039892931, 0.8932243012, 0.8819212643, 0.8700869911, 0.8577286100, 0.8448535652, 0.8314696123, 0.8175848132, 0.8032075315, 0.7883464276, 0.7730104534, 0.7572088465, 0.7409511254, 0.7242470830, 0.7071067812, 0.6895405447, 0.6715589548, 0.6531728430, 0.6343932842, 0.6152315906, 0.5956993045, 0.5758081914, 0.5555702330, 0.5349976199, 0.5141027442, 0.4928981922, 0.4713967368, 0.4496113297, 0.4275550934, 0.4052413140, 0.3826834324, 0.3598950365, 0.3368898534, 0.3136817404, 0.2902846773, 0.2667127575, 0.2429801799, 0.2191012402, 0.1950903220, 0.1709618888, 0.1467304745, 0.1224106752, 0.0980171403, 0.0735645636, 0.0490676743, 0.0245412285, 0.0000000000,-0.0245412285,-0.0490676743,-0.0735645636, -0.0980171403,-0.1224106752,-0.1467304745,-0.1709618888, -0.1950903220,-0.2191012402,-0.2429801799,-0.2667127575, -0.2902846773,-0.3136817404,-0.3368898534,-0.3598950365, -0.3826834324,-0.4052413140,-0.4275550934,-0.4496113297, -0.4713967368,-0.4928981922,-0.5141027442,-0.5349976199, -0.5555702330,-0.5758081914,-0.5956993045,-0.6152315906, -0.6343932842,-0.6531728430,-0.6715589548,-0.6895405447, -0.7071067812,-0.7242470830,-0.7409511254,-0.7572088465, -0.7730104534,-0.7883464276,-0.8032075315,-0.8175848132, -0.8314696123,-0.8448535652,-0.8577286100,-0.8700869911, -0.8819212643,-0.8932243012,-0.9039892931,-0.9142097557, -0.9238795325,-0.9329927988,-0.9415440652,-0.9495281806, -0.9569403357,-0.9637760658,-0.9700312532,-0.9757021300, -0.9807852804,-0.9852776424,-0.9891765100,-0.9924795346, -0.9951847267,-0.9972904567,-0.9987954562,-0.9996988187, -1.0000000000,-0.9996988187,-0.9987954562,-0.9972904567, -0.9951847267,-0.9924795346,-0.9891765100,-0.9852776424, -0.9807852804,-0.9757021300,-0.9700312532,-0.9637760658, -0.9569403357,-0.9495281806,-0.9415440652,-0.9329927988, -0.9238795325,-0.9142097557,-0.9039892931,-0.8932243012, -0.8819212643,-0.8700869911,-0.8577286100,-0.8448535652, -0.8314696123,-0.8175848132,-0.8032075315,-0.7883464276, -0.7730104534,-0.7572088465,-0.7409511254,-0.7242470830, Annexos 108 -0.7071067812,-0.6895405447,-0.6715589548,-0.6531728430, -0.6343932842,-0.6152315906,-0.5956993045,-0.5758081914, -0.5555702330,-0.5349976199,-0.5141027442,-0.4928981922, -0.4713967368,-0.4496113297,-0.4275550934,-0.4052413140, -0.3826834324,-0.3598950365,-0.3368898534,-0.3136817404, -0.2902846773,-0.2667127575,-0.2429801799,-0.2191012402, -0.1950903220,-0.1709618888,-0.1467304745,-0.1224106752, -0.0980171403,-0.0735645636,-0.0490676743,-0.0245412285 }; const float cos_table[256] = { 1.0000000000, 0.9996988187, 0.9987954562, 0.9972904567, 0.9951847267, 0.9924795346, 0.9891765100, 0.9852776424, 0.9807852804, 0.9757021300, 0.9700312532, 0.9637760658, 0.9569403357, 0.9495281806, 0.9415440652, 0.9329927988, 0.9238795325, 0.9142097557, 0.9039892931, 0.8932243012, 0.8819212643, 0.8700869911, 0.8577286100, 0.8448535652, 0.8314696123, 0.8175848132, 0.8032075315, 0.7883464276, 0.7730104534, 0.7572088465, 0.7409511254, 0.7242470830, 0.7071067812, 0.6895405447, 0.6715589548, 0.6531728430, 0.6343932842, 0.6152315906, 0.5956993045, 0.5758081914, 0.5555702330, 0.5349976199, 0.5141027442, 0.4928981922, 0.4713967368, 0.4496113297, 0.4275550934, 0.4052413140, 0.3826834324, 0.3598950365, 0.3368898534, 0.3136817404, 0.2902846773, 0.2667127575, 0.2429801799, 0.2191012402, 0.1950903220, 0.1709618888, 0.1467304745, 0.1224106752, 0.0980171403, 0.0735645636, 0.0490676743, 0.0245412285, 0.0000000000,-0.0245412285,-0.0490676743,-0.0735645636, -0.0980171403,-0.1224106752,-0.1467304745,-0.1709618888, -0.1950903220,-0.2191012402,-0.2429801799,-0.2667127575, -0.2902846773,-0.3136817404,-0.3368898534,-0.3598950365, -0.3826834324,-0.4052413140,-0.4275550934,-0.4496113297, -0.4713967368,-0.4928981922,-0.5141027442,-0.5349976199, -0.5555702330,-0.5758081914,-0.5956993045,-0.6152315906, -0.6343932842,-0.6531728430,-0.6715589548,-0.6895405447, -0.7071067812,-0.7242470830,-0.7409511254,-0.7572088465, -0.7730104534,-0.7883464276,-0.8032075315,-0.8175848132, -0.8314696123,-0.8448535652,-0.8577286100,-0.8700869911, -0.8819212643,-0.8932243012,-0.9039892931,-0.9142097557, -0.9238795325,-0.9329927988,-0.9415440652,-0.9495281806, -0.9569403357,-0.9637760658,-0.9700312532,-0.9757021300, -0.9807852804,-0.9852776424,-0.9891765100,-0.9924795346, -0.9951847267,-0.9972904567,-0.9987954562,-0.9996988187, -1.0000000000,-0.9996988187,-0.9987954562,-0.9972904567, -0.9951847267,-0.9924795346,-0.9891765100,-0.9852776424, -0.9807852804,-0.9757021300,-0.9700312532,-0.9637760658, -0.9569403357,-0.9495281806,-0.9415440652,-0.9329927988, -0.9238795325,-0.9142097557,-0.9039892931,-0.8932243012, -0.8819212643,-0.8700869911,-0.8577286100,-0.8448535652, -0.8314696123,-0.8175848132,-0.8032075315,-0.7883464276, -0.7730104534,-0.7572088465,-0.7409511254,-0.7242470830, -0.7071067812,-0.6895405447,-0.6715589548,-0.6531728430, -0.6343932842,-0.6152315906,-0.5956993045,-0.5758081914, -0.5555702330,-0.5349976199,-0.5141027442,-0.4928981922, Development of a robust three-phase inverter for microgrid (MG) and electric traction experimentation: control subsystem 109 -0.4713967368,-0.4496113297,-0.4275550934,-0.4052413140, -0.3826834324,-0.3598950365,-0.3368898534,-0.3136817404, -0.2902846773,-0.2667127575,-0.2429801799,-0.2191012402, -0.1950903220,-0.1709618888,-0.1467304745,-0.1224106752, -0.0980171403,-0.0735645636,-0.0490676743,-0.0245412285, -0.0000000000, 0.0245412285, 0.0490676743, 0.0735645636, 0.0980171403, 0.1224106752, 0.1467304745, 0.1709618888, 0.1950903220, 0.2191012402, 0.2429801799, 0.2667127575, 0.2902846773, 0.3136817404, 0.3368898534, 0.3598950365, 0.3826834324, 0.4052413140, 0.4275550934, 0.4496113297, 0.4713967368, 0.4928981922, 0.5141027442, 0.5349976199, 0.5555702330, 0.5758081914, 0.5956993045, 0.6152315906, 0.6343932842, 0.6531728430, 0.6715589548, 0.6895405447, 0.7071067812, 0.7242470830, 0.7409511254, 0.7572088465, 0.7730104534, 0.7883464276, 0.8032075315, 0.8175848132, 0.8314696123, 0.8448535652, 0.8577286100, 0.8700869911, 0.8819212643, 0.8932243012, 0.9039892931, 0.9142097557, 0.9238795325, 0.9329927988, 0.9415440652, 0.9495281806, 0.9569403357, 0.9637760658, 0.9700312532, 0.9757021300, 0.9807852804, 0.9852776424, 0.9891765100, 0.9924795346, 0.9951847267, 0.9972904567, 0.9987954562, 0.9996988187 }; #endif /* MAIN_H_ */